CN106847202B - Signal processing circuit, display device and control method thereof - Google Patents
Signal processing circuit, display device and control method thereof Download PDFInfo
- Publication number
- CN106847202B CN106847202B CN201611110207.XA CN201611110207A CN106847202B CN 106847202 B CN106847202 B CN 106847202B CN 201611110207 A CN201611110207 A CN 201611110207A CN 106847202 B CN106847202 B CN 106847202B
- Authority
- CN
- China
- Prior art keywords
- signal
- input
- processing circuit
- trigger
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a signal processing circuit, comprising: the input end of the trigger is connected with the signal input end, and the trigger end is connected with the clock signal; and the input end of the logic AND gate is respectively connected with the input signal and the output end of the trigger, the output end of the logic AND gate is connected with the signal output end, and the signal processing circuit performs noise reduction processing on the input signal of the signal input end. The invention also provides a display device and a control method thereof, which can repair the cascade signal of the source driver when the cascade signal is abnormally transmitted, avoid the abnormal picture caused by the misoperation of the source driver when the cascade signal is abnormal, improve the reliability of the driving chip and reduce the wiring.
Description
Technical Field
The invention belongs to the field of displays, and particularly relates to a signal processing circuit, a display device and a control method thereof.
Background
Recently, flat display devices such as liquid crystal display devices have been increased in size. Large flat display devices drive signal lines by using ICs (integrated circuits) called source drivers. There is a limit to the number of signal lines that can be driven by each source driver. A flat display device, which is enlarged and highly refined, has a plurality of source drivers having a cascade connection configuration as shown in fig. 1. The flat display device sequentially operates a plurality of source drivers and drives all signal lines for one horizontal line.
As shown in fig. 1, the related art flat display device 1 includes a controller 10, source driver ICs 1 through 4, and a display 20. The controller 10 transmits a clock signal CLK, a LOAD signal LOAD, and data signals DDO to DD5 to each of the source drivers. The clock signal CLK is a signal that generates operation clocks of the source driver ICs 1 to 4. The data signals DD0 to DD5 are pixel data. Each of the source driver ICs 1-4 outputs pixel driving signals corresponding to the data signals DD 0-DD 5 to the display 12. The LOAD signal LOAD is a gate signal that puts the data signals DD0 through DD5 into each of the source driver ICs 1 through IC 4. This LOAD signal LOAD is output from the controller 10 to the source driver ICs 1 to 4 at each horizontal period. In the example of fig. 1, the number of source drivers is limited to four for simplification of the drawing. However, a large number of source drivers may be further used.
However, when the power, ground or fluctuating signals around the source driver ICs 1 to 4 of the cascade structure interfere with the cascade signal, the cascade signal may generate noise, which may cause malfunction of the source driver ICs and abnormal screen.
Disclosure of Invention
The invention aims to provide a signal processing circuit, a display device and a control method thereof.
According to an aspect of the present invention, there is provided a signal processing circuit comprising: the input end of the trigger is connected with the signal input end, and the trigger end is connected with the clock signal; and the input end of the logic AND gate is respectively connected with the input signal and the output end of the trigger, the output end of the logic AND gate is connected with the signal output end, and the signal processing circuit performs noise reduction processing on the input signal of the signal input end.
Preferably, the clock signal is set in synchronization with an input signal of the signal input terminal.
Preferably, when the input signal of the signal input terminal is normally transmitted, the output terminal of the flip-flop outputs a high level.
Preferably, when the input signal of the signal input terminal abnormally transmits, the output terminal of the flip-flop outputs a low level.
According to another aspect of the present invention, there is provided a display device including a controller, a plurality of source drivers, and a display,
wherein the controller transmits a clock signal, a load signal, and a data signal to each of the plurality of source drivers;
each source driver outputs a pixel driving signal corresponding to the data signal to a display;
the display device further includes:
and the signal processing circuit is connected with the cascade signals of the source drivers and is used for carrying out noise reduction processing on the cascade signals of each source driver.
Preferably, the signal processing circuit includes: the input end of the trigger is connected with the signal input end, and the trigger end is connected with the clock signal; and the input end of the logic AND gate is respectively connected with the input signal and the output end of the trigger, and the output end of the logic AND gate is connected with the signal output end, wherein the input signal of the signal input end is a cascade signal of the source electrode driver.
Preferably, the clock signal is set in synchronization with an input signal of the signal input terminal.
Preferably, when the input signal of the signal input terminal is normally transmitted, the output terminal of the flip-flop outputs a high level.
Preferably, when the input signal of the signal input terminal abnormally transmits, the output terminal of the flip-flop outputs a low level.
Preferably, the signal processing circuit is located outside the source driver, and is connected between the cascade signal of the source driver and the source driver.
The invention also provides a control method of the display device, which comprises the following steps: transmitting a clock signal, a load signal, and a data signal to each of the plurality of source drivers; carrying out noise reduction processing on the cascade signal of each source electrode driver; and outputting a pixel driving signal corresponding to the data signal to a display.
The signal processing circuit, the display device and the control method thereof can repair the cascade signal of the source driver when the cascade signal is abnormally transmitted, avoid the abnormal picture caused by the misoperation of the source driver when the cascade signal is abnormal, improve the reliability of a driving chip and reduce wiring.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic view of a prior art display device;
FIG. 2 shows a circuit schematic of a signal processing circuit according to an embodiment of the invention;
fig. 3 shows waveforms of signals at a signal input and a signal output of a signal processing circuit and a clock signal according to an embodiment of the invention;
fig. 4 shows a circuit schematic of a display device according to an embodiment of the invention;
fig. 5 illustrates a flowchart of a control method of a display apparatus according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 2 shows a circuit schematic of a signal processing circuit according to an embodiment of the invention. As shown in fig. 1, the signal processing circuit 30 includes a flip-flop 301 and a logic and gate 302.
The flip-flop 301 includes an input terminal D, a trigger terminal C, and an output terminal Q.
IN this embodiment, the flip-flop is a synchronous flip-flop, the input terminal D of the flip-flop 301 is connected to the signal input terminal IN, and the trigger terminal C is connected to the clock signal CLK.
The clock signal CLK and the input signal Vin at the signal input terminal IN are synchronous signals. If the input signal Vin is a square pulse wave, the clock signal CLK is the same square pulse wave as the input signal Vin.
Logical and gate 302 includes input 1, input 2, and output 3.
In this embodiment, the input terminal 1 of the logic and gate is connected to the input signal Vin. The input end 2 of the logic and gate is connected with the output end Q of the flip-flop 301, and the output end 3 of the logic and gate is connected with the signal output end OUT.
Specifically, as shown IN fig. 3, the input signal Vin at the signal input terminal IN is a square pulse wave, and the set clock signal is a square pulse wave identical to the input signal Vin.
Since the flip-flop 301 is a synchronous flip-flop, when the clock signal is at a high level, the output terminal of the flip-flop 301 is controlled by the input signal Vin; when the clock signal is at a low level, the state of the output terminal of the flip-flop 301 is always kept at a low level.
When the input signal Vin at the signal input end IN is normally transmitted, and the clock signal is at a high level, and the input signal Vin is also at a high level, the output end Q of the flip-flop 301 is consistent with the input signal Vin and is also at a high level, so that the input end 1 and the input end 2 of the logic and gate 302 are both at a high level, and the output end 3 is at a high level; when the clock signal is at a low level, and the input signal Vin is also at a low level, the state of the output terminal Q of the flip-flop 301 is always at a low level, and thus the input terminal 1 and the input terminal 2 of the logic and gate 302 are both at a low level, and the output terminal 3 is at a low level. Therefore, the output signal Vout of the signal output terminal OUT coincides with the input signal Vin.
When the input signal Vin at the signal input terminal IN is abnormally transmitted, the clock signal is at a low level, and the input signal Vin is at a high level, the state of the output terminal Q of the flip-flop 301 is always kept at a low level, and further, the input terminal 1 of the logic and gate 302 is at a high level, the input terminal 2 is at a low level, and the output terminal 3 of the logic and gate 302 is at a low level. Therefore, the output signal Vout of the signal output terminal OUT is consistent with the original input signal Vin, so that the input signal Vin is restored to normal.
The signal processing circuit provided by the invention can repair the cascade signal of the source driver when the cascade signal is abnormally transmitted, avoids picture abnormity caused by misoperation of the source driver when the cascade signal is abnormal, improves the reliability of a driving chip and reduces wiring.
Fig. 4 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 4, the display device includes a controller 10, a plurality of source driver ICs 1 to 4, and a display 20.
Wherein the controller 10 transmits a clock signal CLK, a LOAD signal LOAD, and data signals DDO to DD5 to each of the source drivers. The clock signal CLK is a signal that generates operation clocks of the source driver ICs 1 to 4. The data signals DD0 to DD5 are pixel data. Each of the source driver ICs 1-4 outputs pixel driving signals corresponding to the data signals DD 0-DD 5 to the display 12. The LOAD signal LOAD is a gate signal that puts the data signals DD0 through DD5 into each of the source driver ICs 1 through IC 4. This LOAD signal LOAD is output from the controller 10 to the source driver ICs 1 to 4 at each horizontal period. In the example of fig. 1, the number of source drivers is limited to four for simplification of the drawing. However, a large number of source drivers may be further used.
The display device further includes a signal processing circuit 30 connected to the cascade signal DIO of the source driver ICs 1 to 4, and configured to perform noise reduction processing on the cascade signal DIO of each of the source drivers.
The signal processing circuit 30 comprises a flip-flop 301 and a logical and gate 302.
The flip-flop 301 includes an input terminal D, a trigger terminal C, and an output terminal Q.
IN this embodiment, the flip-flop is a synchronous flip-flop, the input terminal D of the flip-flop 301 is connected to the signal input terminal IN, and the trigger terminal C is connected to the clock signal CLK.
The clock signal CLK and the input signal Vin at the signal input terminal IN are synchronous signals. If the input signal Vin is a square pulse wave, the clock signal CLK is the same square pulse wave as the input signal Vin.
Logical and gate 302 includes input 1, input 2, and output 3.
In this embodiment, the input terminal 1 of the logic and gate is connected to the input signal Vin. The input end 2 of the logic and gate is connected with the output end Q of the flip-flop 301, and the output end 3 of the logic and gate is connected with the signal output end OUT.
Specifically, as shown IN fig. 3, the input signal Vin at the signal input terminal IN is a square pulse wave, and the set clock signal is a square pulse wave identical to the input signal Vin.
Since the flip-flop 301 is a synchronous flip-flop, when the clock signal is at a high level, the output terminal of the flip-flop 301 is controlled by the input signal Vin; when the clock signal is at a low level, the state of the output terminal of the flip-flop 301 is always kept at a low level.
When the input signal Vin at the signal input end IN is normally transmitted, and the clock signal is at a high level, and the input signal Vin is also at a high level, the output end Q of the flip-flop 301 is consistent with the input signal Vin and is also at a high level, so that the input end 1 and the input end 2 of the logic and gate 302 are both at a high level, and the output end 3 is at a high level; when the clock signal is at a low level, and the input signal Vin is also at a low level, the state of the output terminal Q of the flip-flop 301 is always at a low level, and thus the input terminal 1 and the input terminal 2 of the logic and gate 302 are both at a low level, and the output terminal 3 is at a low level. Therefore, the output signal Vout of the signal output terminal OUT coincides with the input signal Vin.
When the input signal Vin at the signal input terminal IN is abnormally transmitted, the clock signal is at a low level, and the input signal Vin is at a high level, the state of the output terminal Q of the flip-flop 301 is always kept at a low level, and further, the input terminal 1 of the logic and gate 302 is at a high level, the input terminal 2 is at a low level, and the output terminal 3 of the logic and gate 302 is at a low level. Therefore, the output signal Vout of the signal output terminal OUT is consistent with the original input signal Vin, so that the input signal Vin is restored to normal.
In a preferred embodiment, the signal processing circuit 30 is located outside the source driver ICs 1 to 4, and is connected between the cascade signal DIO of the source driver and the source driver ICs 1 to 4.
Each of the source driver ICs 1-4 outputs a pixel driving signal corresponding to the data signal to a display.
The display device provided by the invention can repair the cascade signal of the source driver when the cascade signal is abnormally transmitted, avoids abnormal pictures caused by misoperation of the source driver when the cascade signal is abnormal, improves the reliability of a driving chip and reduces wiring.
Fig. 5 is a flowchart illustrating a control method of a display apparatus according to an embodiment of the present invention. The control method is suitable for the display device. The display device includes a controller 10, a plurality of source driver ICs 1-4, and a display 20. As shown in fig. 5, the control method includes the following steps.
In step S01, a clock signal, a load signal, and a data signal are transmitted to each of the plurality of source drivers.
In the present embodiment, the controller 10 of the display apparatus transmits a clock signal CLK, a LOAD signal LOAD, and data signals DDO to DD5 to each of the source drivers. The clock signal CLK is a signal that generates operation clocks of the source driver ICs 1 to 4. The data signals DD0 to DD5 are pixel data. Each of the source driver ICs 1-4 outputs pixel driving signals corresponding to the data signals DD 0-DD 5 to the display 12. The LOAD signal LOAD is a gate signal that puts the data signals DD0 through DD5 into each of the source driver ICs 1 through IC 4. This LOAD signal LOAD is output from the controller 10 to the source driver ICs 1 to 4 at each horizontal period.
In step S02, noise reduction processing is performed on the cascade signal of each of the source drivers.
In this embodiment, the signal processing circuit 30 of the display device is connected to the cascade signal DIO of the source driver ICs 1 to 4, and is configured to perform noise reduction processing on the cascade signal DIO signal of each source driver.
In step S03, a pixel drive signal corresponding to the data signal is output to the display.
The control method of the display device provided by the invention can repair the cascade signal of the source driver when the cascade signal is abnormally transmitted, avoids the abnormal picture caused by the misoperation of the source driver when the cascade signal is abnormal, improves the reliability of the driving chip and reduces the wiring.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.
Claims (8)
1. A signal processing circuit, comprising:
the input end of the trigger is connected with the signal input end, and the trigger end is connected with the clock signal;
the input end of the logic AND gate is respectively connected with the input signal and the output end of the trigger, and the output end of the logic AND gate is connected with the signal output end;
the signal processing circuit performs noise reduction processing on an input signal of a signal input end, the trigger is a synchronous trigger, the clock signal is synchronously set with the input signal of the signal input end, when the input signal of the signal input end is normally transmitted, the input signal is at a low level when the clock signal is at a low level, and when the input signal of the signal input end is abnormally transmitted, the input signal is at a high level when the clock signal is at a low level.
2. The signal processing circuit of claim 1, wherein the output terminal of the flip-flop outputs a high level when the input signal at the signal input terminal is normally transmitted.
3. The signal processing circuit of claim 1, wherein the output terminal of the flip-flop outputs a low level when the input signal at the signal input terminal abnormally transfers.
4. A display device comprises a controller, a plurality of source drivers and a display,
wherein the controller sends a clock signal, a load signal, and a data signal to each of the plurality of source drivers;
each source driver outputs a pixel driving signal corresponding to the data signal to a display;
the display device further includes: the signal processing circuit is connected with the cascade signals of the source drivers and is used for carrying out noise reduction processing on the cascade signals of each source driver;
the signal processing circuit includes:
the input end of the trigger is connected with the signal input end, and the trigger end is connected with the clock signal;
the input end of the logic AND gate is respectively connected with the input signal and the output end of the trigger, the output end of the logic AND gate is connected with the signal output end,
the input signal of the signal input end is a cascade signal of the source driver, the flip-flop is a synchronous flip-flop, the clock signal is synchronously set with the input signal of the signal input end, when the input signal of the signal input end is normally transmitted, the input signal is at a low level when the clock signal is at a low level, and when the input signal of the signal input end is abnormally transmitted, the input signal is at a high level when the clock signal is at a low level.
5. The display device according to claim 4, wherein the output terminal of the flip-flop outputs a high level when the input signal of the signal input terminal is normally transmitted.
6. The display device according to claim 4, wherein the output terminal of the flip-flop outputs a low level when the input signal at the signal input terminal abnormally transfers.
7. The display device according to claim 4, wherein the signal processing circuit is located outside the source driver, and is connected between the cascade signal of the source driver and the source driver.
8. A control method of a display device according to any one of claims 4 to 7, characterized in that the control method of the display device comprises:
transmitting a clock signal, a load signal, and a data signal to each of the plurality of source drivers;
connecting a signal processing circuit with the cascade signals of the plurality of source drivers, and performing noise reduction processing on the cascade signals of each source driver;
outputting pixel drive signals corresponding to the data signals to a display,
the signal processing circuit comprises a synchronous trigger, an input signal of a signal input end of the synchronous trigger is a cascade signal of the source electrode driver, and the clock signal and the input signal of the signal input end are synchronously arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611110207.XA CN106847202B (en) | 2016-12-06 | 2016-12-06 | Signal processing circuit, display device and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611110207.XA CN106847202B (en) | 2016-12-06 | 2016-12-06 | Signal processing circuit, display device and control method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106847202A CN106847202A (en) | 2017-06-13 |
| CN106847202B true CN106847202B (en) | 2020-04-24 |
Family
ID=59146369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611110207.XA Active CN106847202B (en) | 2016-12-06 | 2016-12-06 | Signal processing circuit, display device and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106847202B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113053277B (en) * | 2021-04-20 | 2022-09-09 | 合肥京东方显示技术有限公司 | Display panel and driving device and driving method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1655223A (en) * | 2004-02-10 | 2005-08-17 | 夏普株式会社 | Driver circuit for display device and display device |
| KR20090083565A (en) * | 2008-01-30 | 2009-08-04 | 엘지디스플레이 주식회사 | Display device and driving method thereof |
| CN202305673U (en) * | 2011-11-01 | 2012-07-04 | 武汉理工大学 | Alternating current (AC) impedance testing device suitable for fuel cells |
| CN102710255A (en) * | 2012-06-14 | 2012-10-03 | 哈尔滨工业大学 | Clock data recovery circuit capable of resisting double frequency multiplication locking |
| CN102750986A (en) * | 2005-07-15 | 2012-10-24 | 夏普株式会社 | Signal output circuit, shift register, output signal generating method, display device driving circuit, and display device |
| CN205647472U (en) * | 2016-05-25 | 2016-10-12 | 杭州树熊网络有限公司 | Reset circuit and electronic equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006332945A (en) * | 2005-05-25 | 2006-12-07 | Nec Electronics Corp | Semiconductor integrated circuit |
-
2016
- 2016-12-06 CN CN201611110207.XA patent/CN106847202B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1655223A (en) * | 2004-02-10 | 2005-08-17 | 夏普株式会社 | Driver circuit for display device and display device |
| CN102750986A (en) * | 2005-07-15 | 2012-10-24 | 夏普株式会社 | Signal output circuit, shift register, output signal generating method, display device driving circuit, and display device |
| KR20090083565A (en) * | 2008-01-30 | 2009-08-04 | 엘지디스플레이 주식회사 | Display device and driving method thereof |
| CN202305673U (en) * | 2011-11-01 | 2012-07-04 | 武汉理工大学 | Alternating current (AC) impedance testing device suitable for fuel cells |
| CN102710255A (en) * | 2012-06-14 | 2012-10-03 | 哈尔滨工业大学 | Clock data recovery circuit capable of resisting double frequency multiplication locking |
| CN205647472U (en) * | 2016-05-25 | 2016-10-12 | 杭州树熊网络有限公司 | Reset circuit and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106847202A (en) | 2017-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10217391B2 (en) | Shift register unit, gate driving circuit and driving method thereof, and display apparatus | |
| TWI393110B (en) | Apparatus, shift register unit, liquid crystal displaying device and method for eliminating afterimage | |
| TWI540554B (en) | Liquid crystal display device and driving method thereof | |
| CN108597470B (en) | Display device driving system and method and display device | |
| US20180182339A1 (en) | Goa driver circuit and liquid crystal display | |
| CN101656057B (en) | Timing control apparatus and display device having the same | |
| JP2006251772A (en) | Driving circuit of liquid crystal display | |
| US9111509B2 (en) | Display apparatus that generates black image signal in synchronization with the driver IC whose internal clock has the highest frequency when image/timing signals are not received | |
| KR102043534B1 (en) | GOA drive circuits and flat panel displays for flat panel displays | |
| US10504478B2 (en) | Semiconductor device having shifted operation voltages in different modes and electronic apparatus thereof | |
| US8441427B2 (en) | Gate driver having an output enable control circuit | |
| US20130050159A1 (en) | Gate driver and display device therewith | |
| US20180025696A1 (en) | Display device and data driver | |
| KR20160053070A (en) | Display device | |
| WO2012172976A1 (en) | Semiconductor integrated device, display device, and debugging method for semiconductor integrated device | |
| CN104183222A (en) | Display device | |
| CN106847202B (en) | Signal processing circuit, display device and control method thereof | |
| US20130009917A1 (en) | Source Driver Array and Driving Method, Timing Controller and Timing Controlling Method, and LCD Driving Device | |
| CN109767695B (en) | Display device and aging method thereof | |
| US9805683B2 (en) | Gate driver on array circuit for different resolutions, driving method thereof, and display device including the same | |
| CN111312135B (en) | Source driver and operation method thereof | |
| US11158224B2 (en) | Start signal generation circuit, driving method and display device | |
| US10211821B2 (en) | Clock signal transmission circuit and driving method thereof, gate driving circuit, and display device | |
| CN109949770B (en) | Data driving device of display and driver thereof | |
| US9965997B2 (en) | Sequence controlled timing controller, bridge integrated circuit, and method of driving thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: Kunshan Longteng Optronics Co., Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |