KR102043534B1 - GOA drive circuits and flat panel displays for flat panel displays - Google Patents

Abstract

In a GOA driving circuit and a flat panel display applied to a flat panel display, the GOA driving circuit includes a front stage circuit (1), a center stage circuit (2) and a rear stage circuit (3), wherein the front stage circuit ( 1), the GOA driving subunit in the center stage circuit 2 and the rear stage circuit 3 receives the first clock signal CK and the second clock signal XCK, respectively, and sequentially produces corresponding gate driving signals. An interruption period is set in the first clock signal CK and the second clock signal XCK, and an interruption is generated between the corresponding gate driving signals sequentially generated. The touch sensing operation is performed in the interval of the interruption. In this manner, GOA driving circuit scanning interruption can be realized, and the touch scanning frequency is increased.

Description

GOA drive circuits and flat panel displays for flat panel displays

TECHNICAL FIELD The present invention relates to the field of display technology, and more particularly, to a GOA driving circuit and a flat panel display applied to a flat panel display.

Gate driver on array GOA has the advantages of low production cost and slim frame design, which is already applied in liquid crystal display (LCD) field, and touch of natural interface between electronic system and user. Control sensing technology has already been widely applied in each field, in particular in-cell touch (in-cell touch), has the advantage of being thin and sensitive touch.

The prior art uses a combination of GOA drive circuitry and touch control technology, under normal circumstances, when the panel is operating finely, an advanced GOA circuit drives scanning, and after all gate line scanning is complete, touch again. Since the control signal output scanning and the GOA circuit driving scanning does not have any interruption, the frequency at which the GOA circuit drives scanning and the frequency at which the touch control signal outputs scanning match, that is, once The GOA circuit drives scanning in response to the one touch control signal outputting the scanning, which limits the touch scanning frequency.

The technical problem to be mainly solved by the present invention is to provide a GOA driving circuit and a flat panel display applied to a flat panel display, it is possible to realize the GOA driving circuit scanning interruption, and to increase the touch scanning frequency.

In order to solve the above technical problem, the technical solution used in the present invention is to provide a GOA driving circuit applied to a flat panel display,

A front stage circuit comprising a GOA drive subunit coupled to a plurality of cascading;

A central stage circuit comprising two cascading GOA driving subunits, wherein the input end of the GOA driving subunit is electrically connected to the output of the last one of the front stage circuits;

A rear stage circuit comprising a plurality of cascading GOA driving subunits, the input end of the first GOA driving subunit being electrically connected to the output end of the last GOA driving subunit of the central stage circuit; Including,

Here, the GOA driving subunits of the front stage circuit, the center stage circuit, and the rear stage circuit each receive a first clock signal and a second clock signal to sequentially produce corresponding gate driving signals, and the first clock signal. And an interruption period is set in the second clock signal to produce an interruption between the sequentially generated corresponding gate driving signals, wherein the flat panel display performs a touch sensing operation in the interval of the interruption; The interruption period is longer than one pulse signal time and shorter than the frame image time.

Here, the GOA driving subunits of each one of the front stage circuit, the center stage circuit, and the rear stage circuit are each electrically connected to one corresponding gate line, so that the corresponding gate driving signal is connected to the corresponding gate. Print sequentially on the line.

Wherein the first clock signal and the second clock signal each include a first period, the interruption period, a recovery period, and a second period;

Here, within the first period, the first clock signal and the second clock signal respectively output a pulse signal, and the polarity of the pulse signal output by the first clock signal is a pulse output by the second clock signal. Opposite to the polarity of the signal, each of the GOA driving subunits of the front stage circuit of the GOA driving circuit sequentially outputting partial gate driving signals to drive the partial gate lines of the flat panel display;

Within the interruption period, the first clock signal is held in a first logic and the second clock signal is held in a second logic, where the polarity of the first logic is opposite to the polarity of the second logic. Within the interruption period, the center stage circuit and the rear stage circuit of the GOA driving circuit stop outputting a gate driving signal;

Within the recovery period, the first clock signal is held in a second logic, the second clock signal outputs one second logic signal and one first logic signal, and the center stage of the GOA driving circuit. The circuit starts to recover the output of the gate drive signal of the next two stages;

Within the second period, the first clock signal and the second clock signal respectively output a pulse signal, and the polarity of the pulse signal output by the first clock signal is equal to that of the pulse signal output by the second clock signal. Contrary to the polarity, the rear stage circuit of the GOA driving circuit outputs the remaining gate driving signal.

Wherein the first logic is at a logic low level and the second logic is at a logic high level.

Here, the interruption period is adjusted according to actual demand.

Here, the front stage circuit, the center stage circuit, and the rear stage circuit each include an odd stage GOA driving subunit and an even stage GOA driving subunit.

Here, the odd stage GOA driving subunit and the even stage GOA driving subunit in the front stage circuit may include a first inverse transform device, a second inverse transform device, a first node and a second node, a NAND, a third inverse transform device, and a first inverse transform device. Including four inverse transform devices;

The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage and an output stage, wherein the input stage is electrically connected to an output stage of the GOA driving subunit of a previous stage;

A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;

A first node and a second node, wherein a first input end of the first node is electrically connected to an output end of the second inverse transform device, the second input end is electrically connected to an output end of the second node, An output end of the first node is electrically connected to a first input end of the second node, and a second input end of the second node is electrically connected to an input end of the second inverse transform device;

Wherein the NAND first input end of the NAND is electrically connected to the first clock signal or the second clock signal, and the second input end is electrically connected to the output end of the second node;

A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the NAND;

The fourth inverse transform device, wherein the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device corresponds to the output terminal of the GOA driving subunit of the current stage. Output one gate drive signal;

Here, a first clock control stage of the first inverse conversion device of the odd stage GOA driving subunit is electrically connected to the first clock signal, and the second clock control stage is electrically connected to the second clock signal. A first input terminal of the NAND is electrically connected to the first clock signal;

A first clock control terminal of the first inverse conversion device of the even-stage GOA driving subunit is electrically connected to the second clock signal, the second clock control terminal is electrically connected to the first clock signal, and The first input terminal of the NAND is electrically connected to the second clock control signal.

Wherein the odd stage GOA driving subunit in the central stage circuit includes a first inverse transform device, a second inverse transform device, a first node and a second node, a tri-state NAND, a third inverse transform device, and a fourth inverse transform device;

The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage, and an output stage, wherein the input stage is electrically connected to an output terminal of the GOA driving subunit of the last one of the front stage circuits. ;

A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;

A first node and a second node, wherein a first input end of the first node is electrically connected to an output end of the second inverse transform device, the second input end is electrically connected to an output end of the second node, An output end of the first node is electrically connected to a first input end of the second node, and a second input end of the second node is electrically connected to an input end of the second inverse transform device;

The tri-state NAND includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal electrically connected to the output terminal of the second node;

A third inverse transform device, wherein an input end of the third inverse transform device is electrically connected to an output end of the tri-state NAND;

The fourth inverse transform device, wherein the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device corresponds to the output terminal of the GOA driving subunit of the current stage. Output one gate drive signal;

Here, the first clock control terminal of the first inverse transform device and the second input terminal of the tri-state NAND in the odd stage GOA driving subunit are electrically connected to the first clock signal, respectively, and the second of the first inverse transform device. A clock control stage and a third input stage of the tri-state NAND are each electrically connected to the second clock signal;

The even stage GOA driving subunit of the central stage circuit includes a first inverse transform device, a second inverse transform device, a first node and a second node, a third inverse transform device, a fourth inverse transform device, and a fifth inverse transform device,

The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage and an output stage, wherein the input stage is electrically connected to an output stage of the GOA driving subunit of a previous stage;

A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;

A first node and a second node, wherein a first input end of the first node is electrically connected to an output end of the second inverse transform device, the second input end is electrically connected to an output end of the second node, An output end of the first node is electrically connected to a first input end of the second node, and a second input end of the second node is electrically connected to an input end of the second inverse transform device;

A third inverse transform device, wherein an input end of the third inverse transform device is electrically connected to an output end of the second node;

A fourth inverse transform device includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the fourth inverse transform device is electrically connected to an output terminal of the third inverse transform device;

The fifth inverse transform device, wherein the input terminal of the fifth inverse transform device is electrically connected to the output terminal of the fourth inverse transform device, and the output terminal of the fifth inverse transform device corresponds to the output terminal of the GOA driving subunit of the current stage. Output one gate drive signal;

Here, the first clock control terminal of the first inverse conversion device and the second input terminal of the fourth inverse conversion device of the even-stage GOA driving subunit are electrically connected to the second clock signal, respectively, Two clock control stages are electrically connected to the first clock signal.

Here, the odd stage GOA driving subunit and the even stage GOA driving subunit in the rear stage circuit are respectively a first inverse transform device, a second inverse transform device, a first node and a second node, a NAND, a third inverse transform device, and a first inverse transform device. Including 4 inverse converters,

The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage, and an output stage, wherein the input stage is electrically connected to an output terminal of the GOA driving subunit of the last one of the front stage circuits. ;

A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;

A first node and a second node, wherein a first input end of the first node is electrically connected to an output end of the second inverse transform device, the second input end is electrically connected to an output end of the second node, An output end of the first node is electrically connected to a first input end of the second node, and a second input end of the second node is electrically connected to an input end of the second inverse transform device;

Wherein the NAND first input end of the NAND is electrically connected to the first clock signal or the second clock signal, and the second input end is electrically connected to the output end of the second node;

A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the NAND;

The fourth inverse transform device, wherein the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device corresponds to the output terminal of the GOA driving subunit of the current stage. Output one gate drive signal;

Here, a first clock control stage of the first inverse conversion device of the odd stage GOA driving subunit is electrically connected to the first clock signal, and the second clock control stage is electrically connected to the second clock signal. A first input terminal of the NAND is electrically connected to the first clock signal;

A first clock control terminal of the first inverse conversion device of the even-stage GOA driving subunit is electrically connected to the second clock signal, the second clock control terminal is electrically connected to the first clock signal, and The first input terminal of the NAND is electrically connected to the second clock control signal.

In order to solve the above technical problem, another technical solution used in the present invention is to provide a GOA driving circuit applied to a flat panel display,

A front stage circuit comprising a GOA drive subunit coupled to a plurality of cascading;

A central stage circuit comprising two cascading GOA driving subunits, wherein the input end of the GOA driving subunit is electrically connected to the output of the last one of the front stage circuits;

A rear stage circuit comprising a plurality of cascading GOA driving subunits, the input end of the first GOA driving subunit being electrically connected to the output end of the last GOA driving subunit of the central stage circuit; Including,

Here, the GOA driving subunits of the front stage circuit, the center stage circuit, and the rear stage circuit each receive a first clock signal and a second clock signal to sequentially produce corresponding gate driving signals, and the first clock signal. And an interruption period is set in the second clock signal to generate an interruption between the sequentially generated gate driving signals, and the flat panel display performs a touch sensing operation in the interruption interval.

Here, the GOA driving subunits of each one of the front stage circuit, the center stage circuit, and the rear stage circuit are each electrically connected to one corresponding gate line, so that the corresponding gate driving signal is connected to the corresponding gate. Print sequentially on the line.

Wherein the first clock signal and the second clock signal each include a first period, the interruption period, a recovery period, and a second period;

Here, within the first period, the first clock signal and the second clock signal respectively output a pulse signal, and the polarity of the pulse signal output by the first clock signal is a pulse output by the second clock signal. Opposite to the polarity of the signal, each of the GOA driving subunits of the front stage circuit of the GOA driving circuit sequentially outputting partial gate driving signals to drive the partial gate lines of the flat panel display;

Within the interruption period, the first clock signal is held in a first logic and the second clock signal is held in a second logic, where the polarity of the first logic is opposite to the polarity of the second logic. Within the interruption period, the center stage circuit and the rear stage circuit of the GOA driving circuit stop outputting a gate driving signal;

Within the recovery period, the first clock signal is held in a second logic, the second clock signal outputs one second logic signal and one first logic signal, and the center stage of the GOA driving circuit. The circuit starts to recover the output of the gate drive signal of the next two stages;

Within the second period, the first clock signal and the second clock signal respectively output a pulse signal, and the polarity of the pulse signal output by the first clock signal is equal to that of the pulse signal output by the second clock signal. Contrary to the polarity, the rear stage circuit of the GOA driving circuit outputs the remaining gate driving signal.

Wherein the first logic is at a logic low level and the second logic is at a logic high level.

Here, the interruption period is adjusted according to actual demand.

Here, the front stage circuit, the center stage circuit, and the rear stage circuit each include an odd stage GOA driving subunit and an even stage GOA driving subunit.

Here, the odd stage GOA driving subunit and the even stage GOA driving subunit in the front stage circuit may include a first inverse transform device, a second inverse transform device, a first node and a second node, a NAND, a third inverse transform device, and a first inverse transform device. Including 4 inverse converters,

The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage and an output stage, wherein the input stage is electrically connected to an output stage of the GOA driving subunit of a previous stage;

A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;

A first node and a second node, wherein a first input end of the first node is electrically connected to an output end of the second inverse transform device, the second input end is electrically connected to an output end of the second node, An output end of the first node is electrically connected to a first input end of the second node, and a second input end of the second node is electrically connected to an input end of the second inverse transform device;

Wherein the NAND first input end of the NAND is electrically connected to the first clock signal or the second clock signal, and the second input end is electrically connected to the output end of the second node;

A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the NAND;

The fourth inverse transform device, wherein the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device corresponds to the output terminal of the GOA driving subunit of the current stage. Output one gate drive signal;

Here, a first clock control stage of the first inverse conversion device of the odd stage GOA driving subunit is electrically connected to the first clock signal, and the second clock control stage is electrically connected to the second clock signal. A first input terminal of the NAND is electrically connected to the first clock signal;

A first clock control terminal of the first inverse conversion device of the even-stage GOA driving subunit is electrically connected to the second clock signal, the second clock control terminal is electrically connected to the first clock signal, and The first input terminal of the NAND is electrically connected to the second clock control signal.

Here, the odd stage GOA driving subunit in the central stage circuit includes a first inverse transform device, a second inverse transform device, a first node and a second node, a tri-state NAND, a third inverse transform device, and a fourth inverse transform device.

The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage, and an output stage, wherein the input stage is electrically connected to an output terminal of the GOA driving subunit of the last one of the front stage circuits. ;

A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;

A first node and a second node, wherein a first input end of the first node is electrically connected to an output end of the second inverse transform device, the second input end is electrically connected to an output end of the second node, An output end of the first node is electrically connected to a first input end of the second node, and a second input end of the second node is electrically connected to an input end of the second inverse transform device;

The tri-state NAND includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal electrically connected to the output terminal of the second node;

A third inverse transform device, wherein an input end of the third inverse transform device is electrically connected to an output end of the tri-state NAND;

The fourth inverse transform device, wherein the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device corresponds to the output terminal of the GOA driving subunit of the current stage. Output one gate drive signal;

Here, the first clock control terminal of the first inverse transform device and the second input terminal of the tri-state NAND in the odd stage GOA driving subunit are electrically connected to the first clock signal, respectively, and the second of the first inverse transform device. A clock control stage and a third input stage of the tri-state NAND are each electrically connected to the second clock signal;

The even stage GOA driving subunit of the central stage circuit includes a first inverse transform device, a second inverse transform device, a first node and a second node, a third inverse transform device, a fourth inverse transform device, and a fifth inverse transform device,

The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage and an output stage, wherein the input stage is electrically connected to an output stage of the GOA driving subunit of a previous stage;

A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;

A first node and a second node, wherein a first input end of the first node is electrically connected to an output end of the second inverse transform device, the second input end is electrically connected to an output end of the second node, An output end of the first node is electrically connected to a first input end of the second node, and a second input end of the second node is electrically connected to an input end of the second inverse transform device;

A third inverse transform device, wherein an input end of the third inverse transform device is electrically connected to an output end of the second node;

A fourth inverse transform device includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the fourth inverse transform device is electrically connected to an output terminal of the third inverse transform device;

The fifth inverse transform device, wherein the input terminal of the fifth inverse transform device is electrically connected to the output terminal of the fourth inverse transform device, and the output terminal of the fifth inverse transform device corresponds to the output terminal of the GOA driving subunit of the current stage. Output one gate drive signal;

Here, the first clock control terminal of the first inverse conversion device and the second input terminal of the fourth inverse conversion device of the even-stage GOA driving subunit are electrically connected to the second clock signal, respectively, Two clock control stages are electrically connected to the first clock signal.

Here, the odd stage GOA driving subunit and the even stage GOA driving subunit in the rear stage circuit are respectively a first inverse transform device, a second inverse transform device, a first node and a second node, a NAND, a third inverse transform device, and a first inverse transform device. Including 4 inverse converters,

The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage, and an output stage, wherein the input stage is electrically connected to an output terminal of the GOA driving subunit of the last one of the front stage circuits. ;

A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;

A first node and a second node, wherein a first input end of the first node is electrically connected to an output end of the second inverse transform device, the second input end is electrically connected to an output end of the second node, An output end of the first node is electrically connected to a first input end of the second node, and a second input end of the second node is electrically connected to an input end of the second inverse transform device;

Wherein the NAND first input end of the NAND is electrically connected to the first clock signal or the second clock signal, and the second input end is electrically connected to the output end of the second node;

A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the NAND;

The fourth inverse transform device, wherein the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device corresponds to the output terminal of the GOA driving subunit of the current stage. Output one gate drive signal;

Here, a first clock control stage of the first inverse conversion device of the odd stage GOA driving subunit is electrically connected to the first clock signal, and the second clock control stage is electrically connected to the second clock signal. A first input terminal of the NAND is electrically connected to the first clock signal;

A first clock control terminal of the first inverse conversion device of the even-stage GOA driving subunit is electrically connected to the second clock signal, the second clock control terminal is electrically connected to the first clock signal, and The first input terminal of the NAND is electrically connected to the second clock control signal.

In order to solve the above technical problem, another technical solution used in the present invention is to provide a flat panel display, and includes the GOA driving circuit.

The beneficial effects of the present invention are as follows. Distinguished from the context of the prior art, the GOA driving circuit applied to the flat panel display of the present invention includes a front stage circuit, a center stage circuit and a rear stage circuit which are sequentially connected, and each of the first clock signal and the second clock signal, respectively. By providing a signal to the front stage circuit, the center stage circuit and the rear stage circuit to sequentially produce the corresponding gate drive signal, the present invention sets the interruption period of the first clock signal and the second clock signal When the first clock signal and the second clock signal are scanned to reach an interruption period, the GOA driving circuit generates an interruption from the corresponding gate driving signals sequentially generated, and after the interruption period, GOA drive circuitry recovers to produce the corresponding gate drive signal, and within an interruption period The flat panel display performs a touch sensing operation, thereby performing a touch sensing operation while the Kate line drives the scanning, and does not need to wait for the gate line to finish scanning driving and proceed with the touch sensing operation. Increased, and realize multi-touch.

1 is a structural diagram of a GOA driving circuit embodiment applied to a flat panel display of the present invention.
2 is a circuit diagram of an odd stage GOA driving subunit among front stage circuits of an embodiment of the present invention.
3 is a circuit diagram of an even stage GOA driving subunit among front stage circuits of an embodiment of the present invention.
4 is a circuit diagram of an odd stage GOA driving subunit among the center stage circuits of the embodiment of the present invention.
5 is a circuit diagram of an even stage GOA driving subunit among the center stage circuits of the embodiment of the present invention.
6 is a circuit diagram of an odd stage GOA driving subunit among the rear stage circuits of the embodiment of the present invention.
7 is a circuit diagram of an even stage GOA driving subunit among the rear stage circuits of the embodiment of the present invention.
8 is an output sequence state diagram of the GOA driving circuit of the embodiment of the present invention.

An embodiment of the present invention provides a GOA driving circuit applied to a flat panel display, the GOA driving circuit is integrated in the array substrate, to provide a drive signal to the gate line, as shown in Figure 1, The GOA driving circuit includes a front stage circuit 1, a center stage circuit 2 and a rear stage circuit 3, which are sequentially electrically connected, and the front stage circuit 1 has a plurality of cascading GOA drives. A sub unit; The center stage circuit 2 comprises two cascading GOA drive subunits, wherein the input of the previous GOA drive subunit in the center stage circuit 2 is the last one of the front stage circuits 1. Is electrically connected to an output of a GOA driven subunit of the apparatus; The rear stage circuit 3 comprises a number of cascading GOA driving sub units, wherein the input of the first GOA driving sub unit of the rear stage circuit 3 is the last GOA driving sub of the center stage circuit 2. Is electrically connected to the output of the unit; The cascading connection here refers to a serial connection, ie the output of the previous GOA driving subunit of the plurality of GOA driving subunits is connected to the input of the last GOA driving subunit, and the front stage circuit 1 and the rear stage circuit (3) includes two or more GOA driving subunits each, and the GOA driving subunit of the embodiment of the present invention is realized through a shift register.

Here, the GOA driving subunits of the front stage circuit 1, the center stage circuit 2, and the rear stage circuit 3 receive the first clock signal and the second clock signal, respectively, and sequentially generate corresponding gate driving signals. When the gate line is connected to the GOA driving subunit, the gate driving signal can be provided to the gate line through the GOA driving subunit, and an interruption period is set for the first clock signal and the second clock signal, Interruption is generated between the generated corresponding gate driving signals, so that the flat panel display performs a touch sensing operation within the interval of interruption. When the first clock signal and the second clock signal scan the interruption period, the signal of any of the GOA driving subunits of the GOA driving circuit is interrupted, that is, does not produce a signal, and the interruption is a GOA driving circuit. May occur in any one GOA drive subunit other than the first and the last one of which is to provide a drive signal only to the gate line of the GOA drive circuit, and the flat panel display may proceed with touch sensing operation, and interruption. After a period, the GOA drive subunit recovers the signal and continues to provide a drive signal to the gate line. In another embodiment of the present invention, two or more interruption periods may be set for the first clock signal and the second clock signal.

Distinguished from the prior art, the GOA driving circuit applied to the flat panel display of the embodiment of the present invention includes a front stage circuit 1, a center stage circuit 2 and a rear stage circuit 3, which are sequentially connected, respectively. The signal is provided to the front stage circuit 1, the center stage circuit 2 and the rear stage circuit 3 via the first clock signal and the second clock signal so as to sequentially produce the corresponding gate driving signal. According to the embodiment of the present invention, when an interruption period is set for the first clock signal and the second clock signal, and the first clock signal and the second clock signal are scanned to reach the interruption period, the corresponding GOA driving circuit generates sequentially. Interrupts are generated from one gate drive signal, and after an interruption period, the GOA drive circuit recovers to produce the corresponding gate drive signal and interrupts Within a period, the flat panel display performs a touch sensing operation, thereby performing a touch sensing operation while the Kate line drives the scanning, and thus does not need to wait for all the gate lines to finish scanning driving, thereby performing a touch sensing operation. The frequency of operation is increased, and multi-touch is realized.

Here, as shown in FIG. 1, the GOA driving subunits of each stage of the front stage circuit 1, the center stage circuit 2 and the rear stage circuit 3 are each electrically connected to one corresponding gate line. Are sequentially connected to the corresponding gate line.

The output stages of the GOA driving subunit, which are sequentially connected among the front stage circuit, the center stage circuit, and the rear stage circuit, are sequentially connected to a plurality of sequentially adjacent gate lines, respectively. For example, the output stage of one GOA driving subunit here. When connected to this gate line Gn, the output terminal of the previous GOA driving subunit is connected to the gate line Gn-1, and the output terminal of the last GOA driving subunit is connected to the gate line Gn + 1. ; When the first clock signal and the second clock signal are scanned in the interruption period, the signal of the GOA driving circuit may be interrupted. For example, the interruption may be performed by driving the GOA to which the output terminal and the gate line Gn are connected. In the interruption period, that is, within the interruption period, the GOA driving subunit does not output the gate driving signal to the gate line Gn. At this time, the touch sensing operation may be performed, and after the interruption period, The GOA driving subunit recovers to output a gate driving signal to the gate line Gn, and the signal is transmitted to the last GOA driving subunit connected to the output terminal, so that the last GOA driving subunit is connected to the gate line Gn + 1 Outputs the gate drive signal to the GOA drive circuit to restore the drive signal scanning.

Here, the first clock signal and the second clock signal each include a first period, an interruption period, a recovery period, and a second period.

Here, within the first period, the first clock signal and the second clock signal output pulse signals, respectively, and the polarity of the pulse signal output by the first clock signal is opposite to the pulse signal output by the second clock signal. The GOA driving subunit of the front stage circuit of the GOA driving circuit sequentially outputs partial gate driving signals to drive partial gate lines of the flat panel display; That is, within the first period, the GOA driving subunit in the front stage circuit outputs the gate driving signal to the gate line connected thereto.

Within the interruption period, the first clock signal is maintained in the first logic and the second clock signal is maintained in the second logic, where the polarity of the first logic is opposite to the polarity of the second logic and within the interruption period. The center stage circuit and the rear stage circuit in the GOA driving circuit stop the output of the gate driving signal; That is, during the interruption period, the GOA driving subunit output terminal of the center stage circuit does not output a signal and does not output the gate driving signal to the gate line connected thereto, so within the interruption period, the gate line drives the interruption. Instead, the touch control signal scanning can proceed; The length of the interruption period of the embodiment of the present invention can be adjusted according to actual demand, and is generally longer than one pulse signal time and shorter than the frame image time.

Within the recovery period, the first clock signal is held in the second logic, the second clock signal outputs one second logic signal and one first logic signal, the center stage circuit of the GOA driving circuit being the next two stages. Recovering the output of the gate drive signal of; Within the recovery period, the GOA driving subunit in the center stage circuit recovers the gate line connected thereto to output the gate driving signal, i.e., after the touch control signal scanning is finished, the GOA driving circuit continues the unfinished gate line. Proceed with driving signal scanning.

Within the second period, the first clock signal and the second clock signal output pulse signals, respectively, and the polarity of the pulse signal output by the first clock signal is opposite in polarity to the pulse signal output by the second clock signal. The rear stage circuit in the driving circuit outputs the remaining gate driving signal to complete the gate line driving signal scanning.

An embodiment of the present invention divides the first clock signal and the second clock signal into several parts of a first period, an interruption period, a recovery period, and a second period, and is also installed in the first period, and is provided on the gate line as a front stage circuit. Outputs a drive signal, and when the first clock signal and the second clock signal reach the interruption period, the drive signal is transmitted to the center stage circuit, and in the interruption period, the center stage circuit does not output the signal, This terminates the transmission of the drive signal to the gate line, so that the touch control signal scanning can proceed in the interruption period, and in the recovery period, the center stage circuit also recovers the transmission of the drive signal to the gate line, and the second period. In this case, the driving signal is transmitted to the rear stage circuit, and in the second period, the rear stage circuit is connected to the gate. A drive signal is output to the output.

Here, the first logic is at a logic low level and the second logic is at a logic high level.

2 to 8, the front stage circuit, the center stage circuit and the rear stage circuit each include one odd stage GOA driving sub unit and one even stage GOA driving sub unit connected to each other; That is, the GOA driving circuit of the embodiment of the present invention includes six GOA driving subunits, and drive signals to six gate lines Gn, Gn + 1, Gn + 2, Gn + 3, Gn + 4, and Gn + 5. Can be provided.

2 and 3, the odd stage GOA driving subunit and the even stage GOA driving subunit in the front stage circuit have the same structure, and each includes the following members.

The first inverse converters 11 and 21 comprise an input stage, a first clock control stage, a second clock control stage and an output stage, wherein the input stage is electrically connected to the output stage of the GOA driving subunit of the previous stage, A signal input of the GOA driving subunit of the stage; In the embodiment of the present invention, the input terminal of the first inverse converter 11 of the odd stage GOA driving subunit of the front stage circuit is connected to the start signal of the GOA driving circuit, and of the even stage GOA driving subunit of the front stage circuit. The input end of the first inverse transform device 21 is connected to the output of the fourth inverse transform device 17 of the odd stage GOA driving subunit of the front stage circuit.

The second inverse transform device 12, 22, wherein the input end of the second inverse transform device 12, 22 is electrically connected to the output terminal of the first inverse transform device 11, 21.

The first node 13, 23 and the second node 14, 24, wherein the first input end of the first node 13, 23 is electrically connected to the output end of the second inverse transform device 12, 22. The second input terminal is electrically connected to the output terminal of the second node 14, 24, and the output terminal of the first node 13, 23 is electrically connected to the first input terminal of the second node 14, 24. The second input end of the second node 14, 24 is electrically connected to the input end of the second inverse transform device 12, 22.

The NAND 15, 25, wherein the first input terminal of the NAND 15, 25 is electrically connected to the first clock signal CK or the second clock signal XCK, and the second input terminal is a second node. It is electrically connected to the output terminals of (14, 24).

The third inverse transform device 16, 26, wherein the input end of the third inverse transform device 16, 26 is electrically connected to the output end of the NAND 15, 25.

The fourth inverse transform device (17, 27), wherein the input terminal of the fourth inverse transform device (17, 27) is electrically connected to the output terminal of the third inverse transform device (16, 26), the fourth inverse transform device (17, 27) Is an output terminal of the GOA driving subunit of the current stage, and outputs a corresponding gate driving signal; The output terminal of the fourth inverse transform device 17 is connected to the gate line Gn, and the output terminal of the fourth inverse transform device 27 is connected to the gate line Gn + 1.

Here, the first clock control terminal of the first inverse converter 11 of the odd stage GOA driving subunit in the front stage circuit is electrically connected to the first clock signal CK, and the second clock control terminal is connected to the second clock. It is electrically connected to the signal XCK, and the first input terminal of the NAND 15 is electrically connected to the first clock signal CK.

The first clock control terminal of the first inverse conversion device 21 of the even-stage GOA driving subunit in the front stage circuit is electrically connected to the second clock signal XCK, and the second clock control terminal is connected to the first clock signal ( It is electrically connected to CK, and the first input terminal of the NAND 25 is electrically connected to the second clock control signal XCK.

An output terminal of the fourth inverse transform device 17 of the odd stage GOA driving subunit in the front stage circuit of the embodiment of the present invention is connected to an input terminal of the first inverse conversion device 21 of the even stage GOA driving subunit in the front stage circuit.

With this circuit design, within the first period, the first and second clock signals having opposite polarity of pulse signal polarities are output so that the front stage circuit outputs a drive signal to the corresponding gate line.

The odd stage GOA driving subunit in the center stage circuit and the even stage GOA driving sub unit are slightly different in structure, as shown in FIG. 4, the odd stage GOA driving sub unit in the central stage circuit includes the following members. .

The first inverse conversion device 31 comprises an input stage, a first clock control stage, a second clock control stage and an output stage, wherein the input stage is electrically connected to the output terminal of the last one GOA driving subunit of the front stage circuit. A signal input of the GOA driving subunit of the current stage; In the embodiment of the present invention, the input terminal of the first inverse converter 31 of the odd stage GOA driving subunit in the center stage circuit is the output terminal of the fourth inverse converter 27 of the even stage GOA driving subunit in the front stage circuit. Connected.

In the second inverse transform device 32, the input terminal of the second inverse transform device 32 is electrically connected to the output terminal of the first inverse transform device 31.

The first node 33 and the second node 34, wherein the first input of the first node 33 is electrically connected to the output of the second inverse transform device 32, the second input of which is connected to the second node. Is electrically connected to an output terminal of the node, an output terminal of the first node 33 is electrically connected to a first input terminal of the second node 34, and a second input terminal of the second node 34 is connected to a second inverse transform device ( 32 is electrically connected to the input terminal.

The tri-state NAND 35 includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal being electrically connected to the output terminal of the second node 34.

The third inverse transform device 36 is wherein the input end of the third inverse transform device 36 is electrically connected to the output end of the tri-state NAND 35.

The fourth inverse transform device 37 is wherein the input terminal of the fourth inverse transform device 37 is electrically connected to the output terminal of the third inverse transform device 36, and the output terminal of the fourth inverse transform device 37 is the GOA of the current stage. As an output terminal of the driving sub unit, the driving unit is connected to the gate line Gn + 2 and outputs a corresponding gate driving signal.

Here, the first clock control terminal of the first inverse transform device 31 of the odd stage GOA driving subunit and the second input terminal of the tri-state NAND 35 are electrically connected to the first clock signal CK, respectively, and the first inverse transform is performed. The second clock control terminal of the device 31 and the third input terminal of the tri-state NAND 35 are each electrically connected to the second clock signal XCK.

As shown in Fig. 5, the even stage GOA driving subunit in the center stage circuit includes the following members.

The first inverse transform device 41 comprises an input stage, a first clock control stage, a second clock control stage and an output stage, wherein the input stage is electrically connected to the output stage of the GOA driving subunit of the previous stage, that is, the central stage. It is connected to the output terminal of the fourth inverse converter 37 in the circuit odd stage GOA driving subunit.

In the second inverse transform device 42, the input terminal of the second inverse transform device 42 is electrically connected to the output terminal of the first inverse transform device 41.

The first node 43 and the second node 44 are wherein the first input end of the first node 43 is electrically connected to the output end of the second inverse transform device 42, and the second input end is connected to the second node. Is electrically connected to an output terminal of the node 44, an output terminal of the first node 43 is electrically connected to a first input terminal of the second node 44, and a second input terminal of the second node 44 is connected to the second terminal 44. It is electrically connected to an input terminal of the inverse transform device 42.

The third inverse transform device 45 is wherein the input end of the third inverse transform device 45 is electrically connected to the output end of the second node 44.

The fourth inverse transform device 46 includes a first input terminal, a second input terminal, and an output terminal, and the first input terminal of the fourth inverse transform device 46 is electrically connected to the output terminal of the third inverse transform device 45.

The fifth inverse transform device 47 is wherein the input terminal of the fifth inverse transform device 47 is electrically connected to the output terminal of the fourth inverse transform device 46, and the output terminal of the fifth inverse transform device 47 is the GOA of the current stage. As an output terminal of the driving subunit, the driving line unit is connected to the gate line Gn + 3 and outputs a corresponding gate driving signal.

Here, the first clock control terminal of the first inverse conversion device 41 and the second input terminal of the fourth inverse conversion device 46 of the even-stage GOA driving subunit are electrically connected to the second clock signal XCK, respectively. The second clock control terminal of the inverse conversion device 41 is electrically connected to the first clock signal CK.

With this circuit design, within the interruption period, the first clock signal and the second clock signal held in the first and second logics having opposite polarities, respectively, are transmitted by an odd stage GOA driving subunit in the center stage circuit. When the gate line drive signal scanning is interrupted and the recovery period is reached, the first clock signal outputs one second logic, and the second clock signal outputs one second logic. The odd stage GOA driving subunit in the center stage circuit recovers signal output, and when the first clock signal continues to output one second logic and the second clock signal outputs one first logic, The even-stage GOA driving subunit in the stage circuit outputs a signal, thereby recovering the GOA driving circuit from transmitting a driving signal to the gate line.

6 and 7, the odd stage GOA driving subunit and the even stage GOA driving subunit in the rear stage circuit have the same structure, and each includes the following members.

The first inverse converter 61, 71 comprises an input stage, a first clock control stage, a second clock control stage and an output stage, wherein the input stage is electrically connected to the output stage of the GOA driving subunit of the previous stage, A signal input of the GOA driving subunit of the stage; In the embodiment of the present invention, the input terminal of the first inverse converter 61 of the odd stage GOA driving subunit of the rear stage circuit is connected to the output terminal of the fifth inverse converter 47 of the even stage GOA driving subunit of the center stage circuit. The input terminal of the first inverse conversion device 71 of the even-stage GOA driving subunit in the rear stage circuit, which is electrically connected and is a signal input terminal of the odd stage GOA driving subunit in the rear stage circuit, is the odd stage GOA driving sub of the rear stage circuit. It is connected to the output terminal of the fourth inverse transform device 67 of the unit.

The second inverse transform devices 62, 72, wherein the input terminals of the second inverse transform devices 62, 72 are electrically connected to the output terminals of the first inverse transform devices 61, 71.

The first node 63, 73 and the second node 64, 74, wherein the first input of the first node 63, 73 is electrically connected to the output of the second inverse transform device 62, 72. The second input terminal is electrically connected to the output terminal of the second node 64, 74, and the output terminal of the first node 63, 73 is electrically connected to the first input terminal of the second node 64, 74. The second input end of the second node 64, 74 is electrically connected to the input end of the second inverse transform device 62, 72.

NAND 65, 75, wherein the first input terminal of NAND 65, 75 is electrically connected to a first clock signal CK or a second clock signal XCK, the second input terminal of which is a second node. Is electrically connected to the output terminals of (64, 74).

The third inverse transform devices 66, 76, wherein the input terminals of the third inverse transform devices 66, 76 are electrically connected to the output terminals of the NAND 65, 75.

The fourth inverse transform device (67, 77), wherein the input terminal of the fourth inverse transform device (67, 77) is electrically connected to the output terminal of the third inverse transform device (66, 76), the fourth inverse transform device (67, 77) Is an output terminal of the GOA driving subunit of the current stage, and outputs a corresponding gate driving signal; The output terminal of the fourth inverse transform device 67 is connected to the gate line Gn + 4, and the output terminal of the fourth inverse transform device 77 is connected to the gate line Gn + 5.

Here, the first clock control terminal of the first inverse converter 61 of the odd stage GOA driving subunit is electrically connected to the first clock signal CK, and the second clock control terminal is the second clock signal XCK. Is electrically connected to the first input terminal of the NAND 65, and is electrically connected to the first clock signal CK.

The first clock control terminal of the first inverse conversion device 71 of the even-stage GOA driving subunit is electrically connected to the second clock signal XCK, and the second clock control terminal is electrically connected to the first clock signal CK. The first input terminal of the NAND 75 is electrically connected to the second clock control signal XCK.

The circuit design allows the rear stage circuit to output a drive signal to a corresponding gate line by outputting a first clock signal and a second clock signal having opposite pulse signal polarities within a second period.

In other embodiments of the present invention, the front stage circuit may include more than two GOA drive subunits, and if the front stage circuit includes more than two GOA drive subunits, the odd numbered GOA drive subunits. The structure and the connection method of the unit are the same as the odd stage GOA drive subunit in the front stage circuit in the above embodiment, and the structure and the connection method of the even-numbered GOA drive subunit are the even stage GOA drive in the front stage circuit in the embodiment. The same as the sub unit, for example, if the front stage circuit includes five sequentially connected GOA driving sub units, the structure and connection method of the first, third and fifth GOA driving sub units are the front of the above embodiment. Same as the odd stage GOA driving subunit in the stage circuit, and the second and fourth GOA driving sub units Structure and method of connection is the same as that of the even-numbered stage driven GOA subunit of the front-stage circuit of the embodiment.

In another embodiment of the present invention, the rear stage circuit may include more than two GOA drive subunits, and if the rear stage circuit includes more than two GOA drive subunits, the odd-numbered GOA drive subunits. The structure and the connection method of the unit are the same as the odd stage GOA drive subunit in the rear stage circuit in the above embodiment, and the structure and the connection method of the even-numbered GOA drive subunit are the even stage GOA drive in the rear stage circuit in the embodiment. The same as the sub unit, for example, if the rear stage circuit includes five sequentially connected GOA driving sub units, the structure and connection scheme of the first, third, and fifth GOA driving sub units are rear in the above embodiment. Same as the odd stage GOA driving subunit in the stage circuit, and the structure of the second and fourth GOA driving subunits Results method is the same as the even-numbered stage driven GOA subunit of the rear-stage circuit of the embodiment.

Another embodiment of the present invention provides a flat panel display, wherein the flat panel display includes the GOA driving circuit in the above embodiment.

Distinguished from the prior art, the GOA driving circuit of the flat panel display of the embodiment of the present invention includes a front stage circuit, a center stage circuit and a rear stage circuit which are sequentially connected, and are respectively fronted through a first clock signal and a second clock signal. A signal is provided to the stage circuit, the center stage circuit, and the rear stage circuit so that they sequentially produce corresponding gate drive signals, and embodiments of the present invention establish an interruption period for the first clock signal and the second clock signal. When the first clock signal and the second clock signal are scanned to reach the interruption period, the GOA driving circuit generates an interruption in the corresponding gate driving signals sequentially generated, and after the interruption period, the GOA The drive circuit recovers to produce the corresponding gate drive signal and, within the interruption period, the flat panel dissipation. Ray performs a touch sensing operation, thereby performing a touch sensing operation while the Kate line drives scanning, and thus does not have to wait for all the gate lines to finish scanning driving and proceed with the touch sensing operation, thereby increasing the frequency of the touch sensing operation. Increased, realize multi-touch.

The foregoing descriptions are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, but all equivalent structures or equivalent process changes, or other related directly or indirectly, which are made using the specification and drawings of the present invention. All applications in the technical field are likewise within the scope of the patent protection of the present invention.

Claims (19)

A front stage circuit comprising a GOA drive subunit coupled to a plurality of cascading;
A central stage circuit comprising two cascading GOA driving subunits, the input of the first GOA driving subunit being electrically connected to the output of the last one of the front stage circuits;
A rear stage circuit comprising a plurality of cascading GOA driving subunits, the input end of the first GOA driving subunit being electrically connected to the output end of the last GOA driving subunit of the central stage circuit; Including,
The GOA driving subunits of the front stage circuit, the center stage circuit, and the rear stage circuit each receive a first clock signal and a second clock signal to sequentially produce corresponding gate driving signals, and the first clock signal and the first clock signal. An interruption period is set in the second clock signal to generate an interruption between the corresponding sequentially generated gate driving signals, and the flat panel display performs a touch sensing operation in the interval of the interruption; The interruption period is longer than one pulse signal time and shorter than the frame image time,
The GOA driving subunits of each one of the front stage circuit, the center stage circuit, and the rear stage circuit are each electrically connected to one corresponding gate line, such that the corresponding gate drive signal is connected to the corresponding gate line. Output sequentially,
The first clock signal and the second clock signal each include a first period, the interruption period, a recovery period, and a second period;
Within the first period, the first clock signal and the second clock signal respectively output a pulse signal, and the polarity of the pulse signal output by the first clock signal is equal to that of the pulse signal output by the second clock signal. Opposite to polarity, wherein the GOA driving subunits in the front stage circuit sequentially output partial gate driving signals to drive partial gate lines of the flat panel display;
Within the interruption period, the first clock signal is held in a first logic, the second clock signal is held in a second logic, and the polarity of the first logic is opposite to the polarity of the second logic, Within the interruption period, the center stage circuit and the rear stage circuit stop output of a gate drive signal;
Within the recovery period, the first clock signal is held in a second logic, the second clock signal outputs one second logic signal and one first logic signal, and the center stage circuit has two Start to recover the output of the gate drive signal of the stage;
Within the second period, the first clock signal and the second clock signal respectively output a pulse signal, and the polarity of the pulse signal output by the first clock signal is equal to that of the pulse signal output by the second clock signal. Opposite polarity, the rear stage circuit outputs the remaining gate drive signal GOA driving circuit applied to the flat panel display, characterized in that.
delete delete The method of claim 1,
Wherein said first logic is at a logic low level and said second logic is at a logic high level.
The method of claim 1,
GOA driving circuit applied to the flat panel display, characterized in that the interruption period is adjusted according to the actual demand.
The method of claim 1,
And the front stage circuit, the center stage circuit, and the rear stage circuit each comprise an odd stage GOA driving subunit and an even stage GOA driving subunit, respectively.
The method of claim 6,
The odd stage GOA driving subunit and the even stage GOA driving subunit in the front stage circuit are respectively a first inverse transform device, a second inverse transform device, a first node and a second node, a NAND, a third inverse transform device and a fourth inverse transform. Including devices,
The first inverse conversion device comprises an input stage, a first clock control stage, a second clock control stage and an output stage, the input stage being electrically connected to an output stage of the GOA driving subunit of a previous stage;
A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;
The first node and the second node, the first input terminal of the first node is electrically connected to the output terminal of the second inverse transform device, the second input terminal is electrically connected to the output terminal of the second node, An output terminal of one node is electrically connected to a first input terminal of the second node, and a second input terminal of the second node is electrically connected to an input terminal of the second inverse transform device;
A NAND, wherein a first input terminal of the NAND is electrically connected to the first clock signal or the second clock signal, and the second input terminal is electrically connected to an output terminal of the second node;
A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the NAND;
In the fourth inverse transform device, the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device is an output terminal of the GOA driving subunit of the current stage, Output a drive signal;
A first clock control terminal of the first inverse conversion device of the odd stage GOA driving subunit is electrically connected to the first clock signal, the second clock control terminal is electrically connected to the second clock signal, and A first input terminal of the NAND is electrically connected to the first clock signal;
A first clock control terminal of the first inverse conversion device of the even-stage GOA driving subunit is electrically connected to the second clock signal, the second clock control terminal is electrically connected to the first clock signal, and And a first input terminal of the NAND is electrically connected to the second clock control signal.
The method of claim 6,
The odd stage GOA driving subunit in the central stage circuit includes a first inverse transform device, a second inverse transform device, a first node and a second node, a tri-state NAND, a third inverse transform device, and a fourth inverse transform device,
The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage and an output stage, the input stage being electrically connected to an output stage of the GOA driving subunit of the last one of the front stage circuits;
A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;
The first node and the second node, the first input terminal of the first node is electrically connected to the output terminal of the second inverse transform device, the second input terminal is electrically connected to the output terminal of the second node, An output terminal of one node is electrically connected to a first input terminal of the second node, and a second input terminal of the second node is electrically connected to an input terminal of the second inverse transform device;
The tri-state NAND includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal electrically connected to the output terminal of the second node;
A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the tri-state NAND;
In the fourth inverse transform device, the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device is an output terminal of the GOA driving subunit of the current stage, Output a drive signal;
The first clock control terminal of the first inverse transform device and the second input terminal of the three state NAND in the odd stage GOA driving subunit are each electrically connected to the first clock signal, and the second clock control of the first inverse converter is performed. A stage and a third input terminal of the tri-state NAND are each electrically connected to the second clock signal;
The even stage GOA driving subunit of the central stage circuit includes a first inverse transform device, a second inverse transform device, a first node and a second node, a third inverse transform device, a fourth inverse transform device, and a fifth inverse transform device,
The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage and an output stage, the input stage being electrically connected to an output stage of the GOA driving subunit of a previous stage;
A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;
The first node and the second node, the first input terminal of the first node is electrically connected to the output terminal of the second inverse transform device, the second input terminal is electrically connected to the output terminal of the second node, An output terminal of one node is electrically connected to a first input terminal of the second node, and a second input terminal of the second node is electrically connected to an input terminal of the second inverse transform device;
A third inverse transform device, wherein an input of the third inverse transform device is electrically connected to an output of the second node;
A fourth inverse transform device includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the fourth inverse transform device is electrically connected to an output terminal of the third inverse transform device;
In the fifth inverse transform device, the input terminal of the fifth inverse transform device is electrically connected to the output terminal of the fourth inverse transform device, and the output terminal of the fifth inverse transform device is an output terminal of the GOA driving subunit of the current stage, Output a drive signal;
The first clock control terminal of the first inverse transform device and the second input terminal of the fourth inverse transform device of the even-stage GOA driving subunit are electrically connected to the second clock signal, respectively, and the second clock of the first inverse transform device is included. The control stage is a GOA driving circuit applied to the flat panel display, characterized in that electrically connected to the first clock signal.
The method of claim 6,
The odd stage GOA driving subunit and the even stage GOA driving subunit in the rear stage circuit are respectively a first inverse transform device, a second inverse transform device, a first node and a second node, a NAND, a third inverse transform device, and a fourth inverse transform device. Including devices,
The first inverse conversion device comprises an input stage, a first clock control stage, a second clock control stage and an output stage, the input stage being electrically connected to an output stage of the GOA driving subunit of the last one of the front stage circuits;
A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;
The first node and the second node, the first input terminal of the first node is electrically connected to the output terminal of the second inverse transform device, the second input terminal is electrically connected to the output terminal of the second node, An output terminal of one node is electrically connected to a first input terminal of the second node, and a second input terminal of the second node is electrically connected to an input terminal of the second inverse transform device;
A NAND, wherein a first input terminal of the NAND is electrically connected to the first clock signal or the second clock signal, and the second input terminal is electrically connected to an output terminal of the second node;
A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the NAND;
In the fourth inverse transform device, the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device is an output terminal of the GOA driving subunit of the current stage, Output a drive signal;
A first clock control terminal of the first inverse conversion device of the odd stage GOA driving subunit is electrically connected to the first clock signal, the second clock control terminal is electrically connected to the second clock signal, and A first input terminal of the NAND is electrically connected to the first clock signal;
A first clock control terminal of the first inverse conversion device of the even-stage GOA driving subunit is electrically connected to the second clock signal, the second clock control terminal is electrically connected to the first clock signal, and And a first input terminal of the NAND is electrically connected to the second clock control signal.
A front stage circuit comprising a GOA drive subunit coupled to a plurality of cascading;
A central stage circuit comprising two cascading GOA driving subunits, the input of the first GOA driving subunit being electrically connected to the output of the last one of the front stage circuits;
A rear stage circuit comprising a plurality of cascading GOA driving subunits, the input end of the first GOA driving subunit being electrically connected to the output end of the last GOA driving subunit of the central stage circuit; Including,
The GOA driving subunits of the front stage circuit, the center stage circuit, and the rear stage circuit each receive a first clock signal and a second clock signal to sequentially produce corresponding gate driving signals, and the first clock signal and the first clock signal. An interruption period is set in the second clock signal to generate an interruption between the sequentially generated gate driving signals, and the flat panel display performs a touch sensing operation in the interval of the interruption.
The GOA driving subunits of each one of the front stage circuit, the center stage circuit, and the rear stage circuit are each electrically connected to one corresponding gate line, such that the corresponding gate drive signal is connected to the corresponding gate line. Output sequentially,
The first clock signal and the second clock signal each include a first period, the interruption period, a recovery period, and a second period;
Within the first period, the first clock signal and the second clock signal respectively output a pulse signal, and the polarity of the pulse signal output by the first clock signal is equal to that of the pulse signal output by the second clock signal. Opposite to polarity, wherein the GOA driving subunits in the front stage circuit sequentially output partial gate driving signals to drive partial gate lines of the flat panel display;
Within the interruption period, the first clock signal is held in a first logic, the second clock signal is held in a second logic, and the polarity of the first logic is opposite to the polarity of the second logic, Within the interruption period, the center stage circuit and the rear stage circuit stop output of a gate drive signal;
Within the recovery period, the first clock signal is held in a second logic, the second clock signal outputs one second logic signal and one first logic signal, and the center stage circuit has two Start to recover the output of the gate drive signal of the stage;
Within the second period, the first clock signal and the second clock signal respectively output a pulse signal, and the polarity of the pulse signal output by the first clock signal is equal to that of the pulse signal output by the second clock signal. Opposite polarity, the rear stage circuit outputs the remaining gate drive signal GOA driving circuit applied to the flat panel display, characterized in that.
delete delete The method of claim 10,
Wherein said first logic is at a logic low level and said second logic is at a logic high level.
The method of claim 10,
GOA driving circuit applied to the flat panel display, characterized in that the interruption period is adjusted according to the actual demand.
The method of claim 10,
And the front stage circuit, the center stage circuit, and the rear stage circuit each comprise an odd stage GOA driving subunit and an even stage GOA driving subunit, respectively.
The method of claim 15,
The odd stage GOA driving subunit and the even stage GOA driving subunit in the front stage circuit are respectively a first inverse transform device, a second inverse transform device, a first node and a second node, a NAND, a third inverse transform device, and a fourth inverse transform device. Including devices,
The first inverse conversion device comprises an input stage, a first clock control stage, a second clock control stage and an output stage, the input stage being electrically connected to an output stage of the GOA driving subunit of a previous stage;
A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;
The first node and the second node, the first input terminal of the first node is electrically connected to the output terminal of the second inverse transform device, the second input terminal is electrically connected to the output terminal of the second node, An output terminal of one node is electrically connected to a first input terminal of the second node, and a second input terminal of the second node is electrically connected to an input terminal of the second inverse transform device;
A NAND, wherein a first input terminal of the NAND is electrically connected to the first clock signal or the second clock signal, and the second input terminal is electrically connected to an output terminal of the second node;
A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the NAND;
In the fourth inverse transform device, the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device is an output terminal of the GOA driving subunit of the current stage, Output a drive signal;
A first clock control terminal of the first inverse conversion device of the odd stage GOA driving subunit is electrically connected to the first clock signal, the second clock control terminal is electrically connected to the second clock signal, and A first input terminal of the NAND is electrically connected to the first clock signal;
A first clock control terminal of the first inverse conversion device of the even-stage GOA driving subunit is electrically connected to the second clock signal, the second clock control terminal is electrically connected to the first clock signal, and And a first input terminal of the NAND is electrically connected to the second clock control signal.
The method of claim 15,
The odd stage GOA driving subunit in the central stage circuit includes a first inverse transform device, a second inverse transform device, a first node and a second node, a tri-state NAND, a third inverse transform device, and a fourth inverse transform device,
The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage and an output stage, the input stage being electrically connected to an output stage of the GOA driving subunit of the last one of the front stage circuits;
A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;
The first node and the second node, the first input terminal of the first node is electrically connected to the output terminal of the second inverse transform device, the second input terminal is electrically connected to the output terminal of the second node, An output terminal of one node is electrically connected to a first input terminal of the second node, and a second input terminal of the second node is electrically connected to an input terminal of the second inverse transform device;
The tri-state NAND includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal electrically connected to the output terminal of the second node;
A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the tri-state NAND;
In the fourth inverse transform device, the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device is an output terminal of the GOA driving subunit of the current stage, Output a drive signal;
The first clock control terminal of the first inverse transform device and the second input terminal of the three state NAND in the odd stage GOA driving subunit are each electrically connected to the first clock signal, and the second clock control of the first inverse converter is performed. A stage and a third input terminal of the tri-state NAND are each electrically connected to the second clock signal;
The even stage GOA driving subunit of the central stage circuit includes a first inverse transform device, a second inverse transform device, a first node and a second node, a third inverse transform device, a fourth inverse transform device, and a fifth inverse transform device,
The first inverse conversion device includes an input stage, a first clock control stage, a second clock control stage and an output stage, the input stage being electrically connected to an output stage of the GOA driving subunit of a previous stage;
A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;
The first node and the second node, the first input terminal of the first node is electrically connected to the output terminal of the second inverse transform device, the second input terminal is electrically connected to the output terminal of the second node, An output terminal of one node is electrically connected to a first input terminal of the second node, and a second input terminal of the second node is electrically connected to an input terminal of the second inverse transform device;
A third inverse transform device, wherein an input of the third inverse transform device is electrically connected to an output of the second node;
A fourth inverse transform device includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the fourth inverse transform device is electrically connected to an output terminal of the third inverse transform device;
In the fifth inverse transform device, the input terminal of the fifth inverse transform device is electrically connected to the output terminal of the fourth inverse transform device, and the output terminal of the fifth inverse transform device is an output terminal of the GOA driving subunit of the current stage, Output a drive signal;
The first clock control terminal of the first inverse transform device and the second input terminal of the fourth inverse transform device of the even-stage GOA driving subunit are electrically connected to the second clock signal, respectively, and the second clock of the first inverse transform device is included. The control stage is a GOA driving circuit applied to the flat panel display, characterized in that electrically connected to the first clock signal.
The method of claim 15,
The odd stage GOA driving subunit and the even stage GOA driving subunit in the rear stage circuit are respectively a first inverse transform device, a second inverse transform device, a first node and a second node, a NAND, a third inverse transform device, and a fourth inverse transform device. Including devices,
The first inverse conversion device comprises an input stage, a first clock control stage, a second clock control stage and an output stage, the input stage being electrically connected to an output stage of the GOA driving subunit of the last one of the front stage circuits;
A second inverse transform device, wherein an input of the second inverse transform device is electrically connected to an output of the first inverse transform device;
The first node and the second node, the first input terminal of the first node is electrically connected to the output terminal of the second inverse transform device, the second input terminal is electrically connected to the output terminal of the second node, An output terminal of one node is electrically connected to a first input terminal of the second node, and a second input terminal of the second node is electrically connected to an input terminal of the second inverse transform device;
A NAND, wherein a first input terminal of the NAND is electrically connected to the first clock signal or the second clock signal, and the second input terminal is electrically connected to an output terminal of the second node;
A third inverse transform device, wherein an input terminal of the third inverse transform device is electrically connected to an output terminal of the NAND;
In the fourth inverse transform device, the input terminal of the fourth inverse transform device is electrically connected to the output terminal of the third inverse transform device, and the output terminal of the fourth inverse transform device is an output terminal of the GOA driving subunit of the current stage, Output a drive signal;
A first clock control terminal of the first inverse conversion device of the odd stage GOA driving subunit is electrically connected to the first clock signal, the second clock control terminal is electrically connected to the second clock signal, and A first input terminal of the NAND is electrically connected to the first clock signal;
A first clock control terminal of the first inverse conversion device of the even-stage GOA driving subunit is electrically connected to the second clock signal, the second clock control terminal is electrically connected to the first clock signal, and And a first input terminal of the NAND is electrically connected to the second clock control signal.
19. A flat panel display comprising a GOA drive circuit according to any of claims 10 and 13-18.

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