JP2007140256A - Drive circuit, latch circuit, array substrate using the same, and image display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit capable of preventing malfunctions due to clock skews, a plurality of latch circuits connected in series and an image display apparatus that uses the latch circuits. <P>SOLUTION: The drive circuit is provided with inverter circuits 21 to 23 and latch circuits 31 to 34. The inverter circuit 21 generates a first inverted clock signal obtained by inverting a reference clock signal GCLK. The inverter circuit 22 generates a first clock signal LCLK, obtained by inverting the first inverted clock signal generated in the inverter circuit 21. The inverter circuit 23 generates a second inverted clock signal/LCLK, obtained by inverting the first clock signal LCLK generated in the inverter circuit 22. The plurality of latch circuits 31 to 34 connected in series transmit a pulse signal, in synchronism with the first clock signal LCLK and the second inverted clock signal/LCLK. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive circuit, a latch circuit, an array substrate using the same, and an image display apparatus.

  In a thin film transistor liquid crystal display device incorporating a conventional driving circuit, pixels (subpixels) arranged in a matrix, TFTs (Thin Film Transistors) provided in each pixel (subpixel), and gate lines for driving the TFTs The driver circuit and the source line driver circuit are also formed on the same substrate.

  In a thin film transistor liquid crystal display device including a driver circuit, a shift register including a plurality of latch circuits connected in series is used for a gate line driver circuit and a source line driver circuit. Conventionally, complementary clock signals whose phases are inverted from each other are input to the latch circuit constituting the shift register. However, when a clock skew occurs in the complementary clock signal, a malfunction such as data penetration occurs in the shift register.

  Next, a description will be given of a data punch-through malfunction occurring in the shift register. FIG. 25 shows a conventional gate line driving circuit. In addition, signal waveforms input to and output from the gate line driver circuit are shown in FIGS. FIG. 26A shows the case of normal operation with no clock skew, and FIG. 26B shows the case of abnormal operation with a clock skew. 26A and 26B show the waveforms of the start signal STY, the gate clock signal (CLKY, / CLKY), the outputs Q1 to Q4 of the latch circuits 101 to 104, and the output signals to the gate lines GL1 to GL3, respectively. ing.

  In FIG. 26B, there is a period T1 in which the complementary gate clock signals (CLKY, / CLKY) are both at the “H” level due to clock skew. In this period T1, when the start signal STY is at the “H” level, the N-channel transistor (not shown) constituting the transfer inverter 111 in the first-stage latch circuit 101 shown in FIG. Both the N-channel transistors (not shown) constituting the transfer inverter 113 in the latch circuit 102 are turned on. Therefore, a malfunction called a data punch-out phenomenon in which the “H” level of the start signal STY propagates to the latch circuit several stages ahead occurs. Here, a period Td shown in FIG. 26B indicates a signal propagation delay time from switching of the gate clock signal (CLKY, / CLKY) or switching of the input signal to switching of the outputs Q1 and Q2.

  The data punch-out phenomenon due to clock skew will be described in more detail with reference to FIG. FIG. 28 is a circuit diagram showing the latch circuits 101 and 102 shown in FIG. 27 in more detail. In the circuit shown in FIG. 28, when the CLKY signal is switched from “L” to “H” when the start signal STY is “H” level, the N-channel transistors MN10 and MN11 are turned on and the node A is set to “L”. The node B is pulled up to “H” after Td from the switching of CLKY.

  At this time, the / CLKY signal must be switched from “H” to “L” at the same time as shown in FIG. 26A. However, due to clock skew, the / CLKY signal has a period T1 (as shown in FIG. 26B). The state remains “H” for T1> Td). For this reason, the N-channel transistors MN12 and MN13 of the second-stage latch circuit 102 remain in the ON state during this period, so that the “H” level of the start signal STY penetrates to the next-stage latch circuit. Thus, Q2 in FIG. 26B (node B in FIG. 28) becomes “H”, and after Td, Q2 becomes “H”. Further, the N-channel transistor constituting the transfer inverter of the latch circuit 103 is also turned on because its gate signal is CLKY, and after T2 after Q2 becomes “H”, Q3 becomes “H”. In FIGS. 26A and 26B, the delay time from Q1, Q2, Q3, Q4 to GL1, GL2, GL3, GL4 is omitted.

  Therefore, in order to reduce the clock skew, in Patent Document 1, the global clock signal output from the buffer is supplied to the normal phase / reverse phase 2 via the first inverter and the second inverter provided for each stage of the latch circuit. The clock skew is reduced by generating two clock signals.

JP 2001-134247 A

  However, in the case of the shift register described in Patent Document 1, the number of stages of gate lines to which a global clock signal is connected is several hundreds, and hundreds of inverters are also connected. For this reason, when a polycrystalline silicon thin film transistor having particularly poor characteristics and large variations is used for a buffer, an inverter, or the like, the waveform of the global clock signal may become large if variations occur in the poor characteristics.

  Therefore, even if a clock signal is generated from a global clock signal having a large waveform round via an inverter, the rounding of the waveform cannot be sufficiently reduced, and the clock skew may not be reduced. On the other hand, in order to reduce the rounding of the waveform of the global clock signal, it is conceivable to increase the buffer size of the circuit that generates the global clock signal. However, even in this case, if the transistor characteristics vary, the power consumption of the circuit becomes very large.

  Accordingly, an object of the present invention is to provide a drive circuit, a latch circuit, an array substrate using the same, and an image display device that can prevent malfunction due to clock skew.

  According to another aspect of the present invention, a first inverter circuit that inverts a reference clock signal to generate a first inverted clock signal, and inverts a first inverted clock signal generated by the first inverter circuit to generate a first clock signal. The second inverter circuit, the third inverter circuit that inverts the first clock signal generated by the second inverter circuit to generate the second inverted clock signal, and the first clock signal and the second inverted clock signal. A plurality of latch circuits connected in series for transmitting a pulse signal.

  The drive circuit according to the present invention includes a first inverter circuit that inverts a reference clock signal to generate a first inverted clock signal, a second inverter circuit, a third inverter circuit, and a latch circuit. There is an effect that it is possible to reduce the error and prevent malfunction due to the clock skew. In addition, an image display device having a driving circuit including a latch circuit and a driving circuit described in the present invention can also prevent malfunction due to clock skew.

(Embodiment 1)
FIG. 1 shows a block diagram of a thin film transistor liquid crystal display device (hereinafter also simply referred to as a liquid crystal display device) which is an image display device incorporating a driving circuit according to the present embodiment. The liquid crystal display device shown in FIG. 1 shows a liquid crystal display unit 1 in which pixels (sub-pixels) are arranged in a matrix (not shown), a gate line driving circuit 2 and a source line driving circuit 3 for driving each pixel. ing. Further, a circuit diagram of the liquid crystal display unit 1 is shown in FIG. In the liquid crystal display unit 1 shown in FIG. 2, a transistor (TFT 11) for driving individual pixels (sub-pixels), a liquid crystal cell 12 connected to the drain electrode (pixel electrode) of the TFT 11, and a drain electrode of the TFT 11 are connected. And the accumulated storage capacity 13.

  Further, in the liquid crystal display unit 1 shown in FIG. 2, the gate electrode of the TFT 11 is connected to the gate lines GL (GL (m−1), GL (m), GL (m + 1),...) That are scanning signal lines. The source electrode of the TFT 11 is connected to a source line SL (SL (n−1), SL (n), SL (n + 1),...) That is a data signal line. A common potential VCOM is applied to the counter electrode of the liquid crystal cell 12 and the other electrode of the storage capacitor 13 (not shown). Note that the pixels (subpixels) of the liquid crystal display unit 1 correspond to the RGB stripes of the color filter, and three subpixels (RGB) perform color display for one pixel.

  The gate line driving circuit 2 includes a vertical shift register 14 composed of a latch circuit and a gate line driving buffer 15 including a logic circuit. Each gate line drive buffer 15 outputs a scanning signal to each connected gate line GL. A gate clock signal CLKY and a start signal STY are input to the vertical shift register 14 from the outside of the panel.

  Next, a circuit diagram of the vertical shift register 14 is shown in FIG. In the vertical shift register 14 shown in FIG. 3, the latch circuits (1) to (4) connected in series are shown in four stages. The gate clock signal CLKY input from the outside of the panel becomes a global gate clock signal GCLKY (GCLK in FIG. 3) which is a reference clock signal in the panel, and is distributed to each latch circuit. A start signal STY (ST in FIG. 3) is input to the first-stage latch circuit 31. The output Q1 of the first-stage latch circuit 31 is input to the input of the second-stage latch circuit 32, and the output Q2 of the second-stage latch circuit 32 is input to the third-stage latch circuit 33. The output Q3 of the third-stage latch circuit 33 is input to the latch circuit 34 of the third stage.

  Next, a circuit diagram of the gate line driving buffer 15 is shown in FIG. The gate line drive buffer 15 performs an AND operation (AND element 35) on the output Q1 of the first-stage latch circuit 31 and the output Q2 of the second-stage latch circuit 32, and further controls the ENAB signal for controlling the pulse width. And a signal obtained by performing an AND operation (AND element 36) is output to the first gate line GL1. Similarly, the gate line drive buffer 15 performs an AND operation (AND element 37) on the output Q2 of the second-stage latch circuit 32 and the output Q3 of the third-stage latch circuit 33, and further controls the pulse width. A signal obtained by performing an AND operation (AND element 38) with the ENAB signal is output to the second gate line GL2. Further, the gate line drive buffer 15 performs an AND operation (AND element 39) on the output Q3 of the third-stage latch circuit 33 and the output Q4 of the fourth-stage latch circuit 34, and further controls the pulse width. A signal obtained by performing an AND operation (AND element 40) with the ENAB signal is output to the third gate line GL3.

  Next, a circuit diagram of the first-stage latch circuit 31 and the second-stage latch circuit 32 is shown in FIG. In FIG. 5, a transfer inverter 16 to which gate clock signals (LCLK, / LCLK) are supplied, a feedback inverter 17 connected in series with the transfer inverter 16, and an inverter 18 connected in parallel with the feedback inverter 17. One latch circuit is configured. Note that gate clock signals (LCLK, / LCLK) are also supplied to the feedback inverter 17.

  Next, in the vertical shift register 14 (FIG. 3) according to the present embodiment, the point that the clock skew can be reduced and the malfunction due to the clock skew can be prevented will be described.

  First, the global clock signal GCLK is input to the inverter 21 connected to each latch circuit. Further, the output of the inverter 21 is input to the inverter 22, and the inverter 22 generates one clock signal of two clock signals (LCLK, / LCLK) of the normal phase and the reverse phase (in FIG. 3, the global clock signal GCLK and In-phase clock signal LCLK is generated). Further, a part of the output of the inverter 22 is input to the inverter 23, and the inverter 23 generates the other clock signal (LCLK, / LCLK) of the two clock signals (LCLK, / LCLK) (in FIG. 3, the global clock). A clock signal / LCLK having a phase opposite to that of the signal GCLK is generated).

  In the shift register according to the present embodiment, the global clock signal GCLK is once received by the inverter 21 before the inverter 22 generates two clock signals (LCLK, / LCLK) of normal phase and reverse phase. Therefore, in the present embodiment, even if the waveform of the global clock signal GCLK is very large, the waveform can be shaped via the inverter 21. Therefore, the waveform of the output from the inverter 21 is reduced, and the waveform of the clock signals (LCLK, / LCLK) generated by the inverters 22 and 23 is also reduced. That is, by providing the inverter 21, clock signals (LCLK, / LCLK) with a small clock skew can be obtained. This is because the inverter 21 functions to shape the waveform of the clock signal (LCLK, / LCLK).

  In this embodiment, one set of inverters 21 to 23 is provided for one stage of the latch circuit, but the present invention is not limited to this, and one set of inverters is provided for a plurality of stages of latch circuits. The same effect can be obtained even when the inverter 21 is provided.

  Next, a block diagram showing a configuration of the source line driving circuit 3 is shown in FIG. The source line drive circuit 3 shown in FIG. 6 includes a horizontal shift register 4, a digital data bus line 19, a first latch circuit 5, a second latch circuit 6, a D / A conversion circuit (DAC) 7, an analog And an amplifier (Amp.) 8. In this example, the case of 4-bit digital gradation data (DATA) is shown. The digital gradation data (DATA) is latched in the first latch circuit 5 by the shift pulse signals (first latch signals LAT1_1, LAT1_2,... LAT1_m) from the horizontal shift register 4. The time until the latching of the digital gradation data (DATA) for one horizontal line in the first latch circuit 5 is called one line period. The second latch circuit 6 latches the data latched by the first latch circuits 5 at different timings at the same timing. After the latch operation in the second latch circuit 6 is completed, each first latch circuit 5 sequentially performs the latch operation for the next horizontal line. While the first latch circuit 5 is performing the latch operation, the D / A conversion circuit (DAC) 7 analogizes the digital gradation data (DATA) latched by the second latch circuit for the immediately preceding horizontal line. Convert to gradation voltage. The analog gradation voltage is supplied to the corresponding source signal line SL through the analog amplifier 8. By repeating the above-described operation, an image is displayed in the entire pixel display area in the array substrate.

  A source clock signal CLKX and a start signal STX are input to the horizontal shift register 4 from the outside of the panel. The horizontal shift register 4 has the same circuit configuration as the vertical shift register 14 (FIG. 3). A source clock signal CLKX input from the outside of the panel becomes a global clock GCLKX (GCLK in FIG. 3) in the panel and is distributed to each latch circuit. A start signal STX (ST in FIG. 3) is input to the first-stage latch circuit 31. The output Q1 of the first-stage latch circuit 31 is input to the input of the second-stage latch circuit 32, and the output Q2 of the second-stage latch circuit 32 is input to the third-stage latch circuit 33. The output Q3 of the third-stage latch circuit 33 is input to the latch circuit 34 of the third stage. In the horizontal shift register 4 according to the present embodiment, the clock skew can be reduced, and the malfunction due to the clock skew can be prevented in the same manner as in the vertical shift register 14.

(Embodiment 2)
FIG. 7 shows a block diagram of a liquid crystal display device incorporating a driving circuit according to this embodiment. The liquid crystal display device shown in FIG. 7 is different from the liquid crystal display device shown in FIG. 1 in that a plurality of level conversion circuits (L / S) 41 to 45 are provided.

  In recent years, there has been a demand for lower input / output voltages in order to reduce the power consumption of devices and to reduce the EMI (measures against unwanted emission). However, in a liquid crystal display device, a polycrystalline silicon thin film transistor having an operating voltage higher than that of a single crystal silicon transistor is used, and the operating voltage of the driving circuit needs to be increased. In view of this, in the liquid crystal display device, a level conversion circuit (L / S) is mounted on the drive circuit side so that a high voltage is supplied to the inside of the panel as necessary, thereby reducing the voltage.

  FIG. 8 shows a circuit diagram of the level conversion circuit (L / S). In the level conversion circuit shown in FIG. 8, the gates of the P-channel MOS transistors MP3 and MP4 whose sources are connected to the power supply (VDD) are the second CMOS inverter (MP2, MN2) and the first CMOS inverter (MP1, MN1). Are connected to each output. The first CMOS inverter (MP1, MN1) has an input signal IN (corresponding to the clock signal CLKY in FIGS. 9 and 10), and the second CMOS inverter (MP2, MN2) has an input signal / IN (see FIG. 9). 9 and FIG. 10, the clock signal / CLKY corresponds). Here, FIGS. 9 and 10 are diagrams for explaining generation of the clock signal when the level conversion circuit shown in FIG. 8 is provided. In the case of FIG. 9, two clock signals are output from the level conversion circuit, and in the case of FIG. 10, one clock signal is output from the level conversion circuit and is divided into two.

  In the level conversion circuit shown in FIG. 8, the output signal OUT is output from the node M2 through the buffer circuit. The input signal IN and its inverted signal / IN are low voltage level signals, and this level conversion circuit converts the “H” level to the power supply (VDD). In this level conversion circuit (L / S), a two-phase signal (input signal IN and its inverted signal / IN) is used as an input signal, but the input signal is a single-phase signal (only the input signal IN). Thus, the inverted signal / IN may be generated by an inverter circuit in the level conversion circuit (L / S).

  Referring to FIG. 7, clock signal CLKY and its inverted signal / CLKY are input from the outside of the panel to the input terminals of level conversion circuit 41 and its inverted signal / IN, respectively. The global clock signal GCLKY is output from the output M2 of the level conversion circuit 41 through the buffer circuit.

  The vertical shift register 14 according to the present embodiment has the configuration shown in FIG. The global clock signal GCLKY, which is an output signal of the gate clock level conversion circuit, is distributed to each latch circuit. A start signal STY is input to the first-stage latch circuit 31. The output Q1 of the first-stage latch circuit 31 is input to the input of the second-stage latch circuit 32, and the output Q2 of the second-stage latch circuit 32 is input to the third-stage latch circuit 33. The output Q3 of the third-stage latch circuit 33 is input to the latch circuit 34 of the third stage. Similarly, the start signal STY is input to the first-stage latch circuit 31 via the level conversion circuit 42. The ENAB signal is also input to the gate line drive buffer 15 via the level conversion circuit 43.

  Next, in the vertical shift register 14 (FIG. 3) according to the present embodiment, the point that the clock skew can be reduced and the malfunction due to the clock skew can be prevented will be described.

  First, the global clock signal GCLK is input to the inverter 21 connected to each latch circuit. Further, the output of the inverter 21 is input to the inverter 22, and the inverter 22 generates one clock signal of two clock signals (LCLK, / LCLK) of the normal phase and the reverse phase (in FIG. 3, the global clock signal GCLK and In-phase clock signal LCLK is generated). Further, a part of the output of the inverter 22 is input to the inverter 23, and the inverter 23 generates the other clock signal (LCLK, / LCLK) of the two clock signals (LCLK, / LCLK) (in FIG. 3, the global clock). A clock signal / LCLK having a phase opposite to that of the signal GCLK is generated).

  In the shift register according to the present embodiment, the global clock signal GCLK is once received by the inverter 21 before the inverter 22 generates two clock signals (LCLK, / LCLK) of normal phase and reverse phase. Therefore, in the present embodiment, even if the waveform of the global clock signal GCLK is very large, the waveform can be shaped via the inverter 21. Therefore, the waveform of the output from the inverter 21 is reduced, and the waveform of the clock signals (LCLK, / LCLK) generated by the inverters 22 and 23 is also reduced. That is, by providing the inverter 21, clock signals (LCLK, / LCLK) with a small clock skew can be obtained. This is because the inverter 21 functions to shape the waveform of the clock signal (LCLK, / LCLK).

  Further, since the inverter 22 generates a clock signal (LCLK, / LCLK) with a small clock skew, the transistor size (channel width and channel length) cannot be made sufficiently small. However, in the present embodiment, since the inverter 21 is provided in front of the inverter 22, the transistor size of the inverter 21 can be made smaller than the transistor size of the inverter 22. For example, the transistor size of the inverter 21 can be set to the minimum dimension acceptable in the process. Thereby, it is possible to reduce the load of the global clock signal GCLK, and it is possible to reduce the buffer size on the side where the global clock signal GCLK is supplied. In addition, since the buffer size can be reduced, an increase in power consumption of the entire circuit can be suppressed. Furthermore, since the buffer size can be reduced, the layout of the buffer unit is also facilitated.

  In this embodiment, one set of inverters 21 to 23 is provided for one stage of the latch circuit, but the present invention is not limited to this, and one set of inverters is provided for a plurality of stages of latch circuits. The same effect can be obtained even when the inverter 21 is provided.

  Next, referring to FIG. 7, the source clock signal CLKX and its inverted signal / CLKX are input from the outside of the panel to the input terminal of the level conversion circuit 44 and the input terminal to which the inverted signal / IN is input. . Then, the global clock signal GCLKX is output from the output M2 of the level conversion circuit 44 through the buffer circuit. The horizontal shift register 4 according to the present embodiment has a configuration shown in FIG. 3 (in FIG. 3, the global clock signal GCLKX is GCLK). Similarly, the start signal STX (ST in FIG. 3) is also input to the first-stage latch circuit 31 via the level conversion circuit 45. Similarly, the clock skew can be reduced, and malfunction due to the clock skew can be prevented.

(Embodiment 3)
FIG. 11 is a block diagram of a liquid crystal display device incorporating a drive circuit according to this embodiment. The liquid crystal display device shown in FIG. 11 is different from the liquid crystal display device shown in FIG. 7 in that timing delay circuits 46 and 47 are provided after the output of the level conversion circuits 41 and 44 for inputting the gate clock signal CLKY and the source clock signal CLKX. It is a point.

  FIG. 12 shows a circuit diagram of the timing delay circuit according to the present embodiment. FIG. 13 is a circuit diagram of the shift register according to this embodiment. In the circuit shown in FIG. 12, the output of the level conversion circuit becomes the reference clock signal BCLK of the timing delay circuit 46.

  Further, in the circuit shown in FIG. 12, the reference clock signal BCLK is supplied to the rising delay circuit 51 and the falling delay circuit 52 which are timing delay means. The rising delay circuit 51 outputs the reference clock signal BCLKB, and the falling delay circuit 52 outputs the reference clock signal BCLKA. Note that the reference clock signal BCLKA and the reference clock signal BCLKB are two-phase reference clock signals having different phases.

  The reference clock signals BCLKA and BCLKB are respectively input to different systems of inverters and buffers, and the complementary first clock signal group (CLKA, / CLKA) and second clock signal group (CLKB, / CLKA) shown in FIG. CLKB).

  In the shift register according to the present embodiment, as shown in FIG. 13, the first clock signal group (CLKA, / CLKA) and the second clock signal group (CLKB, / CLKB) are alternately latched. Are input to each stage. When driven in this manner, the shift register shown in FIG. 13 including the latch circuit shown in FIG. 5 constitutes the transfer inverter 16 constituting the first stage latch circuit 31 and the second stage latch circuit 32. Since the transfer inverters 16 of the adjacent latch circuits such as the transfer inverter 16 are not simultaneously turned on, the occurrence of a data punch-through phenomenon can be suppressed. In the waveform shown in FIG. 14, the clock skew between the clock signal CLKA and the clock signal / CLKA and between the clock signal CLKB and the clock signal / CLKB is the same as that of the first clock signal group (CLKA, / CLKA). Omitted because it is sufficiently small compared to the timing difference with the clock signal group (CLKB, / CLKB). Here, a period Td shown in FIG. 14 indicates a signal propagation delay time from switching of the clock signals (CLKY, / CLKY) to switching of the output Q1.

  The reason why the data punch-out phenomenon does not occur in the shift register according to this embodiment will be described with reference to FIG. FIG. 15 is a circuit diagram showing the latch circuits 31 and 32 in the first and second stages extracted from the latch circuits 31 to 34 shown in FIG. First, in the latch circuits 31 and 32 shown in FIG. 15, when the input start signal STY is “H” level, the N-channel transistors MN14 and MN15 are turned on when the clock signal CLKA is switched from “L” to “H”. The node A is turned on, the node A is pulled down to “L”, and the node B is pulled up to “H”.

  At this time, since the clock signal CLKB is switched from “H” to “L” before the clock signal CLKA is switched, and the N-channel transistor MN17 is in the OFF state, the data punch-out phenomenon does not occur. Further, even when the clock signal CLKB is switched from “L” to “H”, the clock signal CLKA supplied to the latch circuit of the next stage (not shown) has already been switched, so that the data punch-out phenomenon does not occur similarly. .

  FIGS. 16A and 16B show an example of the rising delay circuit 51 and the falling delay circuit 52 shown in FIG. In the rise delay circuit 51 shown in FIG. 16A, an AND operation (AND element 54) is performed on the input reference clock signal BCLK and the reference clock signal BCLK via the even-numbered inverter chain 53, and the inverter 55 is connected. Is output as a reference clock signal BCLKB. In the falling delay circuit shown in FIG. 16B, an OR operation (OR element 57) is performed between the input reference clock signal BCLK and the reference clock signal BCLK via the even-numbered inverter chain 56, and the inverter 58 is connected. And output as a reference clock signal BCLKA.

  However, the signal line names shown in FIG. 12 are as follows in the case of the vertical shift register 14. BCLK is BCLKY, ST is STY, CLKA and / CLKA are CLKYA and / CLKYA, and CLKB and / CLKB are CLKYB and / CLKYB.

  Further, the generation method of the two-phase clocks (the first clock signal group (CLKA, / CLKA) and the second clock signal group (CLKB, / CLKB)) supplied to the latch circuit is the rising delay shown in FIG. The method is not limited to the method using the circuit 51 and the falling delay circuit 52, and another method capable of generating the same timing may be used. Furthermore, although the shift register has been described in this embodiment, the same effect can be obtained by applying the contents according to this embodiment to a timing controller described later.

  By using the timing delay circuit, the vertical shift register 14 and the horizontal shift register 4 according to the present invention, an image display apparatus capable of stable operation without causing a data punch-out phenomenon can be obtained.

(Embodiment 4)
FIG. 17 shows a block diagram of a liquid crystal display device incorporating a driving circuit according to this embodiment. The liquid crystal display device shown in FIG. 17 is different from the liquid crystal display device shown in FIG. 11 in that the number of output signals of the timing delay circuits 48 and 49 is two (in the case of the vertical shift register 14, the global clock signal GCLKYA). , GCLKYB).

  FIG. 18 shows a circuit diagram of the timing delay circuit according to the present embodiment. FIG. 19 is a circuit diagram of the shift register according to this embodiment. The pulse generation circuit 48 shown in FIG. 18 includes a rise delay circuit 51, a fall delay circuit 52, and a buffer, which are pulse generation means. The output of the level conversion circuit becomes the reference clock signal BCLK, and the reference clock signal BCLK is input to the rising delay circuit 51 and the falling delay circuit 52 through the buffer.

  A reference clock signal BCLKB is generated from the rising delay circuit 51, and a reference clock signal BCLKA is generated from the falling delay circuit 52, and output as global clock signals GCLKB and GCLKA through a buffer. Note that the reference clock signal BCLKB and the reference clock signal BCLKA, and the global clock signal GCLKB and the global clock signal GCLKA have different phases.

  Further, the global clock signal GCLKA is supplied to the first and third stage latch circuits 31 and 33 shown in FIG. 19, and the global clock signal GCLKB is supplied to the second and fourth stage latch circuits 32 shown in FIG. , 34. The supplied global clock signal GCLKA is first input to the inverter 60 connected to the first-stage and third-stage latch circuits 31 and 33, and the output is inverted by the inverter 61 and output as the clock signal / LCLKA. A part of the output of the inverter 61 is further input to the inverter 62, inverted, and output as the clock signal LCLKA. Similarly, the supplied global clock signal GCLKB is first input to the inverter 63 connected to the second-stage and fourth-stage latch circuits 32 and 34, and its output is inverted by the inverter 64 and output as the clock signal LCLKB. The A part of the output of the inverter 64 is further input to the inverter 65, inverted and output as the clock signal / LCLKB.

  By generating the clock signals (LCLKA, / LCLKA and LCLKB, / LCLKB) that are input to the respective latch circuits by the above-described method, between the complementary clock signals (between LCLKA and / LCLKA, LCLKB and / LCLKB, The clock skew becomes smaller and a more stable operation can be obtained. In addition, the shift register according to this embodiment generates a two-phase clock signal having different phases, and inputs a clock signal having a different phase every other stage to a latch circuit constituting the shift register. With this configuration, the transfer inverters in the adjacent latch circuits such as the transfer inverter constituting the first-stage latch circuit and the transfer inverter constituting the second-stage latch circuit are simultaneously turned on. It is possible to suppress the occurrence of a data punch-through phenomenon without entering a state.

  However, the signal line names shown in FIG. 18 are as follows in the case of the vertical shift register 14. BCLK is BCLKY, ST is STY, CLKA and / CLKA are CLKYA and / CLKYA, and CLKB and / CLKB are CLKYB and / CLKYB.

  Note that the main purpose of the present invention is to shift the phases of CLKA, / CLKA and CLKB, / CLKB. For this reason, the method of generating complementary clock signals input to the latch circuits at each stage is shown in FIG. The method is not limited to the method shown, and for example, a method of generating using a circuit configuration in which the inverters 60 and 63 are not provided may be used. Further, the method is not limited to the method using the rising delay circuit 51 and the falling delay circuit 52 shown in FIG. 18, and another method capable of generating the same timing may be used.

(Embodiment 5)
FIG. 20 is a block diagram of a liquid crystal display device incorporating a drive circuit according to this embodiment. The liquid crystal display device shown in FIG. 20 is different from the liquid crystal display devices shown in FIGS. 1, 7, 11, and 17 in that a timing controller 10 is incorporated.

  The timing controller 10 shown in FIG. 20 includes a control signal (CLKY, STY) for the gate line driving circuit 2 from a master clock signal MCLK, a horizontal synchronization signal HSYNC, and a vertical synchronization signal VSYNC input from the outside through a level conversion circuit. Control signals (CLKX, STX) of the shift register 4 of the source line driver circuit, a second latch signal for controlling the second latch circuit 6, and control signals for the D / A conversion circuit 7 and the analog amplifier 8 are generated. In the liquid crystal display device incorporating the timing controller 10 shown in FIG. 20, the master clock signal MCLK, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC, which are input signals, are generally low voltages, and voltages are generated by the level conversion circuit (L / S). After the level is converted, it is input to the timing controller 10. In the liquid crystal display device shown in FIG. 20, the master clock signal MCLK, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC are single-phase inputs. The gate clock signal CLKY, the vertical shift register 14, the source clock signal CLKX, and the horizontal shift register 4 shown in FIG.

  FIG. 21 shows a circuit diagram of the timing controller according to the present embodiment. The timing controller shown in FIG. 21 is provided with four stages of two latch circuits 71 to 74 connected in series. That is, the latch circuit 71a and the latch circuit 71b are connected in series to form the first stage, the latch circuit 72a and the latch circuit 72b are connected in series to form the second stage, and the latch circuit 73a and the latch circuit 73b are connected in series. A stage is configured, and a latch circuit 74a and a latch circuit 74b are connected in series to form a fourth stage. Note that each of the latch circuits 71a to 74b shown in FIG. 21 has the same circuit configuration as that shown in FIG. 5, and transmits a pulse signal in synchronization with the clock signal.

  FIG. 22 shows a circuit diagram for generating global half clock signal GHCLK from master clock signal MCLK. In FIG. 22, a level conversion circuit 78 that converts the voltage level of the master clock signal MCLK, a frequency dividing circuit 79 that divides the level-converted signal, and a buffer that outputs the frequency-divided signal as a global half clock signal GHCLK. And. The frequency dividing circuit and the buffer circuit are included in the timing controller 10.

  Next, the global half clock signal GHCLK generated in FIG. 22 is distributed to each latch circuit in the timing controller 10 and performs various timing controls of the timing controller 10. Note that signals 1 to 4 are input to the latch circuits 71 to 74 at the respective stages shown in FIG. These signals 1 to 4 are signals generated by the timing controller 10 for controlling the horizontal shift register 4, the second latch circuit 6, the D / A conversion circuit 7, the analog amplifier 8, and the gate line driving circuit 2. This is a signal used, for example, a signal obtained by converting the voltage level of the HSYNC signal by the level conversion circuit and output through the buffer circuit.

  In FIG. 22, the global half clock signal GHCLK is first input to an inverter 75 connected to each latch circuit. Further, the output of inverter 75 is input to inverter 76, and inverter 76 generates clock signal LHCLK in phase with global half clock signal GHCLK. Further, the output of inverter 76 is input to inverter 77, and inverter 77 generates a clock signal / LHCLK having a phase opposite to that of global half clock signal GHCLK.

  The timing controller according to the present embodiment receives the global half clock signal GHCLK by the inverter 75 before the clock signals (LHCLK, / LHCLK) are generated by the inverters 76 and 77 as in the second embodiment. . Therefore, the timing controller according to the present embodiment can shape the waveform through the inverter 75 even if the waveform of the global half clock signal GHCLK is very large. Therefore, since the waveform rounding of the output from the inverter 75 is reduced, the waveform rounding of the clock signals (LHCLK, / LHCLK) generated by the inverter 76 and the inverter 77 is also reduced. That is, by providing the inverter 75, a clock signal (LHCLK, / LHCLK) having a small clock skew can be obtained.

  The clock signal generation circuit of the timing controller according to the present embodiment has been described in the second embodiment, but may be the third and fourth embodiments.

(Embodiment 6)
FIG. 23 shows a circuit diagram of the latch circuit according to the present embodiment. In this embodiment, the transistor size (channel width (W) and channel length (L)) constituting the feedback inverter 17 of the latch circuit shown in Embodiment 1 or Embodiment 2 is set as the transfer inverter 16. It should be equal to or larger than the transistor size. In the example shown in FIG. 23, the transistor size of the transfer inverter 16 is W / L = 10 μm / 5 μm for the P-channel transistor and W / L = 5 μm / 5 μm for the N-channel transistor. The size of the P channel transistor is W / L = 20 μm / 5 μm, and the size of the N channel transistor is W / L = 10 μm / 5 μm.

  In a general latch circuit, the size of the feedback inverter 17 is made smaller than the size of the transfer inverter 16. However, when the latch circuit is configured in such a size, an erroneous latch of the input signal occurs when the waveform of the clock signal (CLK, / CLK) is rounded. The occurrence of erroneous data latching will be described with reference to the circuit diagram of the latch circuit shown in FIG.

  First, in the latch circuit shown in FIG. 24, when the / CLK signal is switched from “L” to “H” when the input signal IN is “L” level and the node B is “L” level, the P-channel transistor MP20 is turned off. It becomes a state. On the other hand, when the CLK signal is switched from “H” to “L”, the P-channel transistors MP22 and MP23 are turned on and the latch operates. Thereafter, even if the input signal IN is switched to the “H” level, the node B is in a state of latching “L”.

  However, when the waveform of the clock signal (CLK, / CLK) is rounded, the transition time for switching the CLK signal from “H” to “L” becomes long. Therefore, when the input signal IN switches to the “H” level when the voltage level of the CLK signal is approximately between the power supply (VDD) and GND, the N-channel transistors MN20 and MN21 are turned on simultaneously with the P-channel transistors MP22 and MP23. It becomes a state. When the size of the transfer inverter transistors (MP20, MP21, MN20, MN21) is larger than the size of the feedback inverter transistors (MP22, MP23, MN22, MN23), the node A is set to “L” by the N-channel transistors MN20, MN21. The node B is erroneously latched to “H”. In particular, when a polycrystalline silicon thin film transistor is used as a MOS transistor, its transistor characteristics such as threshold voltage are much larger than that of a single crystal silicon transistor, and its variation is very large. In addition, since the parasitic capacitance between the wirings is large, the signal line cannot be driven at a sufficiently high speed, and the waveform is dull.

  In the example shown in FIG. 23, the transistor size of the feedback inverter 17 is made larger than the transistor size of the transfer inverter 16. By configuring the latch circuit according to the present embodiment as described above, the transfer inverter 16 and the feedback inverter 17 are simultaneously turned on due to the rounding of the waveform of the clock signal, and even if a signal collision occurs, the feedback circuit is used. Since the transistor size of the inverter 17 is larger than the transistor size of the transfer inverter 16, the latched signal level does not change. Therefore, the latch circuit according to this embodiment can be configured as described above to prevent erroneous latching of input signals. By using the latch circuit according to this embodiment for the vertical shift register 14, the horizontal shift register 4, and the timing controller 10, an image display device that performs stable operation without erroneous latching can be obtained.

  In the above-described drive circuit, the case where a clocked inverter is used as a latch circuit has been described. However, the present invention is not limited to this, and the same effect can be obtained even when a transmission gate is used.

  Further, in the above description, the drive circuit (shift register, timing controller, etc.) according to the present invention has been described as being mainly used for a drive circuit of a liquid crystal display device. It can also be used for the drive circuit of the apparatus. Furthermore, the active element included in the source line driving circuit and the gate line driving circuit configured by driving circuits such as the shift register and the timing controller according to the present invention, and the pixel configuring the image display device is a polycrystalline silicon thin film transistor.

  Note that a source line driver circuit, a gate line driver circuit, and a timing controller are formed on the array substrate in addition to a plurality of pixels arranged in a matrix and a thin film transistor for controlling each pixel. The latch circuit and driving circuit according to the present invention are applied to the source line driving circuit, gate line driving circuit, and timing controller formed on the array substrate. However, there are various combinations of circuits formed on the array substrate, such as only the source line driver circuit, only the gate line driver circuit, source line driver circuit and gate line driver circuit, source line driver circuit and gate line driver circuit, and timing controller. Conceivable.

1 is a block diagram of a liquid crystal display device according to Embodiment 1 of the present invention. It is a circuit diagram of the liquid crystal display part which concerns on Embodiment 1 of this invention. 1 is a circuit diagram of a shift register according to a first embodiment of the present invention. FIG. 3 is a circuit diagram of a buffer constituting the gate line driving circuit according to the first embodiment of the present invention. 1 is a circuit diagram of a latch circuit according to a first embodiment of the present invention. 1 is a block diagram of a source line drive circuit according to a first embodiment of the present invention. It is a block diagram of the liquid crystal display device which concerns on Embodiment 2 of this invention. FIG. 6 is a circuit diagram of a level conversion circuit according to a second embodiment of the present invention. It is a figure for demonstrating the production | generation of the clock signal which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the production | generation of the clock signal which concerns on Embodiment 2 of this invention. It is a block diagram of the liquid crystal display device which concerns on Embodiment 3 of this invention. It is a circuit diagram of the pulse generation circuit which concerns on Embodiment 3 of this invention. It is a circuit diagram of the shift register which concerns on Embodiment 3 of this invention. It is a figure which shows the waveform of the shift register which concerns on Embodiment 3 of this invention. FIG. 6 is a circuit diagram of a latch circuit according to Embodiment 3 of the present invention. It is a circuit diagram of the rising delay circuit and falling delay circuit which concern on Embodiment 3 of this invention. It is a block diagram of the liquid crystal display device which concerns on Embodiment 4 of this invention. It is a circuit diagram of the pulse generation circuit which concerns on Embodiment 4 of this invention. It is a circuit diagram of the shift register which concerns on Embodiment 4 of this invention. It is a block diagram of the liquid crystal display device which concerns on Embodiment 5 of this invention. FIG. 10 is a block diagram of a level conversion circuit and a frequency dividing circuit according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram of a timing controller according to Embodiment 5 of the present invention. FIG. 10 is a circuit diagram of a latch circuit according to Embodiment 6 of the present invention. FIG. 10 is a circuit diagram of a latch circuit according to Embodiment 6 of the present invention. It is a circuit diagram of a shift register which is a premise of the present invention. It is a figure which shows the waveform for demonstrating the shift register used as the premise of this invention. It is a circuit diagram of a latch circuit which is a premise of the present invention. It is a circuit diagram of a latch circuit which is a premise of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display part, 2 Gate line drive circuit, 3 Source line drive circuit, 4 Horizontal shift register, 5 1st latch circuit, 6 2nd latch circuit, 7 D / A converter circuit, 8 Analog amplifier, 10 Timing controller, 11 TFT, 12 liquid crystal cell, 13 storage capacitor, 14 vertical shift register, 15 gate line drive buffer, 16, 111, 113 transfer inverter, 17, 112, 114 feedback inverter, 18, 21, 22, 23, 55, 58 , 60, 61, 62, 63, 64, 65, 75, 76, 77 Inverter, 19 Digital data bus line, 31, 32, 33, 34, 71, 72, 73, 74, 101, 102, 103, 104 Latch Circuit, 35, 36, 37, 38, 39, 40, 54 AND element, 41, 42, 43, 44, 45 Level conversion Road, 46, 47, 48, 49 a timing delay circuit, 78 a pulse generator circuit, 51 the rise delay circuit 52 fall delay circuit, 53 and 56 even stages inverter chains, 57 OR element, 79 frequency divider.

Claims (16)

A first inverter circuit that inverts a reference clock signal to generate a first inverted clock signal;
A second inverter circuit for generating a first clock signal by inverting the first inverted clock signal generated by the first inverter circuit;
A third inverter circuit that inverts the first clock signal generated by the second inverter circuit to generate a second inverted clock signal;
A drive circuit comprising a plurality of serially connected latch circuits that transmit a pulse signal in synchronization with the first clock signal and the second inverted clock signal. The drive circuit according to claim 1,
The drive circuit characterized in that the channel width and the channel length of the transistors constituting the first inverter are not more than the channel width and the channel length of the transistors constituting the second inverter. The drive circuit according to claim 1 or 2,
The latch circuit includes a data transfer inverter and a feedback inverter connected in series with the data transfer inverter,
A drive circuit characterized in that the channel width and the channel length of the transistors constituting the data feedback inverter are equal to or greater than the channel width and the channel length of the transfer inverter. A reference clock signal generating means for generating a first reference clock and a second reference clock having different phases from each other;
A first inverter circuit that generates a first clock signal from the first reference clock signal or the second reference clock signal;
A second inverter circuit that inverts the first clock signal generated by the first inverter circuit and generates a second clock signal;
A plurality of latch circuits connected in series for transmitting a pulse signal in synchronization with the first clock signal and the second clock signal;
The first reference clock is supplied to the first inverter circuit connected to the odd-numbered latch circuits, and the second reference clock is supplied to the first inverter circuit connected to the even-numbered latch circuits. A driving circuit which is supplied. The drive circuit according to claim 4,
The reference clock signal generation means includes a rising delay circuit and a falling delay circuit, and generates the first reference clock signal and the second reference clock signal by the rising delay circuit and the falling delay circuit. A drive circuit characterized by that. A reference clock signal generating means for generating a first reference clock signal group and a second reference clock signal group having different phases from each other from the reference clock signal;
A drive circuit comprising a plurality of latch circuits connected in series for transmitting a pulse signal in synchronization with the first reference clock signal group or the second reference clock signal group;
The drive circuit, wherein the first reference clock signal group is supplied to an odd-numbered stage of the latch circuit, and the second reference clock signal group is supplied to an even-numbered stage of the latch circuit. The drive circuit according to claim 6,
The reference clock signal generation means includes a rising delay circuit and a falling delay circuit, and the first reference clock signal group and the second reference clock signal group are obtained by the rising delay circuit and the falling delay circuit. A drive circuit characterized by generating. A drive circuit according to any one of claims 1 to 7,
A drive circuit comprising boosting means for converting the voltage level of an input signal supplied from the outside to generate the reference clock signal. The drive circuit according to claim 8, wherein
The reference clock signal is output through a drive buffer, and at least the booster and the drive buffer are formed on the same substrate. A latch circuit that transmits a pulse signal in synchronization with a clock signal,
An inverter for data transfer;
A feedback inverter connected in series with the data transfer inverter;
2. A latch circuit according to claim 1, wherein the channel width and channel length of the transistor constituting the data feedback inverter are equal to or greater than the channel width and channel length of the transistor constituting the transfer inverter. A plurality of pixels arranged in a matrix;
A source line driving circuit for supplying image data to each pixel via a data signal line;
A gate line driving circuit for supplying a scanning signal to each pixel via the scanning signal line;
A timing controller that controls the source line driving circuit and the gate line driving circuit,
At least one of the source line driving circuit, the gate line driving circuit, and the timing controller is configured by the driving circuit according to any one of claims 1 to 9. Image display device. A plurality of pixels arranged in a matrix;
A source line driving circuit for supplying image data to each pixel via a data signal line;
A gate line driving circuit for supplying a scanning signal to each pixel via the scanning signal line;
A timing controller that controls the source line driving circuit and the gate line driving circuit,
The image display device according to claim 10, wherein at least one of the source line driver circuit, the gate line driver circuit, and the timing controller is configured by a latch circuit according to claim 10. The image display device according to claim 11 or 12,
The image display device, wherein the source line driver circuit, the gate line driver circuit, the timing controller, and the active elements constituting the pixel are polycrystalline silicon thin film transistors. A plurality of pixels arranged in a matrix;
A source line driving circuit for supplying image data to each pixel via a data signal line; a gate line driving circuit for supplying a scanning signal to each pixel via a scanning signal line; the source line driving circuit; and the gate line driving circuit. An array substrate comprising at least one circuit of a timing controller to be controlled,
10. The array substrate according to claim 1, wherein the source line driving circuit, the gate line driving circuit, and the timing controller are configured by the driving circuit according to claim 1. A plurality of pixels arranged in a matrix;
A source line driving circuit for supplying image data to each pixel via a data signal line; a gate line driving circuit for supplying a scanning signal to each pixel via a scanning signal line; the source line driving circuit; and the gate line driving circuit. An array substrate comprising at least one circuit of a timing controller to be controlled,
The array substrate according to claim 10, wherein the source line driving circuit, the gate line driving circuit, and the timing controller are configured by a latch circuit according to claim 10. The array substrate according to claim 14 or 15,
The array substrate, wherein the source line driving circuit, the gate line driving circuit, the timing controller, and the active elements constituting the pixels are polycrystalline silicon thin film transistors.

Images