JP2006210992A - Mobile terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a foldable mobile terminal decreasing the number of signal wires between a lower case body and an upper case body of the mobile terminal and reducing the current consumption. <P>SOLUTION: A main CPU 1 of the lower case body 101 transmits control data of an LCD driver 7 to a 12C/SPI conversion circuit 5 of the upper case body 102 through 12C buses (12C DO1a, 12C CLK 1b). The 12C/SPI conversion circuit 5 once stores the received control data and transmits the control data to an LCD driver 7 as SPI DO5b by using a high speed clock. The 12C/SPI conversion circuit 5 generates an SPI CLK5a and SPI CS5c for a transmission period of the control data and transmits them to the LCD driver 7. The LCD driver 7 is in a sleep state for a negative period of the SPI CS5c. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a portable terminal that transmits display data and control data from a control unit to a display unit using a serial interface.

(Background Technology 1)
There is a display driver IC using a serial interface and an electronic device using the display driver IC (see, for example, Patent Document 1).
In the display driver IC of Patent Document 1 and an electronic device using the display driver IC, the MPU and the liquid crystal module are connected by an MPU interface of four signal lines (number of terminal pins). Of the four signal lines, the first is a serial data input signal, the second is a serial clock signal, the third is a chip select signal, and the fourth is a reset signal. The MPU sends display data and command data to the liquid crystal module through the MPU interface of these four signal lines. As a result, command and data transmission is efficiently performed while reducing the number of terminal pins, thereby speeding up data transmission.

(Background Technology 2)
FIG. 4 is a block diagram showing a configuration of a main part related to display control of a conventional folding portable terminal. In a conventional portable terminal 200, a lower casing 201 and an upper casing 202 are foldably coupled by a hinge (not shown), and are electrically connected by an interface 203 by a cable or the like. On the lower housing 201 side, there are a main CPU 11, an LCD controller 12, a serial communication unit 13 that performs P / S conversion (parallel / serial conversion), and the like. The LCD controller 12 includes a GPIO (general purpose IO) 121. The upper housing 202 side includes a serial communication unit 14 that performs S / P conversion (serial / parallel conversion), an LCD (liquid crystal unit) 15, and the like. The LCD 15 includes an LCD driver 16.

  Each unit is connected by two general-purpose I2C buses (IIC bus, Inter-IC bus, IC bus) developed by Philips, I2C DO11a and I2C CLK11b, and in accordance with the I2C protocol Send and receive. The serial communication unit 13 and the serial communication unit 14 perform communication dedicated to high-speed image data of 80 MHz by using the serial data 13a and the clock 13b. The GPIO 121 and the LCD driver 16 are connected with three general-purpose SPI (serial peripheral interface) signals SPI CLK 121a, SPI DO 121b, and SPI CS 121c developed by Motorola, and transmit signals for controlling the LCD driver 16 Used for. Therefore, the number of signal lines of the interface 203 connecting the lower casing 201 and the upper casing 202 is as many as seven.

  FIG. 5 is a time chart of the I2C bus and the SPI signal in the conventional block diagram of FIG. The main CPU 11 outputs I2C CLK11b and I2C DO11a. In the general-purpose I2C bus protocol, I2C CLK11b is always generated, and in this example, is 400 kHz. The I2C DO11a is a data group that starts with a start bit (1 bit) and ends with an end bit (1 bit). In addition, a slave address (7 bits, the address of the opposing slave IC), R / W (1 bit, read / write) ACK (1 bit, response signal), control byte (8 bits), command (8 bits), data 11d (8 bits), etc. In this example, it is composed of 38 bits (about 0.1 ms). This group of 38 bits completes reading / writing of a group of data from a predetermined master IC to a slave IC.

  In addition, the main CPU 11 performs software control of the GPIO 121 via the I2C bus and outputs three general-purpose SPI signals (SPI CLK 121a, SPI DO 121b, and SPI CS 121c). For example, the SPI CLK 121a, SPI DO 121b, and SPI CS 121c are assigned to any of 8 bits of the data 11d of the I2C DO 11a, and the GPIO 121 is controlled by software for each group of 38 bits (about 0.1 ms) of the I2C bus. Is called.

  In the general-purpose SPI protocol, the SPI CLK 121a is generated only when it is necessary to transmit data. Under the software control of the main CPU 11, the GPIO 121 raises and lowers the SPI CLK 121a every 38 bits (about 0.1 ms = 38 bits / 400 kHz) of the I2C bus. Accordingly, the frequency of the SPI CLK 121a is 5.26 kHz which is a (38 bit × 2) frequency division of 400 kHz of the I2C CLK 11b. This speed is slow. Further, under the software control of the main CPU 11, the GPIO 121 outputs the SPI DO 121b in synchronization with the falling edge of the SPI CLK 121a. The SPI CS 121c (chip select) is a signal that becomes active during transmission of necessary data, and the GPIO 121 is activated before the generation of the SPI CLK 121a by the software control of the main CPU 11, and is made negative after the completion of the SPI CLK 121a.

Thus, it takes about 3.3 ms to send the total 16 bits of D7 to D0 and D17 to D10 of SPI DO 121b. A group of 16 bits of D7 to D0 and D17 to D10 in the SPI DO 121b constitutes one control signal, and the LCD driver 16 is controlled. Control of the LCD driver 16 does not need to be performed frequently, and in this example, it is performed at a period of 3.6 ms. That is, the LCD driver control signal A which is a group of 16 bits of the first D7 to D0 and D17 to D10 is sent in 3.3 ms which is shorter than 3.6 ms. Then, after 3.6 ms-3.3 ms = 0.3 ms, the LCD driver control signal B which is a group of 16 bits of the following D7 to D0 and D17 to D10 may be sent. As a result, data is transmitted for most of the period, and the off period during which data is not transmitted is as short as 3.6 ms-3.3 ms = 0.3 ms.
JP 2001-34374 A (pages 4-5, FIGS. 1 and 2)

In the display driver IC disclosed in the background art 1 and the electronic device using the display driver IC, the serial data input signal is basically selected from the MPU interface of four signal lines (number of terminal pins). Since both the display data and the command data are sent to the liquid crystal module by one set of serial clock signals, there is a problem that the display data cannot be further increased in speed.
In the foldable portable terminal disclosed in the background art 2 of the related art, the number of signal lines between the lower casing and the upper casing is as large as seven, and there is a problem in cable wiring and the like. In addition, since the LCD driver is controlled by a low-speed SPI signal line, there is a problem that an off period during which data is not transmitted is short and current consumption increases.

  The present invention has been made to solve the above-described problems, and provides a portable terminal capable of reducing the number of signal lines between a lower housing and an upper housing and reducing current consumption. The purpose is to provide.

  In order to achieve the above object, a mobile terminal according to the present invention is a mobile terminal including a first casing and a second casing that freely engages with the first casing, and the first casing. Main control means, and the second casing is provided with conversion means and display means, and the main control means transmits display control data for the display means to the conversion means via an inter-case transmission path, The conversion means converts the received display control data into an LCD control transmission line format and transmits it to the display means through the LCD control transmission line, and the display means displays the LCD according to the display control data in the LCD control transmission line format. Control is performed.

  It is possible to reduce the number of signal lines between the lower casing and the upper casing of the portable terminal and to reduce current consumption.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a main part related to display control of a folding portable terminal according to an embodiment of the present invention. The main part of the portable terminal 100 is such that a lower casing 101 (first casing) and an upper casing 102 (second casing) are foldably engaged by a hinge (not shown), and are electrically cabled. For example, the interface 103 is connected. The lower casing 101 side includes a main CPU 1, an LCD controller 2, a serial communication unit 3 that performs P / S conversion (parallel / serial conversion), and the like.

  On the upper housing 102 side, there are a serial communication unit 4 for performing S / P conversion (serial / parallel conversion), an LCD (liquid crystal unit) 6 and the like. The serial communication unit 4 includes an I2C / SPI conversion circuit 5. The I2C / SPI conversion circuit 5 may be provided outside the serial communication unit 4. The LCD 6 has a built-in LCD driver 7. The LCD driver 7 has a function of receiving sleep control and power control. Between the I2C / SPI conversion circuit 5 and the LCD driver 7, SPI CLK5a (clock), SPI DO5b (data), and SPI CS5c (chip select), which are general-purpose SPI (serial peripheral interface) signals developed by Motorola, Inc. Connected by a book, it is used to transmit a signal for controlling the LCD driver 7. The use of this control signal is used for various LCD settings such as regulator voltage setting of the LCD 6 and 65k / 256k color switching setting.

  Each part is connected with two I2C DO1a (data) and I2C CLK1b (clock) which are general-purpose I2C buses (IIC bus, Inter-IC bus, inter-IC bus) developed by Philips. As a rule, commands and data are sent and received. The serial communication unit 3 and the serial communication unit 4 perform communication dedicated to high-speed image data of 80 MHz by using the serial data 3a and the clock 3b. Therefore, the number of signal lines of the interface 103 that connects the lower casing 101 and the upper casing 102 is as small as four.

  FIG. 2 is a block diagram showing a configuration of the I2C / SPI conversion circuit 5 according to the embodiment of the present invention. The I2C / SPI conversion circuit 5 includes a frequency dividing circuit 51, an SPI CLK / CS generating circuit 52, a register 53, and the like. The frequency dividing circuit 51 divides the frequency of the 80 MHz clock 3 b and supplies, for example, a 6 MHz clock 51 a to the SPI CLK / CS generating circuit 52. I2C DO1a and I2C CLK1b of the I2C bus are connected to the SPI CLK / CS generation circuit 52 and the register 53.

  The SPI CLK / CS generation circuit 52 outputs SPI CLK 5a and SPI CS 5c at a predetermined timing. The register 53 outputs SPI DO 5b in synchronization with SPI CLK 5a. The SPI CLK 5a, SPI DO 5b, and SPI CS 5c are used as signals for controlling the LCD driver 7. These detailed operations and timing will be described below.

  FIG. 3 is a time chart of the I2C bus and the SPI signal in the block diagram of the embodiment of FIGS. The main CPU 1 outputs I2C CLK1b and I2C DO1a. In the general-purpose I2C bus protocol, I2C CLK1b is always generated, and in this example, is 400 kHz. The I2C DO1a is a data group that starts with a start bit (1 bit) and ends with an end bit (1 bit). In addition, a slave address (7 bits, the address of the opposite slave IC), R / W (1 bit, read / write) ACK (1 bit, response signal), control byte (8 bits), command (8 bits), data 11d (8 bits), etc. In this example, it is composed of 38 bits (about 0.1 ms). This group of 38 bits completes reading / writing of a group of data from a predetermined master IC to a slave IC.

  First, the main CPU 1 notifies that data for SPI is to be transmitted by a command of I2C DO1a of the I2C bus, and SPI DO6b which is a control signal of the LCD driver 8 by 38-bit first group of 8-bit data 1d. Is sent to the I2C / SPI conversion circuit 5. For example, 8-bit data 1d in the first 38-bit group of I2C DO1a is used to send the original data of D7 to D0, which is 8-bit data of SPI DO6b, to I2C / SPI conversion circuit 5 (timing T1), and the next 38 bits. Based on the second group of 8-bit data 1d, the original data of D17 to D10 which are 8-bit data of SPI DO 6b is sent to the I2C / SPI conversion circuit 5 (timing T2). Then, the register 53 of the I2C / SPI conversion circuit 5 temporarily accumulates them.

  Next, the SPI CLK / CS generation circuit 52 performs processing for converting the original data of D7 to D0 and D17 to D10 accumulated in the register 53 into high-speed SPI DO. This first activates the SPI CS 5c at the timing T3. Next, at timing T4, the timing is taken by the high-speed 6 MHz clock 51a to generate SPI CLK 5a (6 MHz). Further, the original data of D7 to D0 and D17 to D10 stored in the register 53 is synchronized with SPI CLK5a (6 MHz), and as the D7 to D0 and D17 to D10 of SPI DO5b, the LCD driver 7 together with the SPI CLK5a. To send. One group of 16-bit data constitutes one control signal and is used by the LCD driver 7 as the LCD driver control signal A. Next, at timing T5, SPI CS5c is made negative.

  Since the LCD driver control signal A is transmitted by the high-speed 6 MHz SPI CLK 5a, (16 bits + α) / 6 MHz = about 3 μS is very short. It is not necessary to frequently control the LCD driver 7 by the LCD driver control signal, and the period up to the next LCD driver control signal B is 3.6 ms in this example. That is, the transmission of the LCD driver control signal A is completed in about 3 μS within the 3.6 ms period. Then, after 3.6 ms−3 μS = about 3.6 ms, the next LCD driver control signal B may be transmitted. As a result, most of the period is an off period in which data is not transmitted.

The current consumption of the LCD driver 7 can be reduced by setting the LCD driver 7 to the sleep state or the power-off state by the negative portion (timing T5 to T6) of the SPI CS 5c representing the off period.
In addition, the output transistor of the three SPI signals of the I2C / SPI conversion circuit 5 is a LOW level (or HIGH level) with low current consumption, and the level of the off period of the three SPI signals is adjusted to that. Also good. In that case, the current consumption of the I2C / SPI conversion circuit 5 itself can also be reduced.

Note that the SPI CLK 5a is not required to have a transmission period of 3 μS for the LCD driver control signal A at 6 MHz, and the LCD driver control signal A has a period of 3.6 ms (between timings T3 and T6) for controlling the LCD driver 7. The sending period (between timings T3 and T5) only needs to be sufficiently small. Therefore, if SPI CLK5a is set to 400 kHz which is the same as I2C CLK1b (400 kHz), the LCD driver control signal A transmission period (between timings T3 and T5) is sufficiently small (16 bits + α) / 400 kHz = about 45 μS.
Therefore, it is not necessary to divide the clock that becomes the source of the SPI CLK 5a by dividing the 80 MHz clock 3b of the high-speed serial communication, and other clocks existing on the upper housing side are used to transmit the LCD driver control signal A (timing). A clock that can sufficiently reduce (between T3 and T5) may be used as appropriate.

Thus, according to the embodiment, current consumption of the LCD driver 7 and the I2C / SPI conversion circuit 5 can be reduced.
Further, although the LCD driver 7 is controlled at a period of 3.6 ms, even if it is necessary to shorten this period, the LCD driver control signal transmission period ends at about 3 μS, so there is a sufficient margin. Can be easily handled.
Further, since the three SPI signals are created by the I2C / SPI conversion circuit 5 by hardware processing, the burden on the main CPU 1 can be reduced.
In addition, the number of signal lines of the interface 103 that connects the lower housing 101 and the upper housing 102 can be reduced.
Further, since the three high-speed SPI signals are in the upper casing 102 and do not pass through the cable of the interface 103, high-frequency noise on the cable can be reduced.

  In this embodiment, three high-speed SPI signals are created by hardware processing using the I2C / SPI conversion circuit on the upper casing side. However, the function of the GPIO 121 on the lower casing side is provided on the upper casing side, and the main CPU Three low-speed SPI signals may be created by software processing. Also in this case, the number of signal lines of the interface 103 that connects the lower housing 101 and the upper housing 102 can be reduced.

  The I2C / SPI conversion circuit and the LCD driver are in the SPI signal format, but may be in another LCD control transmission line format. In addition, the upper housing and the lower housing are connected by the I2C bus, but may be in a form such as another inter-housing transmission path.

  Although the display control between the upper casing and the lower casing of the foldable portable terminal has been described, other applications may be used.

The block diagram which shows the structure of the principal part relevant to the display control of the foldable portable terminal which concerns on the Example of this invention. The block diagram which shows the structure of the I2C / SPI conversion circuit which concerns on the Example of this invention. 4 is a time chart of an I2C bus and an SPI signal according to an embodiment of the present invention. The block diagram which shows the structure of the principal part relevant to the display control of the conventional foldable portable terminal. The time chart of the conventional I2C bus and SPI signal.

Explanation of symbols

1 Main CPU
2 LCD controller 3 Serial communication unit 4 Serial communication unit 5 I2C / SPI conversion circuit 51 Frequency dividing circuit 52 SPI CLK / CS generation circuit 53 Register 6 LCD (liquid crystal unit)
7 LCD driver 100 Mobile terminal 101 Lower casing 102 Upper casing 103 Interface

Claims (7)

In a mobile terminal comprising a first housing and a second housing that freely engages with the first housing,
The first casing is provided with main control means, the second casing is provided with conversion means and display means,
The main control means transmits display control data for the display means to the conversion means via a transmission path between cases,
The conversion means converts the received display control data into an LCD control transmission line format and transmits it to the display means through the LCD control transmission line,
The mobile terminal according to claim 1, wherein the display means performs LCD display control according to display control data in the LCD control transmission line format. The inter-case transmission path is an I2C bus,
The LCD control transmission line is an SPI signal transmission line including an SPI clock and SPI data.
The conversion means creates the SPI clock based on the clock present on the second housing side, and transmits the received display control data to the display means as SPI data in the SPI signal format synchronized with the SPI clock. The mobile terminal according to claim 1.   The frequency of the SPI clock is a frequency at which the transmission period of display control data transmitted from the conversion means to the display means in synchronization with the SPI clock is sufficiently smaller than the period of the display control data group. The mobile terminal according to claim 2.   3. The SPI signal according to claim 2, wherein the SPI signal is an SPI clock, SPI data, and an SPI chip select, and the conversion unit creates the SPI clock, the SPI data, and the SPI chip select by hardware processing. Mobile device. 3. The mobile terminal according to claim 2, wherein the display unit is in an active state during transmission of the SPI signal, and the display unit is in a sleep state during a transmission off period of the SPI signal. 3. The mobile terminal according to claim 2, wherein the output level of the output transistor of the SPI signal of the conversion means is a level at which a low current consumption occurs during the transmission off period of the SPI signal. In a mobile terminal comprising a first housing and a second housing that freely engages with the first housing,
The first casing is provided with main control means, and the second casing is provided with I / O means and display means,
The main control means controls the I / O means by an I2C bus and transmits display control data in the SPI signal format from the I / O means to the display means through an SPI signal transmission path.
The portable terminal characterized in that the display means performs LCD display control according to display control data of the SPI signal transmission path.

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