CN109584825B - Display driving assembly and display device - Google Patents
Display driving assembly and display device Download PDFInfo
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- CN109584825B CN109584825B CN201811586506.XA CN201811586506A CN109584825B CN 109584825 B CN109584825 B CN 109584825B CN 201811586506 A CN201811586506 A CN 201811586506A CN 109584825 B CN109584825 B CN 109584825B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The application discloses display driving subassembly and display device, wherein, display driving subassembly is including the multistage drive circuit that cascades the setting, and drive circuit includes pre-charge sub-circuit, and pre-charge sub-circuit sets up to the level of pre-charging that produces first preset scanning signal according to this level of scanning signal, and pre-charge sub-circuit includes first edge trigger, and the pulse input end of first edge trigger is connected in this level of scanning line, and the intrinsic output or the inverting output of first edge trigger are connected in first preset scanning line. The technical scheme of the application provides the display device who charges evenly, has improved the display effect.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to a display driving assembly and a display device.
Background
The statements herein merely provide background information related to the present application and may not necessarily constitute prior art. Display devices have become important display platforms in the fields of modern information technology and the like, and have been widely applied to products such as video signals and the like. In a display device, a driving signal is generated according to an image signal to be displayed, and a progressive scanning driving method is generally adopted to drive a display panel in the display device.
However, as the resolution of the display panel is higher and higher, the charging is not uniform, especially the far end of the display panel is not saturated.
Disclosure of Invention
The main purpose of this application is to provide a display drive assembly, has realized the even display device that charges, has improved the display effect.
In order to achieve the above object, the display driving assembly provided by the present application includes a plurality of stages of driving circuits cascaded to be set, each of the driving circuits includes a pre-charge sub-circuit, the pre-charge sub-circuit is set to be a pre-charge level for generating a first preset stage scanning signal according to a current stage scanning signal, the pre-charge sub-circuit includes a first edge trigger, a pulse input end of the first edge trigger is connected to the current stage scanning line, and an intrinsic output end or an inverted output end of the first edge trigger is connected to the first preset stage scanning line.
Optionally, the pre-charge sub-circuit includes a switching device, a gate electrode of the switching device is connected to the intrinsic output end or the inverted output end of the first edge trigger, a source electrode of the switching device is connected to a high-level signal source, and a drain electrode of the switching device is connected to the first preset-level scan line.
Optionally, the first preset-level scanning line is a last two-level scanning line of the current-level scanning line.
Optionally, the pre-charge sub-circuit comprises a first inverter, an input terminal of the first inverter is connected to the intrinsic output terminal of the first edge flip-flop, and an output terminal of the first inverter is connected to the control input terminal of the first edge flip-flop; the switching device is a negative metal oxide semiconductor thin film transistor, and the first edge trigger is a rising edge trigger.
Optionally, the pre-charge sub-circuit includes a first one-way conduction device, an anode of the first one-way conduction device is connected to the output end of the first inverter, and a cathode of the first one-way conduction device is connected to the gate electrode of the switching device.
Optionally, the driving circuit includes a charging sub-circuit, the charging sub-circuit is configured to generate a turn-on level of a second preset-level scanning signal according to the current-level scanning signal, the charging sub-circuit includes a second edge trigger, a pulse input end of the second edge trigger is connected to the current-level scanning line, and an intrinsic output end or an inverted output end of the second edge trigger is connected to the second preset-level scanning line.
Optionally, the second preset-level scan line is a next-level scan line of the current-level scan line.
Optionally, the charging sub-circuit includes a second inverter, an input end of the second inverter is connected to an intrinsic output end of the second edge flip-flop, an output end of the second inverter is connected to a control input end of the second edge flip-flop, and an output end of the second inverter is connected to the next-stage scan line; wherein the second edge flip-flop is a falling edge flip-flop.
Optionally, the charging sub-circuit includes a second one-way conduction device, an anode of the second one-way conduction device is connected to the next-stage scan line, and a cathode of the second one-way conduction device is connected to the pulse input end of the second edge trigger.
In order to achieve the above object, the present application further provides a display device, which includes a display panel and a display driving assembly, wherein the display panel includes a plurality of scan lines; the display driving assembly comprises a multistage driving circuit which is arranged in a cascade mode, the driving circuit comprises a pre-charging sub-circuit, the pre-charging sub-circuit is arranged to be a pre-charging flat which generates a first preset scanning signal according to the current scanning signal, the pre-charging sub-circuit comprises a first edge trigger, the pulse input end of the first edge trigger is connected to the current scanning line, and the intrinsic output end or the reverse phase output end of the first edge trigger is connected to the first preset scanning line.
In the technical scheme of this application, the display driver component is including the multistage drive circuit that cascades the setting, and drive circuit includes pre-charge sub-circuit, and pre-charge sub-circuit sets up to the level of pre-charging that produces first predetermined level scanning signal according to this level scanning signal, and pre-charge sub-circuit includes first edge trigger, and the pulse input end of first edge trigger is connected in this level scanning line, and the intrinsic output or the inverting output of first edge trigger are connected in first predetermined level scanning line. Under the effect of the first edge trigger, when the scanning signal of the current stage on the scanning line of the current stage is at a rising edge or a falling edge, the intrinsic output end or the inverted output end of the first edge trigger outputs a corresponding level, a precharge level is directly generated or generated through conversion of other components in the precharge sub-circuit, and the scanning line of the first preset stage is precharged, so that the far end of the display panel is prevented from being insufficiently charged, the charging uniformity is improved, and the display effect of the display device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram of an exemplary display device;
FIG. 2 is a schematic diagram of a display driving device and a scan line in an embodiment of the display apparatus of the present application;
fig. 3 is a timing diagram of the present-stage scan signal, the next-stage scan signal and the next two-stage scan signal in fig. 2.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are referred to in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" appearing throughout is to include three juxtapositions, exemplified by "A and/or B" including either scheme A, or scheme B, or a scheme in which both A and B are satisfied. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
Hereinafter, the technical solution of the present application will be described in detail by taking a liquid crystal display device as an example, and for other types of display devices, those skilled in the art may refer to the technical solution described hereinafter to improve the corresponding display driving components.
In one example, as shown in fig. 1, the lcd device includes a display driving assembly 100 ' and a display panel 200 ', wherein the display driving assembly 100 ' includes a Gate-chip on film (G-COF) 110 ' and a Source-chip on film (S-COF) 120 '; the display panel 200 ' has a display region 210 ' and a non-display region 220 '. The liquid crystal display device is further provided with a backlight module (not shown in the figure), and the backlight module is configured to generate relatively uniform backlight as a light source of the liquid crystal display device. The display panel 200 ' includes a plurality of pixels, a plurality of data lines, a plurality of scan lines, etc., wherein the plurality of pixels are disposed in the display region 210 ', and other related circuits, etc., are disposed in the non-display region 220 '. The pixels on the display panel 200' are generally arranged in a rectangular array, and the pixels include pixel electrodes and pixel switching devices. The pixel switching device is usually a Thin-film transistor (TFT), and under the action of a scanning signal on a scanning line, the TFT controls the data line to charge the corresponding pixel electrode, so as to form a voltage between the pixel electrode and the common electrode of the pixel capacitor, and control the deflection angle of the liquid crystal in the pixel. In general, the display panel 200' includes three pixels of red, green and blue pixels, and at least one of the red, green and blue pixels forms a pixel group, thereby displaying a color picture according to the spatial color mixing principle. Under the combined action of the scanning signals on the scanning lines and the data signals on the data lines, liquid crystals in the pixels deflect, the light transmittance is correspondingly modulated, and a certain gray scale is displayed by combining with backlight. In order to maintain the pixel level on the pixel electrode to secure the display effect, a storage capacitor or the like may be further provided in the pixel. The scan lines of the display panel 200 ' are connected to the G-COF110 ' of the display driving device 100 ' and operate under the action of the scan signals output from the G-COF110 ', and the data lines are connected to the S-COF120 ' of the display driving device 100 ' and operate under the action of the data signals output from the S-COF120 '. Of course, the display driving assembly 100' may further include a Printed Circuit Board (PCB), a timing control chip (TCON IC), and the like. In a large-sized display panel, in order to avoid the occurrence of charging unevenness, a plurality of G-COFs 110 ', i.e., G-COF 1111', G-COF2112 ', G-COF 3113' shown in fig. 1, etc., may be provided to charge different regions of the display panel, respectively. In order to ensure the effective transmission of large-scale display data, a plurality of S-COFs 120 ', namely S-COFs 1121 ', S-COFs 2122 ' and the like shown in FIG. 1, can be arranged to reduce the burden of each S-COF. However, the cost of the display device in this example is relatively high due to the high cost of G-COF and S-COF.
The application provides a display driving assembly, through set up the pre-charge sub-circuit in display driving assembly, realizes evenly charging to display panel to improve display effect.
In one embodiment of the present application, as shown in fig. 2, the display driving device includes a plurality of stages of driving circuits 110 arranged in a cascade, the driving circuit 110 includes a pre-charge sub-circuit 111, the pre-charge sub-circuit 111 is arranged to generate a pre-charge level of a first preset stage scanning signal according to the present stage scanning signal, the pre-charge sub-circuit 111 includes a first edge flip-flop D1, a pulse input terminal C of the first edge flip-flop D1 is connected to the present stage scanning line 210, and an intrinsic output terminal Q or an inverted output terminal of the first edge flip-flop D1
Connected to the first predetermined level scan line 210.
Specifically, the display driving components are arranged in cascade, and each stage of the driving circuit 110 is connected with the scanning line 210 and the adjacent stageOr several stages of scan lines 220, and the driving circuit 110 includes a pre-charge sub-circuit 111 to generate a pre-charge level of the next stage scan line under the control of the present stage scan signal on the present stage scan line, so as to pre-charge the next stage scan line in advance, thereby compensating for the problem of insufficient far-end charge in the display panel. In the present embodiment, the precharge sub-circuit 111 includes a first edge flip-flop D1, wherein the edge flip-flop can receive input data when a certain appointed transition (rising edge or falling edge) of a pulse arrives, and commonly used edge flip-flops include D flip-flops and the like. When the pulse input terminal C of the first edge flip-flop D1 receives the rising edge or the falling edge of the present stage scan signal, its intrinsic output terminal Q or the inverted output terminal Q
A level related to the level of the control input D will be output. By selecting the appropriate kind of first edge flip-flop D1, the intrinsic output Q or the inverted output can be set
The output level is directly used as the pre-charge level of the first preset level scanning line; or, the intrinsic output end Q or the inverted output end is converted by other components in the pre-charge sub-circuit 111
The output level is converted into a pre-charge level of the first preset-level scanning line, and pre-charge of the first preset-level scanning line is achieved. The series relationship between the first preset scan line and the current scan line is related to the timing relationship between the signals in the driving circuit 110. The first edge flip-flop D1 can be a rising edge flip-flop or a falling edge flip-flop, and has an intrinsic output Q and an inverted output
The output signals are mutually inverted.
In the present embodiment, the display driving assembly includes a plurality of stages of driving circuits 110 arranged in a cascade, the driving circuits 110 include a pre-charge sub-circuit 111, and the pre-charge sub-circuit 111 is arrangedTo generate the precharge level of the first preset stage scan signal according to the present stage scan signal, the precharge sub-circuit 111 includes a first edge flip-flop D1, a pulse input terminal C of the first edge flip-flop D1 is connected to the present stage scan line, and an intrinsic output terminal Q or an inverted output terminal of the first edge flip-flop D1
Connected to the first preset scanning line. Under the action of the first edge flip-flop D1, when the scan signal of the current stage on the scan line of the current stage is at the rising edge or the falling edge, the intrinsic output terminal Q or the inverted output terminal of the first edge flip-flop D1
The corresponding level of output, directly produce the precharge tie or through the conversion of other components and parts in the pre-charge sub-circuit produce the precharge tie, to first predetermine a scanning line precharge to avoid display panel's distal end to charge inadequately, improve the homogeneity of charging, thereby improve display device's display effect, and, the circuit structure of this application technical scheme is simple, helps reducing display device's cost.
As shown in fig. 2, the relationship between the nth stage driving circuit 110 and the nth stage scan line Gate line (N), the nth +1 th stage scan line Gate line (N +1), and the N +2 th stage scan line Gate line (N +2) will be described in detail hereinafter as an example, that is, the last two stage scan line Gate line (N +2) of the present stage scan line Gate line (N) may be used as the first preset stage scan line, and when it is necessary to precharge the other stage scan lines, the signal timings and the connection manner between the driving circuit 110 and the scan lines 120 may be adaptively adjusted.
Alternatively, as shown in fig. 2, the pre-charge sub-circuit 111 includes a switching device M having a gate electrode connected to the intrinsic output terminal Q or the inverted output terminal of the first edge flip-flop D1
The source electrode of the switching device M is connected to the high-level signal source, and the drain electrode of the switching device M is connected to the first preset-level scanning line.
As shown in FIGS. 2 and 3, when the first edge flip-flop D1 has either the intrinsic Q or the inverted Q output
When the switching device M is controlled to be in the on state, the source electrode and the drain electrode of the switching device M are communicated, so that the high level Vgh' generated by the high level signal source can be output to the Gate line (N +2), and the Gate line (N +2) is precharged, so that the level of the scanning signal G (N +2) on the Gate line (N +2) reaches at least the next high level state in advance. Further, when the Gate line (N +2) itself is in the on state, the scan signal G (N +2) reaches a high level state meeting the display driving requirement to drive the display of the corresponding pixel. Wherein, the source electrode of the switching device M can be connected with a constant voltage high level signal source; in this arrangement, it is necessary to determine the number of stages of the scanning lines connected to the source electrode of the switching device M in accordance with the timing relationship between the signals. In fig. 3, the period of each scanning signal corresponds to one frame duration of a display screen, and generally, the display is realized by a progressive driving method.
In a specific example, as shown in fig. 2, the pre-charge sub-circuit 111 includes a first inverter B1, an input terminal of the first inverter B1 is connected to the intrinsic output terminal Q of the first edge flip-flop D1, and an output terminal of the first inverter B1 is connected to the control input terminal D of the first edge flip-flop D1; the switching device M is a negative Metal Oxide Semiconductor thin film transistor (NMOS TFT), and the first edge trigger D1 is a rising edge trigger.
As shown in fig. 3, when the nth stage scan signal g (N) is converted from a low state to a high state, since the first edge flip-flop D1 is a rising edge flip-flop, specifically, a rising edge flip-flop D, and functions to assign the logic level of the control input terminal D to the intrinsic output terminal Q when the pulse input terminal C receives the rising edge of the scan signal g (N), the input terminal of the first inverter B1 is in a low state. When the switching device M is turned on by the inversion of the first inverter B1 because the Gate thereof is at a high level, the high level signal source outputs a high level Vgh' to the Gate line (N +2) connected to the drain electrode of the switching device M, and precharges the Gate line (N + 2).
Alternatively, as shown in fig. 2, the pre-charge sub-circuit 111 includes a first unidirectional conducting device a1, an anode of the first unidirectional conducting device a1 is connected to the output terminal of the first inverter B1, and a cathode of the first unidirectional conducting device a1 is connected to the gate electrode of the switching device M.
The first unidirectional-conduction device a1 may be a diode or the like having unidirectional-conduction characteristics. When the output terminal of the first inverter B1 is in a high state and the Gate electrode of the switching device M is in a low state, the first one-way conduction device a1 is turned on, so that the Gate electrode of the switching device M is turned to a high state to be turned on, thereby precharging the Gate line (N + 2). When the output end of the first inverter B1 is in a low level state and the Gate electrode of the switching device M is in a high level state, the first one-way conducting device a1 is turned off in the reverse direction, so as to avoid display errors caused by the influence of an interference signal on the Gate line (N + 2).
In the above embodiment of the present application, as shown in fig. 2, the driving circuit includes a charging sub-circuit 112, the charging sub-circuit 112 is configured to generate the on level of the second preset-level scan signal according to the present-level scan signal, the charging sub-circuit 112 includes a second edge flip-flop D2, a pulse input terminal C of the second edge flip-flop D2 is connected to the present-level scan line, and an intrinsic output terminal Q or an inverted output terminal of the second edge flip-flop D2
Connected to the second preset scanning line.
Specifically, the charging sub-circuit 112 includes a second edge flip-flop D2, and when the pulse input terminal C of the second edge flip-flop D2 receives the rising edge or the falling edge of the present stage scan signal, its intrinsic output terminal Q or the inverted output terminal Q
Level of outputIn relation to the level of the control input D. By selecting the appropriate kind of second edge flip-flop D2, the intrinsic output Q or the inverted output can be set
The output level is directly used as the starting level of the second preset level scanning line, and each pixel connected to the second preset level scanning line is controlled to be started to display an image; alternatively, the intrinsic output Q or the inverse output Q is converted by other components in the charging sub-circuit 112
And converting the output level into a starting level of a second preset level scanning line to realize the display of an image. The series relationship between the second predetermined scan line and the current scan line is related to the timing relationship between the signals in the driving circuit 110. The second edge flip-flop D2 can be a rising edge flip-flop or a falling edge flip-flop, and has an intrinsic output Q and an inverted output
The output signals are mutually inverted.
As shown in fig. 2, the following scan line Gate line (N) with the second predetermined scan line as the current scan line Gate line (N) is taken as an example for detailed description, and when the on-level of the other scan lines needs to be generated, the signal timing and the connection manner between the driving circuit 110 and the scan lines 120 may be adaptively adjusted.
Alternatively, as shown in fig. 2, the charge sub-circuit 112 includes a second inverter B2, an input terminal of the second inverter B2 is connected to the intrinsic output terminal Q of the second edge flip-flop D2, an output terminal of the second inverter B2 is connected to the control input terminal D of the second edge flip-flop D2, and an output terminal of the second inverter B2 is connected to the scan line of the next stage; the second edge flip-flop D2 is a falling edge flip-flop.
As shown in fig. 2 and fig. 3, when the nth stage scan signal g (N) is converted from a low state to a high state, since the second edge flip-flop D2 is a falling edge flip-flop, specifically, a falling edge D flip-flop, which functions to assign the logic level of the control input terminal D to the intrinsic output terminal Q when the pulse input terminal C receives the falling edge of the scan signal g (N), the input terminal of the second inverter B2 is in a low state. Through the inversion of the second inverter B2, the on level of the current-stage scanning signal g (N) is output to the Gate line (N +1) connected to the output terminal of the second inverter B2, and each pixel line connected to the Gate line (N +1) is turned on, thereby displaying a certain image. In general, the turn-on level Vgh of the scan signal may be greater than or equal to the precharge level Vgh' output from the high-level signal source.
Alternatively, as shown in fig. 2, the charging sub-circuit 112 includes a second one-way conduction device a2, an anode of the second one-way conduction device a2 is connected to the last-stage scan line Gate line (N +1), and a cathode of the second one-way conduction device a2 is connected to the pulse input terminal C of the second edge flip-flop D2.
Wherein the second unidirectional conducting device a2 may be a diode or the like with unidirectional conducting characteristics. When the output terminal of the second inverter B2 is in a high state and the pulse input terminal C of the second edge flip-flop D2 is in a low state, the second unidirectional conducting device a2 is turned on to ensure the normal operation of the driving circuit 110. When the output terminal of the second inverter B2 is in a low state and the pulse input terminal C of the second edge flip-flop D2 is in a high state, the second unidirectional-conducting device a2 is turned off in the reverse direction to avoid mutual interference between signals.
As shown in fig. 2, the present application further provides a display device, which includes a display panel and a display driving assembly, wherein the display panel includes a plurality of scan lines 210, and the specific structure of the display driving assembly refers to the above embodiments, which is not described herein again.
The above description is only an alternative embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that can be directly or indirectly applied to other related fields without departing from the spirit of the present application are intended to be included in the scope of the present application.
Claims (7)
1. A display driver assembly, comprising a plurality of driving circuits arranged in a cascade, the driving circuits comprising:
the pre-charging sub-circuit is set to generate a pre-charging level of a first preset-level scanning line according to a current-level scanning signal and comprises a first edge trigger, wherein the pulse input end of the first edge trigger is connected to the current-level scanning line, and the intrinsic output end or the inverted output end of the first edge trigger is connected to the first preset-level scanning line; the first preset-level scanning line is a last two-level scanning line of the current-level scanning line;
the drive circuit further includes:
the charging sub-circuit is set to generate the starting level of a second preset scanning line according to a current scanning signal and comprises a second edge trigger, the pulse input end of the second edge trigger is connected to the current scanning line, and the intrinsic output end or the inverted output end of the second edge trigger is connected to the second preset scanning line; and the second preset scanning line is a next scanning line of the current level.
2. The display driving assembly of claim 1, wherein the pre-charge sub-circuit comprises:
and a gate electrode of the switching device is connected to the intrinsic output end or the inverted output end of the first edge trigger, a source electrode of the switching device is connected to a high-level signal source, and a drain electrode of the switching device is connected to the first preset-level scanning line.
3. The display driving assembly of claim 2, wherein the pre-charge sub-circuit comprises:
the input end of the first inverter is connected to the intrinsic output end of the first edge trigger, and the output end of the first inverter is connected to the control input end of the first edge trigger;
the switching device is a negative metal oxide semiconductor thin film transistor, and the first edge trigger is a rising edge trigger.
4. A display driving assembly according to claim 3, wherein the pre-charge sub-circuit comprises:
and the anode of the first one-way conduction device is connected to the output end of the first phase inverter, and the cathode of the first one-way conduction device is connected to the gate electrode of the switching device.
5. The display drive assembly of claim 1, wherein the charging circuit comprises:
the input end of the second inverter is connected to the intrinsic output end of the second edge trigger, the output end of the second inverter is connected to the control input end of the second edge trigger, and the output end of the second inverter is connected to the next-stage scanning line;
wherein the second edge flip-flop is a falling edge flip-flop.
6. The display drive assembly of claim 1, wherein the charging circuit comprises:
and the anode of the second one-way conduction device is connected to the rear-stage scanning line, and the cathode of the second one-way conduction device is connected to the pulse input end of the second edge trigger.
7. A display device, characterized in that the display device comprises:
a display panel including a plurality of scan lines; and the number of the first and second groups,
a display driver assembly according to any of claims 1 to 6.
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| CN114283758B (en) * | 2021-12-30 | 2023-01-10 | 惠科股份有限公司 | Display panel, pre-charging method of display panel and display device |
| CN115719585A (en) * | 2022-11-15 | 2023-02-28 | 武汉华星光电技术有限公司 | Display panel and display device |
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| CN105206247A (en) * | 2015-11-05 | 2015-12-30 | 京东方科技集团股份有限公司 | Gate driving circuit and driving method thereof as well as display device |
| CN105355176A (en) * | 2015-11-26 | 2016-02-24 | 深圳市华星光电技术有限公司 | Display panel and array gate driving circuit |
| CN107068094A (en) * | 2017-05-10 | 2017-08-18 | 厦门天马微电子有限公司 | Gate driving circuit, display panel, display device and driving method |
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2018
- 2018-12-24 CN CN201811586506.XA patent/CN109584825B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101136161A (en) * | 2006-08-30 | 2008-03-05 | 三星Sdi株式会社 | Display device, driving method and digital driving system |
| CN101783128A (en) * | 2010-04-02 | 2010-07-21 | 福州华映视讯有限公司 | Method for driving liquid crystal display |
| CN105206247A (en) * | 2015-11-05 | 2015-12-30 | 京东方科技集团股份有限公司 | Gate driving circuit and driving method thereof as well as display device |
| CN105355176A (en) * | 2015-11-26 | 2016-02-24 | 深圳市华星光电技术有限公司 | Display panel and array gate driving circuit |
| CN107068094A (en) * | 2017-05-10 | 2017-08-18 | 厦门天马微电子有限公司 | Gate driving circuit, display panel, display device and driving method |
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| CN109584825A (en) | 2019-04-05 |
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