CN114283758B - Display panel, pre-charging method of display panel and display device - Google Patents
Display panel, pre-charging method of display panel and display device Download PDFInfo
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- CN114283758B CN114283758B CN202111648644.8A CN202111648644A CN114283758B CN 114283758 B CN114283758 B CN 114283758B CN 202111648644 A CN202111648644 A CN 202111648644A CN 114283758 B CN114283758 B CN 114283758B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a display panel, a pre-charging method of the display panel and a display device, wherein the display panel comprises at least one pre-charging circuit, and the pre-charging circuit is simultaneously connected with at least 3 rows of scanning lines; the pre-charging circuit comprises a pulse trigger, a first switch and a second switch, wherein the first switch and the second switch are respectively connected to different output ends of the pulse trigger, the types of the first switch and the second switch are different, and when the nth row of scanning lines receive scanning signals, the pulse trigger controls the first switch and the second switch to be switched on, so that pixels corresponding to the nth + a row of scanning lines and the nth + b row of scanning lines are pre-charged; wherein n, a and b are natural numbers more than or equal to 1, and a is not equal to b. Through the design, the pixels in the display panel can be precharged, the response time of liquid crystal is shortened, and the charging rate of the pixels is improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel, a precharge method for the display panel, and a display device.
Background
The liquid crystal display panel mainly comprises an array substrate and a color film substrate which are oppositely boxed together and clamp liquid crystal therebetween, wherein a scanning line, a data line, a pixel electrode and a thin film transistor are formed on the array substrate, a common electrode is formed on the color film substrate, and the pixel electrode and the corresponding common electrode form a pixel. Each pixel electrode is controlled by a thin film transistor, when the thin film transistor is turned on, the pixel is charged in the turn-on time, and after the thin film transistor is turned off, the pixel voltage is maintained until the pixel is charged again in the next scanning.
With the development of display technology, the scanning frequency is higher and higher, which results in insufficient charging time for pixels; the liquid crystal is driven by alternating current, namely, the polarity of the pixel voltage of the pixel charged currently is opposite to the polarity of the pixel voltage of the last frame stored by the pixel, and if the charging time of the pixel is insufficient, the response time of the liquid crystal is prolonged, and the picture display is influenced.
Disclosure of Invention
The present application provides a display panel, a pre-charging method of the display panel, and a display device, which pre-charges pixels in the display panel, so as to shorten the response time of liquid crystal and improve the charging rate of the pixels.
The application discloses a display panel, which comprises a plurality of scanning lines arranged in parallel and at least one pre-charging circuit, wherein the pre-charging circuit is simultaneously connected with at least 3 rows of scanning lines; the pre-charging circuit comprises a pulse trigger, a first switch and a second switch, the pulse trigger comprises a first input end, a second input end, a first output end and a second output end, the first input end is connected with the nth row of scanning lines, the second input end is connected with a first high level signal line, and the first output end and the second output end output opposite level signals;
the first switch is an N-type switch, a base electrode of the first switch is connected with the first output end, a collector electrode of the first switch is connected with a second high-level signal line, and an emitter electrode of the first switch is connected with the N + a-th row scanning line; the second switch is a P-type switch, the base of the second switch is connected with the second output end, the collector of the second switch is connected with a third high-level signal line, and the emitter of the second switch is connected with the (n + b) th row scanning line; when the nth row of scanning lines receives scanning signals, the pulse trigger controls the first switch and the second switch to be opened, so that pixels corresponding to the (n + a) th row of scanning lines and the (n + b) th row of scanning lines are precharged; wherein n, a and b are natural numbers more than or equal to 1, and a is not equal to b.
Optionally, a is equal to 1.
Optionally, the precharge circuit further includes a first diode, a second diode, a third diode, and a third switch, an anode of the first diode is connected to the nth row scan line, and a cathode of the first diode is connected to the first input terminal; the anode of the second diode is connected with the (n + 1) th row of scanning lines, and the cathode of the second diode is connected with the first input end; the anode of the third diode is connected with the junction of the anode of the second diode and the n +1 th row of scanning lines, and the cathode of the third diode is connected with the emitter of the first switch;
the third switch is an N-type switch, the base of the third switch is connected with the second output end, the collector of the third switch is connected with a fourth high-level signal line, and the emitter of the third switch is connected with the N + c-th row scanning line; when the nth row of scanning lines receive scanning signals, the pulse trigger controls the first switch and the second switch to be opened, so that pixels corresponding to the (n + a) th row of scanning lines and the (n + b) th row of scanning lines are precharged; when the (n + 1) th row of scanning lines receives scanning signals, the pulse trigger controls the third switch to be opened, so that pixels corresponding to the (n + c) th row of scanning lines are precharged; wherein c is a natural number greater than 1, and c is not equal to b.
Optionally, the precharge circuit further includes a first diode, a second diode, a third diode, and a third switch, an anode of the first diode is connected to the nth row scan line, and a cathode of the first diode is connected to the first input terminal; the anode of the second diode is connected with the (n + 1) th row scanning line, and the cathode of the second diode is connected with the first input end; the anode of the third diode is connected with the junction of the anode of the second diode and the (n + 1) th row of scanning lines, and the cathode of the third diode is connected with the emitter of the first switch;
the third switch is a P-type switch, the base of the third switch is connected with the first output end, the collector of the third switch is connected with a fourth high-level signal line, and the emitter of the third switch is connected with the n + c-th row scanning line; when the nth row of scanning lines receives scanning signals, the pulse trigger controls the first switch and the second switch to be opened, so that pixels corresponding to the (n + a) th row of scanning lines and the (n + b) th row of scanning lines are precharged; when the (n + 1) th row of scanning lines receives scanning signals, the pulse trigger controls the third switch to be opened, so that pixels corresponding to the (n + c) th row of scanning lines are precharged; wherein c is a natural number greater than 1, and c is not equal to b.
Optionally, the precharge circuit further includes a first diode, a second diode, a third switch, and a fourth switch, an anode of the first diode is connected to the nth row scan line, and a cathode of the first diode is connected to the first input terminal; the anode of the second diode is connected with the (n + 1) th row scanning line, and the cathode of the second diode is connected with the first input end; the anode of the third diode is connected with the junction of the anode of the second diode and the n +1 th row of scanning lines, and the cathode of the third diode is connected with the emitter of the first switch;
the third switch is an N-type switch, the base of the third switch is connected with the second output end, the collector of the third switch is connected with a fourth high-level signal line, and the emitter of the third switch is connected with the N + c-th row scanning line; the fourth switch is a P-type switch, the base of the fourth switch is connected with the first output end, the collector of the fourth switch is connected with a fifth high-level signal line, and the emitter of the fourth switch is connected with the n + d-th row scanning line; when the nth row of scanning lines receives scanning signals, the pulse trigger controls the first switch and the second switch to be opened, so that pixels corresponding to the (n + a) th row of scanning lines and the (n + b) th row of scanning lines are precharged; when the (n + 1) th row of scanning lines receives scanning signals, the pulse trigger controls the third switch and the fourth switch to be opened, so that pixels corresponding to the (n + c) th row of scanning lines and the (n + d) th row of scanning lines are precharged; wherein c and d are natural numbers larger than 1, and b, c and d are different from each other.
Optionally, the n + a row of scanning lines, the n + b row of scanning lines, the n + c row of scanning lines, and the n + d row of scanning lines are adjacent scanning lines.
Optionally, b is equal to 3, c is equal to 4, and d is equal to 2; the first switch and the fourth switch are arranged in parallel, and the second switch and the third switch are arranged in parallel.
The application also discloses a display panel pre-charging method, which is used for pre-charging the display panel and comprises the following steps:
the first high-level signal line, the second high-level signal line and the third high-level signal line are conducted, so that a second input end of a pulse trigger, a collector of a first switch and a collector of a second switch in the pre-charging circuit are all connected with high-level signals;
the nth row of scanning lines receive scanning signals and charge pixels corresponding to the nth row of scanning lines;
a first input end of a pulse trigger in the pre-charging circuit receives a high-level signal, and a first output end and a second output end of the trigger output opposite signals, so that a first switch and a second switch are opened; and
the scanning line of the n + a row receives a high-level signal of the second high-level signal line, and pixels corresponding to the scanning line of the n + a row are precharged; the n + b row of scanning lines receive high-level signals of the third high-level signal line and pre-charge pixels corresponding to the n + b row of scanning lines;
wherein n, a and b are natural numbers more than or equal to 1, and a is not equal to b.
Optionally, the precharge circuit further includes a first diode, a second diode, a third switch, and a fourth switch, an anode of the first diode is connected to the nth row scan line, and a cathode of the first diode is connected to the first input terminal; the anode of the second diode is connected with the (n + 1) th row scanning line, and the cathode of the second diode is connected with the first input end; the anode of the third diode is connected with the junction of the anode of the second diode and the (n + 1) th row of scanning lines, and the cathode of the third diode is connected with the emitter of the first switch;
the first switch and the third switch are N-type switches, the second switch and the fourth switch are P-type switches, the base of the third switch is connected with the second output end, the collector of the third switch is connected with a fourth high-level signal line, and the emitter of the third switch is connected with an N + c row scanning line; the base electrode of the fourth switch is connected with the first output end, the collector electrode of the fourth switch is connected with a fifth high-level signal line, and the emitter electrode of the fourth switch is connected with the n + d-th row scanning line;
the n + a row of scanning lines receive high-level signals of the second high-level signal line and pre-charge pixels corresponding to the n + a row of scanning lines; after the step of receiving the high level signal of the third high level signal line by the n + b-th row of scanning lines and pre-charging the pixels corresponding to the n + b-th row of scanning lines, the method also comprises the following steps:
the n +1 th row of scanning lines receives the scanning signals and charges the pixels corresponding to the n +1 th row of scanning lines;
a first input end of the pulse trigger receives a high-level signal through the second diode, and a first output end and a second output end of the pulse trigger output opposite signals, so that a third switch and a fourth switch are opened; and
the n + c row of scanning lines receive high-level signals of the fourth high-level signal line and pre-charge pixels corresponding to the n + c row of scanning lines; the n + d th row of scanning lines receive high-level signals of the fifth high-level signal line and pre-charge pixels corresponding to the n + d th row of scanning lines;
wherein a equals 1, b equals 3, c equals 4, and d equals 2.
The application also discloses a display device, including backlight unit and as above display panel, backlight unit does display panel provides backlight.
This application is through add the precharge circuit in display panel, utilize the principle of two reverse output ends in the pulse trigger, combine the first switch and the second switch of two kinds of different grade types, when making to the pixel that nth row scanning line corresponds charges, the pulse trigger opens first switch and second switch simultaneously, carry out the precharge to the pixel that nth + a row scanning line and nth + b row scanning line correspond, when nth + a row scanning line and nth + b row scanning line receive scanning signal like this, after combining the voltage of preceding precharge process, can adjust charging voltage to higher level, thereby accelerate the response time of liquid crystal, improve the charge rate of pixel, guarantee the display effect of picture. Moreover, the voltage for precharging the pixels corresponding to the scanning line of the n + a row and the scanning line of the n + b row is from a high-level signal line instead of the voltage in the scanning line, so that the problem of voltage reduction corresponding to the scanning line of the n + a row caused by voltage division is avoided.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of a display device provided herein;
FIG. 2 is a flowchart illustrating a pre-charging method for a display panel according to the present disclosure;
FIG. 3 is a schematic diagram of a display panel circuit according to a first embodiment of the present disclosure;
FIG. 4 is a diagram of a display panel circuit according to a second embodiment of the present application;
FIG. 5 is a schematic diagram of a display panel circuit according to a third embodiment of the present application;
FIG. 6 is a diagram of a display panel circuit according to a fourth embodiment of the present application;
FIG. 7 is a flowchart illustrating a precharge method of a display panel according to a fourth embodiment of the present application.
10, a display device; 100. a display panel; 110. scanning a line; 120. a first high-level signal line; 130. a second high-level signal line; 140. a third high-level signal line; 150. a fourth high-level signal line; 160. a fifth high-level signal line; 200. a precharge circuit; 210. a pulse trigger; 211. a first input terminal; 212. a second input terminal; 213. a first output terminal; 214. a second output terminal; 220. a first switch, 230, a second switch; 240. a third switch; 250. a fourth switch; 260. a first diode; 270. a second diode; 280. a third diode; 300. a backlight module is provided.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
The present application is described in detail below with reference to the figures and alternative embodiments.
As shown in fig. 1 and fig. 3, the present application discloses a display device 10, where the display device 10 includes a backlight module 300 and a display panel 100, and the backlight module 300 provides backlight for the display panel 100. The display panel 100 includes a pre-charge circuit 200, specifically, the display panel 100 includes a plurality of scan lines 110 arranged in parallel and at least one pre-charge circuit 200, and the pre-charge circuit 200 is simultaneously connected to at least 3 rows of scan lines 110; the precharge circuit 200 includes a pulse flip-flop 210, a first switch 220 and a second switch 230, the pulse flip-flop 210 includes a first input terminal 211, a second input terminal 212, a first output terminal 213 and a second output terminal 214, the first input terminal 211 is connected to the nth row scan line 110, the second input terminal 212 is connected to the first high level signal line 120, and the first output terminal 213 and the second output terminal 214 output opposite level signals.
The first switch 220 is an N-type switch, a base of the first switch 220 is connected to the first output terminal 213, a collector of the first switch 220 is connected to the second high-level signal line 130, and an emitter of the first switch 220 is connected to the N + a-th row scan line 110; the second switch 230 is a P-type switch, a base of the second switch 230 is connected to the second output terminal 214, a collector of the second switch 230 is connected to the third high-level signal line 140, and an emitter of the second switch 230 is connected to the n + b-th row scan line 110; when the nth row of scan lines 110 receives a scan signal, the pulse trigger 210 controls the first switch 220 and the second switch 230 to be opened, so that the pixels corresponding to the nth + a row of scan lines 110 and the nth + b row of scan lines 110 are precharged; wherein n, a and b are natural numbers more than or equal to 1, and a is not equal to b.
When a row of pixels are charged, at least two rows of pixels can be precharged, the precharge circuit 200 is additionally arranged in the display panel 100, the principle of two reverse output ends in the pulse trigger 210 is utilized, and the first switch 220 and the second switch 230 of two different types are combined, so that when the pixels corresponding to the nth row of scanning lines 110 are charged, the pulse trigger 210 simultaneously turns on the first switch 220 and the second switch 230, and precharges the pixels corresponding to the (n + a) th row of scanning lines 110 and the (n + b) th row of scanning lines 110, therefore, when the (n + a) th row of scanning lines 110 and the (n + b) th row of scanning lines 110 receive scanning signals, the charging voltage can be adjusted to a higher level after the voltage in the previous precharge process is combined, the response time of liquid crystals is shortened, the charging rate of the pixels is improved, and the display effect of a picture is ensured. Moreover, the voltage for precharging the pixels corresponding to the n + a row scanning line 110 and the n + b row scanning line 110 comes from a high-level signal line instead of the voltage in the scanning line 110, thereby avoiding the problem of voltage reduction corresponding to the n + a row scanning line 110 caused by voltage division.
Specifically, the pulse trigger 210 may be a T-type trigger or a T-type leading edge pulse trigger, and the specific working principle thereof is as follows: when the gate driver chip outputs the CLK signal to the nth row scan line 110, the first input terminal 211 of the pulse flip-flop 210 receives the CLK signal, the input signal T =1, the present state and the next state of the pulse flip-flop 210 are opposite, that is, the states of the first output terminal 213 and the second output terminal 214 are opposite, at this time, the signal output by the first output terminal 213 is 1 or 0, the signal output by the second output terminal 214 is 0 or 1, and the first output terminal 213 and the second output terminal 214 can only open different types of switches, so as to precharge the pixels corresponding to the n + a row scan line 110 and the n + b row scan line 110.
The first high-level signal line 120 may be externally connected to a power supply, or may be directly connected to a working voltage vdd inside the display panel 100; the second high-level signal line 130 and the third high-level signal line 140 may be connected to an external power source, or may be connected to a gate-on signal line VGH in the display panel 100.
The pre-charging circuit 200 can be implemented in a driving chip to reduce the frame of the display panel 100, and also avoid the problem that the structure of the display panel 100 is complex due to a circuit with a complex structure. Furthermore, by the precharge circuit 200 built inside the driver chip, a peripheral circuit can be provided, and the operating time of the pulse flip-flop 210 can be adjusted by adjusting Vdd. Meanwhile, the precharge circuit 200 may be implemented with or without an upper device. In addition, by adjusting Vdd, precharging can be carried out on some pictures instead of precharging all the pictures, so that more using requirements are met.
The present invention is applicable not only to a dot inversion driving method but also to a column inversion driving method or other inversion driving methods.
Correspondingly, as shown in fig. 2, the present application further discloses a display panel pre-charging method, for pre-charging the display panel 100, including the steps of:
s1: conducting a first high-level signal line, a second high-level signal line and a third high-level signal line to enable a second input end of a pulse trigger, a collector of a first switch and a collector of a second switch in the pre-charging circuit to be connected with high-level signals;
s2: the nth row of scanning lines receive scanning signals and charge pixels corresponding to the nth row of scanning lines;
s3: a first input end of a pulse trigger in the pre-charging circuit receives a high-level signal, and a first output end and a second output end of the trigger output opposite signals, so that a first switch and a second switch are opened;
s4: the scanning line of the n + a row receives a high-level signal of the second high-level signal line, and pixels corresponding to the scanning line of the n + a row are precharged; and the n + b row of scanning lines receive the high-level signal of the third high-level signal line and pre-charge the pixels corresponding to the n + b row of scanning lines.
The precharge circuit 200 in the present application may form a group of charging structures with three scan lines 110 and pixels thereof, where each three scan lines 110 corresponds to one precharge circuit 200; the precharge circuit 200 may further form a group of charging structures with the four scan lines 110 and the pixels thereof, and each four scan lines 110 corresponds to one precharge circuit 200; the precharge circuit 200 may further form a group of charging structures with five scan lines 110 and pixels thereof, and each five scan lines 110 corresponds to one precharge circuit 200, and the detailed implementation is described in the following embodiments.
The first embodiment is as follows:
as shown in fig. 3, the precharge circuit 200 is simultaneously connected to three scan lines 110, one precharge circuit 200 is corresponding to each three scan lines 110, and when the pixels corresponding to the first scan line 110 in the charging structure are charged, the pixels corresponding to the other two rows of scan lines 110 are simultaneously precharged.
In the present embodiment, the precharge circuit 200 can be connected to any three scan lines 110, i.e., a and b are natural numbers greater than or equal to 1, and a is not equal to b. When a is equal to 1 and b is equal to 2, the pre-charging circuit 200 is connected to three adjacent scan lines 110, and at this time, if the pixels corresponding to the scan line 110 in the current row are charged, the pixels corresponding to the scan lines 110 in the next two rows can be pre-charged at the same time; moreover, the arrangement of the pre-charge circuit 200 is regular, and one pre-charge circuit 200 is designed for every three scan lines 110, so that the design and installation of the pre-charge circuit 200 are facilitated, and errors are avoided.
Taking the display panel 100 with a resolution of 3840 × 2160 as an example, if the number of the active scan lines 110 is 2160, 2160/3=720 registers are required, and one precharge circuit 200 is disposed on each register.
The second embodiment:
as shown in fig. 4, unlike the first embodiment, the precharge circuit 200 is connected to four scan lines 110 at the same time, and each of the precharge circuits 200 corresponds to every four scan lines 110.
At this time, the precharge circuit 200 further includes a first diode 260, a second diode 270, a third diode 280, and a third switch 240, wherein an anode of the first diode 260 is connected to the nth scan line 110, and a cathode of the first diode 260 is connected to the first input terminal 211; the anode of the second diode 270 is connected to the (n + 1) th row of scan lines 110, and the cathode of the second diode 270 is connected to the first input end 211; the anode of the third diode 280 is connected to the junction between the anode of the second diode 270 and the n +1 th scan line 110, and the cathode of the third diode 280 is connected to the emitter of the first switch 220. When the nth row scan line 110 receives a scan signal, a high level from the nth row scan line 110 is supplied to the first input terminal 211 of the pulse flip-flop 210 through the first diode 260, but cannot be supplied to the (n + 1) th row scan line 110 through the second diode 270; when a =1, the scan line 110 in the n +1 row is the next scan line 110, and when the scan line 110 in the nth row receives the scan signal, the first switch 220 is turned on to precharge the pixel corresponding to the scan line 110 in the n +1 row, and at this time, due to the action of the third diode 280, the high-level signal does not enter the first input terminal 211 of the pulse trigger 210 through the second diode 270.
The third switch 240 is an N-type switch, a base of the third switch 240 is connected to the second output terminal 214, a collector of the third switch 240 is connected to the fourth high-level signal line 150, and an emitter of the third switch 240 is connected to the (N + c) -th row scan line 110; when the nth row of scan lines 110 receives a scan signal, the pulse trigger 210 controls the first switch 220 and the second switch 230 to be opened, so that pixels corresponding to the nth + a row of scan lines 110 and the nth + b row of scan lines 110 are precharged; when the scan line 110 in the (n + 1) th row receives a scan signal, the pulse trigger 210 controls the third switch 240 to be opened, so that the pixels corresponding to the scan line 110 in the (n + c) th row are precharged; wherein a, b and c are natural numbers which are more than or equal to 1, and a, b and c are not equal to each other.
Because the first output end 213 and the second output end 214 change the output state once every time the T-type flip-flop receives a pulse, that is, when the nth row scan line 110 receives a scan signal, the first input end 211 of the pulse flip-flop 210 receives a high level signal, at this time, the output signal of the first output end 213 is 1, and the output signal of the second output end 214 is 0, at this time, only the first switch 220 and the second switch 230 can be controlled to be turned on, so as to precharge the pixels corresponding to the nth + a row scan line 110 and the nth + b row scan line 110. When the scan line 110 in the (n + 1) th row receives a scan signal, the first input terminal 211 of the pulse flip-flop 210 also receives a high level signal, but the output signal of the first output terminal 213 is 0 at this time, and the output signal of the second output terminal 214 is 1 at this time, only the third switch 240 can be controlled to be opened at this time, so as to precharge the pixel corresponding to the scan line 110 in the (n + c) th row.
Compared with the first embodiment, the present embodiment can precharge all pixels corresponding to the scan lines 110 by using fewer precharge circuits 200, and the precharge effect is not reduced. At this time, also taking the display panel 100 with the resolution of 3840 × 2160 as an example, if the number of the effective scan lines 110 is 2160, 2160/4 =540registers are required, and one precharge circuit 200 is disposed on each register, so that the number of registers and precharge circuits 200 is advantageously reduced, and the cost is reduced.
In addition, the n + a-th row scan line 110, the n + b-th row scan line 110 and the n + c-th row scan line 110 may be any three scan lines 110, preferably, the three scan lines 110 are adjacent scan lines 110, specifically, a is equal to 1, b is equal to 2, and c is equal to 3, so as to facilitate circuit design.
Example three:
as shown in fig. 5, the precharge circuit 200 in this embodiment is connected to four scan lines 110 similarly to precharge the pixels corresponding to three rows of scan lines 110, and unlike the second embodiment, the precharge circuit 200 has a P-type switch 240, the base of the third switch 240 is connected to the first output terminal 213, the collector of the third switch 240 is connected to the fourth high-level signal line 150, and the emitter of the third switch 240 is connected to the n + c row scan line 110; when the nth row of scan lines 110 receives a scan signal, the pulse trigger 210 controls the first switch 220 and the second switch 230 to be opened, so that the pixels corresponding to the nth + a row of scan lines 110 and the nth + b row of scan lines 100 are precharged; when the scan line 110 in the (n + 1) th row receives a scan signal, the pulse trigger 210 controls the third switch 240 to be opened, so that the pixels corresponding to the scan line 110 in the (n + c) th row are precharged; wherein a, b and c are natural numbers which are more than or equal to 1, and a, b and c are not equal to each other.
Similarly, when the nth row scan line 110 receives a scan signal, the first input terminal 211 of the pulse flip-flop 210 receives a high level signal, the output signal of the first output terminal 213 is 1, and the output signal of the second output terminal 214 is 0, at this time, only the first switch 220 and the second switch 230 can be controlled to be turned on, so as to precharge the pixels corresponding to the nth + a row scan line 110 and the nth + b row scan line 110. When the scan line 110 in the (n + 1) th row receives a scan signal, the first input terminal 211 of the pulse flip-flop 210 also receives a high level signal, but the output signal of the first output terminal 213 is 0 at this time, and the output signal of the second output terminal 214 is 1 at this time, only the third switch 240 can be controlled to be turned on, so as to precharge the pixel corresponding to the scan line 110 in the (n + c) th row.
In this embodiment, the n + a row scan line 110, the n + b row scan line 110, and the n + c row scan line 110 may be any three scan lines 110, preferably, the three scan lines 110 are adjacent scan lines 110, specifically, a is equal to 1, b is equal to 3, and c is equal to 2, so as to facilitate circuit design.
Example four:
as shown in fig. 6, the precharge circuit 200 in this embodiment is connected to five scan lines 110 at the same time, unlike the first embodiment, the precharge circuit 200 further includes a first diode 260, a second diode 270, a third diode 280, a third switch 240, and a fourth switch 250, the anode of the first diode 260 is connected to the nth scan line 110, and the cathode of the first diode 260 is connected to the first input terminal 211; the anode of the second diode 270 is connected to the (n + 1) th row of scan lines 110, and the cathode of the second diode 270 is connected to the first input end 211; the anode of the third diode 280 is connected to the junction between the anode of the second diode 270 and the n +1 th row of scan lines 110, and the cathode of the third diode 280 is connected to the emitter of the first switch 220.
The third switch 240 is an N-type switch, a base of the third switch 240 is connected to the second output terminal 214, a collector of the third switch 240 is connected to the fourth high-level signal line 150, and an emitter of the third switch 240 is connected to the N + c-th row scan line 110; the fourth switch 250 is a P-type switch, a base of the fourth switch 250 is connected to the first output terminal 213, a collector of the fourth switch 250 is connected to the fifth high-level signal line 160, and an emitter of the fourth switch 250 is connected to the (n + d) th scan line 110.
When the nth row of scan lines 110 receives a scan signal, the pulse trigger 210 controls the first switch 220 and the second switch 230 to be opened, so that pixels corresponding to the nth + a row of scan lines 110 and the nth + b row of scan lines 110 are precharged; when the (n + 1) th row of scan lines 110 receives a scan signal, the pulse trigger 210 controls the third switch 240 and the fourth switch 250 to be opened, so that pixels corresponding to the (n + c) th row of scan lines 110 and the (n + d) th row of scan lines 110 are precharged; wherein a, b, c and d are natural numbers more than or equal to 1, and a, b, c and d are different from each other.
The present embodiment fully utilizes the characteristics of the pulse flip-flop 210 and the types of switches to maximize the precharging efficiency of the precharging circuit 200, and compared with other embodiments, the present embodiment further precharges the pixels corresponding to all the scan lines 110 through fewer precharging circuits 200 on the basis of other embodiments. Also taking the display panel 100 with the resolution of 3840 × 2160 as an example, if the number of the effective scan lines 110 is 2160, 2160/5=432 registers are needed, and one precharge circuit 200 is disposed on each register, thereby further reducing the number of registers and precharge circuits 200 and further reducing the cost.
Certainly, the first output terminal 213 and the second output terminal 214 may also be connected to more switches, and may also precharge more rows of pixels at the same time, so as to improve the precharging efficiency.
In addition, the n + a-th row scan line 110, the n + b-th row scan line 110, the n + c-th row scan line 110, and the n + d-th row scan line 110 are adjacent scan lines 110. Further, a is equal to 1, b is equal to 3, c is equal to 4, and d is equal to 2; the first switch 220 and the fourth switch 250 are arranged in parallel, and the second switch 230 and the third switch 240 are arranged in parallel. Not only can the pre-charging circuit 200 be arranged reasonably, but also the disorder of wiring can be avoided.
Correspondingly, as shown in fig. 7, the present embodiment further discloses a precharge method for the display panel 100, that is, after the step S4, the method further includes the steps of:
s5: the n +1 th row of scanning lines receive scanning signals and charge pixels corresponding to the n +1 th row of scanning lines;
s6: the first input end of the pulse trigger receives a high-level signal through the second diode, and the first output end and the second output end of the trigger output opposite signals, so that the third switch and the fourth switch are opened;
s7: the n + c row of scanning lines receive high-level signals of the fourth high-level signal line and pre-charge pixels corresponding to the n + c row of scanning lines; and the n + d row of scanning lines receive the high-level signal of the fifth high-level signal line and pre-charge the pixels corresponding to the n + d row of scanning lines.
In the above embodiments, the second high-level signal line 130, the third high-level signal line 140, the fourth high-level signal line 150 and/or the fifth high-level signal line 160 may be connected together and directly connected to an external power line, so as to facilitate the wiring design, and further enable the high-level signal lines to always keep receiving high-level signals, without adjustment, and thus the use is more convenient. Of course, the second high-level signal line 130, the third high-level signal line 140, the fourth high-level signal line 150 and/or the fifth high-level signal line 160 may also be connected to the corresponding gate-on signal lines.
Moreover, the display panel 100 in the present application can be matched with the pre-charge circuit 200 in different embodiments according to needs, and the pre-charge circuit 200 in different embodiments can be combined into the same display panel 100 to meet more use requirements.
It should be noted that, on the premise of not affecting the implementation of the specific embodiment, the limitations of the steps involved in the present disclosure are not considered as limiting the order of the steps, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present disclosure.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (6)
1. A display panel, comprising:
a plurality of scan lines arranged in parallel;
at least one pre-charge circuit, the said pre-charge circuit is connected with at least 3 rows of scanning lines at the same time;
the precharge circuit includes: the pulse trigger comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the nth row of scanning lines, the second input end is connected with a first high-level signal line, and the first output end and the second output end output opposite level signals;
the first switch is an N-type switch, the base electrode of the first switch is connected with the first output end, the collector electrode of the first switch is connected with a second high-level signal line, and the emitter electrode of the first switch is connected with the N + a row scanning line; and
the second switch is a P-type switch, the base of the second switch is connected with the second output end, the collector of the second switch is connected with a third high-level signal line, and the emitter of the second switch is connected with the n + b-th row scanning line;
when the nth row of scanning lines receives scanning signals, the pulse trigger controls the first switch and the second switch to be opened, so that pixels corresponding to the (n + a) th row of scanning lines and the (n + b) th row of scanning lines are precharged;
the pre-charging circuit further comprises a first diode, a second diode, a third switch and a fourth switch, wherein the anode of the first diode is connected with the nth row scanning line, and the cathode of the first diode is connected with the first input end; the anode of the second diode is connected with the (n + 1) th row scanning line, and the cathode of the second diode is connected with the first input end; the anode of the third diode is connected with the junction of the anode of the second diode and the (n + 1) th row of scanning lines, and the cathode of the third diode is connected with the emitter of the first switch;
the third switch is an N-type switch, the base of the third switch is connected with the second output end, the collector of the third switch is connected with a fourth high-level signal line, and the emitter of the third switch is connected with the N + c-th row scanning line;
the fourth switch is a P-type switch, the base of the fourth switch is connected with the first output end, the collector of the fourth switch is connected with a fifth high-level signal line, and the emitter of the fourth switch is connected with the n + d-th row scanning line;
when the nth row of scanning lines receives scanning signals, the pulse trigger controls the first switch and the second switch to be opened, so that pixels corresponding to the (n + a) th row of scanning lines and the (n + b) th row of scanning lines are precharged;
when the (n + 1) th row of scanning lines receives scanning signals, the pulse trigger controls the third switch and the fourth switch to be opened, so that pixels corresponding to the (n + c) th row of scanning lines and the (n + d) th row of scanning lines are precharged;
wherein n, a, b, c and d are natural numbers more than or equal to 1, and a, b, c and d are different from each other.
2. The display panel according to claim 1, wherein a is equal to 1.
3. The display panel according to claim 1, wherein the n + a row scan line, the n + b row scan line, the n + c row scan line, and the n + d row scan line are adjacent scan lines.
4. A display panel as claimed in claim 3 characterized in that b equals 3, c equals 4, d equals 2; the first switch and the fourth switch are arranged in parallel, and the second switch and the third switch are arranged in parallel.
5. A precharge method of a display panel for precharging the display panel according to any one of claims 1 to 4, comprising the steps of:
conducting a first high-level signal line, a second high-level signal line and a third high-level signal line to enable a second input end of a pulse trigger, a collector of a first switch and a collector of a second switch in the pre-charging circuit to be connected with high-level signals;
the nth row of scanning lines receive scanning signals and charge pixels corresponding to the nth row of scanning lines;
a first input end of a pulse trigger in the pre-charging circuit receives a high-level signal, and a first output end and a second output end of the trigger output opposite signals, so that a first switch and a second switch are opened; and
the n + a row of scanning lines receive high-level signals of the second high-level signal line and pre-charge pixels corresponding to the n + a row of scanning lines; the n + b row of scanning lines receive high-level signals of the third high-level signal line and pre-charge pixels corresponding to the n + b row of scanning lines;
wherein n, a and b are natural numbers more than or equal to 1, and a is not equal to b;
the pre-charging circuit comprises a first diode, a second diode, a third switch and a fourth switch, wherein the anode of the first diode is connected with the nth row of scanning lines, and the cathode of the first diode is connected with the first input end; the anode of the second diode is connected with the (n + 1) th row of scanning lines, and the cathode of the second diode is connected with the first input end; the anode of the third diode is connected with the junction of the anode of the second diode and the n +1 th row of scanning lines, and the cathode of the third diode is connected with the emitter of the first switch;
the first switch and the third switch are N-type switches, the second switch and the fourth switch are P-type switches, the base of the third switch is connected with the second output end, the collector of the third switch is connected with a fourth high-level signal line, and the emitter of the third switch is connected with an N + c row scanning line; the base electrode of the fourth switch is connected with the first output end, the collector electrode of the fourth switch is connected with a fifth high-level signal line, and the emitter electrode of the fourth switch is connected with the n + d-th row of scanning lines;
the n + a row of scanning lines receive high-level signals of the second high-level signal lines and pre-charge pixels corresponding to the n + a row of scanning lines; after the step of receiving the high level signal of the third high level signal line by the n + b-th row of scanning lines and pre-charging the pixels corresponding to the n + b-th row of scanning lines, the method further comprises the following steps:
the n +1 th row of scanning lines receive scanning signals and charge pixels corresponding to the n +1 th row of scanning lines;
the first input end of the pulse trigger receives a high-level signal through the second diode, and the first output end and the second output end of the trigger output opposite signals, so that the third switch and the fourth switch are opened; and
the n + c row of scanning lines receive high-level signals of the fourth high-level signal line and pre-charge pixels corresponding to the n + c row of scanning lines; the n + d row of scanning lines receive high-level signals of the fifth high-level signal line and pre-charge pixels corresponding to the n + d row of scanning lines;
wherein a is equal to 1, b is equal to 3, c is equal to 4, and d is equal to 2.
6. A display device comprising a display panel as claimed in any one of claims 1 to 4 and a backlight module for providing backlight to the display panel.
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| CN115547271A (en) | 2022-12-30 |
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