TWI688939B - Shift register and touch display apparatus thereof - Google Patents

Abstract

The present disclosure relates to a shift register. The shift register sequentially generates a plurality of pulse signals shifted in a predetermined phase. The shift register includes a plurality of unit circuits connected in stages. Each unit circuit includes an output terminal, an input transistor, an output transistor, and a pull-up transistor. The input transistor controlled by a first control signal outputs a high level voltage to a first node based on an external trigger signal. The output transistor outputs a shifted pulse signal to the output terminal, which is simultaneously with a clock control signal, based on the first node in the high level voltage. A blank period is inserted between two adjacent unit circuits. The pull-up transistor pulls the output terminal of the unit circuit served as a next stage in the two adjacent unit circuits to be high level voltage. A touch display apparatus with the shift register is also provided.

Description

Shift register and touch display device with shift register

The invention relates to a shift register and a touch display device with the shift register.

The touch display device can realize the display function and the touch function in time-sharing. The touch display device includes multiple data lines and multiple scan lines. The orthogonal arrangement of multiple data lines and multiple scan lines defines multiple pixel units arranged in a matrix. The touch display device also includes a timing controller, a gate driver, and a source driver. The gate driver outputs a scan driving signal to the scan line to scan the pixel unit. The source driver outputs a data driving signal to the data line to load the corresponding image data signal to the pixel unit. The gate driver is usually composed of multiple cascaded unit circuits. Each unit circuit at least receives the first clock control signal, the second clock control signal, the set signal and the reset signal. The unit circuit is composed of a plurality of thin film transistors, driving transistors, and at least one capacitor. The capacitor is connected in parallel between the gate and drain of the driving transistor. The driving transistor outputs the signal synchronized with the received clock control signal as the scanning signal when it is turned on. The unit circuit of each stage works in the precharge stage, the pull-up stage and the pull-down stage. The touch stage can be inserted between any two of the precharge stage, the pull-up stage, and the pull-down stage. When the touch stage is inserted between the pre-charging stage and the pull-up stage, since the driving transistor remains on during the touch stage, its corresponding gate voltage will be affected by capacitance and leakage current, and will cause The turn-on voltage of the driving transistor becomes larger. When entering the pull-up stage from the touch stage, due to the drop of the gate voltage of the driving transistor and the change of characteristics This makes the output terminal unable to output the first voltage, which causes abnormal display and horizontal lines, which affects the stability of the touch display device.

In view of this, it is necessary to provide a shift register that can improve stability.

It is also necessary to provide a touch display device with a shift register that can improve stability.

A shift register capable of generating a plurality of pulse shift signals that shift a pulse signal by a predetermined phase, including: a plurality of unit circuits connected in cascade, each unit circuit receiving an external clock control signal, including: output Terminal, the output terminal is electrically connected to at least one external signal line for providing pulse displacement signals for the corresponding connected signal lines, wherein the output terminal of the unit circuit of the N+1th stage outputs to the N+1th signal line And the pulse displacement signal output from the output terminal of the unit circuit of the Nth stage to the Nth signal line is delayed by a predetermined phase, and there is a blank section inserted between the pulse displacement signals output by any two adjacent unit circuits ; Input transistor, under the control of the first control signal, according to the external trigger signal used to characterize the unit circuit of the current stage to start working to output a high level to the first node; output transistor, including A first control terminal electrically connected to a node, a first connection terminal receiving a clock control signal and a second connection terminal electrically connected to the output terminal, the output transistor outputs a clock to the output terminal according to the high level of the first node A pulse displacement signal synchronized with the control signal; a pull-up transistor, which includes a second control terminal electrically connected to the output terminal, a first connection terminal electrically connected to the second control terminal, and a first connection terminal electrically connected to the high-voltage voltage source Two connection ends; Among them, after inserting a blank section between the unit circuit of the Nth stage and the unit circuit of the N+1th stage, and during the period when the unit circuit of the N+1th stage starts to output the pulse displacement signal, the pull-up transistor The pulse displacement signal at the output of the unit circuit of level 1 is pulled up to a high level.

A touch display device defines a display area and a non-display area set around the display area. At least one gate driver is provided in the non-display area. At least one gate driver includes at least one shift register. The shift register can generate multiple pulse shift signals that shift the pulse signal by a predetermined phase, including: multiple unit circuits connected in cascade, each unit circuit receives an externally provided clock control signal, including: output terminal, output The terminal is electrically connected to at least one external signal line to provide pulse displacement signals for the corresponding connected signal lines, wherein the output end of the unit circuit of the N+1th stage is output to the pulse displacement of the N+1th signal line The signal and the pulse displacement signal output from the output terminal of the unit circuit of the Nth stage to the Nth signal line are delayed by a predetermined phase, and there is a blank section inserted between the pulse displacement signals output by any two adjacent unit circuits; Crystal, the input transistor is under the control of the first control signal, according to the external trigger signal used to characterize the start of the unit circuit of the current stage to output a high level to the first node; output transistor, which includes the first node The first control terminal that is connected sexually, the first connection terminal that receives the clock control signal, and the second connection terminal that is electrically connected to the output terminal, the output transistor outputs to the output terminal in synchronization with the clock control signal according to the high level of the first node Pulse shift signal; pull-up transistor, which includes a second control end electrically connected to the output end, a first connection end electrically connected to the second control end, and a second connection end electrically connected to the high-voltage voltage source ; Among them, after inserting a blank section between the unit circuit of the Nth stage and the unit circuit of the N+1th stage, and during the period when the unit circuit of the N+1th stage starts to output the pulse displacement signal, the pull-up transistor The pulse displacement signal at the output of the +1-level unit circuit is pulled up to a high level.

Compared with the conventional technology, the above-mentioned shift register and touch display device are used to insert a blank section between the output pulse shift signals of some adjacent two-stage unit circuits by keeping the module pulled up at the lower stage The output pulse displacement signal of the output terminal of the output unit circuit is high level, which avoids the output pulse displacement signal of the output terminal of the unit circuit output by the lower stage after inserting the blank section is less than the high level, avoiding the generation of horizontal lines, thereby ensuring The stability of the touch display device.

1: Touch display device

10: Pixel unit

11: Display area

13: Non-display area

G1-Gn: scan line

D1-Dm: data cable

20: Gate driver

200: shift register

30: source driver

VCK1-VCK4: clock control signal line

21: Unit circuit

STV: Start pulse signal

S: setting end

R: reset terminal

CK: Clock control signal input terminal

C1: the first control terminal

C2: Second control terminal

OUT: output

22: Input module

22a: Sub output

23: output module

24: Reset module

25: keep module

P1: Precharge phase

P2: Pull-up stage

P3: pull-down stage

T1: input transistor

T2: output transistor

N1: the first node

C: storage capacitor

VDD: high voltage power supply

VGL: low voltage power supply

T3: the first transistor

T4: second transistor

T5: pull-down transistor

T6: pull-up transistor

TP1-TPn: Sub-touch stage

DP1-DPn: Sub-display stage

FIG. 1 is a schematic diagram of a module of a touch display device according to a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram of the module of the gate driver shown in FIG. 1.

FIG. 3 is an equivalent circuit diagram of the unit circuit shown in FIG. 2.

FIG. 4 is a driving timing chart of the unit circuit shown in FIG. 2.

The invention provides a shift register. The shift register can generate multiple pulse shift signals that shift the pulse signal by a predetermined phase, including: multiple unit circuits connected in cascade, each unit circuit receives an externally provided clock control signal, including: output terminal, output The terminal is electrically connected to at least one external signal line to provide pulse displacement signals for the corresponding connected signal lines, wherein the output end of the unit circuit of the N+1th stage is output to the pulse displacement of the N+1th signal line The signal and the pulse displacement signal output from the output terminal of the unit circuit of the Nth stage to the Nth signal line are delayed by a predetermined phase, and there is a blank section inserted between the pulse displacement signals output by any two adjacent unit circuits; Input transistor, under the control of the first control signal, output high level to the first node according to the external trigger signal to start the operation of the unit circuit characterizing the current stage; output transistor, including the first The first control terminal electrically connected to the node, the first connection terminal receiving the clock control signal and the second connection terminal electrically connected to the output terminal, the output transistor outputs to the output terminal and the clock control according to the high level of the first node Signal-shifted pulse displacement signal; pull-up transistor, which includes a second control end electrically connected to the output end, a first connection end electrically connected to the second control end, and a second connection electrically connected to the high-voltage voltage source Connection; where, after inserting a blank section between the unit circuit of the Nth stage and the unit circuit of the N+1th stage, and during the period when the unit circuit of the N+1th stage begins to output the pulse displacement signal, the pull-up transistor will The pulse displacement signal at the output of the unit circuit of the N+1th stage is pulled up to a high level.

In one embodiment, in the blank section, all unit circuits stop outputting the pulse displacement signal.

In one embodiment, the unit circuit further includes a reset module. The reset module receives the reset signal provided by the outside. The reset module includes a pull-down transistor. The pull-down transistor includes a third control terminal that receives the reset signal, a first connection terminal that is electrically connected to the output terminal, and a second connection terminal that is electrically connected to the low-voltage power supply. The pull-down transistor outputs a low level to the output terminal according to a reset signal externally used to characterize the reset of the unit circuit of the current stage.

In one embodiment, the reset module also receives the externally provided second control signal. The reset module also includes a first transistor. The first transistor includes a fourth control terminal that receives the second control signal, a second connection terminal electrically connected to the first node, and a second connection terminal electrically connected to the low-voltage power supply. The first transistor outputs a low level to the first node according to the high level of the second control signal.

In one embodiment, the first control signal, the clock control signal, and the second control signal are from three adjacent clock lines, and the three are sequentially delayed by a predetermined phase.

In one embodiment, the reset module further includes a second transistor. The second transistor includes a fifth control terminal receiving the reset signal, a second connection terminal electrically connected to the first node, and a second connection terminal electrically connected to the low-voltage power supply. The second transistor outputs a low level to the first node according to the high level of the reset signal.

In an embodiment, a touch display device defines a display area and a non-display area provided around the display area. At least one gate driver is provided in the non-display area. At least one gate driver includes at least one shift register. The shift register can generate multiple pulse shift signals that shift the pulse signal by a predetermined phase, including: multiple unit circuits connected in cascade, each unit circuit receives an externally provided clock control signal, including: output terminal, output The terminal is electrically connected to at least one external signal line to provide pulse displacement signals for the corresponding connected signal lines, wherein the output end of the unit circuit of the N+1th stage is output to the pulse displacement of the N+1th signal line The signal and the pulse displacement signal output from the output terminal of the unit circuit of the Nth stage to the Nth signal line are delayed by a predetermined phase, and there is a blank section inserted between the pulse displacement signals output by any two adjacent unit circuits; Crystal, the input transistor is under the control of the first control signal, according to the external trigger signal used to characterize the start of the unit circuit of the current stage to output a high level to the first node; output transistor, which includes the first node The first control terminal that is connected sexually, the first connection terminal that receives the clock control signal, and the second connection terminal that is electrically connected to the output terminal, the output transistor outputs to the output terminal in synchronization with the clock control signal according to the high level of the first node Pulse shift signal; pull-up transistor, which includes a second control end electrically connected to the output end, a first connection end electrically connected to the second control end, and a second connection end electrically connected to the high-voltage voltage source ; Among them, after inserting a blank section between the unit circuit of the Nth stage and the unit circuit of the N+1th stage, and during the period when the unit circuit of the N+1th stage starts to output the pulse displacement signal, the pull-up transistor The pulse displacement signal at the output of the unit circuit of level 1 is pulled up to a high level.

In an embodiment, the touch display device works alternately in the touch phase and the display phase. The display phase includes multiple sub-display phases. The touch stage includes multiple sub-touch stages. The sub-touch stage can be inserted between any two adjacent sub-display stages. The sub-touch stage is a blank section.

The specific implementation of the touch display device of the present invention will be described below with reference to the drawings.

Please also refer to FIG. 1, which is a schematic diagram of a module of a touch display device 1 according to an embodiment of the present invention. The touch display device 1 defines a display area 11 and a non-display area 13 provided around the display area 11. The display area 11 includes a plurality of parallel scan lines G1-Gn and a plurality of parallel data lines D1-Dm. Among them, n, m are positive integers. Multiple scan lines G1-Gn extend along the first direction X, multiple data lines D1-Dm extend along the second direction Y perpendicular to the first direction, and interlace with the multiple scan lines G1-Gn respectively to define a mesh A grid-like, hollow part of the grid defines a plurality of pixel units 10 arranged in a matrix. It can be understood that the multiple scan lines G1-Gn and the multiple data lines D1-Dm of the touch display device of the present disclosure can be arranged as needed, for example, the scan lines G1-Gn and the data lines D1-Dm are not orthogonally interlaced, and It is an oblique interlace, and is not limited to this embodiment. A gate driver 20 and a source driver 30 are provided in the non-display area 13. The gate driver 20 is electrically connected to the scanning lines G1-Gn, and is used to drive the scanning lines G1-Gn. The source driver 30 is also used to output data signals to the data lines D1-Dm, so that the corresponding pixel unit 10 loads the data signals. It can be understood that the touch display device may further include a timing controller. The timing controller is used to provide a plurality of synchronization control signals and at least one clock control signal to the gate driver 20. In this embodiment, the timing driver provides the clock control signal to the gate driver 20 through the clock control signal lines VCK1-VCK4. The pulse signal on any clock control signal line VCK1-VCK4 is a pulse signal with a predetermined frequency, and the phase of the pulse signal on four clock control signal lines VCK1-VCK4 Delay in turn. The multiple synchronization control signals may include horizontal synchronization (Vsync), vertical synchronization (Vsync), and data enable (EN). Any pixel unit 10 is electrically connected to the gate driver 20 through a scanning line Gi, and is electrically connected to the source driver 30 through a data line Di.

Please refer to FIG. 2 and FIG. 3 together, which is a schematic diagram of the module of the gate driver 20 of the first embodiment. The gate driver 20 is composed of at least one shift register 200. The shift register 200 is used to generate a plurality of pulse shift signals that shift the pulse signal by a predetermined phase. Each shift register 200 is composed of a plurality of unit circuits 21 connected in cascade. Each unit circuit 21 is electrically connected to the scanning lines G1-Gn, respectively, so as to provide pulse displacement signals for the scanning lines G1-Gn as scanning signals. The shift register 200 is electrically connected to four clock control signal lines VCK1-VCK4, and receives a start pulse signal STV. Each unit circuit 21 is used to output a pulse displacement signal to be provided as a scan signal to the corresponding scan line Gi. Each unit circuit 21 has the same circuit structure and has the same pins.

The first control terminal C1, the second control terminal C2, and the clock control signal input terminal CK of each unit circuit 21 are electrically connected to three of the clock control signal lines VCK1-VCK4, respectively. The phases of the three clock control signals VCK are sequentially delayed. The clock control signal input terminal CK of the first-level unit circuit 21 is electrically connected to the clock control signal line VCK1, the first control terminal C1 of the first-level unit circuit 21 is electrically connected to the clock control signal line VCK2, and the first-level unit circuit The second control terminal C2 of 21 is electrically connected to the clock control signal line VCK3. The clock control signal input terminal CK of the second-level unit circuit 21 is electrically connected to the clock control signal line VCK2, the first control terminal C1 of the second-level unit circuit 21 is electrically connected to the clock control signal line VCK3, and the second-level unit circuit The second control terminal C2 of 21 is electrically connected to the clock control signal line VCK4. The clock control signal input terminal CK of the third-level unit circuit 21 is electrically connected to the clock control signal line VCK3, and the first control of the third-level unit circuit 21 The terminal C1 is electrically connected to the clock control signal line VCK4, and the second control terminal C2 of the third-stage unit circuit 21 is electrically connected to the clock control signal line VCK1. The clock control signal input terminal CK of the fourth-level unit circuit 21 is electrically connected to the clock control signal line VCK4, the first control terminal C1 of the fourth-level unit circuit 21 is electrically connected to the clock control signal line VCK1, the fourth-level unit The second control terminal C2 of the circuit 21 is electrically connected to the clock control signal line VCK2.

Each unit circuit 21 includes a setting terminal S, a reset terminal R, a first control terminal C1, a second control terminal C2, a clock control signal input terminal CK and an output terminal OUT. The unit circuit 21 includes a flip-flop circuit, and controls the output of the output terminal OUT according to the input signals of the setting terminal S and the reset terminal R. Specifically, when the setting terminal S receives an effective level (taking a high level as an example) and the reset terminal R receives an invalid level (taking a low level as an example), the output terminal OUT of the unit circuit 21 outputs a high level When the setting terminal S is at a low level and the reset terminal R receives a high level, the output of the unit circuit 21 is cleared, and the output terminal OUT outputs a low level. The pulse width of the clock control signal input terminal CK is used to determine the pulse width of the output signal.

The unit circuit 21 includes an input module 22 having a setting terminal S, an output module 23 having a clock control signal input terminal CK, a reset module 24 having a reset terminal R, and a holding module 25.

The output module 23 is used to control whether the output terminal OUT outputs a pulse signal synchronized with the clock control signal input from the clock control signal input terminal CK as the unit circuit 21 needs to output according to the signals received by the setting terminal S and the reset terminal R Displacement pulse signal. The output module 23 includes an output transistor T2 and a storage capacitor C. The control terminal of the output transistor T2 and the sub-output terminal 22a of the input module 22 are connected to the first node N1, the source is connected to the clock control signal input terminal CK, and the drain is connected to the output terminal OUT. Both ends of the storage capacitor C are connected between the first node N1 and the output terminal OUT.

The input module 22 includes a setting terminal S for receiving a trigger signal, a sub-output terminal 22a, and a first control terminal C1 for receiving a clock control signal. The input module 22 includes an input transistor T1. The control terminal of the input transistor T1 is connected to the first control terminal C1, the source terminal is connected to the setting terminal S, and the drain terminal is connected to the sub-output terminal 22a. The input module 22 is used to control the input of the self-setting terminal S under the control of the first control terminal C1 The output timing of the trigger signal. The trigger signal loaded on the setting end S of the unit circuit 21 of the Nth stage is the output pulse displacement signal of the output terminal OUT of the unit circuit 21 of the N-1th stage.

The reset module 24 is used to control the unit circuit 21 of the current stage to stop outputting the pulse shift element signal according to the reset signal input from the reset terminal R. The reset signal loaded on the reset terminal R of the unit circuit 21 of the Nth stage is the output voltage of the output terminal OUT of the unit circuit 21 of the N+1th stage. The reset module 24 includes a pull-down transistor T5 connected in series with the output transistor T2, a first transistor T3 connected between the first node N1 and the low-voltage power supply VGL, and a second transistor connected in parallel with the first transistor T3 Crystal T4. The control terminal of the first transistor T3 is connected to the second control terminal C2, and the control terminal of the second transistor T4 is connected to the reset terminal R. The control terminal of the pull-down transistor T5 is connected to the reset terminal R, the source is connected to the output terminal OUT, and the drain is connected to the low-voltage power supply VGL. The source of the pull-down transistor T5 is also connected to the output terminal OUT, so that a second node N2 is defined between the output transistor T2 and the pull-down transistor T5.

In the present invention, the pulse displacement signals generated by the unit circuit 21 are sequentially shifted, and there is a case where a blank section is inserted between the pulse displacement signals output by some adjacent two-stage unit circuits 21. The holding module 25 is used to pull up the pulse displacement signal output by the output terminal OUT of the unit circuit 21 in the next stage output of the adjacent unit circuit 21 in this part, so as to maintain the pulse displacement signal output by the output terminal OUT to maintain the high level V1 Output. For example, please refer to FIG. 4, if some adjacent unit circuits 21 are the fifth-stage unit circuit 21 and the sixth-stage unit circuit 21, if there is no holding module 25, the output is output at the output terminal of the fifth-stage unit circuit 21 After the pulse displacement signal, the level V1' of the output pulse output signal of the output terminal OUT of the sixth-stage unit circuit 21 is less than the high level V1, as shown by the dotted line in the figure, comparablely, when the holding module 25 is present, then The output signal of the output terminal OUT of the sixth-stage unit circuit 21 maintains the high level V1.

In this embodiment, the holding module 25 includes a pull-up transistor T6. The control terminal and the drain of the pull-up transistor T6 are respectively connected to the output terminal OUT, and the source is connected to the high-voltage power supply VDD. pull up The transistor T6 is turned on after the blank section and the unit circuit 21 starts to output the pulse displacement signal, thereby pulling up the potential of the output terminal OUT to raise it to VDD-Vth.

The setting end S of the first-stage unit circuit 21 is electrically connected to the start pulse signal STV, and the setting end S of the other-stage unit circuit 21 is electrically connected to the output end OUT of the previous-stage unit circuit 21. The reset terminal R of the last-stage unit circuit 21 is electrically connected to the start pulse signal STV, and the reset terminal of the other-stage unit circuit 21 is electrically connected to the output terminal OUT of the subsequent-stage unit circuit 21.

In this embodiment, the input transistor T1, the output transistor T2, the first transistor T3, the second transistor T4, the pull-down transistor T5, and the pull-up transistor T6 are all N-type thin film transistors.

Please also refer to FIG. 4, which is a timing diagram of the corresponding signals of the fifth-level unit circuit 21. The touch display device 1 can work alternately in the touch phase and the display phase. Within a frame duration, the touch stage includes multiple sub-touch stages TP1-TPn, and the display stage includes multiple sub-display periods DP1-DPn. The sum of the times of the multiple sub-display periods DP1-DPn is equal to the total length of time that all scan lines G1-Gn are loaded into the scan signal once. That is, in any of the sub-display periods, part of the scan lines G1-Gn is scanned. A sub-touch stage TPx is inserted between two adjacent sub-display stages. During the sub-touch stage TPx period, all the scanning lines G1-Gn are not scanned. In this embodiment, the sub-touch stage TPx is a blank section inserted between the pulse displacement signals output by some adjacent two unit circuits 21. In the touch stage TPx, the electrical averages of the first control terminal C1, the second control terminal C2, the setting terminal S, the reset terminal R, and the clock control signal input terminal CK of the unit circuit 21 are at a low level. The display phase DP further includes a precharge phase P1, a pull-up phase P2, and a pull-down phase P3 that are performed in chronological order. In the pre-charging phase P1, the input module 22 pre-charges the control terminal of the output transistor T2 and the first node N1. In the pull-up phase P2, the output module 23 pulls up the output terminal OUT to a high level V1 according to the first terminal voltage output by the input module 22 and the clock control signal of the clock control signal input terminal CK. In the pull-down phase P3, the reset module 24 resets the output terminal OUT to a low level according to the signal of the reset terminal R.

In this embodiment, a blank section is inserted between the output pulse displacement signals of the fifth-stage unit circuit 21 and the sixth-stage unit circuit 21, that is, the sub-touch stage TP1 is inserted in the precharge stage P1 of the sixth-stage unit circuit 21 And the pull-up phase P2. Understandably, other sub-touch stages TPx may be inserted between the output pulse displacement signals of any two adjacent unit circuits 21. The sub-touch stage TP2 can be inserted between the output pulse displacement signals of the ninth unit circuit 21 and the tenth unit circuit 21, that is, the sub-touch stage TP2 is inserted in the precharge stage P1 and pull-up of the tenth unit circuit 21 Between stages P2.

Next, the sixth-stage unit circuit 21 will be used as an example for detailed description.

The first control terminal C1 of the sixth-stage unit circuit 21 is electrically connected to the clock control signal line VCK3, the second control terminal C2 is electrically connected to the clock control signal line VCK4, and the clock control signal input terminal CK is electrically connected to the clock control signal line VCK2 The connection terminal S receives the pulse displacement signal output from the unit circuit 21 of the fifth stage, and the reset terminal R receives the pulse displacement signal output from the unit circuit 21 of the seventh stage.

When the signals of the first control terminal C1 (that is, the clock control signal line VCK3) and the setting terminal S are at a high level, and the signals of the second control terminal C2 (that is, the clock control signal line VCK4) and the reset terminal R are at a low level The sixth-stage unit circuit 21 is in the precharge phase P1. The input transistor T1 is turned on, the voltage at the setting terminal S charges the storage capacitor C, and the voltage at the first node N1 rises. The output transistor T2 is turned on when the voltage of the first node N1 is greater than the threshold voltage, so that the output terminal OUT outputs a pulse displacement signal synchronized with the clock control signal input terminal CK (that is, the clock control signal line VCK2). Since the signal of the clock control signal input terminal CK is low level, the output terminal OUT outputs low level.

In the sub-touch stage TP1, the signals of the first control terminal C1, the second control terminal C2, the setting terminal S, the clock control signal input terminal CK, and the reset terminal R are low. The output transistor T2 remains on. At this time, the voltage of the first node N1 gradually decreases with time, and the output terminal OUT maintains the output of the second voltage.

When the signals of the first control terminal C1, the second control terminal C2, the setting terminal S, and the reset terminal R are low, and the signal of the clock control signal input terminal CK is high, the unit circuit 21 is in the pull-up phase P2 . The storage capacitor C is discharged to maintain the output transistor T2 in a conductive state. At this time, the pull-up transistor T6 is turned on, so that the output terminal OUT remains at the high level V1.

When the signals of the first control terminal C1 and the setting terminal S are low, and the signals of the second control terminal C2 and the reset terminal R are high, the unit circuit 21 is in the pull-down phase P3. The first transistor T3 and the second transistor T4 are turned on, so that the first node N1 is pulled down to the second voltage, and then the output transistor T2 is turned off. The pull-down transistor T5 is turned on, so that the output terminal OUT outputs the second voltage. At this time, the storage capacitor C is discharged through the first transistor T3, the second transistor T4, and the pull-down transistor T5.

In summary, in the touch display device 1 with the above structure, when a blank section is inserted between the output pulse displacement signals of some adjacent two-stage unit circuits 21, the unit circuit at the lower stage output is pulled up by the holding module 25 The output pulse displacement signal of the output terminal 21 of the output 21 is a high level V1, which avoids the output circuit of the output circuit OUT of the lower stage after inserting a blank section. The output pulse displacement signal of the output terminal OUT of the 21 is less than the high level, avoiding the generation of horizontal lines , Thereby ensuring the stability of the touch display device 1.

S: setting end

R: reset terminal

C1: the first control terminal

C2: Second control terminal

CK: Clock control signal input terminal

OUT: output

VDD: high voltage power supply

VGL: low voltage power supply

22: Input module

22a: Sub output

23: output module

24: Reset module

25: keep module

T1: input transistor

T2: output transistor

T3: the first transistor

T4: second transistor

T5: pull-down transistor

T6: pull-up transistor

N1: the first node

C: storage capacitor

Claims (8)

A shift register capable of generating a plurality of pulse shift signals that shift a pulse signal by a predetermined phase, including: a plurality of unit circuits connected in cascade, each of the unit circuits receiving an externally provided clock control signal, including : Output terminal, the output terminal is electrically connected to at least one external signal line to provide a pulse displacement signal for the corresponding connected signal line, wherein the output terminal of the unit circuit of the N+1th stage is connected to the Nth The pulse displacement signal output on the +1 signal line and the pulse displacement signal output from the unit circuit of the Nth stage to the Nth signal line are delayed by the predetermined phase, and there is a blank section inserted in any two adjacent Between the pulse displacement signals output by the unit circuit; input transistors, the input transistors under the control of the first control signal, according to an external trigger used to characterize the current stage of the unit circuit to start working A signal to output a high level to the first node; an output transistor, which includes a first control end electrically connected to the first node, a first connection end receiving the clock control signal, and an electrical connection with the output end Connected to the second connection terminal, the output transistor outputs a pulse displacement signal synchronized with the clock control signal to the output terminal according to the high level of the first node; a pull-up transistor including A second control terminal electrically connected to the output terminal, a first connection terminal electrically connected to the second control terminal, and the second connection terminal electrically connected to the high-voltage voltage source; After the blank section is inserted between the unit circuit and the unit circuit of the N+1th stage, and during the period when the unit circuit of the N+1th stage starts to output the pulse displacement signal, the pull-up transistor The pulse displacement signal of the output end of the unit circuit of the N+1 stage is pulled up to a high level. The shift register according to claim 1, wherein in the blank section, all of the unit circuits stop outputting pulse shift signals. The shift register according to claim 1, wherein the unit circuit further includes a reset module; the reset module receives an externally provided reset signal; the reset module includes a pull-down transistor The pull-down transistor includes a third control terminal that receives the reset signal, a first connection terminal that is electrically connected to the output terminal, and a second connection terminal that is electrically connected to a low-voltage power supply; The crystal outputs a low level to the output terminal according to a reset signal externally used to characterize the reset of the unit circuit at the current stage. The shift register according to claim 3, wherein the reset module further receives a second control signal provided from outside; the reset module further includes a first transistor; the first transistor It includes a fourth control terminal that receives the second control signal, a first connection terminal that is electrically connected to the first node, and a second connection terminal that is electrically connected to the low-voltage power supply; the first transistor is based on The high level of the second control signal outputs a low level to the first node. The shift register according to claim 4, wherein the first control signal, the clock control signal, and the second control signal are from three adjacent clock lines, and the predetermined delay is sequentially delayed between the three Phase. The shift register according to claim 3, wherein the reset module further includes a second transistor; the second transistor includes a fifth control terminal that receives the reset signal, and the A first connection terminal electrically connected to the first node and a second connection terminal electrically connected to the low-voltage power supply; the second transistor outputs low to the first node according to the high level of the reset signal Level. A touch display device, which defines a display area and a non-display area arranged around the display area; the non-display area is provided with at least one gate driver; the at least one gate driver includes at least one shift register ; Wherein, the at least one shift register uses the shift register described in any one of the request items 1 to 6. The touch display device according to claim 7, wherein the touch display device works alternately in a sub-touch stage and a sub-display stage; the at least one shift register is respectively in the adjacent sub-display stage Output two pulse displacement signals as scanning signals required for the operation of the thin film transistor array circuit of the touch display device; the sub-touch stage is inserted between any two adjacent sub-display stages, the sub The touch stage is the blank section.

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