CN113178174B - Grid driving module, grid control signal generation method and display device - Google Patents
Grid driving module, grid control signal generation method and display device Download PDFInfo
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- CN113178174B CN113178174B CN202110301058.XA CN202110301058A CN113178174B CN 113178174 B CN113178174 B CN 113178174B CN 202110301058 A CN202110301058 A CN 202110301058A CN 113178174 B CN113178174 B CN 113178174B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
Abstract
The application discloses a grid driving module, a grid control signal generation method and a display device, wherein the grid driving module comprises a first input end for receiving a first control signal, a second input end for receiving a clock signal, a logic control circuit for receiving the first control signal and the clock signal to generate a logic control signal, a level conversion circuit and a shift output buffer circuit for receiving the clock signal; the shift output buffer circuit comprises a plurality of cascaded shift buffer units; the level conversion circuit performs level conversion on the logic control signal to generate a second control signal, and outputs the second control signal to the shift output buffer circuit; the shift output buffer circuit respectively generates a gate control signal corresponding to a gate line in the display panel through a second control signal and a clock signal; the low level and the high level of the second control signal are the preset low level and the preset high level of the grid control signal for driving the display panel, and the level conversion is firstly carried out and then the shift is carried out, so that the number of the level converters is reduced.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a gate driving module, a method for generating a gate control signal, and a display device.
Background
A TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the major types of flat panel displays, and has become an important Display platform in modern IT and video products. The TFT-LCD mainly adopts a driving principle that a system main board connects R/G/B compression signals, control signals and power supplies with a connector on a printed circuit board through wires, data are processed by a Timing Controller (TCON) on the printed circuit board and then are connected with a display area through a Source-Chip on Film (S-COF) and a Gate-Chip on Film (G-COF), and therefore the liquid crystal display can obtain the required power supplies and signals.
At present, a gate driving chip mainly receives a control signal of TCON, and in cooperation with the control signal, a low level (VGL) and a high level (VGH) of the display panel are output and driven through a level shift device (level shift), the VGH is a voltage for controlling the opening of a TFT, the VGL is a voltage for controlling the closing of the TFT, the output VGH and VGL are connected to the inside of the panel through an output buffer, a plurality of level shifters in one-to-one correspondence with gate lines inside the display panel are needed, however, the area occupied by the gate driving chip by the level shifters is too large, and the cost is higher.
Disclosure of Invention
The application aims to provide a grid driving module, a grid control signal generation method and a display device, so that the area of a grid driving chip is saved, the internal circuit design of the grid driving chip is simplified, and the cost of the grid driving chip can be reduced.
The application discloses a gate driving module, which comprises a first input end for receiving a first control signal, a second input end for receiving a clock signal, a logic control circuit for receiving the first control signal and the clock signal to generate a logic control signal, a level conversion circuit and a shift output buffer circuit for receiving the clock signal; the input end of the logic control circuit is coupled with the first input end and the second input end, and the logic control circuit receives the first control signal input by the first input end and the clock signal input by the second input end to generate a logic control signal; the input end of the level conversion circuit is coupled with the output end of the logic control circuit, and the level conversion circuit performs level conversion on the logic control signal to generate a second control signal; the shift output buffer circuit is coupled with the second input end and the output end of the level conversion circuit, and the shift output buffer circuit simultaneously receives the first control signal output by the level conversion circuit and the clock signal output by the second input end; the gate driving module comprises a gate line coupled with the shift output buffer circuit; the shift output buffer circuit comprises a plurality of cascaded shift buffer units, and each shift buffer unit generates a gate control signal according to the second control signal and the corresponding clock signal and outputs the gate control signal to the gate line.
Optionally, the 1 st shift buffer unit of the shift output buffer circuit directly outputs the second control signal as the gate control signal to the corresponding 1 st gate line in the display panel; the control end of the Nth shift buffer unit of the shift output buffer circuit is connected with the second input end; the input end of the Nth shift buffer unit is connected with the output end of the (N-1) th shift buffer unit, the output end of the Nth shift buffer unit outputs the grid control signal of the corresponding Nth grid line in the display panel, and the output end of the Nth shift buffer unit is connected with the input end of the (N + 1) th shift buffer unit; wherein, N is a natural number which is more than or equal to 2.
Optionally, the 1 st shift buffer unit of the shift output buffer circuit directly outputs the second control signal as the gate control signal to the corresponding 1 st gate line in the display panel, and the output terminal of the 1 st shift buffer unit is directly connected to the input terminal of the 2 nd shift buffer unit; the Nth shift buffer unit comprises a trigger, and the control end of the trigger of the Nth shift buffer unit is connected with the second input end; the input end of the trigger of the Nth shift buffer unit of the shift output buffer circuit is connected with the output end of the trigger of the Nth-1 th shift buffer unit; an output terminal of the flip-flop of the nth shift buffer unit outputs a gate control signal of a corresponding nth gate line in the display panel, and an output terminal of the flip-flop of the nth shift buffer unit is connected to an input terminal of the flip-flop of the (N + 1) th shift buffer unit; wherein, N is a natural number which is more than or equal to 2.
Optionally, the 1 st shift buffer unit of the shift output buffer circuit includes a buffer, an input terminal of the buffer is directly connected to an output terminal of the level shifter circuit, an output terminal of the buffer outputs a gate control signal corresponding to the 1 st gate line in the display panel, and an output terminal of the 1 st shift buffer unit is directly connected to an input terminal of the 2 nd shift buffer unit; the Nth shift buffer unit of the shift output buffer circuit comprises a trigger and a buffer; the control end of the trigger of the Nth shift buffer unit is connected with the second input end; the output end of the trigger of the Nth shift buffer unit is connected with the input end of the buffer of the Nth shift buffer unit; an output terminal of the buffer of the nth shift buffer unit outputs a gate control signal of a corresponding nth gate line in the display panel, and an output terminal of the buffer of the nth shift buffer unit is connected to an input terminal of the flip-flop of the (N + 1) th shift buffer unit; the input end of the flip-flop of the Nth shift buffer unit is connected with the output end of the flip-flop of the (N-1) th shift buffer unit; wherein, N is a natural number which is more than or equal to 2.
Optionally, each shift buffer unit further includes a voltage stabilizing circuit; the voltage stabilizing circuit is connected between the output end of the current shift buffer unit and the ground wire.
Optionally, the level shift circuit includes a high level signal receiving terminal and a low level signal receiving terminal, which respectively receive the high level signal and the low level signal, and the level shift circuit performs level shift on the logic control signal according to the high level signal and the low level signal to generate the second control signal.
Optionally, the logic control circuit is a first trigger, the first trigger is a rising edge trigger, a control end of the first trigger is connected to the second input end, an input end of the first trigger is connected to the first input end, an output end of the first trigger is connected to an input end of the level conversion circuit, and an output end of the first trigger outputs the logic control signal to the level conversion circuit.
Optionally, the first control signal is a frame start signal.
The application also discloses a generation method of the grid control signal, which comprises the following steps:
receiving a first control signal and a clock signal, and generating a logic control signal;
carrying out level conversion on the logic control signal to generate a second control signal;
generating a grid control signal of the 1 st grid line according to the second control signal and the clock signal, and outputting the grid control signal to the corresponding 1 st grid line in the display panel; and
shifting step by step according to the grid control signal of the 1 st grid line, respectively generating a grid control signal of the Nth grid line, and outputting the grid control signal to the corresponding Nth grid line in the display panel;
wherein N is a natural number greater than or equal to 2; the low level and the high level of the second control signal are preset low level and high level for driving the display panel.
The application also discloses a display device, display device includes display panel, and with display panel drive connection's at least one as above gate drive module, gate drive module generates gate control signal jointly, and output extremely corresponding gate line in the display panel.
Compared with the scheme of shifting first and then performing level conversion, the gate driving module firstly generates a first control signal into a second control signal through a level conversion circuit, and the second control signal generates a plurality of gate control signals corresponding to the gate lines through a shift output buffer circuit; because the level is shifted after the level conversion, the effect can be realized by only arranging one level converter without a plurality of level converters which are in one-to-one correspondence with the grid lines in the display panel, the area of a grid driving chip is greatly saved, the design of an internal circuit of the grid driving chip is simplified, and the cost of the grid driving chip is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic structural diagram of a gate driving module according to an embodiment of the present application;
fig. 2 is a circuit diagram of a gate driving module according to an embodiment of the present application;
FIG. 3 is a timing waveform diagram of an embodiment of the present application;
fig. 4 is a flowchart illustrating a method for generating a gate control signal according to another embodiment of the present application;
fig. 5 is a schematic view of a display device according to another embodiment of the present application.
100, a gate driving module; 110. a first input terminal; 120. a second input terminal; 130. a logic control circuit; 131. a first flip-flop; 140. a level conversion circuit; 141. a level shifter; 150. a shift output buffer circuit; 160. a shift buffer unit; 161. a trigger; 162. a buffer; 190. a voltage stabilizing circuit; 200. a display panel; 210. a gate line; 300. a display device.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
As shown in fig. 1 and fig. 2, as an embodiment of the present application, a gate driving module 100 of a display panel is disclosed, the gate driving module 100 includes a first input terminal 110 receiving a first control signal, a second input terminal 120 receiving a clock signal, a logic control circuit 130 receiving the first control signal input by the first input terminal 110 and the clock signal input by the second input terminal 120 to generate a logic control signal, a level shift circuit 140, and a shift output buffer circuit 150 receiving the clock signal input by the second input terminal 120; specifically, the input terminal of the logic control circuit 130 is coupled to the first input terminal 110 and the second input terminal 120, and the logic control circuit 130 receives the first control signal input by the first input terminal 110 and the clock signal input by the second input terminal 120 to generate a logic control signal; an input end of the level shift circuit 140 is coupled to an output end of the logic control circuit 130, and performs level shift on the logic control signal to generate a second control signal; the shift output buffer circuit 150 is coupled to the second input terminal 120 and the output terminal of the level shift circuit 140, and the shift output buffer circuit 150 receives the first control signal output by the level shift circuit 140 and the clock signal output by the second input terminal 120 at the same time; the gate driving module 100 includes a gate line 210 coupled to the shift output buffer circuit 150.
Wherein the shift output buffer circuit 150 comprises a plurality of cascaded shift buffer units 160; an input terminal of the level shift circuit 140 is coupled to an output terminal of the logic control circuit 130, and the level shift circuit 140 performs level shift on the logic control signal to generate a second control signal, and outputs the second control signal to the shift output buffer circuit 150; the low level and the high level of the second control signal are preset drives the low level and the high level of the display panel, the shift output buffer circuit 150 generates the grid control signals corresponding to the grid lines in the display panel respectively through the second control signal and the clock signal, and the shift is performed after the level conversion, so that a plurality of level converters corresponding to the grid lines in the display panel one to one are not needed, the number of level conversion circuits is greatly reduced, components required by a grid driving module are saved, the chip area is reduced, and the chip cost of the grid driving module is reduced.
This application will be driven display panel's low level and high level mainly lean on level shift circuit carries out the conversion and obtains, level shift circuit includes high level signal receiving terminal and low level signal receiving terminal, receives high level signal and low level signal respectively, level shift circuit will logic control signal carries out level shift and generates the second control signal according to high level signal and low level signal. The level conversion circuit comprises a level converter, and the level converter converts a logic control signal output by the first trigger into a second control signal and outputs the second control signal to the shift output buffer circuit.
The shift output buffer circuit 150 includes a plurality of cascaded shift buffer cells 160, and the 1 st shift buffer cell of the shift output buffer circuit directly outputs a second control signal as a gate control signal to a corresponding 1 st gate line within the display panel; specifically, the shift buffer unit 160 of the shift output buffer circuit 1 includes a buffer 161, an input terminal of the buffer 162 is directly connected to an output terminal of the level shifter circuit 140, an output terminal of the buffer 162 outputs a gate control signal corresponding to the 1 st gate line in the display panel, and an output terminal of the shift buffer unit 160 of the 1 st is directly connected to an input terminal of the shift buffer unit 160 of the 2 nd.
The internal structure of the shift buffer unit 160 cascaded with the first shift buffer unit is the same, taking N shift buffer units as an example (where N is a natural number greater than or equal to 2), the control terminal of the nth shift buffer unit 160 is connected to the second input terminal 120; an input terminal of the nth shift buffer unit 160 is connected to an output terminal of the N-1 th shift buffer unit 160, an output terminal of the nth shift buffer unit 160 outputs a gate control signal corresponding to the nth gate line in the display panel 200, and an output terminal of the nth shift buffer unit is connected to an input terminal of the N +1 th shift buffer unit. The cascaded shift buffer units 160 may implement a shift function, generate and output gate control signals corresponding to gate lines in the display panel according to corresponding clock signals and second control signals, and after the generated nth gate control signal is output to the display panel, the N +1 th shift buffer unit generates and outputs an N +1 th gate control signal to the display panel according to the nth gate control signal and a corresponding N +1 th clock signal.
Unlike the specific circuit of the shift buffer unit 160 of the 1 st, the shift buffer unit 160 of the nth includes a flip-flop 161 and a buffer 162; the buffer in the nth shift buffer unit may be the same as the buffer in the 1 st shift buffer unit. In fig. 2, the buffers in the 1 st shift buffer unit to the buffers in the nth shift buffer unit are sequentially the first buffer (Output buffer 1) … … nth buffer (Output buffer N), and the control terminal of the flip-flop 161 of the nth shift buffer unit 160 is connected to the second input terminal 120; the Output terminal of the flip-flop 161 of the nth shift buffer unit is connected to the input terminal of the buffer (Output buffer N) of the nth shift buffer unit; an output terminal of the buffer of the nth shift buffer unit 160 outputs a gate control signal corresponding to an nth gate line within the display panel, and an output terminal of the buffer of the nth shift buffer unit 160 is connected to an input terminal of the flip-flop of the (N + 1) th shift buffer unit; the input terminal of the flip-flop of the nth shift buffer unit is connected to the output terminal of the flip-flop 161 of the N-1 st shift buffer unit.
In order to ensure the stability of the voltage output by the shift buffer unit, the nth shift buffer unit further comprises a voltage stabilizing circuit, wherein the voltage stabilizing circuit comprises a capacitor; the voltage stabilizing circuit is connected between the output end of the current shift buffer unit and the ground wire, N is a natural number which is more than or equal to 1, and each shift buffer unit comprises a capacitor. The provision of the capacitor may help the shift buffer unit to maintain the previous output voltage.
In the gate driving module 100, the logic control circuit 130 may be a first flip-flop 131, the first flip-flop 131 is a rising edge flip-flop, a control terminal of the first flip-flop 131 is connected to the second input terminal 120, an input terminal of the first flip-flop 131 is connected to the first input terminal 110, an output terminal of the first flip-flop 131 is connected to an input terminal of the level shift circuit 140, and an output terminal of the first flip-flop 131 outputs the logic control signal to the level shift circuit 140; the flip-flops in the Nth shift buffer unit may be selected from the same flip-flops as the first flip-flop 131, and as shown in FIG. 2, the buffers in the first to Nth shift buffer units are sequentially labeled as a first flip-flop (D1) … … Nth flip-flop (Dn).
This scheme will now be further explained with reference to the circuit schematic of fig. 2 and the timing waveform schematic of fig. 3. The level shifter 141 converts the voltage at the input terminal into a desired voltage according to a first control signal (e.g., a frame start signal STV) for output; the output buffers 1, 2, 3 … …, n are buffers 162, which can not only output the second control signal, but also amplify the output capability. D1, D2, D3, … … and Dn are rising edge flip-flops 161, which function to assign the logic voltage of the D terminal to Q when the control terminal CLK terminal receives a rising edge signal; CLK1 and CLK2 … … CLKn provide the first, second and third … … nth control signals for the timing control chip; c1, C2, C3 … … Cn are the regulation capacitors of the buffer output.
When the D1 flip-flop receives CLK1 as a rising edge, the D1 flip-flop inputs a square wave signal as shown in fig. 2, and the square wave signal (the first control signal) with a low level and a high level of 0V to 3.3V is converted into a square wave signal (the second control signal) from VGL to VGH by the level shifter 141, and the square wave signal generates a gate control signal after passing through the shift output buffer circuit and is input into the display panel to drive the TFT to be turned on or off. The waveform of the gate control signal Output1 corresponding to the first gate line is shown in fig. 3.
When the rising edge of CLK2 comes, the D2 flip-flop outputs the input gate-output1 to output buffer2, which outputs a gate-output2 waveform. By analogy, when the gate-output n normally outputs, the gate-output1, gate-output2, … … and gate-output n-1 can normally output more stably due to the action of the voltage stabilizing capacitor. At the moment, the grid driving module can start to work normally, the complexity of an internal circuit of the grid driving module is simplified on the basis of realizing the original function, n-1 level converters and bidirectional shift register modules are omitted, the area of a grid driving chip where the grid driving module is located is saved, and therefore the cost for manufacturing the grid driving chip is saved.
It should be noted that the first control signal may be a frame start Signal (STV), but is not limited to be a frame start signal, and may also be a common ac signal as long as the start time of the gate control signal can be found. The first control signal may be output by a timing control chip (TCON) in the display panel, but the ac signal or the STV signal may not be limited to be output by the timing control chip in future according to different circuit architectures.
As shown in fig. 1 and 2, as another embodiment of the present application, another gate driving module 100 is disclosed, which is different from the above embodiment in that the 1 st shift buffer unit 160 directly outputs the second control signal as the gate control signal to the corresponding 1 st gate line in the display panel, and the output terminal of the 1 st shift buffer unit 160 is directly connected to the input terminal of the 2 nd shift buffer unit.
The nth (N is a natural number greater than or equal to 2) shift buffer unit 160 includes a flip-flop, and a control terminal of the flip-flop of the nth shift buffer unit is connected to the second input terminal; the input terminal of the flip-flop of the nth shift buffer unit 160 is connected to the output terminal of the flip-flop of the N-1 th shift buffer unit; an output terminal of the flip-flop of the nth shift buffer unit 160 outputs a gate control signal corresponding to an nth gate line in the display panel, and an output terminal of the flip-flop of the nth shift buffer unit 160 is connected to an input terminal of the flip-flop of the N +1 th shift buffer unit 160.
Correspondingly, the level shifter performs level shifting on the logic control signal to generate a second control signal, and outputs the second control signal to the shift buffer unit; the shift buffer unit respectively generates the gate control signals corresponding to the gate lines in the display panel through the second control signal and the clock signal, and the shift buffer unit does not need a buffer for amplification, so that the number of the buffers can be saved.
As shown in fig. 4, as another embodiment of the present application, a method for generating a gate control signal corresponding to the gate driving module is disclosed, which includes:
s1: receiving a first control signal and a clock signal, and generating a logic control signal;
s2: carrying out level conversion on the logic control signal to generate a second control signal;
s3: generating a grid control signal of the 1 st grid line according to the second control signal and the clock signal, and outputting the grid control signal to the corresponding 1 st grid line in the display panel;
s4: shifting step by step according to the grid control signal of the 1 st grid line, respectively generating a grid control signal of the Nth grid line, and outputting the grid control signal to the corresponding Nth grid line in the display panel;
and the low level and the high level of the second control signal are preset low level and high level for driving the display panel.
As shown in fig. 5, as another embodiment of the present application, the present application further discloses a display device 300, where the display device 300 includes a display panel 200, and at least one gate driving module 100 as described above, which is in driving connection with the display panel, and the gate driving modules 100 jointly generate a gate control signal and output the gate control signal to corresponding gate lines 210 in the display panel 200.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, which can be applied to the above solutions.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A gate driving module, comprising:
a first input terminal receiving a first control signal;
a second input terminal receiving a clock signal;
a logic control circuit, an input terminal of the logic control circuit being coupled to the first input terminal and the second input terminal, the logic control circuit receiving the first control signal input by the first input terminal and the clock signal input by the second input terminal to generate a logic control signal;
the input end of the level conversion circuit is coupled with the output end of the logic control circuit, and the level conversion circuit performs level conversion on the logic control signal to generate a second control signal;
a shift output buffer circuit coupled to the second input terminal and the output terminal of the level shift circuit, the shift output buffer circuit receiving the second control signal output by the level shift circuit and the clock signal output by the second input terminal; and
a gate line coupled to the shift output buffer circuit;
the shift output buffer circuit comprises a plurality of cascaded shift buffer units, wherein the shift buffer unit of the first stage generates a gate control signal according to the second control signal and outputs the gate control signal to the gate line, and from the shift buffer unit of the second stage, the shift buffer unit of each stage generates a gate control signal according to an output end signal of the shift buffer unit of the previous stage and the corresponding clock signal and outputs the gate control signal to the gate line.
2. A gate driving module as claimed in claim 1, wherein the shift buffer unit 1 of the shift output buffer circuit directly outputs the second control signal as the gate control signal to the corresponding gate line 1 in the display panel;
the control end of the Nth shift buffer unit of the shift output buffer circuit is connected with the second input end; the input end of the Nth shift buffer unit is connected with the output end of the (N-1) th shift buffer unit, the output end of the Nth shift buffer unit outputs the grid control signal of the corresponding Nth grid line in the display panel, and the output end of the Nth shift buffer unit is connected with the input end of the (N + 1) th shift buffer unit;
wherein, N is a natural number which is more than or equal to 2.
3. A gate driving module as claimed in claim 1, wherein the shift buffer unit 1 of the shift output buffer circuit directly outputs the second control signal as the gate control signal to the corresponding gate line 1 in the display panel, and the output terminal of the shift buffer unit 1 is directly connected to the input terminal of the shift buffer unit 2;
the Nth shift buffer unit of the shift output buffer circuit comprises a trigger, and the control end of the trigger of the Nth shift buffer unit is connected with the second input end;
the input end of the flip-flop of the Nth shift buffer unit is connected with the output end of the flip-flop of the (N-1) th shift buffer unit;
the output end of the flip-flop of the Nth shift buffer unit outputs a gate control signal of a corresponding Nth gate line in the display panel, and the output end of the flip-flop of the Nth shift buffer unit is connected with the input end of the flip-flop of the (N + 1) th shift buffer unit;
wherein, N is a natural number which is more than or equal to 2.
4. A gate driving module as claimed in claim 1, wherein the shift buffer unit 1 of the shift output buffer circuit comprises a buffer, an input terminal of the buffer is directly connected to an output terminal of the level shifter circuit, an output terminal of the buffer outputs a gate control signal corresponding to the gate line 1 of the display panel, and an output terminal of the shift buffer unit 1 is directly connected to an input terminal of the shift buffer unit 2;
the Nth shift buffer unit of the shift output buffer circuit comprises a trigger and a buffer;
the control end of the trigger of the Nth shift buffer unit is connected with the second input end;
the output end of the trigger of the Nth shift buffer unit is connected with the input end of the buffer of the Nth shift buffer unit;
the output end of the buffer of the Nth shift buffer unit outputs a gate control signal of a corresponding Nth gate line in the display panel, and the output end of the buffer of the Nth shift buffer unit is connected with the input end of the flip-flop of the (N + 1) th shift buffer unit;
the input end of the flip-flop of the Nth shift buffer unit is connected with the output end of the flip-flop of the (N-1) th shift buffer unit;
wherein N is a natural number of 2 or more.
5. A gate drive module as claimed in claim 3 or 4, wherein each of the shift buffer units further comprises a voltage stabilizing circuit; the voltage stabilizing circuit is connected between the output end of the current shift buffer unit and the ground wire.
6. The gate driving module of claim 1, wherein the level shifter circuit comprises a high level signal receiving terminal and a low level signal receiving terminal for receiving a high level signal and a low level signal, respectively, and the level shifter circuit performs level shifting on the logic control signal according to the high level signal and the low level signal to generate the second control signal.
7. The gate driving module of claim 1, wherein the logic control circuit is a first flip-flop, the first flip-flop is a rising edge flip-flop, a control terminal of the first flip-flop is connected to the second input terminal, an input terminal of the first flip-flop is connected to the first input terminal, an output terminal of the first flip-flop is connected to an input terminal of the level shift circuit, and an output terminal of the first flip-flop outputs the logic control signal to the level shift circuit.
8. The gate driving module of claim 1, wherein the first control signal is a frame start signal.
9. A method for generating a gate control signal, comprising the steps of:
receiving a first control signal and a clock signal, and generating a logic control signal;
carrying out level conversion on the logic control signal to generate a second control signal;
generating a grid control signal of the 1 st grid line according to the second control signal, and outputting the grid control signal to the corresponding 1 st grid line in the display panel; and
shifting step by step according to the grid control signal of the 1 st grid line, respectively generating a grid control signal of the Nth grid line, and outputting the grid control signal to the corresponding Nth grid line in the display panel;
the low level and the high level of the second control signal are preset low level and high level for driving the display panel;
wherein N is a natural number of 2 or more.
10. A display device, comprising a display panel, and at least one gate driving module according to any one of claims 1 to 8 in driving connection with the display panel, wherein the gate driving module generates a gate control signal and outputs the gate control signal to a corresponding gate line of the display panel.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN202110301058.XA CN113178174B (en) | 2021-03-22 | 2021-03-22 | Grid driving module, grid control signal generation method and display device |
| PCT/CN2021/142900 WO2022199189A1 (en) | 2021-03-22 | 2021-12-30 | Gate drive module, method for generating gate control signal, and display apparatus |
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| CN202110301058.XA CN113178174B (en) | 2021-03-22 | 2021-03-22 | Grid driving module, grid control signal generation method and display device |
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| CN113178174B (en) * | 2021-03-22 | 2022-07-08 | 重庆惠科金渝光电科技有限公司 | Grid driving module, grid control signal generation method and display device |
| CN114429746B (en) * | 2022-01-18 | 2024-03-15 | Tcl华星光电技术有限公司 | Display device and electronic apparatus |
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| CN113178174A (en) | 2021-07-27 |
| WO2022199189A1 (en) | 2022-09-29 |
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