WO2022199189A1

WO2022199189A1 - Gate drive module, method for generating gate control signal, and display apparatus

Info

Publication number: WO2022199189A1
Application number: PCT/CN2021/142900
Authority: WO
Inventors: 彭格格; 余思慧
Original assignee: 重庆惠科金渝光电科技有限公司; 惠科股份有限公司
Priority date: 2021-03-22
Filing date: 2021-12-30
Publication date: 2022-09-29
Also published as: CN113178174B; CN113178174A

Abstract

A gate drive module (100), comprising a logic control circuit (130), which receives a first control signal and a clock signal to generate a logic control signal, a level conversion circuit (140), and a shift output buffer circuit (150), which receives the clock signal, wherein the level conversion circuit (140) performs level conversion on the logic control signal to generate a second control signal, and outputs the second control signal to the shift output buffer circuit (150); and the shift output buffer circuit (150) respectively generates, by means of the second control signal and the clock signal, a gate control signal corresponding to a gate line (210) in a display panel (200).

Description

Gate driving module, method for generating gate control signal, and display device

This application claims the priority of the Chinese patent application filed on March 22, 2021, with the application number 202110301058X, and the application title is "A gate driver module, a method for generating gate control signals, and a display device", The entire contents of which are incorporated herein by reference.

technical field

The present application relates to the field of display technology, and in particular, to a gate driving module, a method for generating a gate control signal, and a display device.

Background technique

The statements herein merely provide background information related to the present application and do not necessarily constitute prior art.

TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display) is one of the main varieties of current flat panel display, and has become an important display platform in modern IT and video products. The main driving principle of TFT-LCD is that the system motherboard connects the R/G/B compression signal, control signal and power supply to the connector on the printed circuit board through wires, and the data passes through the timing controller (Timing Controller, TCON) on the printed circuit board. ) after processing, connect with the display area through the source-level thin film driver chip (Source-Chip on Film, S-COF) and the gate thin film driver chip (Gate-Chip on Film, G-COF), so that the liquid crystal display can obtain the required power and signal.

At present, the gate driver chip mainly accepts the control signal of TCON. With this control signal, it outputs the low level (VGL) and the high level (VGH) that drive the display panel through the level shifter. VGH is the control signal. The voltage at which the TFT is turned on, and VGL is the voltage that controls the turn-off of the TFT. The output VGH and VGL are connected to the inside of the panel through the output buffer. Multiple level shifters corresponding to the gate lines inside the display panel are required, but this setting occupies The area of the gate driving chip is too large and the cost is high.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide a gate driving module, a method for generating a gate control signal and a display device, which saves the area of the gate driving chip, simplifies the internal circuit design of the gate driving chip, and reduces the size of the gate driving chip. cost.

The present application discloses a gate driving module. The gate driving module includes a first input terminal for receiving a first control signal, a second input terminal for receiving a clock signal, and a logic control signal generated by receiving the first control signal and the clock signal. A logic control circuit, a level conversion circuit and a shift output buffer circuit for receiving a clock signal; the input end of the logic control circuit is coupled to the first input end and the second input end, and the logic control circuit receives the The first control signal input from the first input terminal and the clock signal input from the second input terminal generate a logic control signal; the input terminal of the level conversion circuit is coupled to the output terminal of the logic control circuit Then, perform level conversion on the logic control signal to generate a second control signal; the shift output buffer circuit is coupled with the second input terminal and the output terminal of the level conversion circuit, and the shift output buffer circuit is coupled with the second input terminal and the output terminal of the level conversion circuit. The buffer circuit simultaneously receives the first control signal output from the level conversion circuit and the clock signal output from the second input terminal; the gate driving module includes a gate line coupled to the shift output buffer circuit; wherein, The shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units generates a gate control signal according to the second control signal and the corresponding clock signal and outputs it to the shift output buffer. the gate line.

The present application also discloses a method for generating a gate control signal, comprising the steps of:

receiving a first control signal and a clock signal to generate a logic control signal;

performing level conversion on the logic control signal to generate a second control signal;

generating a gate control signal of the first gate line according to the second control signal and the clock signal, and outputting it to the corresponding first gate line in the display panel; and

According to the gate control signal of the first gate line, the gate control signal is shifted step by step, and the gate control signal of the Nth gate line is respectively generated and output to the corresponding Nth gate line in the display panel;

Wherein, N is a natural number greater than or equal to 2; the low level and high level of the second control signal are preset low level and high level for driving the display panel.

The present application also discloses a display device, the display device includes a display panel, and a gate driving module drivingly connected to the display panel, the gate driving module includes a first input terminal for receiving a first control signal, a clock receiving a second input end of the signal, a logic control circuit for receiving the first control signal and the clock signal to generate a logic control signal, a level conversion circuit, and a shift output buffer circuit for receiving the clock signal; the input end of the logic control circuit is connected to the a first input terminal and a second input terminal are coupled, and the logic control circuit generates a logic control signal by receiving the first control signal input from the first input terminal and the clock signal input from the second input terminal; The input end of the level conversion circuit is coupled to the output end of the logic control circuit, and the logic control signal is level-converted to generate a second control signal; the shift output buffer circuit is connected to the second control signal. The input end and the output end of the level shift circuit are coupled, and the shift buffer circuit simultaneously receives the first control signal output by the level shift circuit and the clock signal output by the second input end; gate driving The module includes a gate line coupled to the shift output buffer circuit; wherein the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units according to the first The two control signals and the corresponding clock signal generate gate control signals and output them to the gate lines.

Compared with the previous scheme of first shifting and then performing level conversion, the gate driving module of the present application first generates the second control signal by passing the first control signal through the level conversion circuit, and the second control signal passes through the shift buffer. The circuit then generates multiple gate control signals corresponding to the gate lines; because the level shift is performed first and then the shift is performed, multiple level shifters corresponding to the internal gate lines of the display panel are not required, and it is only necessary to set One level converter can achieve the above effects, which greatly saves the area of the gate driving chip, simplifies the internal circuit design of the gate driving chip, and reduces the cost of the gate driving chip.

Description of drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, constitute a part of the specification, illustrate embodiments of the application, and together with the description, serve to explain the principles of the application. Obviously, the drawings in the following description are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. In the attached image:

FIG. 1 is a schematic structural diagram of a gate driving module according to an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of a gate driving module according to an embodiment of the present application;

3 is a schematic diagram of timing waveforms according to an embodiment of the present application;

4 is a schematic diagram of a circuit of a gate driving module according to another embodiment of the present application;

FIG. 5 is a schematic flowchart of a method for generating a gate control signal according to another embodiment of the present application.

Detailed ways

Specific structural and functional details disclosed herein are merely representative and for purposes of describing example embodiments of the present application. The application may, however, be embodied in many alternative forms and should not be construed as limited only to the embodiments set forth herein.

In the description of this application, it should be understood that the terms "center", "lateral", "top", "bottom", "left", "right", "vertical", "horizontal", "top", The orientation or positional relationship indicated by "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying the indicated device. Or elements must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as a limitation of the present application. In addition, the terms "first" and "second" are for descriptive purposes only, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, "plurality" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood in specific situations.

The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the exemplary embodiments. As used herein, the singular forms "a", "an" and "an" are intended to include the plural unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and/or "comprising" as used herein specify the presence of stated features, integers, steps, operations, units and/or components, but do not preclude the presence or addition of one or more Other features, integers, steps, operations, units, components and/or combinations thereof.

The present application will be further described below with reference to the accompanying drawings and embodiments.

As shown in FIG. 1 and FIG. 2 , as an embodiment of the present application, a gate driving module 100 of a display panel is disclosed. The gate driving module 100 includes a first input terminal 110 for receiving a first control signal, a clock receiving The second input terminal 120 of the signal, the logic control circuit 130 that receives the first control signal input from the first input terminal 110 and the clock signal input from the second input terminal 120 to generate a logic control signal, and the level The conversion circuit 140 and the shift output buffer circuit 150 receiving the clock signal input from the second input terminal 120 ; specifically, the input terminal of the logic control circuit 130 and the first input terminal 110 and the second input terminal 120 coupled, the logic control circuit 130 receives the first control signal input from the first input terminal 110 and the clock signal input from the second input terminal 120 to generate a logic control signal; the level conversion circuit The input end of 140 is coupled to the output end of the logic control circuit 130, and the logic control signal is level-converted to generate a second control signal; the shift output buffer circuit 150 is connected to the second input end 120 and the output terminal of the level conversion circuit 140 is coupled, the shift buffer circuit 150 simultaneously receives the first control signal output by the level conversion circuit 140 and the clock signal output by the second input terminal 120; The pole driving module 100 includes a gate line 210 coupled to the shift output buffer circuit 150 .

The shift output buffer circuit 150 includes a plurality of cascaded shift buffers 160; the input end of the level shift circuit 140 is coupled to the output end of the logic control circuit 130, and the level shift circuit 130 The circuit 140 performs level conversion of the logic control signal to generate a second control signal, and outputs it to the shift output buffer circuit 150; the low level and high level of the second control signal are preset to drive the The low level and the high level of the display panel, the shift output buffer circuit 150 respectively generates the gate control signal corresponding to the gate line in the display panel through the second control signal and the clock signal, because the power is performed first After the level conversion is shifted, there is no need for multiple level shifters corresponding to the gate lines inside the display panel, which greatly reduces the number of level shift circuits, saves the components required for the gate drive module, and reduces the The chip area is reduced, thereby reducing the chip cost of the gate drive module.

In the present application, the low level and high level for driving the display panel are mainly obtained by conversion by the level conversion circuit. The level conversion circuit includes a high-level signal receiving end and a low-level signal receiving end, respectively. After receiving the high level signal and the low level signal, the level conversion circuit performs level conversion on the logic control signal according to the high level signal and the low level signal to generate a second control signal. The level shift circuit includes a level shifter, and the level shifter converts the logic control signal output by the first flip-flop into a second control signal and outputs it to the shift output buffer circuit.

The shift output buffer circuit 150 includes a plurality of cascaded shift buffers 160, and the first shift buffer 160 of the shift output buffer circuit directly outputs the second control signal as a gate control signal to the corresponding first gate line in the display panel; specifically, the first shift buffer 160 of the shift output buffer circuit includes a buffer 161, and the input end of the buffer 162 is directly The output terminal of the level conversion circuit 140 is connected, and the output terminal of the buffer 162 outputs the gate control signal corresponding to the first gate line in the display panel, and the first one of the shift The output terminal of the buffer 160 is directly connected to the input terminal of the second shift buffer 160 .

Afterwards, the internal structure of the shift buffer 160 cascaded with the first shift buffer is the same. Taking N shift buffers as an example (the N is a natural number greater than or equal to 2), the Nth The control terminals of the shift buffers 160 are connected to the second input terminal 120 ; the input terminals of the Nth shift buffers 160 are connected to the output terminals of the N-1th shift buffer 160 , The output terminal of the Nth shift buffer 160 outputs the gate control signal corresponding to the Nth gate line in the display panel 200 , and the output terminal of the Nth shift buffer is connected to The input terminal of the N+1th said shift buffer. The cascaded shift buffers 160 can realize the function of shifting, and generate and output gate control signals corresponding to the gate lines in the display panel according to the corresponding clock signal and the second control signal. After the gate control signal is output to the display panel, the N+1th shift buffer generates the N+1th gate control signal according to the Nth gate control signal and the corresponding N+1th clock signal and outputs it to the display panel. Display panel.

Different from the specific circuit of the first shift buffer 160, the Nth shift buffer 160 includes a flip-flop 161 and a buffer 162; the buffer in the Nth shift buffer The same buffer as the first said shift buffer can be used. In FIG. 2, the buffers in the first shift buffer to the buffers in the Nth shift buffer are sequentially the first buffer (Output buffer 1)...the Nth buffer (Output buffer n), the control end of the flip-flop 161 of the Nth shift buffer 160 is connected to the second input end 120; the control end of the flip-flop 161 of the Nth shift buffer 161 The output end is connected to the input end of the buffer (Output buffer n) of the Nth shift buffer; the output end of the buffer of the Nth shift buffer 160 outputs and the display panel The gate control signal of the corresponding Nth gate line in the Nth shift buffer 160, and the output end of the buffer of the Nth shift buffer 160 is connected to the N+1th shift buffer. The input terminal of the flip-flop; the input terminal of the flip-flop of the Nth shift buffer is connected to the output terminal of the flip-flop 161 of the N-1th shift buffer.

In order to ensure the stability of the voltage output by the shift buffer, the Nth shift buffer further includes a voltage stabilizing circuit, and the voltage stabilizing circuit includes a capacitor; the voltage stabilizing circuit is connected to the current shift buffer. Between the output end of the device and the ground line, N is a natural number greater than or equal to 1, and each of the shift buffers includes a capacitor. The setting of the capacitor can help the shift buffer maintain the previous output voltage.

In the above gate driving module 100, the logic control circuit 130 may be a first flip-flop 131, the first flip-flop 131 is a rising edge flip-flop, and the control end of the first flip-flop 131 is connected to the The second input terminal 120, the input terminal of the first flip-flop 131 is connected to the first input terminal 110, the output terminal of the first flip-flop 131 is connected to the input terminal of the level conversion circuit 140, and the first flip-flop 131 is connected to the input terminal of the level conversion circuit 140. The output terminal of a flip-flop 131 outputs the logic control signal to the level conversion circuit 140; the flip-flop in the Nth shift buffer can be selected from the same flip-flop as the first flip-flop 131, As shown in FIG. 2 , the buffers in the first flip-flop 131 to the N-th shift buffer are sequentially designated as the first flip-flop ( D1 ) . . . the N-th flip-flop (Dn).

The present solution will now be further described with reference to the schematic circuit diagram of FIG. 2 and the schematic diagram of timing waveforms of FIG. 3 . The level converter 141 converts the input terminal voltage into a required voltage for output according to the first control signal (such as the frame start signal STV); output buffer1, output buffer2, output buffer3...output buffer n is a buffer The controller 162 is capable of not only outputting the second control signal, but also amplifying the output. D1, D2, D3, ..., Dn are rising edge flip-flops 161, whose function is to assign the logic potential of the D terminal to Q when the control terminal CLK terminal receives the rising edge of the signal; CLK1, CLK2...CLKn Provide the first, second, third...nth control signal for the timing control chip; C1, C2, C3...Cn are the stabilizing capacitors output by the buffer.

Set the initial state of the first control signal (STV signal) as low level L, when the D1 flip-flop receives the rising edge of CLK1, the D1 flip-flop input is a square wave signal as shown in Figure 2, the low level The square wave signal (the first control signal) with the high level of 0V to 3.3V is converted into the square wave signal (the second control signal) from VGL to VGH through the level shifter 141, and the square wave signal passes through the shift output buffer. After the circuit, a gate control signal is generated and input into the display panel to drive the TFT to be turned on and off. The waveform of the gate control signal Output 1 corresponding to the first gate line is shown in FIG. 3 .

When the rising edge of CLK2 comes, the D2 flip-flop outputs the input gate-output1 to the output buffer2, thereby outputting the gate-output 2 waveform. By analogy, when gate-output n is output normally, gate-output1, gate-output2, ..., gate-output n-1 can output normally more stably because of the function of its voltage-stabilizing capacitor. At this time, the gate drive module can start to work normally. On the basis of realizing the original function, the complexity of the internal circuit of the gate drive module is simplified, and n-1 level converters and bidirectional shift register modules are saved, saving The area of the gate driving chip where the gate driving module is located, thereby saving the cost of manufacturing the gate driving chip.

It should be noted that the first control signal can be a frame start signal (STV), but is not limited to being a frame start signal, and can also be an ordinary AC signal, as long as the gate control signal can be activated time. The first control signal may be output by a timing control chip (TCON) in the display panel, but in the future with different circuit structures, the AC signal or STV signal here may not be limited to output by the timing control chip.

As shown in FIG. 1 and FIG. 2 , as another embodiment of the present application, another gate driving module 100 is disclosed. Different from the above embodiment, the first shift buffer 160 directly converts the first The two control signals are output as gate control signals to the corresponding first gate line in the display panel, and the output end of the first shift buffer 160 is directly connected to the second shift buffer. input.

The Nth (N is a natural number greater than or equal to 2) the shift buffer 160 includes a flip-flop 170, and the control terminal of the flip-flop of the Nth shift buffer is connected to the second input terminal; The input segments of the flip-flops 170 of the N shift buffers 160 are connected to the outputs of the flip-flops of the N-1th shift buffer; the Nth shift buffer The output terminal of the flip-flop 170 of 160 outputs a gate control signal corresponding to the Nth gate line in the display panel, and the Nth flip-flop 170 of the shift buffer 160 outputs a gate control signal. The output terminal is connected to the input terminal of the flip-flop 170 of the N+1th shift buffer 160 .

Correspondingly, the level converter performs level conversion on the logic control signal to generate a second control signal, and outputs it to the shift output buffer unit; the shift output buffer unit passes the second control signal and the The clock signals respectively generate gate control signals corresponding to the gate lines in the display panel, and no buffers are needed for amplification, so that the number of buffers can also be saved.

As shown in FIG. 4 , as another embodiment of the present application, a method for generating a gate control signal corresponding to the above gate driving module is disclosed, including the steps of:

S1: receive the first control signal and the clock signal, and generate a logic control signal;

S2: perform level conversion on the logic control signal to generate a second control signal;

S3: generate a gate control signal of the first gate line according to the second control signal and the clock signal, and output it to the corresponding first gate line in the display panel;

S4: Shifting step by step according to the gate control signal of the first gate line, respectively generating the gate control signal of the Nth gate line, and outputting it to the corresponding Nth gate line in the display panel ;

Wherein, the low level and high level of the second control signal are preset low level and high level for driving the display panel.

As shown in FIG. 5 , as another embodiment of the present application, the present application further discloses a display device 300 . The display device 300 includes a display panel 200 , and at least one drive connected to the display panel is as described above. The gate driving module 100 , the gate driving modules 100 jointly generate gate control signals and output them to the corresponding gate lines 210 in the display panel 200 .

It should be noted that the limitations of the steps involved in this scheme are not considered to limit the sequence of steps without affecting the implementation of the specific scheme. The steps written in the front may be executed first. It can also be executed later, or even executed at the same time, as long as the solution can be implemented, it should be regarded as belonging to the protection scope of the present application.

The panel of the present application can be a TN panel (the full name is Twisted Nematic, that is, a twisted nematic panel), an IPS panel (In-Plane Switching, plane switching), a VA panel (Multi-domain Vertica Alignment, multi-quadrant vertical alignment technology), Of course, other types of panels may also be used, as applicable.

The above content is a further detailed description of the present application in conjunction with specific preferred embodiments, and it cannot be considered that the specific implementation of the present application is limited to these descriptions. For those of ordinary skill in the technical field of the present application, without departing from the concept of the present application, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present application.

Claims

A gate drive module, comprising:

a first input end, receiving a first control signal;

The second input terminal receives the clock signal;

a logic control circuit, the input end of the logic control circuit is coupled to the first input end and the second input end, the logic control circuit receives the first control signal input from the first input end and the The clock signal input by the second input terminal generates a logic control signal;

a level conversion circuit, the input end of the level conversion circuit is coupled with the output end of the logic control circuit, and the logic control signal is level-converted to generate a second control signal;

a shift output buffer circuit, coupled to the second input terminal and the output terminal of the level shift circuit, the shift buffer circuit simultaneously receives the first control signal output by the level shift circuit and the first control signal output by the level shift circuit the clock signal output from the two input terminals; and

a gate line, coupled to the shift output buffer circuit;

Wherein, the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units generates a gate control signal according to the second control signal and the corresponding clock signal, and generates a gate control signal. output to the gate line.
The gate driving module of claim 1, wherein the first shift buffer of the shift output buffer circuit directly outputs the second control signal to the display panel as a gate control signal The corresponding 1st gate line within;

The control terminal of the Nth shift buffer of the shift output buffer circuit is connected to the second input terminal; the input terminal of the Nth shift buffer is connected to the N-1th shift buffer The output end of the buffer, the output end of the Nth shift buffer outputs a gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer The output terminal of is connected to the input terminal of the N+1th shift buffer;

Wherein, the N is a natural number greater than or equal to 2.
The gate driving module of claim 1, wherein the first shift buffer of the shift output buffer circuit directly outputs the second control signal as a gate control signal to the display panel For the corresponding first gate line in the first gate line, the output end of the first shift buffer is directly connected to the input end of the second shift buffer;

The Nth shift buffer of the shift output buffer circuit includes a flip-flop, and the control terminal of the flip-flop of the Nth shift buffer is connected to the second input terminal;

The input section of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;

The output end of the flip-flop of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal. The output terminal of the flip-flop is connected to the input terminal of the flip-flop of the N+1th shift buffer;

Wherein, the N is a natural number greater than or equal to 2.
The gate driving module of claim 1, wherein the first shift buffer of the shift output buffer circuit comprises a buffer, and the input terminal of the buffer is directly connected to the level The output end of the conversion circuit, the output end of the buffer outputs the gate control signal corresponding to the first gate line in the display panel, and the output end of the first shift buffer is directly connected the input terminal of the second said shift buffer;

The Nth shift buffer of the shift output buffer circuit includes a flip-flop and a buffer;

The control end of the flip-flop of the Nth shift buffer is connected to the second input end;

The output end of the flip-flop of the Nth shift buffer is connected to the input end of the buffer of the Nth shift buffer;

The output end of the buffer of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal of the corresponding Nth gate line in the display panel. The output end of the buffer is connected to the input end of the flip-flop of the N+1th shift buffer;

The input end of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;

Wherein, the N is a natural number greater than or equal to 2.
The gate driving module of claim 3, wherein each of the shift buffers further comprises a voltage regulator circuit; the voltage regulator circuit is connected between the current output end of the shift buffer and the ground between the lines.
The gate driving module according to claim 1, wherein the level conversion circuit comprises a high-level signal receiving end and a low-level signal receiving end, respectively receiving the high-level signal and the low-level signal, so the The level conversion circuit performs level conversion on the logic control signal according to the high-level signal and the low-level signal to generate a second control signal.
The gate driving module of claim 1, wherein the logic control circuit is a first flip-flop, the first flip-flop is a rising edge flip-flop, and a control end of the first flip-flop is connected to the The second input terminal, the input terminal of the first flip-flop is connected to the first input terminal, the output terminal of the first flip-flop is connected to the input terminal of the level conversion circuit, and the output terminal of the first flip-flop is connected to the input terminal of the level conversion circuit. The output terminal outputs the logic control signal to the level conversion circuit.
The gate driving module of claim 1, wherein the first control signal is a frame start signal.
The gate driving module according to claim 4, wherein each of the shift buffers further comprises a voltage regulator circuit; one end of the voltage regulator circuit is connected between the output end of the current shift buffer and the voltage regulator circuit. Between the input ends of the flip-flop, the other end is grounded.
The gate driving module of claim 5, wherein each of the voltage stabilization units includes a voltage stabilization capacitor.
The gate driving module according to claim 7, wherein the rising edge of the clock signal and the corresponding rising edge of the gate control signal are at the same time.
11. The gate driving module of claim 11, wherein the falling edge of the gate-controlled signal corresponding to the scan line of the current row and the rising edge of the clock signal corresponding to the scan line of the next row are at the same time.
A method for generating a gate control signal, comprising the steps of:

receiving a first control signal and a clock signal to generate a logic control signal;

performing level conversion on the logic control signal to generate a second control signal;

generating a gate control signal of the first gate line according to the second control signal and the clock signal, and outputting it to the corresponding first gate line in the display panel; and

According to the gate control signal of the first gate line, the gate control signal is shifted step by step, and the gate control signal of the Nth gate line is respectively generated and output to the corresponding Nth gate line in the display panel;

Wherein, the low level and high level of the second control signal are preset low level and high level for driving the display panel.
The method for generating a gate control signal according to claim 13, wherein the display panel is connected to a gate driving module, and the gate driving module comprises:

a first input end, receiving a first control signal;

The second input terminal receives the clock signal;

a logic control circuit, the input end of the logic control circuit is coupled to the first input end and the second input end, the logic control circuit receives the first control signal input from the first input end and the The clock signal input by the second input terminal generates a logic control signal;

a level conversion circuit, the input end of the level conversion circuit is coupled with the output end of the logic control circuit, and the logic control signal is level-converted to generate a second control signal;

a shift output buffer circuit, coupled to the second input terminal and the output terminal of the level shift circuit, the shift buffer circuit simultaneously receives the first control signal output by the level shift circuit and the first control signal output by the level shift circuit the clock signal output from the two input terminals; and

a gate line, coupled to the shift output buffer circuit;

Wherein, the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units generates a gate control signal according to the second control signal and the corresponding clock signal, and generates a gate control signal. output to the gate line.
The method for generating a gate control signal according to claim 14, wherein the first shift buffer of the shift output buffer circuit directly outputs the second control signal as the gate control signal, which is the same as the gate control signal. the corresponding first gate line in the display panel, the output end of the first shift buffer is directly connected to the input end of the second shift buffer;

The Nth shift buffer of the shift output buffer circuit includes a flip-flop, and the control terminal of the flip-flop of the Nth shift buffer is connected to the second input terminal;

The input section of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;

The output end of the flip-flop of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal. The output terminal of the flip-flop is connected to the input terminal of the flip-flop of the N+1th shift buffer;

Wherein, the N is a natural number greater than or equal to 2;

Each of the shift buffers further includes a voltage-stabilizing circuit; the voltage-stabilizing circuit is connected between the output terminal of the current shift buffer and the ground line.
The method for generating a gate control signal according to claim 14, wherein the first shift buffer of the shift output buffer circuit comprises a buffer, and the input end of the buffer is directly connected to the The output end of the level conversion circuit, the output end of the buffer outputs the gate control signal corresponding to the first gate line in the display panel, and the first output of the shift buffer The terminal is directly connected to the input terminal of the second shift buffer;

The Nth shift buffer of the shift output buffer circuit includes a flip-flop and a buffer;

The control end of the flip-flop of the Nth shift buffer is connected to the second input end;

The output end of the flip-flop of the Nth shift buffer is connected to the input end of the buffer of the Nth shift buffer;

The output end of the buffer of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal of the corresponding Nth gate line in the display panel. The output end of the buffer is connected to the input end of the flip-flop of the N+1th shift buffer;

The input end of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;

Wherein, the N is a natural number greater than or equal to 2;

Each of the shift buffers further includes a voltage-stabilizing circuit; one end of the voltage-stabilizing circuit is connected between the current output end of the shift buffer and the input end of the flip-flop, and the other end is grounded.
A display device, comprising a display panel, and a gate driving module drivingly connected to the display panel, the gate driving module generates a gate control signal and outputs it to a corresponding gate line of the display panel; the The gate drive module includes:

a first input end, receiving a first control signal;

The second input terminal receives the clock signal;

a logic control circuit, the input end of the logic control circuit is coupled to the first input end and the second input end, the logic control circuit receives the first control signal input from the first input end and the The clock signal input by the second input terminal generates a logic control signal;

a level conversion circuit, the input end of the level conversion circuit is coupled with the output end of the logic control circuit, and the logic control signal is level-converted to generate a second control signal;

a shift output buffer circuit, coupled to the second input terminal and the output terminal of the level shift circuit, the shift buffer circuit simultaneously receives the first control signal output by the level shift circuit and the first control signal output by the level shift circuit a clock signal output from the two input terminals; and

a gate line, coupled to the shift output buffer circuit;

Wherein, the shift output buffer circuit includes a plurality of cascaded shift buffers, each of the shift output buffer units generates a gate control signal according to the second control signal and the corresponding clock signal, and generates a gate control signal. output to the gate line.
18. The display device of claim 17, wherein the first shift buffer of the shift output buffer circuit directly outputs the second control signal as a gate control signal to a second control signal in the display panel. The corresponding first gate line;

The control terminal of the Nth shift buffer of the shift output buffer circuit is connected to the second input terminal; the input terminal of the Nth shift buffer is connected to the N-1th shift buffer The output end of the buffer, the output end of the Nth shift buffer outputs a gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer The output terminal of is connected to the input terminal of the N+1th shift buffer;

Wherein, the N is a natural number greater than or equal to 2;

The level conversion circuit includes a high-level signal receiving terminal and a low-level signal receiving terminal, which respectively receive the high-level signal and the low-level signal, and the level conversion circuit according to the high-level signal and the low-level signal, The logic control signal is level-converted to generate a second control signal.
The display device of claim 17, wherein the first shift buffer of the shift output buffer circuit comprises a buffer, and the input end of the buffer is directly connected to the level conversion circuit , the output end of the buffer outputs the gate control signal corresponding to the first gate line in the display panel, and the output end of the first shift buffer is directly connected to the second an input of the shift buffer;

The Nth shift buffer of the shift output buffer circuit includes a flip-flop and a buffer;

The control end of the flip-flop of the Nth shift buffer is connected to the second input end;

The output end of the flip-flop of the Nth shift buffer is connected to the input end of the buffer of the Nth shift buffer;

The output end of the buffer of the Nth shift buffer outputs the gate control signal corresponding to the Nth gate line in the display panel, and the Nth shift buffer outputs the gate control signal of the corresponding Nth gate line in the display panel. The output end of the buffer is connected to the input end of the flip-flop of the N+1th shift buffer;

The input end of the flip-flop of the Nth shift buffer is connected to the output end of the flip-flop of the N-1th shift buffer;

Wherein, the N is a natural number greater than or equal to 2;

The logic control circuit is a first flip-flop, the first flip-flop is a rising edge flip-flop, the control terminal of the first flip-flop is connected to the second input terminal, and the input terminal of the first flip-flop is connected to the second input terminal. The first input terminal and the output terminal of the first flip-flop are connected to the input terminal of the level conversion circuit, and the output terminal of the first flip-flop outputs the logic control signal to the level conversion circuit.