CN109509420B - Reference voltage generating circuit and display device - Google Patents
Reference voltage generating circuit and display device Download PDFInfo
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- CN109509420B CN109509420B CN201811595734.3A CN201811595734A CN109509420B CN 109509420 B CN109509420 B CN 109509420B CN 201811595734 A CN201811595734 A CN 201811595734A CN 109509420 B CN109509420 B CN 109509420B
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The application discloses a reference voltage generating circuit and a display device, wherein the reference voltage generating circuit comprises a digital-to-analog converter, a time schedule controller, n voltage signal output ends, a signal trigger circuit and a communication switch circuit; the signal input end of the signal trigger circuit is connected with the first output end of the time schedule controller, n signal trigger ends of the signal trigger circuit are all connected with the second output end of the time schedule controller, and n signal output ends of the signal trigger circuit are correspondingly connected with n controlled ends of the communication switch circuit one by one; the n input ends of the communication switch circuit are connected with the output end of the digital-to-analog converter, and the n output ends of the communication switch circuit are connected with the n voltage signal output ends in a one-to-one correspondence mode. According to the technical scheme, the circuit structure of the chip can be simplified, and the cost of the chip is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a reference voltage generating circuit and a display device.
Background
In the display device, after voltage signals output by a system mainboard are processed by a time schedule controller, the voltage signals are connected with a display panel through a source electrode driving circuit and a grid electrode driving circuit, so that the display device can normally display. In order to enable the voltage output by the source driving circuit to conform to the watching habit of a user, a reference voltage needs to be provided for the source driving circuit, and the reference voltage can be generated through a digital adjustable gamma voltage chip, wherein each path of output in the chip needs to be converted by a digital-to-analog converter and then output to the source driving circuit, the number of output channels in the chip corresponds to the number of digital-to-analog converters one by one, and the complexity and the cost of circuits in the chip are increased due to the excessive number of digital-to-analog converters.
Disclosure of Invention
The application provides a reference voltage generating circuit and a display device, aiming at simplifying the circuit structure inside a chip and reducing the chip cost.
To achieve the above object, the present application provides a reference voltage generating circuit, including:
a digital-to-analog converter configured to output an analog voltage signal;
a time schedule controller;
n voltage signal output terminals;
the signal trigger circuit is provided with a signal input end, n signal trigger ends and n signal output ends, the signal input end of the signal trigger circuit is connected with the first output end of the time schedule controller, the n signal trigger ends of the signal trigger circuit are all connected with the second output end of the time schedule controller, and the signal trigger circuit is configured to receive a frame start signal output by the first output end of the time schedule controller and output a high-level control signal from one of the n signal output ends when receiving a clock signal output by the second output end of the time schedule controller;
the communication switch circuit is provided with n controlled ends, n input ends and n output ends, the n input ends of the communication switch circuit are connected with the output end of the digital-to-analog converter, the n controlled ends of the communication switch circuit are connected with the n signal output ends of the signal trigger circuit in a one-to-one correspondence manner, the n output ends of the communication switch circuit are connected with the n voltage signal output ends in a one-to-one correspondence manner, and the communication switch circuit is configured to generate a reference voltage signal and output the reference voltage signal from the output end corresponding to the controlled end when each controlled end receives a high-level control signal output by the signal trigger circuit;
wherein n is an integer greater than or equal to 1.
Optionally, the signal trigger circuit includes n sequentially connected flip-flops, a clock signal input end of each flip-flop is a signal trigger end of the signal trigger circuit, a data output end of each flip-flop is a signal output end of the signal trigger circuit, and a data input end of the flip-flop disposed at the head is a signal input end of the signal trigger circuit and is connected to a data output end of the flip-flop at the end position.
Optionally, in two adjacent flip-flops, the data output terminal of the flip-flop disposed at the previous position is connected to the data input terminal of the flip-flop disposed at the subsequent position.
Optionally, when any signal output end of the signal trigger circuit outputs a high-level control signal, the other n-1 signal output ends all output a low-level control signal.
Optionally, the communication switch circuit includes n switch tubes, n capacitors and n operational amplifiers, a controlled end of each switch tube is a controlled end of the communication switch circuit, an input end of each switch tube is an input end of the communication switch circuit, an output end of each switch tube is connected to an input end of each operational amplifier in a one-to-one correspondence manner, an output end of each switch tube is connected to one end of each capacitor in a one-to-one correspondence manner, and an output end of each operational amplifier is an output end of the communication switch circuit; the other end of each capacitor is grounded.
Optionally, when the switching tube is turned on, the capacitor connected to the output end of the switching tube is charged, and the operational amplifier connected to the output end of the switching tube outputs the reference voltage signal;
when the switch tube is closed, the capacitor connected with the output end of the switch tube discharges, and the operational amplifier connected with the output end of the switch tube keeps outputting the reference voltage signal.
Optionally, the reference voltage generating circuit further includes a source driving circuit, and the source driving circuit is connected to the n voltage signal output terminals.
In order to achieve the above object, the present application further provides a reference voltage generating circuit applied to a digitally adjustable gamma voltage chip, the reference voltage generating circuit comprising:
a memory configured to output a digital voltage signal;
the digital-to-analog converter is connected with the memory and is configured to convert the digital voltage signal into an analog voltage signal and output the analog voltage signal;
a time schedule controller;
n voltage signal output terminals;
the signal trigger circuit is provided with a signal input end, n signal trigger ends and n signal output ends, the signal input end of the signal trigger circuit is connected with the first output end of the time schedule controller, the n signal trigger ends of the signal trigger circuit are all connected with the second output end of the time schedule controller, and the signal trigger circuit is configured to receive a frame start signal output by the first output end of the time schedule controller and output a high-level control signal from one of the n signal output ends when receiving a clock signal output by the second output end of the time schedule controller;
the communication switch circuit is provided with n controlled ends, n input ends and n output ends, the n input ends of the communication switch circuit are connected with the output end of the digital-to-analog converter, the n controlled ends of the communication switch circuit are connected with the n signal output ends of the signal trigger circuit in a one-to-one correspondence manner, the n output ends of the communication switch circuit are connected with the n voltage signal output ends in a one-to-one correspondence manner, and the communication switch circuit is configured to generate a reference voltage signal and output the reference voltage signal from the output end corresponding to the controlled end when each controlled end receives a high-level control signal output by the signal trigger circuit; wherein n is an integer greater than or equal to 1.
To achieve the above object, the present application also provides a display device including the reference voltage generating circuit as described in any one of the above.
Optionally, the display device further includes a display panel, and the source driving circuit of the reference voltage generating circuit is connected to the display panel.
According to the technical scheme, the signal trigger circuit outputs the corresponding control signals to the n controlled ends of the communication switch circuit, so that the communication switch circuit is controlled to sequentially output the analog voltage signals output by the digital-to-analog converter through the n output ends of the communication switch circuit. By the arrangement, the circuit structure in the chip can be simplified, and the cost of the chip is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the structures shown in the drawings without any inventive work.
FIG. 1 is a block diagram of a reference voltage generating circuit according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a signal trigger circuit of the reference voltage generating circuit according to the present invention;
FIG. 3 is a schematic circuit diagram of a communication switch circuit of the reference voltage generating circuit according to the present invention.
The reference numbers illustrate:
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that, if directional indications (such as up, down, left, right, front, and back) are referred to in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship between the components, the motion situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The application provides a reference voltage generating circuit.
Referring to fig. 1, the reference voltage generating circuit includes: a timing controller 10, a digital-to-analog converter 20, n voltage signal output terminals (not shown), a signal trigger circuit 30 and a communication switch circuit 40; the signal input end of the signal trigger circuit 30 is connected to the first output end of the timing controller 10, n signal trigger ends of the signal trigger circuit 30 are all connected to the second output end of the timing controller 10, and n signal output ends of the signal trigger circuit 30 are connected to n controlled ends of the communication switch circuit 40 in a one-to-one correspondence manner; the n input ends of the communication switch circuit 40 are all connected with the output end of the digital-to-analog converter 20, and the n output ends of the communication switch circuit 40 are connected with the n voltage signal output ends in a one-to-one correspondence manner, wherein n is an integer greater than or equal to 1.
In this embodiment, the digital-to-analog converter 20 is configured to read a digital voltage signal in the memory and convert the read digital voltage signal into an analog voltage signal;
in this embodiment, the signal trigger circuit 30 is configured to output a high-level control signal from one of the n signal output terminals according to the clock signal output by the timing controller 10, and output a low-level control signal from the other n-1 signal output terminals;
in this embodiment, the communication switch circuit 40 is configured to generate a reference voltage signal and output the reference voltage signal from an output end corresponding to the controlled end when each controlled end receives a high-level control signal output by the signal trigger circuit, and control the output end to maintain outputting the reference voltage signal when the control signal of the controlled end is at a low level;
in the technical solution of the present application, the reference voltage generating circuit further includes a source driving circuit (not shown) and a memory (not shown), the source driving circuit is connected to the n voltage signal output ends, and the memory is connected to the digital-to-analog converter 20. The reference voltage generating circuit can be disposed in the digitally adjustable gamma voltage chip.
To better explain the inventive concept of the present application, the n signal Output terminals of the signal triggering circuit 30 are respectively denoted by a1 to An, the n Output terminals of the communication switch circuit 40 are respectively denoted by Output 1 to Output n, and a1 to An are respectively in one-to-one correspondence with Output 1 to Output n. When the system is started, the frame start signal Output by the timing controller 10 is high, and when the second Output terminal of the timing controller 10 outputs the first clock signal, the a1 Output terminal of the signal trigger circuit 30 outputs a high-level control signal, and the other n-1 signal Output terminals all Output low-level control signals to the n controlled terminals of the communication switch circuit 40 corresponding to the signal Output terminals one by one, at this time, the digital-to-analog converter 20 reads the digital voltage signal in the memory and converts the digital voltage signal into an analog voltage signal, which is Output through the Output 1 Output terminal of the communication switch circuit 40, that is, the corresponding reference voltage signal is Output through the Output 1 Output terminal. In addition, by setting the capacitors connected in one-to-one correspondence with Output 1 to Output n in the communication switch circuit 40, when the Output terminal of Output 1 outputs the reference voltage signal, the capacitors connected to the Output terminal of Output 1 start to charge, and the timing controller pulls down the frame start signal at this time. When the timing controller 10 outputs the second clock signal, the a2 Output terminal of the signal trigger circuit 30 outputs a high-level control signal, and the other n-1 signal Output terminals all Output a low-level control signal, at this time, the analog voltage signal Output by the digital-to-analog converter 20 is Output through the Output 2 Output terminal of the communication switch circuit 40, and the capacitor connected to the Output 2 Output terminal starts to charge, when the timing controller 10 outputs the second clock signal, although the a1 Output terminal outputs a low-level control signal, because the capacitor connected to the Output 1 Output terminal discharges, the Output 1 Output terminal of the communication switch circuit 40 continues to Output the corresponding reference voltage signal, and so on, when the timing controller 10 outputs the nth clock signal, the An Output terminal of the signal trigger circuit 30 outputs a high-level control signal, and the other n-1 signal Output terminals Output a low-level control signal, the Output n Output end of the communication switch circuit 40 outputs the corresponding reference voltage signal, and Output 1 to Output n-1 continue to Output the corresponding reference voltage signal under the voltage stabilizing effect of each capacitor, so that Output 1 to Output n all Output the corresponding reference voltage signal, the system can work normally, and thus, the normal Output of the reference voltage signal can be realized without adopting a plurality of digital-to-analog converters, and the system can work normally.
According to the technical scheme of the application, the signal trigger circuit 30 outputs the corresponding control signals to the n controlled ends of the communication switch circuit 40, so as to control the communication switch circuit 40 to sequentially output the analog voltage signals output by the digital-to-analog converter 20 through the n output ends of the communication switch circuit 40. By the arrangement, the circuit structure in the chip can be simplified, and the cost of the chip is reduced.
Referring to fig. 1 and 2, in an embodiment, the signal trigger circuit 30 includes n flip-flops connected in sequence, a clock signal input terminal of each flip-flop is a signal trigger terminal of the signal trigger circuit 30, a data output terminal of each flip-flop is a signal output terminal of the signal trigger circuit 30, and a data input terminal of the flip-flop placed at the head is a signal input terminal of the signal trigger circuit 30 and is connected to a data output terminal of the flip-flop placed at the end position. In two adjacent flip-flops, the data output terminal of the flip-flop disposed at the previous position is connected to the data input terminal of the flip-flop disposed at the subsequent position.
To better explain the technical solution of the present application, in this embodiment, n sequentially connected flip-flops are represented by a first flip-flop U1 to An nth flip-flop Un, and n signal output terminals of the signal flip-flop circuit 30 are represented by a1 to An, respectively, where the first flip-flop U1 is a first flip-flop, the nth flip-flop Un is a flip-flop disposed at An end position, clock signal input terminals C1 to Cn of the first flip-flop U1 receive a clock signal output by the timing controller, data output terminals D1 to Dn of the first flip-flop U1 are connected to n controlled terminals of the communication switch circuit 40 in a one-to-one correspondence, that is, the a1 output terminals to An output terminals of the signal flip-flop circuit 30 are connected to n controlled terminals of the communication switch circuit 40 in a one-to-one correspondence, and the data output terminal Q1 of the first flip-flop U1 is connected to the data input terminal D2 of the second flip-flop U2, the data output end Q2 of the second flip-flop U2 is connected with the data input end D3 of the third flip-flop U3, and so on, the data output end Qn-1 of the n-1 th flip-flop Un-1 is connected with the data input end Dn of the n-th flip-flop Un, and the data input end D1 of the first flip-flop U1 receives the frame start signal output by the timing controller 10 and is connected with the data output end Qn of the n-th flip-flop Un.
The n flip-flops are all D flip-flops, and the D flip-flops have the characteristic that when a clock signal input end C of each D flip-flop receives a rising edge of a signal, a value of a data input end D of each D flip-flop is assigned to a data output end Q of each D flip-flop.
Specifically, in the initial state, the frame start signal output by the first output terminal of the timing controller 10 is high, so that the data input terminal D1 of the first flip-flop U1 is high, and when the second output terminal of the timing controller 10 outputs the first clock signal, at this time, since the data input terminal D1 of the first flip-flop U1 is high and the data input terminals D2 of the second flip-flop U2 to Dn of the nth flip-flop Un are all low, when the first clock signal arrives, the data output terminal Q1 of the first flip-flop U1 is high, that is, the output terminal a1 outputs a high-level control signal, and the data output terminals Q2 of the second flip-flop U2 to Qn of the nth flip-flop Un are all low, that is, the output terminals a2 to An output low-level control signals. Then, the program of the timing controller 10 is set to pull the frame start signal low at this time, when the timing controller 10 outputs the second clock signal, the data input terminal D1 of the first flip-flop U1 is low, the data output terminal Q1 is high, since the data output terminal Q1 of the first flip-flop U1 is connected to the data input terminal D2 of the second flip-flop U2, which is equivalent to that the data input terminal D2 of the second flip-flop U2 is high at this time, the data output terminal Q2 is low, and the data input terminals of the third flip-flops U3 to Un-th flip-flops are low, when the second clock signal arrives, the first flip-flop U1 assigns the low level of the data input terminal D1 to the data output terminal Q1 thereof, the second flip-flop U2 assigns the high level of the data input terminal D2 to the data output terminal Q2 thereof, and the data output terminals of the third flip-flops U3 to Un-th flip-flops U2 thereof all assign the low levels of the data output terminals thereof to the data output terminals thereof, therefore, when the second clock signal arrives, only the second flip-flop U2 outputs a high-level control signal, the other n-1 flip-flops output low-level control signals, and so on, when the nth clock signal arrives, the nth flip-flop Un outputs a high-level control signal, and the other n-1 flip-flops output low-level control signals.
Referring to fig. 1, 2 and 3, in an embodiment, the communication switch circuit 40 includes n switch tubes, n capacitors and n operational amplifiers, a controlled end of each switch tube is a controlled end of the communication switch circuit 40, an input end of each switch tube is an input end of the communication switch circuit 40, an output end of each switch tube is connected to an input end of each operational amplifier in a one-to-one correspondence manner, an output end of each switch tube is connected to one end of each capacitor in a one-to-one correspondence manner, and an output end of each operational amplifier is an output end of the communication switch circuit 40; the other end of each capacitor is grounded.
To better describe the idea of the present invention, n switching transistors are represented by a first switching transistor M1 to an nth switching transistor Mn, n operational amplifiers are represented by a first operational amplifier OP1 to an nth operational amplifier OPn, and n capacitors are represented by a first capacitor C1 to an nth capacitor Cn.
Wherein, the controlled terminal of the first switch tube M1 to the controlled terminal of the nth switch tube Mn are connected with the data output terminals Q1 to Qn of the first flip-flop U1 of the signal trigger circuit 30 in a one-to-one correspondence, that is, connected with the output terminals A1 to An of the signal trigger circuit 30 in a one-to-one correspondence, the input end of the first switch tube M1 to the input end of the nth switch tube Mn are all connected with the output end of the digital-to-analog converter 20, the output end of the first switch tube M1 to the output end of the nth switch tube Mn are respectively connected with the input end of the first operational amplifier OP1 to the input end of the nth operational amplifier OPn in a one-to-one correspondence, and the output end of the first switch tube M1 to the output end of the nth switch tube Mn are respectively connected with one end of the first capacitor C1 to one end of the nth capacitor Cn in a one-to-one correspondence manner, and the other end of the first capacitor C1 to the other end of the nth capacitor Cn are all grounded.
Specifically, when the timing controller 10 outputs the first clock signal, the output terminal a1 of the signal trigger circuit 30 is high, the output terminal a2 to the output terminal An is low, at this time, the first switch tube M1 of the communication switch circuit 40 is turned on, the second switch tubes M2 to Mn are turned off, the digital-to-analog converter 20 reads the digital voltage signal in the memory, and converts the digital voltage signal into An analog voltage signal to be input to the n input terminals of the communication switch circuit 40, because the first switch tube M1 is turned on at this time, the second switch tubes M2 to Mn are turned off, the analog voltage signal output by the digital-to-analog converter 20 charges the first capacitor C1, and is output through the first operational amplifier OP 1; when the timing controller 10 outputs the second clock signal, the output terminal a2 of the signal trigger circuit 30 outputs the high-level control signal, the output terminals a1 and A3 to An output terminals output the low-level control signals, at this time, the second switching tube M2 of the communication switching circuit 40 is opened, the other n-1 switching tubes are closed, the analog voltage signal output by the digital-to-analog converter 20 charges the second capacitor C2 and is output through the second operational amplifier OP2, due to the voltage stabilization effect of the first capacitor C1, at this time, although the first switching tube M1 is closed, the first operational amplifier OP1 continues to output the corresponding analog voltage signal, when the timing controller 10 outputs the third clock signal, the third switching tube M3 is opened, the analog voltage signal output by the digital-to-analog converter 20 charges the third capacitor C3 and is output through the third operational amplifier OP3, due to the voltage stabilization effect of the first capacitor C1 and the voltage stabilization effect of the second capacitor C2, the first operational amplifier OP1 and the second operational amplifier OP2 still continue to output the corresponding analog voltage signal, and so on, when the timing controller 10 outputs the nth clock signal, the nth operational amplifier OPn outputs the corresponding analog voltage signal, and the first operational amplifier OP1 to the nth-1 operational amplifier OPn-1 continue to output the corresponding analog voltage signal, i.e. the reference voltage signal, because of the voltage stabilizing function of the corresponding capacitors, at this time, the system operates normally. The n operational amplifiers are used for amplifying and outputting the current signals, so that the driving capability is improved, and the load can work normally.
In this embodiment, the N switching tubes are all N-type insulating field effect tubes, a drain of each N-type insulating field effect tube is an input end of each switching tube, a source of each N-type insulating field effect tube is an output end of each switching tube, and a gate of each N-type insulating field effect tube is a controlled end of each switching tube.
In order to better describe the concept of the present application, specific circuit principles of the present application will be explained below with reference to fig. 1, 2 and 3:
when the system is started, the data input end D1 of the first flip-flop U1 receives the frame start signal output by the timing controller 10 and is high, when the first flip-flop U1 to the nth flip-flop Un receive the rising edge of the first clock signal, the first flip-flop U1 outputs a high-level control signal, the second flip-flop U2 to the nth flip-flop Un output a low-level control signal to control the first switch tube M1 to be turned on, the second switch tube M2 to the nth switch tube Mn to be turned off, the analog voltage signal output by the digital-to-analog converter 20 charges the first capacitor C1 and is output through the first operational amplifier OP1, and at this time, the second operational amplifier OP2 to the nth operational amplifier OPn do not output. Then, the program of the timing controller 10 sets the frame start signal to be low, when the first flip-flop U1 to the nth flip-flop Un receive the rising edge of the second clock signal, the data input terminal D1 of the first flip-flop U1 is low, the data output terminal Q1 is high, the data input terminal D2 of the second flip-flop U2 is connected to the data output terminal Q1 of the first flip-flop U1, so that the data input terminal D2 of the second flip-flop U2 is high, the data output terminal Q2 is low, the data input terminals of the third flip-flop U3 to the nth flip-flop Un are all low, when the second clock signal arrives, the second flip-flop U2 outputs a high-level control signal, and n-1 flip-flops output low-level control signals, at this time, the second switch M2 is opened, and n-1 switches are closed, the analog voltage signal output by the digital-to-analog converter 20 charges the second capacitor C2 and at the same time, the second OP amplifier 2 outputs the operational amplifier 2, and because of the voltage stabilizing function of the first capacitor C1, when the first flip-flop U1 outputs a low-level control signal, the first operational amplifier OP1 keeps outputting an analog voltage signal, and so on, when the first flip-flop U1 to the nth flip-flop Un receive a rising edge of the nth clock signal, the nth flip-flop Un outputs a high-level control signal, the first flip-flop U1 to the nth-1 flip-flop Un-1 all output a low-level control signal, at this time, the nth switch Mn is opened, the n-1 switch tubes are closed, the analog voltage signal output by the digital-to-analog converter 20 is output through the nth operational amplifier OPn while charging the nth capacitor Cn, and because of the voltage stabilizing function of the first capacitor C1 to the nth-1 capacitor Cn-1, at this time, the first operational amplifier OP1 to the nth-1 operational amplifier OPn-1 all maintain outputting an analog voltage signal, at this time, the system can operate normally. By the arrangement, each path of output in the chip is not required to be provided with one digital-to-analog converter 20, so that the circuit structure in the chip is simplified, and the cost of the chip is reduced.
The present application further provides a display device, which includes the reference voltage generating circuit and the display panel as described above, wherein the source driving circuit of the reference voltage generating circuit is electrically connected to the display panel. The detailed structure of the reference voltage generation circuit can refer to the above embodiments, and is not described herein again; it can be understood that, since the display device of the present application uses the reference voltage generation circuit, the embodiments of the display device of the present application include all technical solutions of all embodiments of the reference voltage generation circuit, and the achieved technical effects are also completely the same, and are not described herein again.
In this embodiment, the display device may be a display device having a display panel, such as a television, a tablet computer, or a mobile phone. The display panel may be any one of: a liquid crystal display panel, an OLED display panel, a QLED display panel, a Twisted Nematic (TN) or Super Twisted Nematic (STN) type, an In-Plane Switching (IPS) type, a Vertical Alignment (VA) type, a curved panel, or other display panels.
The above description is only an alternative embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that can be directly or indirectly applied to other related fields without departing from the spirit of the present application are intended to be included in the scope of the present application.
Claims (10)
1. A reference voltage generating circuit, comprising:
a memory configured to output a digital voltage signal;
the digital-to-analog converter is connected with the memory and is configured to convert the digital voltage signal into an analog voltage signal and output the analog voltage signal;
a time schedule controller;
n voltage signal output terminals;
the signal trigger circuit is provided with a signal input end, n signal trigger ends and n signal output ends, the signal input end of the signal trigger circuit is connected with the first output end of the time schedule controller, the n signal trigger ends of the signal trigger circuit are all connected with the second output end of the time schedule controller, and the signal trigger circuit is configured to receive a frame start signal output by the first output end of the time schedule controller and output a high-level control signal from one of the n signal output ends when receiving a clock signal output by the second output end of the time schedule controller;
the communication switch circuit is provided with n controlled ends, n input ends and n output ends, the n input ends of the communication switch circuit are connected with the output end of the digital-to-analog converter, the n controlled ends of the communication switch circuit are connected with the n signal output ends of the signal trigger circuit in a one-to-one correspondence manner, the n output ends of the communication switch circuit are connected with the n voltage signal output ends in a one-to-one correspondence manner, and the communication switch circuit is configured to generate a reference voltage signal and output the reference voltage signal from the output end corresponding to the controlled end when each controlled end receives a high-level control signal output by the signal trigger circuit; wherein n is an integer greater than or equal to 1.
2. The reference voltage generating circuit according to claim 1, wherein said signal flip-flop circuit comprises n flip-flops connected in series, a clock signal input terminal of each of said flip-flops is a signal flip-flop terminal of said signal flip-flop circuit, a data output terminal of each of said flip-flops is a signal output terminal of said signal flip-flop circuit, and a data input terminal of said flip-flop placed at the head is a signal input terminal of said signal flip-flop circuit and is connected to a data output terminal of said flip-flop placed at the end position.
3. The reference voltage generating circuit according to claim 2, wherein in two flip-flops positioned adjacently, a data output terminal of the flip-flop positioned at a previous position is connected to a data input terminal of the flip-flop positioned at a subsequent position.
4. The reference voltage generating circuit as claimed in claim 1, wherein when any one of the signal output terminals of the signal triggering circuit outputs a high-level control signal, the other n-1 signal output terminals output low-level control signals.
5. The reference voltage generating circuit of claim 1, wherein the communication switch circuit comprises n switch transistors, n capacitors and n operational amplifiers, the controlled terminal of each switch transistor is the controlled terminal of the communication switch circuit, the input terminal of each switch transistor is the input terminal of the communication switch circuit, the output terminal of each switch transistor is connected to the input terminal of each operational amplifier in a one-to-one correspondence, the output terminal of each switch transistor is connected to one terminal of each capacitor in a one-to-one correspondence, and the output terminal of each operational amplifier is the output terminal of the communication switch circuit; the other end of each capacitor is grounded.
6. The reference voltage generating circuit of claim 5, wherein when the switch tube is turned on, the capacitor connected to the output terminal of the switch tube is charged, and the operational amplifier connected to the output terminal of the switch tube outputs the reference voltage signal;
when the switch tube is closed, the capacitor connected with the output end of the switch tube discharges, and the operational amplifier connected with the output end of the switch tube keeps outputting the reference voltage signal.
7. The reference voltage generating circuit of claim 1, further comprising a source driver circuit connected to the n voltage signal output terminals.
8. The reference voltage generation circuit of any one of claims 1 to 7, applied to a digitally adjustable gamma voltage chip.
9. A display device characterized by comprising the reference voltage generating circuit according to any one of claims 1 to 8.
10. The display device according to claim 9, wherein the display device further comprises a display panel, and the source driver circuit of the reference voltage generating circuit is connected to the display panel.
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| CN201811595734.3A CN109509420B (en) | 2018-12-25 | 2018-12-25 | Reference voltage generating circuit and display device |
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| CN110111752A (en) * | 2019-04-08 | 2019-08-09 | 北海惠科光电技术有限公司 | A kind of driving circuit and display device |
| CN110379383B (en) * | 2019-06-10 | 2021-05-04 | 惠科股份有限公司 | Reference voltage generating circuit and display device |
| CN112542146B (en) * | 2020-11-03 | 2023-01-10 | 惠科股份有限公司 | Logic operation circuit and display driving circuit |
| CN113178174B (en) * | 2021-03-22 | 2022-07-08 | 重庆惠科金渝光电科技有限公司 | Grid driving module, grid control signal generation method and display device |
| CN113689817B (en) * | 2021-09-03 | 2023-08-01 | Tcl华星光电技术有限公司 | Driving circuit and display device |
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| JP5055605B2 (en) * | 2008-03-17 | 2012-10-24 | 奇美電子股▲ふん▼有限公司 | Source drive circuit for liquid crystal display device and liquid crystal display device including the same |
| CN103810976B (en) * | 2012-11-15 | 2016-04-27 | 联咏科技股份有限公司 | Integrated source electrode driver and liquid crystal display thereof |
| KR102237039B1 (en) * | 2014-10-06 | 2021-04-06 | 주식회사 실리콘웍스 | Source driver and display device comprising the same |
| CN104952408B (en) * | 2015-07-06 | 2018-11-23 | 深圳市华星光电技术有限公司 | Source drive module and liquid crystal display panel |
| CN106384579B (en) * | 2016-08-31 | 2019-03-12 | 深圳市华星光电技术有限公司 | Gamma reference voltage generation circuit, liquid crystal display panel |
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