CN111477162A - Pixel circuit, driving method thereof and display device - Google Patents
Pixel circuit, driving method thereof and display device Download PDFInfo
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- CN111477162A CN111477162A CN202010305039.XA CN202010305039A CN111477162A CN 111477162 A CN111477162 A CN 111477162A CN 202010305039 A CN202010305039 A CN 202010305039A CN 111477162 A CN111477162 A CN 111477162A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
Abstract
The invention provides a pixel circuit, a driving method thereof and a display device, and belongs to the technical field of display. The pixel circuit of the present invention includes: a current output sub-circuit and a time control sub-circuit, the current output sub-circuit configured to generate a drive current and output the drive current to the time control sub-circuit; the time control sub-circuit is configured to: controlling the light emitting time of the light emitting sub-circuit according to the time control signal; the time control sub-circuit includes: the device comprises a control signal writing unit, a capacitance reading unit, a data writing unit, a ramp writing unit and a gating unit; the control signal writing unit and the data writing unit are respectively connected with two ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with two ends of the capacitance reading unit; the current output sub-circuit is connected with the gating unit.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a pixel circuit, a driving method thereof and a display device.
Background
The light emitting diode (L luminance emitting diode; L ED) is a commonly used electroluminescent device, emits light by energy released by the recombination of electrons and holes, and is widely applied in the display field.
Disclosure of Invention
The present invention is directed to at least one of the technical problems of the prior art, and provides a pixel circuit capable of improving a duty ratio of a controllable light emitting time.
The technical scheme adopted for solving the technical problem of the invention is a pixel circuit, which comprises: a current output sub-circuit and a time control sub-circuit, the current output sub-circuit configured to: generating a driving current and outputting the driving current to the time control sub-circuit; the time control sub-circuit is configured to: controlling the light emitting time of the light emitting sub-circuit according to the time control signal; the time control sub-circuit includes: the device comprises a control signal writing unit, a capacitance reading unit, a data writing unit, a ramp writing unit and a gating unit; the control signal writing unit and the data writing unit are respectively connected with two ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with two ends of the capacitance reading unit; the current output sub-circuit is connected with the gating unit;
the control signal writing unit is configured to: responding to the control of the scanning end, and transmitting a time control signal to one end of the capacitance reading unit connected with the scanning end;
the data writing unit is configured to: responding to the control of a scanning end, and transmitting an initial data signal to one end of the capacitance reading unit connected with the scanning end;
the ramp writing unit is configured to: responding to the control of the light-emitting control end, transmitting a ramp signal to one end of the capacitance reading unit connected with the ramp signal so as to enable the voltage at the other end of the capacitance reading unit to change correspondingly;
the gating unit is configured to: and controlling the conduction state of the current output sub-circuit and the light-emitting sub-circuit in response to the voltage of one end of the capacitance reading unit connected with the current output sub-circuit.
Preferably, the control signal writing unit and the gating unit are connected to a first end of the capacitance reading unit;
the data writing unit and the ramp writing unit are connected with the second end of the capacitance reading unit;
the control signal writing unit is configured to: transmitting a time control signal to a first terminal of the capacitance reading unit in response to control of a scanning terminal;
the data writing unit is configured to: and responding to the control of the scanning end, and transmitting an initial data signal to the second end of the capacitance reading unit so as to generate a fixed pressure difference between the two ends of the capacitance reading unit.
Preferably, the gating unit includes: a gating transistor and at least one stage of inverting module;
the input end of the first-stage inverting module is connected with one end of the capacitance reading unit, the output end of the last-stage inverting module is connected with the grid electrode of the gating transistor, the first pole of the gating transistor is connected with the output end of the current output sub-circuit, and the second pole of the gating transistor is connected with the light-emitting sub-circuit;
the inversion module is configured to: providing a gating signal or a turn-off signal to the gating transistor in response to a voltage of one terminal of the capacitance reading unit to which it is connected
Further preferably, the control signal writing unit and the ramp writing unit are connected to a first end of the capacitance reading unit;
the data writing unit and the gating unit are connected with the second end of the capacitance reading unit;
the control signal writing unit is configured to: and responding to the control of the scanning end, and transmitting a time control signal to the first end of the capacitance reading unit.
Further preferably, the capacitance reading unit includes: a second capacitor and a third capacitor; the first stage inverting module comprises: a first driving transistor and a second driving transistor and a light emission control unit; the data writing unit includes: a first compensation transistor and a second compensation transistor;
the control signal writing unit, the ramp writing unit and the first ends of the second capacitor and the third capacitor are connected to a first node;
the control electrode of the first compensation transistor is connected with the scanning end; the first pole of the first compensation transistor is connected with the second pole of the first driving transistor; the second pole of the first compensation transistor, the control pole of the first driving transistor and the second end of the second capacitor are connected to a second node;
the control electrode of the second compensation transistor is connected with the scanning end; the first pole of the second compensation transistor is connected with the first pole of the second driving transistor; a second pole of the second compensation transistor and a control pole of the second driving transistor are connected with a second end of the third capacitor at a third node;
a first pole of the first driving transistor is connected with a first voltage end, and a second pole of the first driving transistor is an output end of the first-stage inverting module; the first pole of the second driving transistor is connected with a second voltage end, and the second pole of the second driving transistor is connected with the output end of the first-stage inverting module through the light-emitting control unit; one of the first driving transistor and the second driving transistor is an N-type transistor, and the other one is a P-type transistor;
the first compensation transistor is configured to: writing a threshold voltage of the first driving transistor and a voltage of the first voltage terminal into the second capacitor in response to control of the scan terminal;
the second compensation transistor is configured to: and writing the threshold voltage of the second driving transistor and the voltage of the second voltage terminal into the third capacitor in response to the control of the scanning terminal.
The light emission control unit is configured to: and responding to the control of the light-emitting control end, and conducting the second pole of the second driving transistor and the output end of the first-stage inverting module.
Further preferably, the time control sub-circuit unit further includes: a time reset unit;
the time reset unit is configured to: and responding to the control of a second reset terminal, and providing reset signals for the control electrode of the first driving transistor and the control electrode of the second driving transistor.
Further preferably, the time resetting unit includes: a second reset transistor and a third reset transistor;
a first pole of the second reset transistor is connected with a first initial voltage end, and a second pole of the second reset transistor is connected with a second node;
a first pole of the third reset transistor is connected with the second initial voltage end, and a second pole of the third reset transistor is connected with a third node;
and the control electrode of the second reset transistor and the control electrode of the third reset transistor are both connected with the second reset end.
Another technical solution to solve the technical problem of the present invention is a display device including the above-mentioned artificial pixel circuit.
Another technical solution adopted to solve the technical problem of the present invention is a driving method applied to any one of the above pixel circuits, the driving method including:
in a scanning stage, providing an effective level signal to the scanning end so that the data writing unit provides an initial data signal for one end of the capacitance reading unit; simultaneously enabling the control signal writing unit to transmit the time control signal to the other end of the capacitance reading unit;
and in a light-emitting stage, providing an effective level signal to the light-emitting control end to enable the ramp wave writing unit to transmit the ramp wave signal to one end of the capacitance reading unit so as to enable the voltage at the other end of the capacitance reading unit to change correspondingly.
Preferably, the pixel circuit is the pixel circuit according to claim 6, and the driving method further includes:
in a reset phase, an active level signal is provided to the second reset terminal, so that the time reset unit provides a reset signal for the first driving transistor and the second driving transistor.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1-5 and fig. 7 are schematic structural diagrams of a pixel circuit according to an embodiment of the invention;
FIG. 6 is a signal timing diagram of the pixel circuit provided in FIGS. 2-5;
fig. 8 is a signal timing diagram of the pixel circuit provided in fig. 7.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Unless otherwise defined, technical or scientific terms used in the embodiments of the present invention should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
At present, a light-emitting time control circuit can be used to adjust the time of the current passing through the light-emitting diode, so as to compensate the brightness of the light-emitting diode and improve the gray scale uniformity. However, since the thin film transistor has the problems of threshold voltage drift, response delay, etc., and it is difficult to accurately control the light emitting time, the light emitting time control circuit usually needs more transistors to compensate the light emitting control, and the light emitting time control circuit occupies a larger space, which severely limits the resolution (PPI) of the display device.
In view of the above, the present invention provides a pixel circuit, and fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, as shown in fig. 1, the pixel circuit includes: a current output sub-circuit and a light-emitting time control sub-circuit.
Example 1:
as shown in fig. 1 to 8, the present embodiment provides a pixel circuit including: a current output sub-circuit and a time control sub-circuit, the current output sub-circuit configured to: generating a driving current and outputting the driving current to the time control sub-circuit; the time control sub-circuit is configured to: controlling the light emitting time of the light emitting sub-circuit according to the time control signal; wherein the time control sub-circuit comprises: the device comprises a control signal writing unit, a capacitance reading unit, a data writing unit, a ramp writing unit and a gating unit; the control signal writing unit and the data writing unit are respectively connected with two ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with two ends of the capacitance reading unit; the current output sub-circuit is connected with the gating unit.
In an embodiment of the present invention, the control signal writing unit is configured to: and responding to the control of the scanning terminal GateT, and transmitting a time control signal to one terminal of the capacitance reading unit connected with the scanning terminal GateT. As shown in fig. 1, the control signal writing unit may include a control signal writing transistor T7, a control electrode of the control signal writing transistor T7 is connected to the scan terminal GateT, a first electrode of the control signal writing transistor T7 is connected to the time control signal output terminal DataT, and a second electrode of the control signal writing transistor T7 is connected to one terminal of the capacitance reading unit.
The data writing unit is configured to: responding to the control of the GateT at the scanning end, and transmitting an initial data signal to one end of the capacitance reading unit connected with the initial data signal; as shown in fig. 1, the data writing unit is connected to the other end of the capacitance reading unit, opposite to the control signal writing unit.
The ramp writing unit is configured to: responding to the control of the light-emitting control end EM, transmitting a ramp signal to one end of the capacitance reading unit connected with the light-emitting control end EM, so that the voltage of the other end of the capacitance reading unit is correspondingly changed; the gating unit is configured to: and controlling the conduction state of the current output sub-circuit and the light-emitting sub-circuit in response to the voltage of one end of the capacitance reading unit connected with the current output sub-circuit. As shown in fig. 1, the ramp writing unit and the gating unit are respectively connected to two ends of the capacitance reading unit. It should be noted that, in the present embodiment, the control signal writing unit and the ramp signal writing unit may be connected to the same end or different ends of the capacitance reading unit.
Taking a light emitting period as an example, in a scanning phase (specifically, a time scanning phase), an active level signal is provided to the scanning terminal GateT, and the time control signal writing transistor T7 turns on the time control signal output terminal DataT, so as to transmit the time control signal V2 to one terminal of the capacitance reading unit; meanwhile, the data writing unit transmits an initial data signal to one end of the capacitance reading unit connected with the data writing unit under the control of the scanning end GateT, and a certain voltage difference is formed between two ends of the capacitance short reading unit. In the light emitting stage, an effective level signal is provided for a light emitting control end EM, a ramp wave writing unit transmits a ramp wave voltage signal of a reference voltage end to one end of a capacitance reading unit, at the moment, the voltage difference of two ends of the capacitance reading unit keeps unchanged, along with the change of the ramp wave voltage signal, based on the bootstrap action of a capacitor, the voltage of the other end of the capacitance reading unit (namely a node connected with a gating unit; a control end of the gating unit) is increased or decreased along with the ramp wave voltage signal, and when the voltage of the node is decreased to meet a first voltage, the gating unit conducts a current output sub-circuit and a light emitting sub-circuit; when the voltage of the node continuously drops to meet the second voltage, the gating unit conducts the current output sub-circuit and the light-emitting sub-circuit.
Under the condition that the initial data signal is certain, the duration from the beginning of entering the display stage to the critical voltage which can enable the gating unit to be switched from the 'off' state to the 'on' state, namely the duration that the gating unit is in the 'off' state in the display stage, can be controlled by adjusting the size and the change condition of the ramp wave voltage. In a period (for example, one frame), under the condition that the total duration of the display phase is certain, the duration for controlling the gating unit to be in the 'off' state can be achieved by controlling the duration for controlling the gating unit to be in the 'on' state. Therefore, the light emitting duration of the light emitting device in one period can be controlled by adjusting the magnitude and the change condition of the ramp wave voltage.
In the embodiment of the invention, in the light-emitting stage, the voltage at the input end of the gating unit can be driven to rise or fall through the ramp voltage signal, and the speed of the change time of the voltage at the input end of the gating unit is controlled according to the time control signal written into the capacitance reading unit in the scanning stage, so that the length of the conduction time of the current output sub-circuit and the light-emitting sub-circuit by the gating unit is controlled, and the light-emitting time of the light-emitting sub-circuit is accurately controlled. Since the magnitude of the current flowing through the light emitting device and the operating time of the light emitting device in a period (for example, a frame) affect the effective luminance of the light emitting device in the period, the driving current provided by the current control circuit 1 and the time control voltage provided by the time signal control terminal DataT can control the effective luminance of the light emitting device in the period, thereby achieving the purpose of adjusting the display gray scale.
Preferably, in this embodiment, the current output sub-circuit includes: a first reset transistor T1, a first threshold compensation transistor T2, a current write transistor T3, a third drive transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, and a first capacitor C1. A first pole of the current writing transistor T3 is connected to the driving voltage terminal DataI, a control pole of the current writing transistor T3 is connected to the second scanning terminal GateI, a second pole of the current writing transistor T3, a first pole of the third driving transistor T4 and a first pole of the second light emission controlling transistor T5 are connected, and a first pole of the third threshold compensating transistor T2 is connected to a second pole of the third driving transistor T4 and a first pole of the first light emission controlling transistor T6; a second pole of the third threshold compensating transistor T2 is connected to a control pole of the third driving transistor T4, one end of the first capacitor C1 and a second pole of the first Reset transistor T1, a control pole of the third threshold compensating transistor T2 is connected to the second scan terminal GateI, a second pole of the second light emission controlling transistor T5 is connected to the other end of the first capacitor C1 and the third voltage terminal VDD3, a second pole of the first light emission controlling transistor T6 is connected to an input terminal of the gating unit, a control pole of the second light emission controlling transistor T5 and a control pole of the first light emission controlling transistor T6 are both connected to the light emission control terminal EM, a control pole of the first Reset transistor T1 is connected to the first Reset terminal Reset, and a first pole of the first Reset transistor T1 is connected to the third initial voltage terminal INI 3.
Preferably, the gating unit includes: a gating transistor and at least one stage of inverting module; the input end of the first-stage inverting module is connected with one end of the capacitance reading unit, the output end of the last-stage inverting module is connected with the control electrode of the gating transistor, the first electrode of the gating transistor is connected with the output end of the current output sub-circuit, and the second electrode of the gating transistor is connected with the light-emitting sub-circuit; the inversion module is configured to: the gate transistor is supplied with a gate signal or a turn-off signal in response to a voltage of one terminal of the capacitance reading unit to which it is connected.
As shown in fig. 2 to 5 and fig. 7, in the pixel circuit provided in this embodiment, the gating unit may include one inversion module and one gating transistor, or a plurality of inversion modules and one gating transistor. When the gating unit comprises a plurality of inverting modules, the plurality of inverting modules are cascaded. In this embodiment, the control terminal of the gating unit is the input terminal of the first-stage inverting module, and is connected to one terminal of the capacitance reading unit; the output end of the last stage of inverting module is connected with the control electrode of the gating transistor.
Specifically, in the present embodiment, one inverting module may include a first driving transistor T9 and a second driving transistor T10. A first electrode of the first driving transistor T9 is connected to the first voltage terminal VDD, a first electrode of the second driving transistor T10 is connected to the second voltage terminal VSS, a second electrode of the first driving transistor T9 is connected to the second electrode of the second driving transistor T10, a control electrode of the first driving transistor T9 is connected to a control electrode of the second driving transistor T10, and one of the first driving transistor T9 and the second driving transistor T10 is an N-type transistor and the other is a P-type transistor. The gate signal is a voltage signal of the second voltage terminal VSS, and the gate signal is a voltage signal of the first voltage terminal VDD.
The active level signal of the P-type transistor is a low level voltage signal; the active level signal of the N-type transistor is a high level voltage signal. The voltage provided by the first voltage terminal VDD is a high level voltage signal, and the voltage provided by the second voltage terminal VSS is a low level voltage signal. In addition, the first voltage terminal VDD of the inverter modules of different stages may be connected to the same voltage terminal, and the second voltage terminal VSS of the inverter modules of different stages may be connected to the same voltage terminal.
In this embodiment, in the plurality of cascaded inverting modules, the input terminal of the first stage inverting module is connected to the control terminal of the gating unit, the output terminal of the last stage inverting module is connected to the control electrode of the gating transistor T8, the first electrode of the gating transistor T8 is connected to the output terminal of the current output sub-circuit, and the second electrode of the gating transistor T8 is connected to the light emitting sub-circuit. The plurality of cascaded inversion modules is configured to: in the light emitting stage, when the control terminal of the gating cell receives the voltage of the first voltage terminal VDD1, a gating signal is supplied to the gating transistor T8. When the control terminal of the gating cell receives the voltage of the second voltage terminal VSS1, a turn-off signal is provided to the gating transistor T8.
In the light emitting stage, since the voltage of the control terminal of the gate unit increases or decreases with the ramp voltage signal and the first and second driving transistors T9 and T10 are alternately turned on in the process of increasing or decreasing, an intermediate state voltage may be caused to exist at the output terminal of the first stage inverter unit. Since the intermediate voltage may be smaller than the high level voltage signal output by the first voltage terminal VDD1 and larger than the low level voltage signal output by the second voltage terminal VSS1, if the output terminal of the first stage inverting unit is directly connected to the gate transistor T8, the intermediate voltage will cause the magnitude of the light emitting driving current passing through the gate transistor T8 to change, thereby affecting the light emitting brightness of the light emitting device in the light emitting sub-circuit. In this embodiment, the first-stage inversion module receives the intermediate-state voltage through the arrangement of the multi-stage inversion module, and after the intermediate-state voltage is inverted by the multi-stage inversion module, the last-stage inversion module outputs a preset gating signal or a preset turn-off signal, so that the gating transistor T8 is fully turned on or turned off, and the change of the magnitude of the light-emitting driving current passing through the gating transistor T8 is avoided.
Preferably, in this embodiment, the light Emitting sub-circuit may include a light Emitting device, the light Emitting device may be a light Emitting Diode (L light Emitting Diode, L ED), an input end of the light Emitting device is connected to an output end of the current output sub-circuit through a gating unit, when the gating unit controls the current output sub-circuit and the light Emitting sub-circuit to be turned on, the light Emitting driving current output by the current output sub-circuit is transmitted to the light Emitting device, so that the light Emitting device emits light, and when the gating unit controls the current output sub-circuit and the light Emitting sub-circuit to be turned off, the light Emitting driving current cannot be transmitted to the light Emitting device, so that the light Emitting device is turned off.
Example 2:
as shown in fig. 2 to 6, the present embodiment provides a pixel circuit, which includes the pixel circuit provided in embodiment 1, and includes: a current output sub-circuit and a time control sub-circuit, the current output sub-circuit configured to: generating a driving current and outputting the driving current to the time control sub-circuit; the time control sub-circuit is configured to: controlling the light emitting time of the light emitting sub-circuit according to the time control signal; wherein the time control sub-circuit comprises: the device comprises a control signal writing unit, a capacitance reading unit, a data writing unit, a ramp writing unit and a gating unit; the control signal writing unit and the data writing unit are respectively connected with two ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with two ends of the capacitance reading unit; the current output sub-circuit is connected with the gating unit.
Particularly, in the embodiment, the control signal writing unit and the gating unit are connected with the first end of the capacitance reading unit; the data writing unit and the ramp writing unit are connected with the second end of the capacitance reading unit; the control signal writing unit is configured to: responding to the control of the first scanning end GateT, and transmitting a time control signal to the first end of the capacitance reading unit; the data writing unit is configured to: and responding to the control of the first scanning end GateT, and transmitting an initial data signal to the second end of the capacitance reading unit so as to generate a fixed pressure difference between the two ends of the capacitance reading unit.
Preferably, as shown in fig. 2 to 5, the capacitance reading unit may include a second capacitor C2 having a first terminal connected to the second pole of the control signal writing transistor T7 and the control terminal of the gating unit.
In this embodiment, the data writing unit may include a data writing transistor T11, a control electrode of the data writing transistor T11 is connected to the first scan terminal GateT, a first electrode of the data writing transistor T11 is connected to the first reference voltage terminal Commom1, and a second electrode of the data writing transistor T11 is connected to the second terminal of the second capacitor C2.
Preferably, the ramp wave writing unit may include a light emission controlling transistor T12, a control electrode of the light emission controlling transistor T12 being connected to the light emission control terminal EM, a first electrode of the light emission controlling transistor T12 being connected to the second reference voltage terminal Common2, and a second electrode of the light emission controlling transistor T12 being connected to the second terminal of the second capacitor C2.
Fig. 6 is a signal timing diagram of a pixel circuit according to an embodiment of the present invention, and the driving process of the present invention is explained with reference to fig. 1 to 6.
In the first Reset period t1 (current Reset period), an active level signal is supplied to the first Reset terminal Reset. The first reset transistor T1 is turned on to connect the first initial voltage terminal INI1 to the second terminal of the first capacitor C1. At this stage, the N-node is reset to the corresponding initial voltage.
In the current compensation phase T2, an active level signal is provided to the second scan terminal GateI, the current writing transistor T3 is controlled to be turned on, the driving voltage terminal DataI is turned on with the first electrode of the third driving transistor T4, and the third threshold compensation transistor T2 turns on the second electrode of the third driving transistor T4 with the first end of the first capacitor C1 to transmit the driving voltage signal VdataI1 output from the driving voltage terminal DataI and the threshold voltage Vth3 of the third driving transistor T4 to the first end of the first capacitor C1.
In the time data reading phase T3, an active level signal is provided to the first scan terminal GateT, the control signal writing transistor T7 and the data writing transistor T11 are turned on, and the time control signal vtime control signal output from the time control signal output terminal DataT1 and the initial data signal Vcomm1 output from the first reference voltage terminal comom 1 are written to two ends of the second capacitor C2, respectively (as shown in fig. 2, the M point potential is V time control signal output terminal DataT1, and the M 'point potential is Vcomm 1.), at this phase, because the charge of the second capacitor C2 remains unchanged, the two ends of the second capacitor C2 establish and store the voltage difference Δ V between the two points M and M'.
In the lighting period T4, an active level signal is provided to the lighting control terminal EM, the lighting control transistor T12 is turned on, the second reference voltage terminal common2 and the second terminal of the second capacitor C2 are turned on, and the ramp voltage signal Vcom2 is transmitted to the first terminal of the second capacitor C2, in which the charge of the second capacitor C2 is kept unchanged, and the voltage difference between the M-point potential and the M' -point potential is kept unchanged. With the change of the ramp voltage signal, the potential of the point M changes, that is, the potential of the control end of the conducting unit changes, so as to control the current output sub-circuit and the light emitting sub-circuit to be connected or disconnected.
Theoretically, when the potential of the M point changes to Vth, the conduction unit is turned on, the current output sub-circuit and the light emitting sub-circuit are turned on, and the light emitting device is turned on to emit light. In order to keep each row from affecting the light emitting time due to the morning and evening of the written data, the ramp voltage signal Vcom2 is set as a periodic ramp signal with a period of 1H. Thus, the light emitting device experiences an off-to-on state in each cycle. The time ratio of the switches depends on the written M-point initial potential and the change mode of the Vcom2 signal. In the case of the timing sequence shown in fig. 4, the ramp voltage signal Vcom2 is first decreased and then increased, and the higher the initial potential at the point M, the later the opening time, the earlier the closing time, and the lower the duty ratio; as the initial potential of the M-point decreases, the light emission duty ratio increases. When the ramp voltage signal Vcom2 is rising first and then falling, the other way round.
It should be noted that, in the present embodiment, a single-stage inversion module is taken as an example for description, in order to improve the time control accuracy, multiple stages of inversion modules may be provided, and specific control and timing may refer to the above description, which is not repeated in the present embodiment.
Example 3:
as shown in fig. 7 and 8, the present embodiment provides a pixel circuit including the pixel circuit provided in embodiment 1, which specifically includes: a current output sub-circuit and a time control sub-circuit, the current output sub-circuit configured to: generating a driving current and outputting the driving current to the time control sub-circuit; the time control sub-circuit is configured to: controlling the light emitting time of the light emitting sub-circuit according to the time control signal; wherein the time control sub-circuit comprises: the device comprises a control signal writing unit, a capacitance reading unit, a data writing unit, a ramp writing unit and a gating unit; the control signal writing unit and the data writing unit are respectively connected with two ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with two ends of the capacitance reading unit; the current output sub-circuit is connected with the gating unit.
The pixel circuit provided in this embodiment is similar to the pixel circuit provided in embodiment 2, and particularly, in this embodiment, the control signal writing unit and the ramp wave writing unit are connected to the first end of the capacitance reading unit; the data writing unit and the gating unit are connected with the second end of the capacitance reading unit; the control signal writing unit is configured to: and responding to the control of the scanning end, and transmitting a time control signal to the first end of the capacitance reading unit.
In a scan phase (specifically, a time scan phase), an active level signal is provided to the first scan terminal GateT, and the time control signal writing transistor T7 turns on the time control signal output terminal DataT, thereby transmitting the time control signal V2 to the first terminal of the second capacitor C2 and the first terminal of the third capacitor C3; meanwhile, the data writing unit transmits the initial data signal to the second end of the second capacitor C2 and the second end of the third capacitor C3 under the control of the scan terminal, and a voltage difference is formed between two ends of the second capacitor C2 and two ends of the third capacitor C3, respectively. In a light emitting stage, an effective level signal is provided for a light emitting control end EM, a ramp wave writing unit transmits a ramp wave voltage signal of a reference voltage end to a first end of a second capacitor C2 and a first end of a third capacitor C3, at the moment, the voltage difference between two ends of a capacitor reading unit keeps unchanged, along with the change of the ramp wave voltage signal, the bootstrap action of the capacitors, the voltage of the first end of a second capacitor C2 and the voltage of the second end of a third capacitor C3 also rise or fall along with the ramp wave voltage signal, and when the voltage of the node falls to meet the first voltage, a gating unit conducts a current output sub-circuit and a light emitting sub-circuit; when the voltage of the node continuously drops to meet the second voltage, the gating unit conducts the current output sub-circuit and the light-emitting sub-circuit.
Preferably, in this embodiment, the capacitance reading unit includes: a second capacitor C2 and a third capacitor C3; the first stage inverting module includes: a first driving transistor T9 and a second driving transistor T10 and a light emission control unit; the data writing unit includes: a first compensation transistor T13 and a second compensation transistor T14.
As shown in fig. 7, the first ends of the control signal writing unit, the ramp wave writing unit, the second capacitor C2 and the third capacitor C3 are connected to the first node M1; the control electrode of the first compensation transistor T13 is connected with the first scanning end GateT; a first pole of the first compensation transistor T13 is connected to a second pole of the first driving transistor T9; the second pole of the first compensation transistor T13 and the control pole of the first driving transistor T9 are connected to the second end of the second capacitor C2 at T14; the control electrode of the second compensation transistor T14 is connected with the first scanning end GateT; a first pole of the second compensating transistor T14 is connected to a first pole of the second driving transistor T10; the second pole of the second compensation transistor T14 and the control pole of the second driving transistor T10 and the second end of the third capacitor C3 are connected to a third node M3.
A first pole of the first driving transistor T9 is connected to the first voltage terminal, and a second pole is the output terminal of the first stage inverting module; a first pole of the second driving transistor T10 is connected to a second voltage end, and a second pole is connected to the output end of the first stage inverting module through the light emitting control unit; one of the first and second driving transistors T9 and T10 is an N-type transistor, and the other is a P-type transistor.
The first compensation transistor T13 is configured to: in response to the control of the first scan terminal GateT, the threshold voltage of the first driving transistor T9 and the voltage of the first voltage terminal are written in the second capacitor C2; the second compensation transistor T14 is configured to: in response to the control of the first scan terminal GateT, the threshold voltage of the second drive transistor T10 and the voltage of the second voltage terminal are written in the third capacitor C3. The light emission control unit is configured to: the second pole of the second driving transistor T10 is turned on with the output terminal of the first-stage inverter module in response to the control of the emission control terminal EM.
Preferably, the ramp wave writing unit may include a light emission control transistor T12, a control electrode of the light emission control transistor T12 being connected to the light emission control terminal EM, a first electrode of the light emission control transistor T12 being connected to the second reference voltage terminal Common2, and a second electrode of the light emission control transistor T12 being connected to the second capacitor C2 and a first terminal of the third capacitor C3 (i.e., the first node M1).
In the embodiment of the invention, the threshold voltages of the first driving transistor T9 and the second driving transistor TT10 of the first-stage inversion module can be compensated by the data writing unit, the influence of the threshold voltage drift on the first driving transistor T9 and the second driving transistor T10 is eliminated, and the accuracy of the control of the turn-on (or turn-off) time of the gate unit by the first driving transistor T9 and the second driving transistor T10 is improved.
In the light emitting period, since the voltage of the third node M3 and the voltage of the fourth node M4 increase or decrease with the ramp voltage signal and the first driving transistor T9 and the second driving transistor T10 are alternately turned on in the increasing or decreasing process, an intermediate voltage may be caused to exist at the second node M2. Since the intermediate voltage may be smaller than the high level voltage signal output by the first voltage terminal VDD1 and larger than the low level voltage signal output by the second voltage terminal VSS1, if the second node N2 is directly connected to the gate transistor T8, the intermediate voltage will cause the magnitude of the light emitting driving current passing through the gate transistor T8 to change, thereby affecting the light emitting brightness of the light emitting device in the light emitting sub-circuit.
Preferably, in this embodiment, the time control sub-circuit unit further includes: a time reset unit; the time reset unit is configured to: the reset signals are supplied to the control electrode of the first driving transistor T9 and the control electrode of the second driving transistor T10 in response to the control of the second reset terminal RSTT.
Preferably, the time resetting unit includes: a second reset transistor T15 and a third reset transistor T16; a first pole of the second reset transistor T15 is connected to the second initial voltage terminal INI2, and a second pole of the second reset transistor T15 is connected to the second node; a first pole of the third reset transistor T16 is connected to the third initial voltage terminal INI3, and a second pole of the third reset transistor T16 is connected to the third node; a control electrode of the second reset transistor T15 and a control electrode of the third reset transistor T16 are both connected to the second reset terminal RSTT.
Fig. 8 is a signal timing diagram of a pixel circuit provided in an embodiment of the present invention, and a driving process of the present invention is explained with reference to fig. 7 and 8.
In the first Reset phase T1 (current Reset phase), an active level signal is provided to the first Reset terminal Reset, and the first Reset transistor T1 is turned on to turn on the first initial voltage terminal INI1 and the second terminal of the first capacitor C1. At this stage, the N-node is reset to the corresponding initial voltage.
In the current compensation phase T2, an active level signal is provided to the second scan terminal GateI, the current writing transistor T3 is controlled to be turned on, the driving voltage terminal DataI is turned on with the first electrode of the third driving transistor T4, and the third threshold compensation transistor T2 turns on the second electrode of the third driving transistor T4 with the first end of the first capacitor C1 to transmit the driving voltage signal VdataI1 output from the driving voltage terminal DataI and the threshold voltage Vth3 of the third driving transistor T4 to the first end of the first capacitor C1.
In the second reset period T3 (time reset period), an active level signal is provided to the second reset terminal RSTT, the second reset transistor T15 and the third reset transistor T16 are turned on, the second reset transistor T15 conducts the second initial voltage terminal INI2 with the second terminal of the second capacitor C2, and the third reset transistor T16 conducts the third initial voltage terminal INI3 with the first terminal of the third capacitor C3. At this stage, the second node M2 and the third node M3 are both reset to respective initial voltages.
In the data reading phase T4, an active level signal is provided to the first scan terminal GateT, the control signal writing transistor T7 is turned on, and the time control signal VdataT1 output by the time control signal output terminal DataT is written into the first terminals of the second capacitor C2 and the third capacitor C3, respectively; meanwhile, the first scan terminal GateT controls the first and second compensation transistors T13 and T14 to be turned on.
At this stage, the voltages of the first ends of the second capacitor C2 and the third capacitor C3 are VdataT1, the voltage of the node M2 is V1+ Vth1, the voltage of the node M3 is V2+ Vth2, where V1 is the voltage output by the first voltage terminal VDD1, V2 is the voltage output by the second voltage terminal VSS1, Vth1 is the threshold voltage of the first driving transistor T9, and Vth2 is the threshold voltage of the second driving transistor T10.
At stage t5, full screen data reading, compensation stage.
In the light emission period t6, an active level signal is supplied to the light emission control terminal EM. The light emission control transistor T12 turns on the reference voltage terminal common with the first terminal of the second capacitor C2 and the first terminal of the third capacitor C3, the ramp wave voltage signal Vcom is transmitted to the first terminal of the second capacitor C2 and the first terminal of the third capacitor C3, and the T23 turns on the second pole of the second driving transistor T10 with the node M, thereby turning on the second pole of the gate transistor T8 with the light emitting device, or turning on the second pole of the gate transistor T8 with the light emitting device through the cascaded multistage inversion module.
In this stage, the voltage of the second capacitor C and the voltage of the first terminal of the third capacitor C are VdataT, the voltage of the N node is V + Vth + Δ V, Δ V is the difference between the ramp-wave voltage signal Vcom and the time control signal VdataT, i.e., Δ V is Vcom-VdataT1, the gate-source voltage Vgs of the first driving transistor T is V + Vth + Δ V-V, the gate-source voltage Vgs of the second driving transistor T is V + Vth + Δ V-V, the gate-source voltage Vgs of the third driving transistor T is VdataI + Vth-V, the light emission driving current I output by the third driving transistor T is k (Vth-Vth) 2 k (Vd ataI + Vth-V) when the gate-source voltage is equal to V + V-V, the gate-source voltage Vgs of the first driving transistor T is VdataI + Vth-V, the light emission driving current I output by the third driving transistor T is k (Vd-Vth) 2 (Vd) when the gate-on voltage of the first driving transistor T is greater than the gate-on voltage of the first driving transistor T0, the gate-off, the first driving transistor T is controlled by the gate-on voltage of the first driving transistor T, the gate-on-gate-driving transistor T, the gate voltage of the first driving transistor T-on-gate-driving transistor T, the second driving transistor T is controlled by the gate-on-off voltage of the first driving transistor T, the gate-driving transistor T, the gate-on-gate-driving transistor T, the gate-gate voltage control signal control transistor T, the gate-gate voltage control transistor T, the gate-on-gate-on-gate-on transistor T is controlled by the gate-off voltage of the gate-on-gate-on transistor T, and the gate-on transistor T, the gate control signal of the second driving transistor T, the gate control transistor T, the gate-on transistor T, the gate-off-on transistor T, the gate control signal of the gate control transistor T, the gate control.
That is, in this embodiment, the data writing unit is configured to perform threshold compensation on the capacitance reading unit, so that the transition (on/off transition) condition of the first-stage inverting module of the gating unit is only related to Δ V and is not related to Vth. The output of the first stage inverting module is independent of Vth, thereby ensuring that the whole pixel circuit is independent of Vth.
It is understood that, in the present embodiment, the gating unit includes a first stage inverting module as an example for explanation. When the gating unit comprises a multi-stage inversion module, the first-stage inversion module can be compensated through the data writing unit, the output of the first-stage inversion module is irrelevant to Vth, and the influence of the output Vth on the last several stages of inversion modules is small, so that the independence of the whole pixel circuit to Vth is ensured. It is understood that, a person skilled in the art may select the number of inversion modules of the gating unit according to the control accuracy of time, and the number of inversion modules included in the gating unit is not particularly limited in this embodiment.
Example 4:
the present embodiment provides a display device, and the present invention further provides a display device, including the pixel circuit in the above embodiments of the present invention.
The display device can be any product or component with a display function, such as electronic paper, an O L ED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The display device adopts the pixel circuit, so that the light-emitting time of a plurality of light-emitting devices can be controlled by one light-emitting time control sub-circuit, the space occupied by the light-emitting time control sub-circuit is greatly reduced, and the pixel density of the display device can be improved.
Example 5:
an embodiment of the present invention further provides a driving method applied to the pixel circuit in the foregoing embodiment, where the driving method includes:
in the scanning stage, an effective level signal is provided for a scanning end, so that the data writing unit provides an initial data signal for one end of the capacitance reading unit; meanwhile, the control signal writing unit transmits the time control signal to the other end of the capacitance reading unit;
in the light emitting stage, an effective level signal is provided to the light emitting control end EM, so that the ramp writing unit transmits a ramp signal to one end of the capacitance reading unit, and the voltage at the other end of the capacitance reading unit is changed correspondingly.
Optionally, the active level signal is a low level signal. Taking a light emitting period as an example, in a scanning phase (specifically, a time scanning phase), an active level signal is provided to the scanning terminal GateT, and the time control signal writing transistor T7 turns on the time control signal output terminal DataT, so as to transmit the time control signal V2 to one terminal of the capacitance reading unit; meanwhile, the data writing unit transmits an initial data signal to one end of the capacitance reading unit connected with the data writing unit under the control of the scanning end GateT, and a certain voltage difference is formed between two ends of the capacitance short reading unit. In the light emitting stage, an effective level signal is provided for a light emitting control end EM, a ramp wave writing unit transmits a ramp wave voltage signal of a reference voltage end to one end of a capacitance reading unit, at the moment, the voltage difference of two ends of the capacitance reading unit keeps unchanged, along with the change of the ramp wave voltage signal, based on the bootstrap action of a capacitor, the voltage of the other end of the capacitance reading unit (namely a node connected with a gating unit; a control end of the gating unit) is increased or decreased along with the ramp wave voltage signal, and when the voltage of the node is decreased to meet a first voltage, the gating unit conducts a current output sub-circuit and a light emitting sub-circuit; when the voltage of the node continuously drops to meet the second voltage, the gating unit conducts the current output sub-circuit and the light-emitting sub-circuit.
In the embodiment of the invention, in the light emitting phase, the voltage across the capacitance reading unit can be driven to increase or decrease by the ramp voltage signal, and the lengths of the turn-on time of the first driving transistor T9 and the turn-on time of the second driving transistor T10 are controlled according to the time control signal written into the capacitance reading unit in the data writing phase, so as to control the length of the turn-on time of the gating unit for outputting the current to the sub-circuit and the light emitting sub-circuit.
Preferably, the pixel circuit includes a reset unit, and the driving method further includes: in the reset phase, the active level signal is supplied to the second reset terminal RSTT, so that the time reset unit supplies the reset signal to the first driving transistor T9 and the second driving transistor T10.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A pixel circuit, comprising: a current output sub-circuit and a time control sub-circuit, the current output sub-circuit configured to: generating a driving current and outputting the driving current to the time control sub-circuit; the time control sub-circuit is configured to: controlling the light emitting time of the light emitting sub-circuit according to the time control signal; wherein the time control sub-circuit comprises: the device comprises a control signal writing unit, a capacitance reading unit, a data writing unit, a ramp writing unit and a gating unit; the control signal writing unit and the data writing unit are respectively connected with two ends of the capacitance reading unit; the ramp writing unit and the gating unit are respectively connected with two ends of the capacitance reading unit; the current output sub-circuit is connected with the gating unit;
the control signal writing unit is configured to: responding to the control of the scanning end, and transmitting a time control signal to one end of the capacitance reading unit connected with the scanning end;
the data writing unit is configured to: responding to the control of a scanning end, and transmitting an initial data signal to one end of the capacitance reading unit connected with the scanning end;
the ramp writing unit is configured to: responding to the control of the light-emitting control end, transmitting a ramp signal to one end of the capacitance reading unit connected with the ramp signal so as to enable the voltage at the other end of the capacitance reading unit to change correspondingly;
the gating unit is configured to: and controlling the conduction state of the current output sub-circuit and the light-emitting sub-circuit in response to the voltage of one end of the capacitance reading unit connected with the current output sub-circuit.
2. The pixel circuit according to claim 1, wherein the control signal writing unit and the gating unit are connected to a first terminal of the capacitance reading unit;
the data writing unit and the ramp writing unit are connected with the second end of the capacitance reading unit;
the control signal writing unit is configured to: transmitting a time control signal to a first terminal of the capacitance reading unit in response to control of a scanning terminal;
the data writing unit is configured to: and responding to the control of the scanning end, and transmitting an initial data signal to the second end of the capacitance reading unit so as to generate a fixed pressure difference between the two ends of the capacitance reading unit.
3. The pixel circuit according to claim 1, wherein the gating unit comprises: a gating transistor and at least one stage of inverting module;
the input end of the first-stage inverting module is connected with one end of the capacitance reading unit, the output end of the last-stage inverting module is connected with the grid electrode of the gating transistor, the first pole of the gating transistor is connected with the output end of the current output sub-circuit, and the second pole of the gating transistor is connected with the light-emitting sub-circuit;
the inversion module is configured to: a gate signal or a turn-off signal is supplied to the gate transistor in response to a voltage of one terminal of the capacitance reading unit to which it is connected.
4. The pixel circuit according to claim 3, wherein the control signal writing unit and the ramp writing unit are connected to a first end of the capacitance reading unit;
the data writing unit and the gating unit are connected with the second end of the capacitance reading unit;
the control signal writing unit is configured to: and responding to the control of the scanning end, and transmitting a time control signal to the first end of the capacitance reading unit.
5. The pixel circuit according to claim 4, wherein the capacitance reading unit includes: a second capacitor and a third capacitor; the first stage inverting module comprises: a first driving transistor and a second driving transistor and a light emission control unit; the data writing unit includes: a first compensation transistor and a second compensation transistor;
the control signal writing unit, the ramp writing unit and the first ends of the second capacitor and the third capacitor are connected to a first node;
the control electrode of the first compensation transistor is connected with the scanning end; the first pole of the first compensation transistor is connected with the second pole of the first driving transistor; the second pole of the first compensation transistor, the control pole of the first driving transistor and the second end of the second capacitor are connected to a second node;
the control electrode of the second compensation transistor is connected with the scanning end; the first pole of the second compensation transistor is connected with the first pole of the second driving transistor; a second pole of the second compensation transistor and a control pole of the second driving transistor are connected with a second end of the third capacitor at a third node;
a first pole of the first driving transistor is connected with a first voltage end, and a second pole of the first driving transistor is an output end of the first-stage inverting module; the first pole of the second driving transistor is connected with a second voltage end, and the second pole of the second driving transistor is connected with the output end of the first-stage inverting module through the light-emitting control unit; one of the first driving transistor and the second driving transistor is an N-type transistor, and the other one is a P-type transistor;
the first compensation transistor is configured to: writing a threshold voltage of the first driving transistor and a voltage of the first voltage terminal into the second capacitor in response to control of the scan terminal;
the second compensation transistor is configured to: and writing the threshold voltage of the second driving transistor and the voltage of the second voltage terminal into the third capacitor in response to the control of the scanning terminal.
The light emission control unit is configured to: and responding to the control of the light-emitting control end, and conducting the second pole of the second driving transistor and the output end of the first-stage inverting module.
6. The pixel circuit of claim 5, wherein the time control sub-circuit unit further comprises: a time reset unit;
the time reset unit is configured to: and responding to the control of a second reset terminal, and providing reset signals for the control electrode of the first driving transistor and the control electrode of the second driving transistor.
7. The pixel circuit according to claim 6, wherein the time reset unit comprises: a second reset transistor and a third reset transistor;
a first pole of the second reset transistor is connected with a first initial voltage end, and a second pole of the second reset transistor is connected with a second node;
a first pole of the third reset transistor is connected with the second initial voltage end, and a second pole of the third reset transistor is connected with a third node;
and the control electrode of the second reset transistor and the control electrode of the third reset transistor are both connected with the second reset end.
8. A display device comprising the pixel circuit according to any one of claims 1 to 7.
9. A driving method applied to the pixel circuit according to any one of claims 1 to 7, wherein the driving method comprises:
in a scanning stage, providing an effective level signal to the scanning end so that the data writing unit provides an initial data signal for one end of the capacitance reading unit; simultaneously enabling the control signal writing unit to transmit the time control signal to the other end of the capacitance reading unit;
and in a light-emitting stage, providing an effective level signal to the light-emitting control end to enable the ramp wave writing unit to transmit the ramp wave signal to one end of the capacitance reading unit so as to enable the voltage at the other end of the capacitance reading unit to change correspondingly.
10. The method for driving the pixel circuit according to claim 9, wherein the pixel circuit is the pixel circuit according to claim 6, and the method further comprises:
in a reset phase, an active level signal is provided to the second reset terminal, so that the time reset unit provides a reset signal for the first driving transistor and the second driving transistor.
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