CN113421528B - Driving circuit, driving method and display device - Google Patents
Driving circuit, driving method and display device Download PDFInfo
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- CN113421528B CN113421528B CN202110690521.4A CN202110690521A CN113421528B CN 113421528 B CN113421528 B CN 113421528B CN 202110690521 A CN202110690521 A CN 202110690521A CN 113421528 B CN113421528 B CN 113421528B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a driving circuit, a driving method and a display device. The driving circuit comprises a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, a fifth node control circuit and an output circuit; the output circuit is used for controlling the communication between the driving signal end and the second voltage end under the control of the potential of the fifth node and controlling the communication between the driving signal end and the first voltage end under the control of the potential of the fourth node. The output circuit controls the communication between the driving signal end and the second voltage end under the control of the potential of the fifth node, so that the driving signal end outputs the second voltage signal, and the load hanging capacity of the driving signal end is enhanced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a driving circuit, a driving method and a display device.
Background
In the conventional pixel circuit, the data writing circuit and the compensation control circuit may include IGZO (indium gallium zinc oxide) thin film transistors, which require a high voltage effective scan signal, and since the data writing circuit and the compensation control circuit include IGZO thin film transistors, the data writing capability is deteriorated, which requires an increase in the output capability of the driving circuit that supplies the scan signal.
Disclosure of Invention
The present invention is directed to a driving circuit, a driving method and a display device, which can solve the problem of poor output capability of the conventional driving circuit for providing high-voltage effective scanning signals.
The embodiment of the invention provides a driving circuit, which comprises a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, a fifth node control circuit and an output circuit, wherein the first node control circuit is connected with the second node control circuit;
the first node control circuit is used for controlling the communication between a first node and a first voltage end under the control of a first clock signal provided by a first clock signal end and controlling the communication between the first node and the first clock signal end under the control of the potential of a second node;
the second node control circuit is used for controlling the communication between the second node and an initial voltage end under the control of the first clock signal;
the third node control circuit is used for controlling the potential of the first node according to the potential of the third node and controlling the communication between the third node and a second clock signal end under the control of the potential of the first node;
the fourth node control circuit is used for controlling the communication between a fourth node and a third voltage end under the control of the potential of the second node, controlling the communication between the fourth node and the second voltage end under the control of the potential of the third node, and controlling the communication between the fourth node and the third voltage end under the control of the first clock signal;
the fifth node control circuit is configured to control communication between the fifth node and the second voltage end under the control of the potential of the fourth node, and control the potential of the fifth node according to the potential of the third node under the control of a second clock signal provided by the second clock signal end;
the output circuit is used for controlling the communication between the driving signal end and the second voltage end under the control of the potential of the fifth node, and controlling the communication between the driving signal end and the first voltage end under the control of the potential of the fourth node.
Optionally, the fifth node control circuit includes a first control sub-circuit and a second control sub-circuit;
the first control sub-circuit is used for controlling the communication between the fifth node and the second voltage end under the control of the potential of the fourth node;
the second control sub-circuit is used for controlling the communication between the third node and the fifth node under the control of a second clock signal.
Optionally, the fifth node control circuit includes a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit;
the first control sub-circuit is used for controlling the communication between the fifth node and the second voltage end under the control of the potential of the fourth node;
the second control sub-circuit is used for controlling the third node and the sixth node to be communicated under the control of a second clock signal;
the third control sub-circuit is used for controlling the communication between the sixth node and the fifth node under the control of a first voltage signal provided by the first voltage end.
Optionally, the fourth node control circuit is further electrically connected to the second node, and is configured to control communication between the fourth node and the third voltage end under control of a potential of the second node.
Optionally, the output circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor;
the control electrode of the first transistor is electrically connected with the fifth node, the first electrode of the first transistor is electrically connected with the second voltage end, and the second electrode of the first transistor is electrically connected with the driving signal end;
a control electrode of the second transistor is electrically connected with the fourth node, a first electrode of the second transistor is electrically connected with the driving signal end, and a second electrode of the second transistor is electrically connected with the first voltage end;
a first end of the first capacitor is electrically connected with the fifth node, and a second end of the first capacitor is electrically connected with the second voltage end;
the first end of the second capacitor is electrically connected with the fourth node, and the second end of the second capacitor is electrically connected with the first voltage end.
Optionally, the third node control circuit includes a third capacitor and a third transistor;
a first end of the third capacitor is electrically connected with the first node, and a second end of the third capacitor is electrically connected with the third node;
a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to a second clock signal terminal, and a second electrode of the third transistor is electrically connected to the third node.
Optionally, the first control sub-circuit includes a fourth transistor, and the second control sub-circuit includes a fifth transistor;
a control electrode of the fourth transistor is electrically connected to the fourth node, a first electrode of the fourth transistor is electrically connected to the second voltage terminal, and a second electrode of the fourth transistor is electrically connected to the fifth node;
a control electrode of the fifth transistor is electrically connected to the second clock signal terminal, a first electrode of the fifth transistor is electrically connected to the third node, and a second electrode of the fifth transistor is electrically connected to the fifth node.
Optionally, the first control sub-circuit includes a fourth transistor, the second control sub-circuit includes a fifth transistor, and the third control sub-circuit includes a sixth transistor;
a control electrode of the fourth transistor is electrically connected to the fourth node, a first electrode of the fourth transistor is electrically connected to the second voltage terminal, and a second electrode of the fourth transistor is electrically connected to the fifth node;
a control electrode of the fifth transistor is electrically connected with the second clock signal end, a first electrode of the fifth transistor is electrically connected with the third node, and a second electrode of the fifth transistor is electrically connected with the sixth node;
a control electrode of the sixth transistor is electrically connected to the first voltage terminal, a first electrode of the sixth transistor is electrically connected to the sixth node, and a second electrode of the sixth transistor is electrically connected to the fifth node.
Optionally, the fourth node control circuit includes a seventh transistor and an eighth transistor;
a control electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the second voltage terminal, and a second electrode of the seventh transistor is electrically connected to the fourth node;
a control electrode of the eighth transistor is electrically connected to the first clock signal terminal, a first electrode of the eighth transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth transistor is electrically connected to the fourth node.
Optionally, the fourth node control circuit includes a seventh transistor, an eighth transistor, and a ninth transistor;
a control electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the second voltage terminal, and a second electrode of the seventh transistor is electrically connected to the fourth node;
a control electrode of the eighth transistor is electrically connected to the first clock signal terminal, a first electrode of the eighth transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth transistor is electrically connected to the fourth node;
a control electrode of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the third voltage terminal, and a second electrode of the ninth transistor is electrically connected to the fourth node.
Optionally, the first node control circuit includes a tenth transistor and an eleventh transistor;
a control electrode of the tenth transistor is electrically connected to the first clock signal terminal, a first electrode of the tenth transistor is electrically connected to the first voltage terminal, and a second electrode of the tenth transistor is electrically connected to the first node;
a control electrode of the eleventh transistor is electrically connected to the second node, a first electrode of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.
Optionally, the second node control circuit includes a twelfth transistor;
a control electrode of the twelfth transistor is electrically connected to the first clock signal terminal, a first electrode of the twelfth transistor is electrically connected to the start voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the second node.
The driving method provided by the embodiment of the invention is applied to the driving circuit, and the driving period comprises an input stage, an output stage and a reset stage; the driving method includes:
in the input stage, a first node control circuit writes a first voltage signal into a first node under the control of a first clock signal, a second node control circuit writes an initial voltage signal provided by an initial voltage end into a second node under the control of the first clock signal, and a third node control circuit writes a second clock signal into a third node under the control of the potential of the first node; the fourth node control circuit writes a third voltage signal into a fourth node under the control of the first clock signal, the fifth node control circuit writes a second voltage signal into a fifth node under the control of the potential of the fourth node, and the output circuit controls the driving signal end to output the first voltage signal under the control of the potential of the fourth node;
in the output stage, the third node control circuit writes a second clock signal into the third node under the control of the potential of the first node, and changes the potential of the first node according to the third node; the fourth node control circuit controls the second voltage signal to be written into a fourth node under the control of the potential of the third node, the fifth node control circuit controls the fifth node to be communicated with the third node under the control of a second clock signal, and the output circuit controls the driving signal end to output the second voltage signal under the control of the potential of the fifth node;
in the reset stage, the second node control circuit writes the initial voltage signal provided by the initial voltage end into the second node under the control of the first clock signal, the first node control circuit writes the first voltage signal into the first node under the control of the first clock signal, the first node control circuit writes the first clock signal into the first node under the control of the potential of the second node, the third node control circuit writes the second clock signal into the third node under the control of the potential of the first node, the fourth node control circuit writes the third voltage signal into the fourth node under the control of the potential of the second node and the first clock signal, the fifth node control circuit writes the second voltage signal into the fifth node under the control of the potential of the fourth node, and the output circuit controls the driving signal end to output the first voltage signal under the control of the potential of the fourth node.
Optionally, the driving period further includes an output cut-off holding phase arranged after the reset phase; the output cutoff holding phase comprises a plurality of holding periods; the holding period comprises a first holding period and a second holding period; the driving method further includes:
in the first holding time period, the fourth node control circuit maintains the potential of the fourth node, the fifth node control circuit maintains the potential of the fifth node, and the output circuit controls the driving signal end to output a first voltage signal under the control of the potential of the fourth node;
in the second holding time period, the fourth node control circuit writes the third voltage signal into the fourth node under the control of the first clock signal, the fifth node control circuit writes the second voltage signal into the fifth node under the control of the potential of the fourth node, and the output circuit controls the driving signal terminal to output the first voltage signal under the control of the potential of the fourth node.
The display device comprises a driving module; the driving module comprises a multi-stage driving circuit.
The driving circuit, the driving method and the display device can provide high-voltage effective scanning signals, and the output circuit controls the connection between the driving signal end and the second voltage end under the control of the potential of the fifth node, so that the driving signal end outputs the second voltage signal, and the load hanging capacity of the driving signal end is enhanced.
Drawings
Fig. 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a driving circuit according to an embodiment of the present invention;
FIG. 3 is a block diagram of a driving circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a driver circuit according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating the operation of the driving circuit shown in FIG. 4 according to the present invention;
fig. 6 is a structural diagram of a four-stage driving circuit included in a driving module in a display device according to an embodiment of the invention;
FIG. 7 is a timing diagram illustrating operation of the driving module shown in FIG. 6 according to an embodiment of the present invention;
FIG. 8 is a circuit diagram of an embodiment of a pixel circuit in a display device according to the present invention;
fig. 9 is an operation timing diagram of the embodiment of the pixel circuit shown in fig. 8.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
As shown in fig. 1, the driving circuit according to the embodiment of the present invention includes a first node control circuit 11, a second node control circuit 12, a third node control circuit 13, a fourth node control circuit 14, a fifth node control circuit 15, and an output circuit 10;
the first node control circuit 11 is electrically connected to the first clock signal terminal NCK, the first voltage terminal V1, the second node N2 and the first node N1, respectively, and is configured to control communication between the first node N1 and the first voltage terminal V1 under control of a first clock signal provided by the first clock signal terminal NCK, and control communication between the first node N1 and the first clock signal terminal NCK under control of a potential of the second node N2;
the second node control circuit 12 is electrically connected to the start voltage end NSTV, the first clock signal end NCK and the second node N2, respectively, and is configured to control communication between the second node N2 and the start voltage end NSTV under the control of the first clock signal;
the third node control circuit 13 is electrically connected to the first node N1, the third node N3 and the second clock signal terminal NCB, respectively, and is configured to control the potential of the first node N1 according to the potential of the third node N3, and to control the connection between the third node N3 and the second clock signal terminal NCB under the control of the potential of the first node N1;
the fourth node control circuit 14 is respectively electrically connected to the second node N2, the third node N3, the fourth node N4, the second voltage end V2, the first clock signal end NCK and the third voltage end V3, and is configured to control communication between the fourth node N4 and the third voltage end V3 under the control of the potential of the second node N2, control communication between the fourth node N4 and the second voltage end V2 under the control of the potential of the third node N3, and control communication between the fourth node N4 and the third voltage end V3 under the control of the first clock signal;
the fifth node control circuit 15 is electrically connected to the second clock signal terminal NCB, the third node N3, the fourth node N4, the fifth node N5 and the second voltage terminal V2, respectively, and is configured to control the communication between the fifth node N5 and the second voltage terminal V2 under the control of the potential of the fourth node N4, and control the potential of the fifth node N5 according to the potential of the third node N3 under the control of the second clock signal provided by the second clock signal terminal NCB;
the output circuit 10 is electrically connected to a fifth node N5, a fourth node N4, a second voltage terminal V2, a first voltage terminal V1 and a driving signal terminal O1, respectively, and is configured to control the connection between the driving signal terminal O1 and the second voltage terminal V2 under the control of the potential of the fifth node N5, and control the connection between the driving signal terminal O1 and the first voltage terminal V1 under the control of the potential of the fourth node N4.
The driving circuit according to the embodiment of the invention can provide a scan signal with high voltage efficiency, and the output circuit 10 controls the connection between the driving signal terminal O1 and the second voltage terminal V2 under the control of the potential of the fifth node N5, so that the driving signal terminal O1 outputs the second voltage signal, and the load hanging capability of the driving signal terminal O1 is enhanced.
In an embodiment of the present invention, the second voltage terminal is a dc voltage terminal. Optionally, the second voltage terminal is a high voltage terminal.
In an embodiment of the present invention, the first voltage terminal may be a first low voltage terminal, the third voltage terminal may be a second low voltage terminal, and a voltage value of a second low voltage signal provided by the second low voltage terminal may be smaller than a voltage value of a first low voltage signal provided by the first low voltage terminal.
In an embodiment of the present invention, the driving circuit may be included in a driving module, the driving module includes a plurality of stages of driving circuits, a start voltage signal provided by a start voltage terminal of a first stage of driving circuit is a predetermined start voltage signal provided externally, and other start voltage terminals except the first stage of driving circuit are driving signal terminals of adjacent previous stage of driving circuits.
When the embodiment of the driving circuit shown in fig. 1 of the present invention is in operation, the driving cycle includes an input phase, an output phase, a reset phase and an output cut-off holding phase;
in the input stage, the first node control circuit 11 writes the first voltage signal into the first node N1 under the control of the first clock signal, the second node control circuit 12 writes the start voltage signal provided by the start voltage terminal NSTV into the second node N2 under the control of the first clock signal, and the third node control circuit 13 writes the second clock signal into the third node N3 under the control of the potential of the first node N1; the fourth node control circuit 14 writes a third voltage signal into the fourth node N4 under the control of the first clock signal, the fifth node control circuit 15 writes a second voltage signal into the fifth node N5 under the control of the potential of the fourth node N4, and the output circuit 10 controls the driving signal terminal O1 to output the first voltage signal under the control of the potential of the fourth node N4;
in the output stage, the third node control circuit 13 writes the second clock signal into the third node N3 under the control of the potential of the first node N1, and changes the potential of the first node N1 according to the third node N3; the fourth node control circuit 14 controls writing of a second voltage signal into the fourth node N4 under the control of the potential of the third node N3, the fifth node control circuit 15 controls communication between the fifth node N5 and the third node N3 under the control of a second clock signal, and the output circuit 10 controls the driving signal terminal O1 to output the second voltage signal under the control of the potential of the fifth node N5;
in the reset phase, the second node control circuit 12 writes the start voltage signal supplied from the start voltage terminal NSTV to the second node under the control of the first clock signal, the first node control circuit 11 writes the first voltage signal to the first node N1 under the control of the first clock signal, the first node control circuit 11 writes the first clock signal to the first node N1 under the control of the potential of the second node N2, the third node control circuit 13 writes the second clock signal to the third node N3 under the control of the potential of the first node N1, the fourth node control circuit 14 writes the third voltage signal to the fourth node N4 under the control of the potentials of the second node N2 and the first clock signal, the fifth node control circuit 15 writes the second voltage signal to the fifth node N5 under the control of the potential of the fourth node N4, the output circuit 10 writes the second voltage signal to the fifth node N4, controlling the driving signal terminal O1 to output a first voltage signal;
the output cutoff holding phase comprises a plurality of holding periods; the holding period comprises a first holding period and a second holding period;
in the first holding period, the fourth node control circuit 14 maintains the potential of the fourth node N4, the fifth node control circuit 15 maintains the potential of the fifth node N5, and the output circuit 10 controls the driving signal terminal O1 to output the first voltage signal under the control of the potential of the fourth node N4;
in the second holding period, the fourth node control circuit 14 writes the third voltage signal to the fourth node N4 under the control of the first clock signal, the fifth node control circuit 15 writes the second voltage signal to the fifth node N5 under the control of the potential of the fourth node N4, and the output circuit 10 controls the driving signal terminal O1 to output the first voltage signal under the control of the potential of the fourth node N4.
As shown in fig. 2, on the basis of the embodiment of the driving circuit shown in fig. 1, the fifth node control circuit may include a first control sub-circuit 21 and a second control sub-circuit 22;
the first control sub-circuit 21 is electrically connected with a fourth node N4, a fifth node N5 and a second voltage terminal V2 respectively, and is used for controlling the communication between the fifth node N5 and the second voltage terminal V2 under the control of the potential of the fourth node N4;
the second control sub-circuit 22 is electrically connected to the second clock signal terminal NCB, the third node N3 and the fifth node N5, respectively, and is configured to control communication between the third node N3 and the fifth node N5 under the control of the second clock signal provided by the NCB.
In operation of the embodiment of the driving circuit shown in fig. 2, the first control sub-circuit 21 controls the communication between the fifth node N5 and the second voltage terminal V2 under the control of the potential at the fourth node N4, and the second control sub-circuit 22 controls the communication between the third node N3 and the fifth node N5 under the control of the second clock signal.
Optionally, the first control sub-circuit includes a fourth transistor, and the second control sub-circuit includes a fifth transistor;
a control electrode of the fourth transistor is electrically connected to the fourth node, a first electrode of the fourth transistor is electrically connected to the second voltage terminal, and a second electrode of the fourth transistor is electrically connected to the fifth node;
a control electrode of the fifth transistor is electrically connected to the second clock signal terminal, a first electrode of the fifth transistor is electrically connected to the third node, and a second electrode of the fifth transistor is electrically connected to the fifth node.
As shown in fig. 3, on the basis of the embodiment of the driving circuit shown in fig. 1, the fifth node control circuit may include a first control sub-circuit 21, a second control sub-circuit 22 and a third control sub-circuit 23;
the first control sub-circuit 21 is electrically connected with a fourth node N4, a fifth node N5 and a second voltage terminal V2 respectively, and is used for controlling the communication between the fifth node N5 and the second voltage terminal V2 under the control of the potential of the fourth node N4;
the second control sub-circuit 22 is electrically connected to the second clock signal terminal NCB, the third node N3 and the sixth node N6, respectively, and is configured to control communication between the third node N3 and the sixth node N6 under the control of the second clock signal provided by the NCB;
the third control sub-circuit 23 is electrically connected to the first voltage terminal V1, the sixth node N6 and the fifth node N5, respectively, and is configured to control communication between the sixth node N6 and the fifth node N5 under the control of the first voltage signal provided by the first voltage terminal V1.
Compared with the embodiment of the driving circuit shown in fig. 2, the embodiment of the driving circuit shown in fig. 3 adds a third control sub-circuit 23, and the third control sub-circuit 23 controls the conduction between N6 and N5 under the control of the first voltage signal, so that the potential of N5 is stable.
Optionally, the first control sub-circuit includes a fourth transistor, the second control sub-circuit includes a fifth transistor, and the third control sub-circuit includes a sixth transistor;
a control electrode of the fourth transistor is electrically connected to the fourth node, a first electrode of the fourth transistor is electrically connected to the second voltage terminal, and a second electrode of the fourth transistor is electrically connected to the fifth node;
a control electrode of the fifth transistor is electrically connected with the second clock signal end, a first electrode of the fifth transistor is electrically connected with the third node, and a second electrode of the fifth transistor is electrically connected with the sixth node;
a control electrode of the sixth transistor is electrically connected to the first voltage terminal, a first electrode of the sixth transistor is electrically connected to the sixth node, and a second electrode of the sixth transistor is electrically connected to the fifth node.
In specific implementation, as shown in fig. 1, the fourth node control circuit 14 may further be electrically connected to the second node N2 for controlling the communication between the fourth node N4 and the third voltage terminal V3 under the control of the potential of the second node N2.
Optionally, the output circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor;
a control electrode of the first transistor is electrically connected with a fifth node, a first electrode of the first transistor is electrically connected with a second voltage end, and a second electrode of the first transistor is electrically connected with a driving signal end;
a control electrode of the second transistor is electrically connected with the fourth node, a first electrode of the second transistor is electrically connected with the driving signal end, and a second electrode of the second transistor is electrically connected with the first voltage end;
a first end of the first capacitor is electrically connected with the fifth node, and a second end of the first capacitor is electrically connected with the second voltage end;
and the first end of the second capacitor is electrically connected with the fourth node, and the second end of the second capacitor is electrically connected with the first voltage end.
Optionally, the third node control circuit includes a third capacitor and a third transistor;
a first end of the third capacitor is electrically connected with the first node, and a second end of the third capacitor is electrically connected with the third node;
a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to a second clock signal terminal, and a second electrode of the third transistor is electrically connected to the third node.
Optionally, the fourth node control circuit includes a seventh transistor and an eighth transistor;
a control electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the second voltage terminal, and a second electrode of the seventh transistor is electrically connected to the fourth node;
a control electrode of the eighth transistor is electrically connected to the first clock signal terminal, a first electrode of the eighth transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth transistor is electrically connected to the fourth node.
Optionally, the fourth node control circuit includes a seventh transistor, an eighth transistor, and a ninth transistor;
a control electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the second voltage terminal, and a second electrode of the seventh transistor is electrically connected to the fourth node;
a control electrode of the eighth transistor is electrically connected to the first clock signal terminal, a first electrode of the eighth transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth transistor is electrically connected to the fourth node;
a control electrode of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the third voltage terminal, and a second electrode of the ninth transistor is electrically connected to the fourth node.
Optionally, the first node control circuit includes a tenth transistor and an eleventh transistor;
a control electrode of the tenth transistor is electrically connected to the first clock signal terminal, a first electrode of the tenth transistor is electrically connected to the first voltage terminal, and a second electrode of the tenth transistor is electrically connected to the first node;
a control electrode of the eleventh transistor is electrically connected to the second node, a first electrode of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.
Optionally, the second node control circuit includes a twelfth transistor;
a control electrode of the twelfth transistor is electrically connected to the first clock signal terminal, a first electrode of the twelfth transistor is electrically connected to the start voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the second node.
As shown in fig. 4, on the basis of the embodiment of the driving circuit shown in fig. 3, the output circuit 10 includes a first transistor T1, a second transistor T2, a first capacitor C1 and a second capacitor C2;
the gate of the first transistor T1 is electrically connected to the fifth node N5, the source of the first transistor T1 is electrically connected to the high voltage terminal, and the drain of the first transistor T1 is electrically connected to the driving signal terminal O1; the high voltage end is used for providing a high voltage signal VGH;
a gate of the second transistor T2 is electrically connected to the fourth node N4, a source of the second transistor T2 is electrically connected to the driving signal terminal O1, and a drain of the second transistor T2 is electrically connected to a first low voltage terminal; the first low voltage terminal is used for providing a first low voltage signal VGL;
a first end of the first capacitor C1 is electrically connected to the fifth node N5, and a second end of the first capacitor C1 is electrically connected to the high voltage terminal;
a first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the first low voltage terminal;
the third node control circuit 13 includes a third capacitor C3 and a third transistor T3;
a first terminal of the third capacitor C3 is electrically connected to the first node N1, and a second terminal of the third capacitor C3 is electrically connected to the third node N3;
a gate of the third transistor T3 is electrically connected to the first node N1, a source of the third transistor T3 is electrically connected to a second clock signal terminal NCB, and a drain of the third transistor T3 is electrically connected to the third node N3;
the first control sub-circuit 21 comprises a fourth transistor T4, the second control sub-circuit 22 comprises a fifth transistor T5, the third control sub-circuit 23 comprises a sixth transistor T6;
a gate of the fourth transistor T4 is electrically connected to the fourth node N4, a source of the fourth transistor T4 is electrically connected to the high voltage terminal, and a drain of the fourth transistor T4 is electrically connected to the fifth node N5;
a gate of the fifth transistor T5 is electrically connected to the second clock signal terminal NCB, a source of the fifth transistor T5 is electrically connected to the third node N3, and a drain of the fifth transistor T5 is electrically connected to the sixth node N6;
the gate of the sixth transistor T6 is electrically connected to the first low voltage terminal, the source of the sixth transistor T6 is electrically connected to the sixth node N6, and the drain of the sixth transistor T6 is electrically connected to the fifth node N5;
the fourth node control circuit 14 includes a seventh transistor T7 and an eighth transistor T8;
a gate of the seventh transistor T7 is electrically connected to the third node N3, a source of the seventh transistor T7 is electrically connected to the high voltage terminal, and a drain of the seventh transistor T7 is electrically connected to the fourth node N4;
a gate of the eighth transistor T8 is electrically connected to the first clock signal terminal NCK, a source of the eighth transistor T8 is electrically connected to the second low voltage terminal, and a drain of the eighth transistor T8 is electrically connected to the fourth node N4; the second low voltage terminal is used for providing a second low voltage signal VGL _ 1;
the fourth node control circuit includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9;
a gate of the seventh transistor T7 is electrically connected to the third node N3, a source of the seventh transistor T7 is electrically connected to the high voltage terminal, and a drain of the seventh transistor T7 is electrically connected to the fourth node N4;
a gate of the eighth transistor T8 is electrically connected to the first clock signal terminal NCK, a source of the eighth transistor T8 is electrically connected to the second low voltage terminal, and a drain of the eighth transistor T8 is electrically connected to the fourth node N4;
a gate of the ninth transistor T9 is electrically connected to the second node N2, a source of the ninth transistor T9 is electrically connected to the third voltage terminal, and a drain of the ninth transistor T9 is electrically connected to the fourth node N4;
the first node control circuit 11 includes a tenth transistor T10 and an eleventh transistor T11;
a gate of the tenth transistor T10 is electrically connected to the first clock signal terminal NCK, a source of the tenth transistor T10 is electrically connected to the first low voltage terminal, and a drain of the tenth transistor T10 is electrically connected to the first node N1;
a gate of the eleventh transistor T11 is electrically connected to the second node N2, a source of the eleventh transistor T11 is electrically connected to the first clock signal terminal NCK, and a drain of the eleventh transistor T11 is electrically connected to the first node N1;
the second node control circuit 12 includes a twelfth transistor T12;
a gate of the twelfth transistor T12 is electrically connected to the first clock signal terminal NCK, a source of the twelfth transistor T12 is electrically connected to the start voltage terminal NSTV, and a drain of the twelfth transistor T12 is electrically connected to the second node N2.
In the embodiment of the driving circuit shown in fig. 4, all transistors may be PMOS transistors (P-type metal-oxide-semiconductor transistors).
In the embodiment of the driving circuit shown in fig. 4, the first voltage terminal is a first low voltage terminal, the second voltage terminal is a high voltage terminal, and the third voltage terminal is a second low voltage terminal.
In the embodiment of the driving circuit shown in fig. 4, T7 and T11 may be double-gate transistors to reduce leakage current.
As shown in fig. 5, when the embodiment of the driving circuit shown in fig. 4 of the present invention is in operation, the driving cycle includes an input phase S1, an output phase S2, a reset phase S3 and an output off hold phase;
in an input stage S1, NSTV provides a high voltage signal, NCK provides a low voltage signal, NCB provides a high voltage signal, T10 is turned on, N1 is at a low voltage, T12 is turned on, N2 is at a high voltage, T11 is turned off, T7 is turned on, T6 is turned on, T3 is turned on, N3 is connected to NCB, N3 is at a high voltage, T5 is turned off, T9 is turned off, T8 is turned on, N4 is connected to VGL _1, T4 is turned on, N5 is at a high voltage, T1 is turned off, T2 is turned on, and O1 outputs a low voltage signal;
in an output stage S2, NSTV provides a low voltage signal, NCK provides a high voltage signal, NCB provides a low voltage signal, T10 turns off, T12 turns off, T3 turns on, N3 accesses a second clock signal, accordingly reduces the potential of N1, T5 turns on, T6 turns on, so that the potential of N5 is a low voltage, T7 turns on, so that the potential of N4 is a high voltage, T1 turns on, T2 turns off, and O1 outputs a high voltage signal;
in a reset phase S3, NSTV provides a low voltage signal, NCK provides a low voltage signal, NCB provides a high voltage signal, T10 is turned on, T12 is turned on, the potential of N1 is low voltage, the potential of N2 is low voltage, T5 is turned off, T9 is turned on, T8 and T11 are turned on, N4 is connected to VGL _1, T4 is turned on, the potential of N5 is high voltage, T1 is turned off, T2 is turned on, and O1 outputs a low voltage signal;
the output hold off phase comprises a plurality of hold periods, the hold periods comprising a first hold period S41 and a second hold period S42;
in the first holding period S41, NSTV provides a low voltage signal, NCK provides a high voltage signal, NCB provides a low voltage signal, T10 and T12 are both off, the potential of N1 is pulled to a higher voltage by the first clock signal provided by NCK due to the parasitic capacitance of T10, the potential of N2 is pulled to a higher voltage by the first clock signal provided by NCK due to the parasitic capacitance of T12, T3 is off, the potential of N3 is maintained at a high voltage, T5 and T6 are on, the potential of N5 is a high voltage, T9 is on, the potential of N4 is maintained at a low voltage, O1 outputs a low voltage signal;
in the second holding period S42, NSTV provides a low voltage signal, NCK provides a low voltage signal, NCB provides a high voltage signal, T10 and T12 are turned on, the potential of N1 is a low voltage, the potential of N2 is a low voltage, T11 is turned on, T3 is turned on, T5 and T6 are turned off, T9 is turned on, N4 is turned on to VGL _1, T4 is turned on, N5 is turned on to VGH, T1 is turned off, T2 is turned on, and O1 outputs a low voltage signal.
In the embodiment of the driving circuit shown in fig. 4, the voltage value of the high voltage signal VGH may be 7V, the voltage value of VGL may be-7V, the voltage value of VGL _1 may be-12V, and the difference between the voltage value of VGL _1 and the voltage value of VGL is less than or equal to 2Vth, where Vth is the threshold voltage of T2, and the effect of introducing VGL _1 is: after the O1 outputs a high voltage signal, VGL1 ensures that O1 outputs a-7V voltage signal by controlling the gate voltage of T2 so that the potential of N4 is less than or equal to the sum of the voltage value of VGL and Vth, so that there is no threshold voltage loss when O1 outputs a low voltage signal.
When the high-voltage output is completed by the T1, the potential of the N4 is low voltage, the T2 is turned on, the O1 outputs a low-voltage signal, the potential of the N4 controls the T4 to be turned on, so that the potential of the N5 is kept at high voltage, the T1 is ensured to be in a turned-off state, and the T8 plays a role in ensuring that the potential of the N4 is always kept at a low-voltage state after the O1 outputs the high-voltage signal.
The driving method provided by the embodiment of the invention is applied to the driving circuit, and the driving cycle comprises an input stage, an output stage and a reset stage; the driving method includes:
in the input stage, a first node control circuit writes a first voltage signal into a first node under the control of a first clock signal, a second node control circuit writes an initial voltage signal provided by an initial voltage end into a second node under the control of the first clock signal, and a third node control circuit writes a second clock signal into a third node under the control of the potential of the first node; the fourth node control circuit writes a third voltage signal into a fourth node under the control of the first clock signal, the fifth node control circuit writes a second voltage signal into a fifth node under the control of the potential of the fourth node, and the output circuit controls the driving signal end to output the first voltage signal under the control of the potential of the fourth node;
in the output stage, the third node control circuit writes a second clock signal into the third node under the control of the potential of the first node, and changes the potential of the first node according to the third node; the fourth node control circuit controls the second voltage signal to be written into the fourth node under the control of the potential of the third node, the fifth node control circuit controls the fifth node to be communicated with the third node under the control of the second clock signal, and the output circuit controls the driving signal end to output the second voltage signal under the control of the potential of the fifth node;
in the reset stage, the second node control circuit writes the initial voltage signal provided by the initial voltage end into the second node under the control of the first clock signal, the first node control circuit writes the first voltage signal into the first node under the control of the first clock signal, the first node control circuit writes the first clock signal into the first node under the control of the potential of the second node, the third node control circuit writes the second clock signal into the third node under the control of the potential of the first node, the fourth node control circuit writes the third voltage signal into the fourth node under the control of the potential of the second node and the first clock signal, the fifth node control circuit writes the second voltage signal into the fifth node under the control of the potential of the fourth node, and the output circuit controls the driving signal end to output the first voltage signal under the control of the potential of the fourth node.
In a specific implementation, the driving period may further include an output cut-off holding phase disposed after the reset phase; the output cutoff holding phase comprises a plurality of holding periods; the holding period comprises a first holding period and a second holding period; the driving method further includes:
in the first holding time period, the fourth node control circuit maintains the potential of the fourth node, the fifth node control circuit maintains the potential of the fifth node, and the output circuit controls the driving signal end to output a first voltage signal under the control of the potential of the fourth node;
in the second holding time period, the fourth node control circuit writes the third voltage signal into the fourth node under the control of the first clock signal, the fifth node control circuit writes the second voltage signal into the fifth node under the control of the potential of the fourth node, and the output circuit controls the driving signal terminal to output the first voltage signal under the control of the potential of the fourth node.
The display device provided by the embodiment of the invention comprises the driving module;
the driving module comprises a multi-stage driving circuit.
As shown in fig. 6, the first stage driver circuit designated by reference numeral P1, the second stage driver circuit designated by reference numeral P2, the third stage driver circuit designated by reference numeral P3, and the fourth stage driver circuit designated by reference numeral P4 are included in the driver module; each stage of the driving circuit is electrically connected to the first clock signal terminal NCK and the second clock signal NCB, respectively.
Fig. 7 shows an operation timing diagram of at least one embodiment of the driving module shown in fig. 6, in which the driving signal output from the driving signal terminal P1 is denoted by O1(1), the driving signal output from the driving signal terminal P2 is denoted by O1(2), the driving signal output from the driving signal terminal P3 is denoted by O1(3), and the driving signal output from the driving signal terminal P4 is denoted by O1 (4).
The structure of the pixel circuit included in the display device according to the embodiment of the present invention may be as shown in fig. 8.
As shown in fig. 8, at least one embodiment of the pixel circuit may include an organic light emitting diode OLED, a first reset transistor M1, a second reset transistor M2, a driving transistor M3, a data write transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, a compensation control transistor M7, and a storage capacitor CST;
the grid electrode of the M1 is electrically connected with a first reset terminal Resetn _ n-1, the source electrode of the M1 is connected with an initial voltage Vinit, and the drain electrode of the M1 is electrically connected with the source electrode of the M2;
the gate of M2 is electrically connected to the second reset terminal Gaten _ N-1, and the drain of M2 is electrically connected to the seventh node N7;
the gate of M3 is electrically connected with N7, the source of M3 is electrically connected with the eighth node N8, and the drain of M3 is electrically connected with the ninth node N9;
the grid electrode of the M4 is electrically connected with the grid line Gaten _ N, the source electrode of the M4 is connected with a data voltage Vdata, and the drain electrode of the M4 is electrically connected with the N9;
a gate of the M5 is electrically connected to the emission control line EM, a source of the M5 is electrically connected to the high level terminal VDD, and a drain of the M5 is electrically connected to the N8;
a gate of the M6 is electrically connected to the emission control line EM, a source of the M6 is electrically connected to the N9, and a drain of the M6 is electrically connected to the tenth node N10;
the grid electrode of M7 is electrically connected with the grid line Gaten _ N, the source electrode of M7 is electrically connected with N7, and the drain electrode of M7 is electrically connected with N8;
a first terminal of CST is electrically connected to N7, and a second terminal of CST is electrically connected to VDD;
the anode of the OLED is electrically connected with N4, and the cathode of the OLED is electrically connected with a low level terminal VSS.
In the embodiment shown in fig. 8, M1, M2, M4 and M7 are all IGZO (indium gallium zinc oxide) thin film transistors, and M3, M5 and M6 are all low temperature polysilicon thin film transistors.
In the 7T1C pixel circuit shown in fig. 8, when operating, an N-type scan signal (which is a scan signal that is active at a high voltage) is required and written into the T4 and the T7, and the T4 and the T7 become IGZO thin film transistors, so that the data writing capability is deteriorated and the output capability of the driving circuit needs to be improved.
Fig. 9 is an operation timing diagram of the embodiment of the pixel circuit shown in fig. 8.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A driving circuit is characterized by comprising a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, a fifth node control circuit and an output circuit;
the first node control circuit is used for controlling the communication between a first node and a first voltage end under the control of a first clock signal provided by a first clock signal end and controlling the communication between the first node and the first clock signal end under the control of the potential of a second node;
the second node control circuit is used for controlling the communication between the second node and an initial voltage end under the control of the first clock signal;
the third node control circuit is used for controlling the potential of the first node according to the potential of the third node and controlling the communication between the third node and a second clock signal end under the control of the potential of the first node;
the fourth node control circuit is used for controlling the communication between a fourth node and a third voltage end under the control of the potential of the second node, controlling the communication between the fourth node and the second voltage end under the control of the potential of the third node, and controlling the communication between the fourth node and the third voltage end under the control of the first clock signal;
the fifth node control circuit is configured to control communication between the fifth node and the second voltage end under the control of the potential of the fourth node, and control the potential of the fifth node according to the potential of the third node under the control of a second clock signal provided by the second clock signal end;
the output circuit is used for controlling the communication between the driving signal end and the second voltage end under the control of the potential of the fifth node, and controlling the communication between the driving signal end and the first voltage end under the control of the potential of the fourth node.
2. The drive circuit of claim 1, wherein the fifth node control circuit comprises a first control sub-circuit and a second control sub-circuit;
the first control sub-circuit is used for controlling the communication between the fifth node and the second voltage end under the control of the potential of the fourth node;
the second control sub-circuit is used for controlling the communication between the third node and the fifth node under the control of a second clock signal.
3. The drive circuit of claim 1, wherein the fifth node control circuit comprises a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit;
the first control sub-circuit is used for controlling the communication between the fifth node and the second voltage end under the control of the potential of the fourth node;
the second control sub-circuit is used for controlling the third node and the sixth node to be communicated under the control of a second clock signal;
the third control sub-circuit is used for controlling the communication between the sixth node and the fifth node under the control of a first voltage signal provided by the first voltage end.
4. A driving circuit according to any of claims 1 to 3, wherein the fourth node control circuit is further electrically connected to the second node for controlling communication between the fourth node and the third voltage terminal under control of the potential of the second node.
5. The drive circuit according to any one of claims 1 to 3, wherein the output circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor;
the control electrode of the first transistor is electrically connected with the fifth node, the first electrode of the first transistor is electrically connected with the second voltage end, and the second electrode of the first transistor is electrically connected with the driving signal end;
a control electrode of the second transistor is electrically connected with the fourth node, a first electrode of the second transistor is electrically connected with the driving signal end, and a second electrode of the second transistor is electrically connected with the first voltage end;
a first end of the first capacitor is electrically connected with the fifth node, and a second end of the first capacitor is electrically connected with the second voltage end;
the first end of the second capacitor is electrically connected with the fourth node, and the second end of the second capacitor is electrically connected with the first voltage end.
6. The drive circuit according to any one of claims 1 to 3, wherein the third node control circuit includes a third capacitor and a third transistor;
a first end of the third capacitor is electrically connected with the first node, and a second end of the third capacitor is electrically connected with the third node;
a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to a second clock signal terminal, and a second electrode of the third transistor is electrically connected to the third node.
7. The drive circuit of claim 2, wherein the first control sub-circuit comprises a fourth transistor, the second control sub-circuit comprises a fifth transistor;
a control electrode of the fourth transistor is electrically connected to the fourth node, a first electrode of the fourth transistor is electrically connected to the second voltage terminal, and a second electrode of the fourth transistor is electrically connected to the fifth node;
a control electrode of the fifth transistor is electrically connected to the second clock signal terminal, a first electrode of the fifth transistor is electrically connected to the third node, and a second electrode of the fifth transistor is electrically connected to the fifth node.
8. The driver circuit of claim 3, wherein the first control sub-circuit comprises a fourth transistor, the second control sub-circuit comprises a fifth transistor, and the third control sub-circuit comprises a sixth transistor;
a control electrode of the fourth transistor is electrically connected to the fourth node, a first electrode of the fourth transistor is electrically connected to the second voltage terminal, and a second electrode of the fourth transistor is electrically connected to the fifth node;
a control electrode of the fifth transistor is electrically connected with the second clock signal end, a first electrode of the fifth transistor is electrically connected with the third node, and a second electrode of the fifth transistor is electrically connected with the sixth node;
a control electrode of the sixth transistor is electrically connected to the first voltage terminal, a first electrode of the sixth transistor is electrically connected to the sixth node, and a second electrode of the sixth transistor is electrically connected to the fifth node.
9. A drive circuit as claimed in any one of claims 1 to 3 wherein the fourth node control circuit comprises a seventh transistor and an eighth transistor;
a control electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the second voltage terminal, and a second electrode of the seventh transistor is electrically connected to the fourth node;
a control electrode of the eighth transistor is electrically connected to the first clock signal terminal, a first electrode of the eighth transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth transistor is electrically connected to the fourth node.
10. The driver circuit according to claim 4, wherein the fourth node control circuit includes a seventh transistor, an eighth transistor, and a ninth transistor;
a control electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the second voltage terminal, and a second electrode of the seventh transistor is electrically connected to the fourth node;
a control electrode of the eighth transistor is electrically connected to the first clock signal terminal, a first electrode of the eighth transistor is electrically connected to the third voltage terminal, and a second electrode of the eighth transistor is electrically connected to the fourth node;
a control electrode of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the third voltage terminal, and a second electrode of the ninth transistor is electrically connected to the fourth node.
11. A drive circuit as claimed in any one of claims 1 to 3 wherein the first node control circuit comprises tenth and eleventh transistors;
a control electrode of the tenth transistor is electrically connected to the first clock signal terminal, a first electrode of the tenth transistor is electrically connected to the first voltage terminal, and a second electrode of the tenth transistor is electrically connected to the first node;
a control electrode of the eleventh transistor is electrically connected to the second node, a first electrode of the eleventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.
12. The drive circuit according to any one of claims 1 to 3, wherein the second node control circuit includes a twelfth transistor;
a control electrode of the twelfth transistor is electrically connected to the first clock signal terminal, a first electrode of the twelfth transistor is electrically connected to the start voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the second node.
13. A driving method applied to the driving circuit according to any one of claims 1 to 12, wherein the driving period includes an input phase, an output phase, and a reset phase; the driving method includes:
in the input stage, a first node control circuit writes a first voltage signal into a first node under the control of a first clock signal, a second node control circuit writes an initial voltage signal provided by an initial voltage end into a second node under the control of the first clock signal, and a third node control circuit controls a second clock signal to be written into a third node under the control of the potential of the first node; the fourth node control circuit writes a third voltage signal into a fourth node under the control of the first clock signal, the fifth node control circuit writes a second voltage signal into a fifth node under the control of the potential of the fourth node, and the output circuit controls the driving signal end to output a first voltage signal under the control of the potential of the fourth node;
in the output stage, the third node control circuit writes a second clock signal into the third node under the control of the potential of the first node, and changes the potential of the first node according to the third node; the fourth node control circuit controls the second voltage signal to be written into the fourth node under the control of the potential of the third node, the fifth node control circuit controls the fifth node to be communicated with the third node under the control of the second clock signal, and the output circuit controls the driving signal end to output the second voltage signal under the control of the potential of the fifth node;
in the reset stage, the second node control circuit writes the initial voltage signal provided by the initial voltage end into the second node under the control of the first clock signal, the first node control circuit writes the first voltage signal into the first node under the control of the first clock signal, the first node control circuit writes the first clock signal into the first node under the control of the potential of the second node, the third node control circuit writes the second clock signal into the third node under the control of the potential of the first node, the fourth node control circuit writes the third voltage signal into the fourth node under the control of the potential of the second node and the first clock signal, the fifth node control circuit writes the second voltage signal into the fifth node under the control of the potential of the fourth node, and the output circuit controls the driving signal end to output the first voltage signal under the control of the potential of the fourth node.
14. The driving method according to claim 13, wherein the driving period further includes an output off hold phase provided after the reset phase; the output cutoff holding phase comprises a plurality of holding periods; the holding period comprises a first holding period and a second holding period; the driving method further includes:
in the first holding time period, the fourth node control circuit maintains the potential of the fourth node, the fifth node control circuit maintains the potential of the fifth node, and the output circuit controls the driving signal end to output a first voltage signal under the control of the potential of the fourth node;
in the second holding time period, the fourth node control circuit writes the third voltage signal into the fourth node under the control of the first clock signal, the fifth node control circuit writes the second voltage signal into the fifth node under the control of the potential of the fourth node, and the output circuit controls the driving signal terminal to output the first voltage signal under the control of the potential of the fourth node.
15. A display device is characterized by comprising a driving module; the driving module comprises a plurality of stages of the driving circuit as claimed in any one of claims 1 to 12.
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| WO2023141862A1 (en) * | 2022-01-27 | 2023-08-03 | 京东方科技集团股份有限公司 | Voltage supply circuit, voltage supply method, voltage supply module and display apparatus |
| CN118103901A (en) * | 2022-07-29 | 2024-05-28 | 京东方科技集团股份有限公司 | Driving signal generating circuit, driving signal generating method, driving signal generating module and display device |
| WO2024087130A1 (en) * | 2022-10-28 | 2024-05-02 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit, and display apparatus |
| WO2024113203A1 (en) * | 2022-11-30 | 2024-06-06 | 京东方科技集团股份有限公司 | Drive circuit, drive method, and display apparatus |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103093826A (en) * | 2013-01-16 | 2013-05-08 | 昆山龙腾光电有限公司 | Shift-register unit, shift register and grid driver |
| JP2014107001A (en) * | 2012-11-30 | 2014-06-09 | Kyocera Corp | Shift register circuit and picture display unit |
| CN107731195A (en) * | 2017-11-22 | 2018-02-23 | 武汉华星光电技术有限公司 | A kind of nmos type GOA circuits and display panel |
| CN108766356A (en) * | 2018-05-18 | 2018-11-06 | 北京大学深圳研究生院 | Integrated gate drive circuitry and display equipment |
| CN209265989U (en) * | 2018-12-06 | 2019-08-16 | 北京京东方技术开发有限公司 | Shift register, emission control circuit, display panel |
| CN110176204A (en) * | 2018-08-24 | 2019-08-27 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit, display device |
| CN110689848A (en) * | 2019-12-10 | 2020-01-14 | 京东方科技集团股份有限公司 | Display device and driving method |
| CN111243650A (en) * | 2020-02-05 | 2020-06-05 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof and grid driving circuit |
| CN111354309A (en) * | 2020-04-15 | 2020-06-30 | 京东方科技集团股份有限公司 | Display driving module, display driving method and display device |
| CN111445832A (en) * | 2020-05-07 | 2020-07-24 | 合肥京东方卓印科技有限公司 | Shift register unit, signal generation unit circuit, driving method and display device |
| CN111508433A (en) * | 2020-05-28 | 2020-08-07 | 京东方科技集团股份有限公司 | Signal generation circuit, signal generation method, signal generation module and display device |
| CN111524486A (en) * | 2020-06-04 | 2020-08-11 | 京东方科技集团股份有限公司 | Reset control signal generation circuit, method, module and display device |
| CN111768733A (en) * | 2020-06-10 | 2020-10-13 | 京东方科技集团股份有限公司 | Light emission control signal generation circuit, method and display device |
| CN111933083A (en) * | 2020-08-21 | 2020-11-13 | 京东方科技集团股份有限公司 | Shift register unit, driving method and display device |
| CN112185297A (en) * | 2020-10-26 | 2021-01-05 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving method, gate driving circuit and display device |
-
2021
- 2021-06-22 CN CN202110690521.4A patent/CN113421528B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014107001A (en) * | 2012-11-30 | 2014-06-09 | Kyocera Corp | Shift register circuit and picture display unit |
| CN103093826A (en) * | 2013-01-16 | 2013-05-08 | 昆山龙腾光电有限公司 | Shift-register unit, shift register and grid driver |
| CN107731195A (en) * | 2017-11-22 | 2018-02-23 | 武汉华星光电技术有限公司 | A kind of nmos type GOA circuits and display panel |
| CN108766356A (en) * | 2018-05-18 | 2018-11-06 | 北京大学深圳研究生院 | Integrated gate drive circuitry and display equipment |
| CN110176204A (en) * | 2018-08-24 | 2019-08-27 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit, display device |
| WO2020113847A1 (en) * | 2018-12-06 | 2020-06-11 | Boe Technology Group Co., Ltd. | Shift register, light-emitting control circuit, and display panel |
| CN209265989U (en) * | 2018-12-06 | 2019-08-16 | 北京京东方技术开发有限公司 | Shift register, emission control circuit, display panel |
| CN110689848A (en) * | 2019-12-10 | 2020-01-14 | 京东方科技集团股份有限公司 | Display device and driving method |
| CN111243650A (en) * | 2020-02-05 | 2020-06-05 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof and grid driving circuit |
| CN111354309A (en) * | 2020-04-15 | 2020-06-30 | 京东方科技集团股份有限公司 | Display driving module, display driving method and display device |
| CN111445832A (en) * | 2020-05-07 | 2020-07-24 | 合肥京东方卓印科技有限公司 | Shift register unit, signal generation unit circuit, driving method and display device |
| CN111508433A (en) * | 2020-05-28 | 2020-08-07 | 京东方科技集团股份有限公司 | Signal generation circuit, signal generation method, signal generation module and display device |
| CN111524486A (en) * | 2020-06-04 | 2020-08-11 | 京东方科技集团股份有限公司 | Reset control signal generation circuit, method, module and display device |
| CN111768733A (en) * | 2020-06-10 | 2020-10-13 | 京东方科技集团股份有限公司 | Light emission control signal generation circuit, method and display device |
| CN111933083A (en) * | 2020-08-21 | 2020-11-13 | 京东方科技集团股份有限公司 | Shift register unit, driving method and display device |
| CN112185297A (en) * | 2020-10-26 | 2021-01-05 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving method, gate driving circuit and display device |
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