JP2014107001A - Shift register circuit and picture display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of a driver circuit formed by connecting shift register circuits in a multistage manner.SOLUTION: A shift register circuit 20 comprises: a transistor 1 reducing a potential of a node 22 according to a potential of a node 21; a transistor 2 reducing the potential of the node 21 according to the potential of the node 22; a transistor 3 increasing the potential of a node 23 by flowing of "CLK" according to a rise of the potential of the node 21; a transistor 4 outputting "CLK" as "OUT" according to a rise of the potential of the node 23; and a transistor 5 outputting "CLK" as "OUT".

Description

  The present invention relates to a shift register circuit and an image display device.

  Conventionally, a shift register circuit that transmits a signal output from a preceding circuit to a subsequent circuit is known. Such a shift register circuit is used as a driver circuit for sequentially operating display elements such as an LCD (Liquid Crystal Display) and an organic EL (Electro-Luminescence) display.

  Hereinafter, the operation of the shift register circuit will be described with reference to FIG. FIG. 12 is a circuit diagram illustrating a conventional shift register circuit. For example, the shift register circuit 30 illustrated in FIG. 12 includes a plurality of transistors 31 to 38 and nodes 40 and 41. In the example shown in FIG. 12, the gates (base) and drain (collector) of the transistors 31 and 37 are diode-connected.

  In such a shift register circuit 30, when the signal input from the previous circuit is not output to the next circuit, the potential of the node 40 is in the low state and the potential of the node 41 is in the high state. In the shift register circuit 30, when the signal input from the previous circuit is output to the next circuit, the potential of the node 40 is in a high state and the potential of the node 41 is in a low state.

  Here, when a pulse of “in” that is an input signal is input from the preceding circuit, the shift register circuit 30 inputs a pulse to the node 40 via the transistor 31 that operates as a diode. In such a case, as a result of the potential of the node 40 being in a high state and the transistor 35 being in an on state, the shift register circuit 30 outputs “CLK” that is a clock signal as “OUT” that is an output signal.

  Further, the shift register circuit 30 inputs an “in” pulse to the gate (base) of the transistor 34. In such a case, the transistor 34 is turned on, and the potential of the node 41 drops to “VGL (low potential)”. The shift register circuit 30 inputs a clock signal pulse to the gate of the transistor 38. As a result, the transistor 38 is turned on, the potential of the node 41 is lowered to “VGL”, the transistor 33 is turned off, and the potential of the node 40 is in a high state.

  Further, the shift register circuit 30 inputs “OUT” output from the circuit in the next stage to the gate of the transistor 32. Then, since the transistor 32 is turned on, the potential of the node 40 drops to “VGL”. After the operation of the shift register circuit 30, the transistors 34 and 38 are turned off, the potential of the node 41 is changed from the low state to the high state, and the transistors 33 and 36 are turned on. As a result, the node 40 is turned on. A stable low state is obtained.

JP 2003-046090 A

  However, since the shift register circuit 30 described above can output only one “OUT” for one “in”, there is a problem that the circuit scale of the driver circuit in which the shift register circuits are arranged in multiple stages is increased. .

  For example, when the shift register circuit 30 is applied to a driver circuit that operates a display element such as an LCD or an organic EL display, the shift register circuits 30 must be provided by the number of scanning lines, resulting in an increase in circuit scale. It is not possible to narrow the frame.

  The present invention has been made in view of the above, and an object of the present invention is to reduce the circuit scale of a driver circuit in which shift register circuits are connected in multiple stages.

  The shift register circuit according to the present invention includes a first conductive path having a gate connected to a first conductive path, a drain connected to a second conductive path, and a source connected to a low potential terminal. There is a first transistor that lowers the potential of the second conductive path in response to an increase in potential. The shift register circuit includes a second conductive path having a gate connected to the second conductive path, a drain connected to the first conductive path, and a source connected to a low potential terminal. There is a second transistor that lowers the potential of the first conductive path in response to the potential rising. In the shift register circuit, the gate is connected to the first conductive path, the drain is connected to the input terminal of the first clock signal, and the source is connected to the third conductive path. A third transistor that raises the potential of the third conductive path in response to an increase in potential of the first conductive path when a clock signal is input; The shift register circuit has a gate connected to the third conductive path, a drain connected to the input terminal of the second clock signal, and a source connected to the first output terminal that outputs the first output signal. A fourth transistor connected to output a first output signal from the first output terminal in response to an increase in potential of the third conductive path is provided. The shift register circuit has a gate connected to the third conductive path, a drain connected to the input terminal of the third clock signal, and a source connected to the second output terminal that outputs the second output signal. A fifth transistor connected to output a second output signal from the second output terminal in response to an increase in potential of the third conductive path is provided.

  The shift register circuit according to the present invention can reduce the circuit scale of a driver circuit that connects shift register circuits in multiple stages.

It is a circuit diagram which shows the shift register circuit of a 1st form. It is a graph explaining the current characteristic of a transistor. It is a figure explaining the signal waveform input into a shift register circuit. FIG. 6 is a diagram for explaining the operation of the shift register circuit at timing (A). FIG. 10 is a diagram for explaining the operation of the shift register circuit at timing (B). FIG. 10 is a diagram for explaining the operation of the shift register circuit at timing (C). It is a figure for demonstrating operation | movement of the shift register circuit in a timing (D). It is a figure for demonstrating operation | movement of the shift register circuit in a timing (E). It is a figure explaining operation | movement of a shift register circuit. It is a first diagram illustrating an application example of a shift register circuit. It is a 2nd figure explaining the application example of a shift register circuit. It is a circuit diagram explaining the conventional shift register circuit.

  Hereinafter, embodiments of a shift register circuit and an image display device according to the present invention will be described in detail with reference to the drawings. Note that this embodiment does not limit the present invention. And the embodiment illustrated below can be suitably changed and combined in the range which does not contradict a shape.

(First form)
[Structure of shift register circuit]
A first embodiment of the shift register circuit will be described with reference to FIG. FIG. 1 is a circuit diagram showing a shift register circuit according to the first embodiment. As shown in FIG. 1, the shift register circuit 20 includes a shift register unit 25 and an OUT waveform control unit 26. Specifically, the shift register circuit 20 includes a plurality of transistors 1 to 14 and a plurality of nodes 21 to 24. Further, the shift register circuit 20 has input terminals for “in” which is a signal output from the preceding shift register circuit and clock signals “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ” and “CLK ₄ ”. Have.

The shift register circuit 20 has output terminals “OUT ₁ ” and “OUT ₂ ” that are outputs of the shift register circuit 20. That is, the shift register circuit 20 sequentially outputs _two signals “OUT ₁ ” and “OUT ₂ ” for one input signal “in”. For example, when the shift register circuit 20 is applied to a driver circuit of an image display device, signals are sequentially sent from the output terminals of “OUT ₁ ” and “OUT ₂ ” to two continuous gate lines in the image display area. Output.

Further, the shift register circuit 20 has an output terminal “OUT _N ” that inputs the potential of the node 23 as “in” to the shift register circuit of the next stage. Here, the shift register circuit at the next stage has a function of sequentially outputting “OUT ₃ ” and “OUT ₄ ” when the shift register circuit 20 inputs “OUT _N ” as “in”. The shift register circuit 20 has an input terminal to which “OUT ₄ ” is input in order to shift to a standby state after outputting “OUT ₁ ” and “OUT ₂ ”.

  Further, the shift register circuit 20 includes a high potential terminal in which the potential is maintained at a value “VGH” higher than a predetermined threshold, and a low potential terminal in which the potential is maintained at a value “VGL” lower than the predetermined threshold. And have. In the following description, the value of “VGH” is a value higher than GND (ground), for example, 8 (V) to 20 (V), and the value of “VGL” is a value lower than GND. -5 (V) to -15 (V).

  Each of the transistors 1 to 14 is, for example, an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but the present invention is not limited to this. For example, each of the transistors 1 to 14 may be an NPN type transistor or a field effect transistor (FET) that employs a type (n-type) MIS (Metal Insulator Semiconductor) structure in which carriers are electrons. Good.

  Each of the transistors 1 to 14 may be a thin film transistor (TFT) which is a kind of FET, that is, an n-MISFET TFT. Alternatively, a circuit that exhibits a function equivalent to that of the shift register circuit 20 may be configured using a PNP transistor, a FET whose carrier is a hole (p-type), a TFT, or the like.

  Here, each of the transistors 1 to 14 has three electrodes of a gate, a source, and a drain, and the source and the drain are defined by the conductivity of the transistor and the relative potential relationship. Therefore, in the following description, it is assumed that each of the transistors 1 to 14 is an n-channel MOSFET, and among the terminals of each of the transistors 1 to 14, the high potential side terminal is the drain, and the low potential side terminal is the source. Describe.

  Here, a connection relationship between the transistors 1 to 14 and the nodes 21 to 24 in the shift register circuit 20 illustrated in FIG. 1 will be described.

  The node 21 is a conductive path that connects the transistors 1, 2, 3, 13, and 14. Specifically, the node 21 is connected to the gate of the transistor 1, the drain of the transistor 2, the gate of the transistor 3, the drain of the transistor 13, and the source of the transistor 14.

  The node 22 is a conductive path that connects the transistors 1, 2, 7, 11, and 12. Specifically, the node 22 is connected to the drain of the transistor 1, the gate of the transistor 2, the source of the transistor 7, the gate of the transistor 11, and the gate of the transistor 12.

The node 23 is a conductive path that connects the transistors 3 to 5, 9, 10, and the output terminal of “OUT _N ”. Specifically, the node 23 is connected to the source of the transistor 3, the gate of the transistor 4, the gate of the transistor 5, the drain of the transistor 9, and the gate of the transistor 10. The node 23 is connected to an output terminal of “OUT _N ” that transmits the potential of the node 23 as “in” input to the shift register circuit in the next stage.

  Node 24 is a conductive path connecting transistors 8-10. Specifically, the node 24 is connected to the source of the transistor 8, the gate of the transistor 9, and the drain of the transistor 10.

  In the transistor 1, the node 21 is connected to the gate, the node 22 is connected to the drain, and the low potential terminal is connected to the source. The transistor 1 is turned on when the potential of the node 21 is higher than a predetermined threshold value. As a result, the potential of the node 22 is lowered to “VGL”.

  In the transistor 2, the node 22 is connected to the gate, the node 21 is connected to the drain, and the low potential terminal is connected to the source. The transistor 2 is turned on when the potential of the node 22 is higher than a predetermined threshold value. As a result, the potential of the node 21 is lowered to “VGL”.

In the transistor 3, the node 21 is connected to the gate, the input terminal of “CLK ₁ ” is connected to the drain, and the node 23 is connected to the source. The transistor 3 is turned on when the potential of the node 21 is higher than a predetermined threshold value. As a result, since “CLK ₁ ” is input to the node 23, the potential of the node 23 rises or falls according to the potential of “CLK ₁ ”.

In the transistor 4, the node 23 is connected to the gate, the input terminal of “CLK ₂ ” is connected to the drain, the drain of the transistor 11 and the output terminal of “OUT ₁ ” are connected to the source. The transistor 4 is turned on when the potential of the node 23 is higher than a predetermined threshold value. As a result, “CLK ₂ ” is output as “OUT ₁ ”.

In the transistor 5, the node 23 is connected to the gate, the input terminal of “CLK ₃ ” is connected to the drain, the drain of the transistor 12 and the output terminal of “OUT ₂ ” are connected to the source. The transistor 5 is turned on when the potential of the node 23 is higher than a predetermined threshold value. As a result, “CLK ₃ ” is output as “OUT ₂ ”.

The transistor 6 has a gate connected to the input terminal of “CLK ₂ ”, a drain connected to the high potential terminal, and a source connected to the drain of the transistor 7. The transistor 6 is turned on when the potential of “CLK ₂ ” is higher than a predetermined threshold value. As a result, “VGH” is supplied to the drain of the transistor 7.

In the transistor 7, the input terminal of “CLK ₄ ” is connected to the gate, the source of the transistor 6 is connected to the drain, and the node 22 is connected to the source. The transistor 6 is turned on when the potential of “CLK ₄ ” is higher than a predetermined threshold value. As a result, when the potentials of “CLK ₂ ” and “CLK ₄ ” are both higher than a predetermined threshold, “VGH” is supplied to the node 22 and the potential of the node 22 rises.

In the transistor 8, the input terminal of “CLK ₄ ” is connected to the gate, the high potential terminal is connected to the drain, and the node 24 is connected to the source. The transistor 8 is turned on when the potential of “CLK ₄ ” is higher than a predetermined threshold value. As a result, “VGH” is supplied to the node 24 and the potential of the node 24 rises.

  In the transistor 9, the node 24 is connected to the gate, the node 23 is connected to the drain, and the low potential terminal is connected to the source. The transistor 9 is turned on when the potential of the node 24 is higher than a predetermined threshold value. As a result, the potential of the node 23 is lowered to “VGL”.

  In the transistor 10, the node 23 is connected to the gate, the node 24 is connected to the drain, and the low potential terminal is connected to the source. The transistor 10 is turned on when the potential of the node 23 is higher than a predetermined threshold value. As a result, the potential of the node 24 is lowered to “VGL”.

In the transistor 11, the node 22 is connected to the gate, the source of the transistor 4 and the output terminal of “OUT ₁ ” are connected to the drain, and the low potential terminal is connected to the source. The transistor 11 is turned on when the potential of the node 22 is higher than a predetermined threshold value. As a result, the potential at the source of the transistor 4, that is, the output terminal of “OUT ₁ ” is lowered to “VGL”.

In the transistor 12, the node 22 is connected to the gate, the source of the transistor 5 and the output terminal “OUT ₂ ” are connected to the drain, and the low potential terminal is connected to the source. The transistor 12 is turned on when the potential of the node 22 is higher than a predetermined threshold value. As a result, the potential at the source of the transistor 5, that is, the output terminal of “OUT ₂ ” is lowered to “VGL”.

The transistor 13 has a gate connected to the input terminal “OUT ₄ ”, a drain connected to the node 21, and a source connected to the low potential terminal. The transistor 13 is turned on when the potential of “OUT ₄ ” is higher than a predetermined threshold value. As a result, the potential of the node 21 is lowered to “VGL”.

  The transistor 14 has a gate connected to an input terminal of a signal “in”, a drain connected to a high potential terminal, and a source connected to a node 21. The transistor 14 is turned on when the potential of the signal “in” is higher than a predetermined threshold value. As a result, “VGH” is supplied to the node 21 and the potential of the node 21 rises.

As described above, the shift register circuit 20 includes the transistor 1 that decreases the potential of the node 22 as the potential of the node 21 increases, and the transistor 2 that decreases the potential of the node 21 as the potential of the node 22 increases. And have. The shift register circuit 20 includes a transistor 3 that outputs “CLK ₁ ” to the node 23 as the potential of the node 21 increases. Further, the shift register circuit 20 outputs “CLK ₂ ” to the output terminal of “OUT ₁ ” and “CLK ₃ ” to the output terminal of “OUT ₂ ” as the potential of the node 23 increases. And a transistor 5 to be used.

Therefore, the shift register circuit 20 can output _two “OUT ₁ ” and “OUT ₂ ” from one “in”. That is, the shift register circuit 20 raises the potential of the node 21 when the “in” pulse is input to the transistor 14. As a result, “CLK ₁ ” is input to the node 23 via the transistor 3, the transistors 4 and 5 are turned on, and the input terminal of “CLK ₂ ” is electrically connected to the output terminal of “OUT ₁ ”. The input terminal of “CLK ₃ ” is electrically connected to the output terminal of “OUT ₂ ”.

For this reason, the shift register circuit 20 receives the “in” pulse and then shifts the phase of “in” by half by “CLK ₁ ”, “CLK ₂ ”, and “CLK ₂ ”. the case shifted half "CLK _3" is input, it is possible to sequentially output "OUT _1" and "OUT _2" for one "in".

  Here, the current flowing between the drain and source of each of the transistors 1 to 14 varies depending on the potential between the gate and source. For this reason, each of the transistors 1 to 14 is completely turned on when the gate potential is sufficiently higher than a predetermined threshold, but is completely turned on when not sufficiently higher than the predetermined threshold. Must not. Each of the transistors 1 to 14 is completely turned off when the gate potential is sufficiently lower than the predetermined threshold value, but is completely turned off when the gate potential is not sufficiently lower than the predetermined threshold value. It is not turned off.

  For example, FIG. 2 is a graph illustrating current characteristics of a transistor. In the graph shown in FIG. 2, the horizontal axis represents the potential Vg (V: Volt) between the gate and source of each of the transistors 1 to 14, and the vertical axis represents the current Id (A: Ampere) between the drain and source in logarithm. did. As shown in FIG. 2, when the potential Vg is sufficiently low, each of the transistors 1 to 14 is in an off state in which almost no current Id flows.

  Each of the transistors 1 to 14 is in an on (low) state in which the current Id flows when the potential Vg is not sufficiently low. Further, each of the transistors 1 to 14 is in an on (medium) state where the current Id does not sufficiently flow when the potential Vg is not sufficiently high. Further, when the potential Vg is sufficiently high, each of the transistors 1 to 14 is saturated with the current Id and is turned on (high), which is a complete on state.

  For this reason, in the conventional shift register circuit 30 illustrated in FIG. 12, when the potential applied to the gates of the transistors 31 to 38 is not sufficiently higher than a predetermined threshold, the transistors 31 to 38 are turned on ( May not be in a high state and may cause malfunction. Further, the conventional shift register circuit 30 is not turned off and may cause malfunction when the potential applied to the gates of the transistors 31 to 38 is not sufficiently lower than a predetermined threshold value. .

On the other hand, the shift register circuit 20 of the present invention lowers the potential of the node 22 according to the potential of the node 21, not the potential of “OUT ₁ ”. As a result, when the shift register circuit 20 outputs “OUT ₁ ” and “OUT ₂ ”, the potential of the node 22 can be reliably lowered, and the potential of the node 21 can be kept sufficiently high. A drop in signal output can be prevented.

Specifically, the shift register circuit 20 includes a transistor 1 that decreases the potential of the node 22 as the potential of the node 21 increases, and a transistor 2 that decreases the potential of the node 21 as the potential of the node 22 increases. And have. The shift register circuit 20 includes a transistor 3 that outputs “CLK ₁ ” to the node 23 as the potential of the node 21 increases. Here, when “CLK ₁ ” flows in the transistor 3, the potential of the node 21 rises due to the bootstrap effect. For this reason, the potential of the node 22 is lowered, the transistor 2 is reliably turned off, and the potential of the node 21 is raised. Therefore, the shift register circuit 20 prevents the potential of “CLK ₁ ” input to the node 23 from being lowered. be able to. As a result, the shift register circuit 20 reliably turns on the transistors 4 and 5, so that the potentials of “OUT ₁ ” and “OUT ₂ ” can be prevented from decreasing.

[Operation Flow of Shift Register Circuit 20]
The operation flow of the shift register circuit 20 will be described. First, a signal input to the shift register circuit 20 will be described with reference to FIG. FIG. 3 is a diagram for explaining a signal waveform input to the shift register circuit. For example, in the example illustrated in FIG. 3, for example, “VST” (vertical scan start signal: Vertical Start) is input to the shift register circuit 20 as “in”, and a plurality of clock signals “CLK ₁ ”, “ “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” are input.

Here, “VST” is a signal that is input to the shift register circuit 20 as “in” when there is no other shift register circuit in the previous stage of the shift register circuit 20. It is a signal which shows the start of the process to transmit. “CLK ₁ ” is a first clock signal whose potential periodically changes from “VGH” to “VGL”, and the shift register circuit 20 outputs “OUT ₁ ” and “OUT ₂ ”. It is a signal indicating a period.

“CLK ₂ ” is a second clock signal whose potential periodically changes from “VGH” to “VGL”, and is a clock signal indicating the timing at which the shift register circuit 20 outputs “OUT ₁ ”. is there. “CLK ₃ ” is a third clock signal whose potential periodically changes from “VGH” to “VGL”, and is a clock signal indicating the timing at which the shift register circuit 20 outputs “OUT ₂ ”. is there. “CLK ₄ ” is a fourth clock signal whose potential periodically changes from “VGH” to “VGL”. In the shift register circuit 20, a clock signal synchronized with the timing at which “in” is input. It is.

The period of "CLK _2" is half of the period of "CLK _1", the potential of "CLK _2", during which the potential of "CLK _1" is "VGH", and "VGH" Become. The period of "CLK _3" is half of the period of "CLK _1", the potential of "CLK _3", while the potential of the "CLK _1" is "VGH", and "VGH" Become. In the following description, as shown in FIG. 3, “CLK ₃ ” is a signal in which the phase of “CLK ₂ ” is delayed by half so that the range in which the potential becomes “VGH” does not overlap. However, the embodiment is not limited to this, and the phase may be delayed by a predetermined amount in accordance with the timing of outputting “OUT ₁ ” and “OUT ₂ ”.

In the following description, the period of “CLK ₂ ” is half of the period of “CLK ₁ ”, but the embodiment is not limited to this. Further, in the following description, in order to facilitate understanding of the operation of the shift register circuit 20 when “in” and each clock signal are input, each clock signal is input after “in” is input. However, for example, a pulse of “CLK ₄ ” may be input simultaneously with “in”.

In the following description, the operation of the shift register circuit 20 is divided into timing (A), timing (B), timing (C), timing (D), and timing (E) indicated by dotted lines in FIG. To do. Specifically, in timing (A), the potential of “in” becomes “VGH”, and the potentials of “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ” become “VGL”. It is timing. The timing (B) means that the potential of “in” becomes “VGL”, the potentials of “CLK ₁ ” and “CLK ₂ ” become “VGH”, and the potentials of “CLK ₃ ” and “CLK ₄ ”. Is the timing when becomes “VGL”.

The timing (C) means that the potential of “in” becomes “VGL”, the potential of “CLK ₁ ” becomes “VGH”, the potential of “CLK ₂ ” becomes “VGL”, and the potential of “CLK ₃ ”. Is the timing when “VGH” and the potential of “CLK ₄ ” becomes “VGL”. The timing (D) means that the potential of “in” becomes “VGL”, the potential of “CLK ₁ ” becomes “VGL”, the potential of “CLK ₂ ” becomes “VGH”, and the potential of “CLK ₃ ”. Is the timing when “VGL” and the potential of “CLK ₄ ” becomes “VGH”. The timing (E) is a timing at which the potentials of “in”, “CLK ₁ ”, and “CLK ₂ ” are “VGL”, and the potentials of “CLK ₃ ” and “CLK ₄ ” are “VGH”. is there.

  Next, the operation of the shift register circuit 20 at each timing (A) to (E) will be described with reference to FIGS. First, the operation of the shift register circuit 20 at the timing (A) will be described with reference to FIG. FIG. 4 is a diagram for explaining the operation of the shift register circuit at the timing (A).

  In FIG. 4, among the conductive paths of the shift register circuit 20, the conductive paths that are in a “High” state that is high enough to enable the transistors 1 to 14 to be turned on are indicated by bold lines. In FIG. 4, the main current flow is indicated by white arrows. In the example shown in FIG. 4, it is assumed that the potential of the node 23 is already “VGL” and the potential of the node 24 is already “VGH” in the previous stage of the timing (A). Such a state can be realized by the timing waveform shown in FIG.

  For example, at timing (A), a pulse “VGH” is input to the gate of the transistor 14 as “in”. Therefore, the transistor 14 is turned on, “VGH” is supplied to the node 21, and the potential of the node 21 rises. In addition, when the potential of the node 21 is in the “High” state, the transistor 1 is turned on, so that the potential of the node 22 is lowered to “VGL” by the transistor 1. Further, since the potential of the node 24 is in the “High” state, the transistor 9 is turned on, so that the potential of the node 23 is lowered to “VGL” by the transistor 9. Further, since the potential of the node 23 is lowered to “VGL”, the transistor 10 is turned off, so that the potential of the node 24 is held in the “High” state.

  Next, the operation of the shift register circuit 20 at the timing (B) will be described with reference to FIG. FIG. 5 is a diagram for explaining the operation of the shift register circuit at the timing (B). In FIG. 5, as in FIG. 4, among the conductive paths of the shift register circuit 20, the conductive paths in the “High” state are indicated by bold lines, and the main current flow is indicated by white arrows.

For example, at the timing (B), since the node 21 is in the “High” state, the transistor 1 is kept on and the potential of the node 22 is held at “VGL”. For this reason, the transistor 2 continues to be turned off, and the node 21 maintains the “High” state. Further, the transistor 3 is turned on by the potential of the node 21 in the “High” state. Here, when the pulse of “CLK ₁ ” is input to the drain of the transistor 3, the potential of the node 21 is further increased by the bootstrap effect, and the transistor 3 is turned on (high). Then, “VGH” of “CLK ₁ ” is surely input to the node 23, so that the node 23 is in a “High” state and the transistor 4 is turned on. Therefore, a pulse of “CLK ₂ ” is output as “OUT ₁ ”.

Here, the transistor 5 is also turned on, but since “CLK ₃ ” is “VGL”, the signal output as “OUT ₂ ” is also “VGL”. Further, since the node 23 is in the “High” state, the transistor 10 is turned on, and the potential of the node 24 is lowered to “VGL”. Thus, when the potential of the node 24 is lowered to “VGL”, the transistor 9 is turned off, so that the potential of the node 23 is kept at “High”. In addition, the potential of the node 23 is transmitted to “OUT _N ” and output as “in” to the next-stage circuit.

Note that when the potential of “CLK ₂ ” becomes “VGH”, the transistor 6 is also turned on. However, since the potential of “CLK ₄ ” is “VGL”, the transistor 7 is kept off, so that the node 22 “VGH” is not supplied, and the potential of the node 22 is kept at “VGL”.

  Next, the operation of the shift register circuit 20 at the timing (C) will be described with reference to FIG. FIG. 6 is a diagram for explaining the operation of the shift register circuit at the timing (C). In FIG. 6, as in FIG. 4, among the conductive paths of the shift register circuit 20, conductive paths that are in the “High” state are indicated by bold lines, and main current flows are indicated by white arrows.

For example, at the timing (C), since the potential of the node 21 is kept in the “High” state, the transistors 1 and 3 are kept on. Therefore, the potential of the node 22 is kept at “VGL” and the potential of the node 23 is kept in the “High” state. Here, since the potential of the node 23 is kept in the “High” state, when the transistor 5 is turned on and the pulse of “CLK ₃ ” is input, the pulse of “CLK ₃ ” is changed to “OUT ₂ ”. Is output. Further, since the potential of the node 23 is kept in the “High” state, “IN” having the same cycle as “CLK ₁ ” is transmitted from “OUT _N ” to the shift register circuit in the next stage.

  Next, the operation of the shift register circuit 20 at the timing (D) will be described with reference to FIG. FIG. 7 is a diagram for explaining the operation of the shift register circuit at the timing (D). In FIG. 7, as in FIG. 4, among the conductive paths of the shift register circuit 20, conductive paths that are in the “High” state are indicated by bold lines, and main current flows are indicated by white arrows.

For example, at timing (D), the potential of “CLK ₁ ” is “VGL”, and the potentials of “CLK ₂ ” and “CLK ₄ ” are “VGH”. In such a case, since the transistors 6 and 7 are turned on, “VGH” is supplied to the node 22. Here, since the node 21 is in the “High” state, the potential of the node 22 is continuously pulled down to “VGL” via the transistor 1, but “VGH” is supplied to the node 22, so Although not present, the potential of the node 22 is in a “High” state. For this reason, the transistor 2 is turned on, and the potential of the node 21 is lowered to “VGL”.

Further, since the transistor 8 is turned on, “VGH” is supplied to the node 24, and the potential of the node 24 is set to the “High” state. Then, since the transistor 9 is turned on, the potential of the node 23 is lowered to “VGL”. As a result, the transistor 4 and 5 because turns off, not output as "OUT _1" is also a pulse is inputted in the "CLK _2", the potential at "OUT _1" is held in the "VGL". Further, since the potential of the node 23 is lowered to “VGL”, the potential of “OUT _N ” input as “in” to the next-stage shift register circuit becomes “VGL”.

In addition, since the potential of the node 22 is not perfect, the transistor 11 and 12 are turned on, and the potentials at the output terminals of “OUT ₁ ” and “OUT ₂ ” are lowered to “VGL”. For this reason, the shift register circuit 20 can prevent “OUT ₁ ” and “OUT ₂ ” from being output at an incorrect timing.

  Next, the operation of the shift register circuit 20 at the timing (E) will be described with reference to FIG. FIG. 8 is a diagram for explaining the operation of the shift register circuit at the timing (E). In FIG. 8, as in FIG. 4, among the conductive paths of the shift register circuit 20, the conductive paths in the “High” state are indicated by bold lines, and the main electric flow is indicated by white arrows.

For example, at the timing (E), the potentials of “CLK ₃ ” and “CLK ₄ ” are “VGH”. At timing (E), a pulse of the signal “OUT ₄ ” corresponding to “OUT ₂ ” is input to the transistor 13, which is a signal output from the next shift register circuit. Therefore, the transistor 13 is turned on and the potential of the node 21 is pulled down to “VGL”, so that the transistor 1 is turned off, so that a decrease in the potential of the node 22 is suppressed and the transistor 3 is turned off. Become.

Further, although the potential of the node 22 is not perfect but is in a “High” state, the transistors 11 and 12 are turned on. As a result, the potentials at the output terminals of “OUT ₁ ” and “OUT ₂ ” are kept at “VGL”. Further, when the potential of “CLK ₄ ” becomes “VGH”, the transistor 8 is turned on, so that “VGH” is supplied to the node 24. As a result, since the potential of the node 24 becomes “High”, the transistor 9 is turned on, and the potential of the node 23 is lowered to “VGL”. Thus, the transistor 5 is kept in the OFF state is not output as "CLK _3", "OUT _2" even pulse is input, the potential at the output terminal of the "OUT _2" is maintained at "VGL". For this reason, the shift register 20 can maintain a stable OFF state.

Next, the operation of the shift register circuit 20 when each signal is input will be described with reference to FIG. FIG. 9 is a diagram illustrating the operation of the shift register circuit. Note that FIG. 9 shows input waveforms of “CLK ₁ ”, “CLK ₂ ”, “CLK ₃ ”, “CLK ₄ ”, and “in” input to the shift register circuit 20, and potential changes of the nodes 21 to 24. , And waveforms of “OUT ₁ ”, “OUT ₂ ”, “OUT ₃ ”, and “OUT ₄ ” are shown. Here, “OUT ₃ ” is a signal that is output first after the next-stage circuit inputs “in”, and is a signal corresponding to “OUT ₁ ” output by the shift register circuit 20. Further, “OUT ₄ ” is a signal output second after the next-stage circuit inputs “in”, and is a signal corresponding to “OUT ₂ ” output by the shift register circuit 20.

  Further, in FIG. 9, the range in which each of the transistors 1 to 14 is in the on (high) state is indicated by shading, the range in which the on (medium) state is set is indicated by dark stippling, and the range in which the on (low) state is set. Shown in light stippling. Further, the range in which each of the transistors 1 to 14 is turned off is shown in white. In the state before T1 in FIG. 9, the potentials of the nodes 21 and 23 are “VGL”, and the potentials of the nodes 22 and 24 are “VGH”.

Further, in FIG. 9, as in the shift register circuit 20, “OUT ₁ ” and “OUT ₂ ” are input in response to the input of “in” synchronized with “CLK ₄ ” that periodically changes. ”Are sequentially output, and the output is stopped by“ OUT ₄ ”input from the subsequent shift register circuit. Here, the above series of flows will be specifically described using the states of the transistors 1 to 14 in the period indicated by T1 to T21 in FIG.

Specifically, T1 is a previous stage until the “in” signal is input, and the potential of “CLK ₁ ” is the potential of “VGH”, “CLK ₂ ”, “CLK ₃ ”, and “CLK ₄ ”. Is a period in which “VGL” is set. In addition, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGH”. This is a period during which an “in” pulse is input.

Further, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGH”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGH”. This is a period during which the “in” pulse becomes “VGH”. In addition, the potential of “CLK ₁ ” is changed to “VGL”, the potential of “CLK ₂ ” is changed to “VGL”, the potential of “CLK ₃ ” is changed from “VGL” to “VGH”, and then is changed to “VGL”. In this period, the potential of “CLK ₄ ” becomes “VGH” and the pulse of “in” becomes “VGH”.

In addition, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGL”. This is a period of “VGL” after an “in” pulse is input. In T6, the potential of “CLK ₁ ” is “VGH”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGL”. It is a period. In T7, the potential of “CLK ₁ ” is “VGH”, the potential of “CLK ₂ ” is “VGH”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGL”. It is a period. In T8, the potential of “CLK ₁ ” is “VGH”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGL”. It is a period.

In T9, the potential of “CLK ₁ ” is “VGH”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is changed from “VGH” to “VGL”, and “CLK ₄ ” This is a period during which the potential of “VGL” becomes “VGL”. In T10, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGL”. It is a period. In T11, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGH”. It is a period. In T12, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGH”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGH”. It is a period.

In T13, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGH”. It is a period. In T14, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGH”, and the potential of “CLK ₄ ” is “VGH”. It is a period. In T15, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGH”. It is a period.

In T16, the potential of “CLK ₁ ” changes from “VGL” to “VGH”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and “CLK ₄ ”. This is a period during which the potential is “VGL”. In T17, the potential of “CLK ₁ ” is “VGH”, the potential of “CLK ₂ ” is “VGH”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGL”. It is a period. In T18, the potential of “CLK ₁ ” transitions from “VGH” to “VGL”, the potential of “CLK ₂ ” transitions from “VGL”, and the potential of “CLK ₃ ” transitions from “VGL” to “VGH”. After that, a transition is made to “VGL” and the potential of “CLK ₄ ” is “VGL”.

In T19, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGL”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGH”. It is a period. In T20, the potential of “CLK ₁ ” is “VGL”, the potential of “CLK ₂ ” is “VGH”, the potential of “CLK ₃ ” is “VGL”, and the potential of “CLK ₄ ” is “VGH”. It is a period. In addition, the potential of “CLK ₁ ” is changed to “VGL”, the potential of “CLK ₂ ” is changed to “VGL”, and the potential of “CLK ₃ ” is changed from “VGL” to “VGH”, and then is changed to “VGL”. In this period, the potential of “CLK ₄ ” is “VGH”.

For example, from before T1 to T1 in FIG. 9, the potential of the node 21 is “VGL”, the potential of the node 22 is “VGH”, and the potential of the node 24 is “VGH”. , 11 and 12 are turned on (high). For this reason, as a result of the potential of the node 21 being kept at “VGL”, the transistor 3 is in an off state, so that the pulse of “CLK ₁ ” is not input to the node 23. Further, since the potential of the node 23 is pulled down to “VGL” via the transistor 9, the potential of the node 23 is kept at “VGL”.

Subsequently, at T2 in FIG. 9, the potential of “CLK ₁ ” transitions to “VGL” and the potential of “CLK ₄ ” transitions to “VGH”, so that the transistor 7 is turned on (high), and the transistor 8 is turned on (low). As a result, “VGH” is supplied to the node 24 and the potential of the node 24 becomes “VGH”. Further, when the potential of the node 24 rises to “VGH”, the transistor 9 is kept on (high), so that the potential of the node 23 is held at “VGL”.

Here, since the “in” pulse is input to the transistor 14, the transistor 14 is turned on (high), “VGH” is supplied to the node 21, and the potential of the node 21 is increased. Thus, when the potential of the node 21 rises, the transistors 1 and 3 are turned on, so that the potential of the node 22 is lowered to “VGL”. As a result, the potential of the node 22 drops to about “GND”, and the transistors 11 and 12 are turned on (medium). As a result, the potentials at the output terminal “OUT ₁ ” and the output terminal “OUT ₂ ” are held at “VGL”.

Subsequently, at T3 in FIG. 9, the potential of “CLK ₂ ” transitions to “VGH”, so that the transistor 6 is turned on (medium). Similarly to T2 in FIG. 9, since the potential of “CLK ₄ ” is “VGH” and the transistor 7 is in an on (high) state, “VGH” is connected to the node 22 via the transistors 6 and 7. Is supplied. On the other hand, since the potential of the node 21 is a value close to “GND” and the transistor 1 is in an on (high) state, the potential of the node 22 holds an intermediate state, that is, a potential in the vicinity of GND.

Subsequently, at T4 in FIG. 9, since the potential of “CLK ₂ ” transitions to “VGL”, the transistor 6 is turned off. Further, since “in” is “VGH”, “VGH” is supplied to the node 21 through the transistor 14 in the on (high) state, and the potential of the node 21 continues to rise.

  Further, when the potential of the node 21 rises, the potential of the node 22 is lowered to “VGL” through the transistor 1, and thus the potential of the node 22 becomes lower than “GND”. Then, since the transistor 2 is turned on (low), the potential drop at the node 21 is suppressed. As a result, the potential of the node 21 is higher than GND, and the potential of the node 22 is lower than GND. In addition, since the potential of the node 22 is lower than GND, the transistors 11 and 12 are turned on (low).

Subsequently, at T5 in FIG. 9, since “in” transitions to “VGL”, the transistor 14 is turned off. For this reason, the node 21 is not supplied with “VGH”. Further, since “CLK ₄ ” becomes “VGL”, the transistors 7 and 8 are turned off.

Here, when the potential of “CLK ₁ ” transitions to “VGH” at T 6 in FIG. 9, a pulse of “CLK ₁ ” flows through the transistor 3 that was in the on (medium) state at T 5. Then, a pulse voltage of “CLK ₁ ” is applied from the drain to the source of the transistor 3, a bootstrap effect is generated, and the potential of the node 21 rises due to coupling.

  Then, since the transistor 1 is turned on (high), the potential of the node 22 is further lowered to “VGL”, and the transistor 2 is turned off. Then, the potential of the node 21 rises to about 1.3 to 1.5 times “VGH”, and the transistor 1 is turned on (high). Then, the potential of the node 22 is completely lowered to “VGL”.

Further, when the voltage at the node 21 is increased, the transistor 3 is turned on (high). As a result, the pulse of “CLK ₁ ” is input to the node 23, so that the potential of the node 23 is increased to “VGH”. Then, since the transistor 10 is turned on (high), the potential of the node 24 is lowered to “VGL”, and the transistor 9 is turned off. As a result, since the potential of the node 23 is maintained at “VGH”, the transistors 4 and 5 are turned on (high). Further, since the potential of the node 23 becomes “VGH”, “OUT _N ” input as “in” in the next stage becomes “VGH”.

Subsequently, at T7 in FIG. 9, the potential of “CLK ₂ ” transitions to “VGH”. Then, following the in FIG. 9 T6, the transistor 4 is ON (high) state, a pulse of "CLK _2" is transmitted to the output terminal of the "OUT _1", a pulse of "CLK _2" is "OUT _1" Is output as In addition, at T8 in FIG. 9, the potential of “CLK ₂ ” transitions to “VGL”. For this reason, the potential of “OUT ₁ ” also changes to “VGL”.

Subsequently, a pulse of “CLK ₃ ” is input at T9 in FIG. Then, following the in FIG. 9 T6, the transistor 5 is on (high) state, a pulse of "CLK _3" is transmitted to the output terminal of the "OUT _2", a pulse of "CLK _3" is "OUT _2" Is output as

As described above, the shift register circuit 20 includes the transistor 1 that electrically connects the node 22 and the low potential terminal according to the potential of the node 21, and when the potential of the node 21 rises, the node 22 The potential of is lowered. The shift register circuit 20 raises the potential of the node 21 due to the bootstrap effect when “CLK ₁ ” flows from the drain to the source of the transistor 3, so that the transistor 1 is turned on (high), The potential of 22 is further lowered. As a result, since the transistor 2 is completely turned off, the potential of the node 21 can be maintained at a high level. As a result, the shift register circuit 20 can reliably maintain the potential of the node 23 at a high level.

When the potential of the node 23 is high, that is, when “CLK ₁ ” is in the “VGH” state, the shift register circuit 20 outputs “CLK ₂ ” as “OUT ₁ ”, and then “CLK ₃ ”. Is output as “OUT ₂ ”. Thus, since the shift register circuit 20 outputs two different pulses for one pulse, the circuit scale of the driver circuit composed of the shift register circuit 20 can be reduced. For this reason, for example, when the shift register circuit 20 is applied to a driver circuit that operates the display element, it is only necessary to install half the number of shift registers of the scanning lines. A frame can be made.

Subsequently, at T10 in FIG. 9, the potential of “CLK ₁ ” transitions to “VGL”. Then, the node 21 returns to a High state that is slightly higher than GND due to coupling when pulled back to the low potential of “CLK ₁ ” from the source to the drain of the transistor 3. Then, the transistor 3 is turned on (medium). When the potential of “CLK ₁ ” transitions to “VGL”, the potential of the node 23 to which “CLK ₁ ” is input through the transistor 3 is decreased to “VGL”. For this reason, the transistors 4, 5, and 10 are turned off.

Subsequently, at T <b> 11 in FIG. 9, the potential of “CLK ₄ ” transitions to “VGH”. Then, since the transistors 7 and 8 are turned on (high), “VGH” is supplied to the node 24. Here, the node 24 is connected only to the gate of the transistor 9. For this reason, the potential of the node 24 rises to “VGH” in an instant. As a result, the transistor 9 is turned on (high), so that the potential of the node 23 is lowered to “VGL”.

Subsequently, when the potential of “CLK ₂ ” transitions to “VGH” at T12 in FIG. 9, the transistor 6 is turned on (medium), so that “VGH” is applied to the node 22 via the transistors 6 and 7. Supplied. As a result, the node 21 and the node 22 try to balance the potential, the potential of the node 21 falls to a value slightly lower than “GND”, and the potential of the node 22 rises to a state slightly lower than “GND”. . At this time, the transistors 1 and 2 are turned on (low). In such a case, since the transistors 11 and 12 are turned on (low), the potentials of the output terminal of “OUT ₁ ” and the output terminal of “OUT ₂ ” are lowered to “VGL”. As a result, the shift register circuit 20 can prevent erroneous output of “CLK ₁ ” and “CLK ₂ ”.

In addition, when the potential of the node 21 is lowered to a state slightly lower than “GND”, the transistor 3 is turned on (low). Further, since “OUT _N ” is output as “in” to the next-stage circuit from T6 to T9 in FIG. 9, the next-stage circuit outputs “OUT ₃ ” at T12.

Subsequently, when the potential of “CLK ₂ ” transitions to “VGL” at T 13 in FIG. 9, the transistor 6 is turned off, so that the supply of “VGH” to the node 22 is stopped. Subsequently, at T14 in FIG. 9, the potential of “CLK ₃ ” transitions to “VGH”. However, since the transistor 5 is off and the transistor 12 is on (low), the output terminal of “OUT ₂ ” The potential is kept at “VGL”.

Subsequently, at T14 in FIG. 9, the next-stage circuit outputs a pulse of “OUT ₄ ”, so that “VGH” is supplied to the gate of the transistor 13, so that the transistor 13 is turned on (high), The potential of the node 21 is lowered to “VGL”. Further, since the potential of the node 21 is “VGL”, the transistors 1 and 3 are turned off.

Subsequently, at T15 in FIG. 9, since the potentials of “CLK ₃ ” and “OUT ₄ ” transition to “VGL”, the transistor 13 is turned off. Subsequently, at T16 in FIG. 9, since the potential of “CLK ₄ ” transitions to “VGL”, the transistors 7 and 8 are turned off. Note that at T16 in FIG. 9, the potential of “CLK ₁ ” transitions from “VGL” to “VGH”. However, since the transistor 3 is turned off, no new power is supplied to the node 23, and the node The potential of 23 is held at “VGL”.

Subsequently, at T < _b > 17 in FIG. 9, the potential of “CLK ₁ ” is “VGH”, and the potential of “CLK ₂ ” is “VGH”. However, since the transistor 3 is off, no new power is supplied to the node 23, and the potential of the node 23 is held at “VGL”. As a result, since the transistor 4 is turned off, the pulse of “CLK ₂ ” is not output as “OUT ₁ ”.

Subsequently, at T18 in FIG. 9, the potential of “CLK ₂ ” becomes “VGL” and the potential of “CLK ₃ ” becomes “VGH”. However, as in T17 in FIG. Therefore, the potential of the node 23 is held at “VGL”. As a result, the transistor 4 is turned off, and the pulse of “CLK ₃ ” is not output as “OUT ₂ ”.

Subsequently, at T19 in FIG. 9, since the potential of “CLK ₄ ” transitions to “VGH”, the transistors 7 and 8 are turned on (low). Subsequently, at “T20” in FIG. 9, when “CLK ₂ ” transitions to “VGH”, the transistor 6 is turned on (medium), so that “VGH” is supplied to the node 22 via the transistors 6 and 7. As a result, the potential of the node 22 rises to “VGH”. In such a case, since the transistor 2 is turned on (high), the potential of the node 21 is held at “VGL”. As a result, the shift register 20 can maintain a stable off state, that is, a non-selected state.

Note that at T20 in FIG. 9, since the potential of the node 23 is maintained at “VGL”, the transistor 4 is not turned on, and “CLK ₂ ” is not output as “OUT ₁ ”. When the potential of the node 22 rises to “VGH”, the transistors 11 and 12 are turned on (high), so that the potentials of the output terminal of “OUT ₁ ” and the output terminal of “OUT ₂ ” are “VGL”. As a result, the output of an erroneous signal in the off state can be prevented.

Further, at T21 in FIG. 9, the potential of “CLK ₂ ” becomes “VGL”, and the pulse of “CLK ₃ ” is input. However, since the potential of the node 23 is maintained at “VGL”, the transistor 5 is in an off state, so that “OUT ₃ ” is not output as “OUT ₂ ”. Thereafter, the shift register circuit 20 continues the operation indicated by T16 to T21 in FIG. 9 unless “in” is input. In addition, when “in” is not input, the shift register circuit 20 outputs “VGH” to the node 22 every time both the potential of “CLK ₂ ” and the potential of “CLK ₄ ” transition to “VGH”. Therefore, a stable off state can be maintained.

[Effect of the shift register circuit 20]
As described above, the shift register circuit 20 includes the transistor 1 that decreases the potential of the node 22 in response to the increase in the potential of the node 21 and the potential of the node 21 in response to the increase in the potential of the node 22. And a transistor 2 for lowering. The shift register circuit 20 includes the transistor 3 that raises the potential of the node 23 in response to the rise of the potential of the node 21. Further, the shift register circuit 20 includes the transistor 4 that outputs “CLK ₂ ” as “OUT ₁ ” in response to the rise in the potential of the node 23, and the “CLK ₂ ” in response to the rise in the potential of the node 23. ₃ ”is output as“ OUT ₂ ”.

Therefore, the shift register circuit 20 can output “OUT ₁ ” and “OUT ₂ ” with respect to one “in”, and thus the circuit scale of the driver circuit including the shift register circuit 20 is reduced. be able to. For example, when the shift register circuit 20 is applied to a driver circuit that operates a display element, the frame size of the driver circuit can be reduced, resulting in a narrow frame.

Note that since the shift register circuit 20 includes the transistor 3 that raises the potential of the node 21 by the bootstrap effect, the potential of “CLK ₁ ” input to the node 23 can be prevented from dropping. As a result, the shift register circuit 20 can turn on the transistors 4 and 5, so that the potential drops of “OUT ₁ ” and “OUT ₂ ” can be prevented.

Further, in the shift register circuit 20, “CLK ₂ ” is input to the gate, the drain is connected to the high potential terminal, the transistor 6 is connected to the drain of the transistor 7, and “CLK ₄ ” is input to the gate. , The transistor 7 having a drain connected to the source of the transistor 6 and a source connected to the node 22. That is, the shift register circuit 20 includes the transistors 6 and 7 that increase the potential of the node 22 when the potentials of “CLK ₂ ” and “CLK ₄ ” are both “VGH”. For this reason, the shift register circuit 20 supplies “VGH” to the node 22 every time both the potential of “CLK ₂ ” and the potential of “CLK ₄ ” are “VGH”, and thus maintains a stable OFF state. be able to.

Further, the shift register circuit 20 lowers the potential of the node 8 in accordance with the rise of the potential of the node 24 and the transistor 8 that raises the potential of the node 24 in response to the rise of the potential of “CLK ₄ ”. The transistor 9 and the transistor 10 that lowers the potential of the node 24 in response to the rise of the potential of the node 23 are included. Therefore, the shift register circuit 20, "OUT _1", and after outputting the "OUT _2", because keeping the potential of the node 23 to "VGL", the result of keeping the transistors 4 and 5 in the OFF state, "OUT ₁ ”And“ OUT ₂ ”can be prevented from being erroneously output.

The shift register circuit 20 includes a transistor 11 that decreases the potential of the output terminal of “OUT ₁ ” in response to an increase in the potential of the node 22, and “OUT ₂ ” in response to an increase in the potential of the node 22. And a transistor 12 for lowering the potential of the output terminal of the transistor. Therefore, the shift register circuit 20 can prevent erroneous output of “OUT ₁ ” and “OUT ₂ ” in the off state.

The shift register circuit 20 has an output terminal “OUT _N ” that outputs the potential of the node 23 as “in” in the next stage. For this reason, the shift register circuit 20 can input an “in” signal to the next-stage circuit at an appropriate timing. Specifically, the shift register circuit 20, "OUT _1", while outputs "OUT _2" and entering the "in" signal to the next-stage circuit, the shift register circuit 20 is to "OUT _2" After the output, “OUT ₃ ” can be output to the next-stage circuit.

In addition, the shift register circuit 20 includes a transistor 13 that lowers the potential of the node 21 in response to an increase in the potential of “OUT ₄ ” output from the circuit in the next stage. For this reason, the shift register circuit 20 can reliably transit to the non-selected state when the circuit in the subsequent stage outputs a signal.

  Further, the shift register circuit 20 includes the transistor 14 that raises the potential of the node 21 in response to the rise of the potential of “in”. For this reason, the shift register circuit 20 can increase the potential of the node 21 when “in” is input, and shift to the selected state.

Further, “CLK ₃ ” obtained by delaying the phase of “CLK ₂ ” by a predetermined amount is input to the shift register circuit 20, and “CLK ₁ ” having a period twice as long as “CLK ₂ ” and “CLK ₃ ”. Is entered. For this reason, the shift register circuit 20 can output “OUT ₁ ” while “CLK ₁ ” is “VGH”, and then can output “OUT ₂ ”.

[Scope of application]
For example, the shift register circuit 20 exemplified in the above embodiment is suitably applied to a driver circuit that operates an image display device using a liquid crystal panel or an organic EL (Electro-Luminescence) panel. The shift register circuit 20 can also be applied to circuits other than the driver circuit described above. The shift register circuit 20 can be applied to an arbitrary device such as a sensor device, a light emitting element array, or a thermal head having a plurality of transistors and a driver circuit for sequentially driving each element.

(Application to LCD panel)
In the following description, an example in which the shift register circuit 20 is applied to a driver circuit that operates an image display device using a liquid crystal panel will be described as an application example of the shift register circuit 20.

  FIG. 10 is a first diagram illustrating an application example of the shift register circuit. In the example illustrated in FIG. 10, the image display device 50 includes a control circuit 51 and a panel 52. Note that the image display device 50 includes a light source device such as a backlight, a color filter substrate, a polarizing plate having different polarization directions, and the like, but the description thereof is omitted in FIG. 10 for easy understanding.

  The control circuit 51 is provided on, for example, an FPC (Flexible Printed Circuits) disposed on the panel 52 or on an external circuit board of the panel 52, and drives a control signal for driving the panel 52. Output to the circuit 55. In FIG. 10, illustration of the FPC or the external circuit board is omitted.

  In addition, a liquid crystal panel is used for the panel 52, and it is composed of a pair of substrates. For example, the panel 52 is composed of a pair of glass substrates including an array substrate in which a thin film transistor is formed in the active area 57 and a color filter substrate facing the array substrate. A peripheral portion 54 is formed around the array substrate in the active area 57. The peripheral portion 54 is provided with a driving circuit 55 and a scanning line driving circuit 56, and the scanning line driving circuit 56 is formed on the glass of the array substrate. The driving circuit 55 and the scanning line driving circuit 56 are connected by a scanning line control line 53.

  The drive circuit 55 is composed of a semiconductor element for driving, and includes a signal line drive circuit for outputting an image signal to a data line extending on the active area, a scanning line control circuit, a counter potential drive circuit, and the like. The drive circuit 55 is mounted on the peripheral portion 54 of the active area 57 by a COG (Chip On Glass) method.

  In addition, a plurality of circuits that exhibit the same function as the shift register circuit 20 described in the first embodiment are applied to the scanning line driving circuit 56 provided in the peripheral portion 54 of the panel 52. Specifically, the scan line driving circuit 56 is connected in multiple stages to shift register units 25 to 25b that perform the same function as the shift register unit 25. Each shift register unit 25 to 25b includes an OUT waveform control unit. 26 are connected to OUT waveform control units 26 to 26b that perform the same functions as the H.26.

The shift register units 25 to 25b are formed on a scanning line driving circuit 56 that is integrally formed on the array substrate of the panel 52. In addition to the shift register units 25 to 25b and the OUT waveform control units 26 to 26b, the scanning line driving circuit 56 includes a shift register circuit including a plurality of shift register units and an OUT waveform control unit. In FIG. 10, the description is omitted for easy understanding. In addition, two scanning lines extending on the active area 57 are connected to each of the OUT waveform control units 26 to 26b. In the example illustrated in FIG. 10, the input lines of “CLK ₁ ” to “CLK ₄ ” are omitted for easy understanding.

  The drive circuit 55 is connected to the scan line drive circuit 56 through the scan line control line 53, and outputs a control signal to the first-stage shift register unit 25 through the scan line control line 53.

  The active area 57 has a plurality of pixels 58 arranged in a matrix. Specifically, in the active area 57, a plurality of data lines are extended in the column direction, and a plurality of scanning lines are extended in the row direction. In the active area 57, pixels 58 are formed corresponding to the intersections of the data lines and the scanning lines.

  Here, the pixel 58 includes a thin film transistor 59 that operates as an active element, and a pixel electrode 60. The image display device 50 displays an image by controlling liquid crystal molecules with a voltage applied between a pixel electrode 60 provided on the array substrate and a common electrode (not shown) provided on the color filter substrate. Here, the panel 52 is described in a vertical electric field method in which the pixel electrode 60 is provided on the array substrate and the common electrode is provided on the color filter substrate. Alternatively, a horizontal electric field method in which a pixel electrode 60 and a common electrode are provided may be used.

The scanning line driving circuit 56 is a circuit in which shift register units 25 to 25b similar to the shift register unit 25 according to the first embodiment are connected in multiple stages, and OUT waveform control units 26 to 26b are connected to the shift register units 25 to 25b. Consists of. Here, the scanning line driving circuit 56 sequentially inputs “OUT ₁ ” and “OUT ₂ ” output from the OUT waveform control unit 26 to the scanning lines extending on the active area 57 by the operation of the shift register unit 25 described above. To do.

Further, since the potential of the node 23 included in the shift register unit 25 is input as “in” to the shift register unit 25a, the scanning line driving circuit 56 outputs the OUT waveform control unit 26a according to the operation of the shift register circuit 25a. “OUT ₃ ” and “OUT ₄ ” are sequentially input to the scanning line extending on the active area 57. As described above, the shift register units 25 to 25b installed in multiple stages sequentially shift the signals, and each OUT waveform control unit 26 to 26b sequentially outputs the two signals. For this reason, when a control signal is input from the drive circuit 55 via the scanning line control line 53, the scanning line driving circuit 56 applies voltages to the scanning lines on the active area 57 in order from the top. Apply.

For example, when the scanning line driving circuit 56 receives the control signal, the operation of the shift register unit 25 and the OUT waveform control unit 26 outputs “OUT ₁ ” to the first scanning line, and then outputs “OUT ₂ ”. Is output to the second scanning line. Next, the scanning line driving circuit 56 outputs “OUT ₃ ” to the third stage scanning line by the operations of the shift register unit 25 a and the OUT waveform control unit 26, and then outputs “OUT ₄ ” to the fourth stage. Output to the scan line. As a result, the scanning line driving circuit 56 sequentially applies a voltage to each scanning line on the active area 57.

  Here, when the scanning line driving circuit 56 is configured using a conventional shift register circuit, the same number of shift register circuits as the scanning lines extended on the active area 57 are connected in multiple stages, and each shift register is connected. A signal is output from the circuit onto each scanning line. However, when the scanning line driving circuit 56 is configured using the shift register circuit 20 including the shift register unit 25 and the OUT waveform control unit 26, a signal is sent from one shift register circuit 20 to two scanning lines. Therefore, the circuit scale of the scanning line driving circuit 56 can be reduced, and the narrowed frame of the image display device 50 can be realized.

  In addition, the shift register circuit 20 can output the output signal without lowering the potential of the signal due to the bootstrap effect, so that the voltage applied to each scanning line by the scanning line driving circuit 56 can be prevented from being lowered. As a result, the image display device 50 can prevent a decrease in the voltage applied to each pixel 58 even when the number of scanning lines increases due to the increase in the size of the active area 57 or the densification of the pixels 58. Can work.

  In the thin film transistor 59, a data line and a source corresponding to the position where the pixel 58 is formed are connected, and a scanning line and a gate corresponding to the position where the pixel 58 is formed are connected. When a voltage is applied to the corresponding scanning line from the scanning line driving circuit 56 and a voltage is applied to the corresponding data line from the driving circuit 55, the voltage applied to the data line is passed through the thin film transistor 59. Applied to the pixel electrode 60.

  Note that FIG. 10 illustrates an example in which the shift register circuit 20 is applied to an image display device using a liquid crystal panel. However, the embodiment is not limited to this. For example, the shift register circuit 20 may be applied to an image display device using an organic EL panel. For example, FIG. 11 is a second diagram illustrating an application example of the shift register circuit 20.

(Application to organic EL)
In the example shown in FIG. 11, the image display device 70 having the scanning register driving circuit 56 having the shift register unit 25 and the OUT waveform control unit 26 and using an organic EL panel is described. In the example shown in FIG. 11, the scanning line driving circuit 56 having the shift register circuit 20 including the shift register unit 25 and the OUT waveform control unit 26 is described for easy understanding. Includes a plurality of circuits similar to the shift register circuit 20. Specifically, the scanning line driving circuit 56 may be configured by connecting, in multiple stages, the same circuits as the shift register circuit 20 by a number that is half the number of scanning lines extending on the active area 57. Note that the shift register circuit 20 is integrally formed on the peripheral portion of the panel 52 on the array substrate, similarly to the image display device 50 using the above-described liquid crystal panel.

  In the example shown in FIG. 11, the pixel 58 includes a light emitting element 80 whose anode is electrically connected to the constant potential supply circuit 71, and a transistor 81 whose one electrode is connected to the cathode of the light emitting element 80. The pixel 58 includes an n-type thin film transistor, and includes a driver element 83 whose drain is connected to the drain of the transistor 82 and whose source is electrically connected to the power supply circuit 72. In addition, the pixel 58 includes a transistor 82 that controls the conduction state between the gate and the drain of the thin film transistor that forms the driver element 83, and a capacitance 84.

  In the example shown in FIG. 11, a constant potential supply circuit 71 that supplies a constant on potential to the anode of the light emitting element 80 provided in each pixel 58, and a transistor 81 provided in the pixel 58 via a control line. And a power supply circuit 72 for supplying an ON potential or a zero potential to the source of the driver element 83.

  The light emitting element 80 has a mechanism for emitting light by current injection, and is formed of, for example, an organic EL element. The organic EL device includes an anode layer and a cathode layer formed of Al, Cu, ITO (Indium Tin Oxide), and the like, and phthalocyanine, trisaluminum complex, benzoquinolinolato, and beryllium complex between the anode layer and the cathode layer. And a light emitting layer formed of an organic material such as an organic material, and has a function of generating light by recombination of holes and electrons injected into the light emitting layer.

  The transistor 81 has a function of controlling conduction between the light emitting element 80 and the driver element 83, and is formed of an n-type thin film transistor in the first embodiment. That is, the drain and the source of the thin film transistor are connected to the light emitting element 80 and the driver element 83, respectively, while the gate is electrically connected to the drive control circuit 73, and supplied from the drive control circuit 73. Based on the potential, the conduction state between the light emitting element 80 and the driver element 83 is controlled.

  The driver element 83 has a function for controlling the current flowing through the light emitting element 80. Specifically, the driver element 83 has a function of controlling a current flowing through the light emitting element 80 in accordance with a potential difference equal to or greater than a threshold value. In the first embodiment, the driver element 83 is formed of an n-type thin film transistor, and controls the light emission luminance of the light emitting element 80 according to the potential difference applied between the gate and the source.

  In such a pixel 58, charges are accumulated in the capacitance 84 by the voltage applied to the signal line by the drive circuit 55. While the drive control circuit 73 applies a voltage to the gate of the transistor 81, a current corresponding to the charge accumulated in the capacitance 84 flows to the light emitting element 80, and the light emitting element 80 emits light.

  As described above, even when each pixel 58 has the light emitting element 80, the scanning line driving circuit 56 includes the shift register unit 25 including the shift register unit 25 and the OUT waveform control unit 26 on two scanning lines. The output signal of each pixel is output. For this reason, the image display device 70 can reduce the circuit scale of the scanning line driving circuit 56 and reduce the frame even when the pixel 58 includes an organic EL panel. Further, since the shift register circuit 20 prevents the potential of the signal output on the scanning line from being lowered, the image display device 70 can be operated normally regardless of the number of pixels on the active area 57.

1 to 14 transistor 20 shift register circuit 21 to 24 node 25 shift register unit 26 OUT waveform control unit

Claims (10)

The gate is connected to the first conductive path, the drain is connected to the second conductive path, and the source is connected to the low potential terminal. A first transistor that lowers the potential of the second conductive path;
In response to an increase in potential of the second conductive path, the gate being connected to the second conductive path, the drain being connected to the first conductive path and the source being connected to the low potential terminal. A second transistor that lowers the potential of the first conductive path;
When the first clock signal is input, the gate is connected to the first conductive path, the drain is connected to the input terminal of the first clock signal, and the source is connected to the third conductive path. A third transistor that increases the potential of the third conductive path in response to an increase in potential of the first conductive path;
A gate connected to the third conductive path; a drain connected to an input terminal for a second clock signal; and a source connected to a first output terminal for outputting a first output signal. A fourth transistor for outputting the second clock signal as a first output signal from the first output terminal in response to an increase in potential of the conductive path of
The third connected to the third conductive path, the drain connected to the third clock signal input terminal, and the source connected to the second output terminal for outputting the second output signal. And a fifth transistor for outputting the third clock signal as a second output signal from the second output terminal in response to an increase in the potential of the conductive path of the shift register circuit. A sixth transistor having a gate connected to the input terminal of the second clock signal and a drain connected to a high-potential device; the sixth transistor raising the potential of the source in response to the input of the second clock signal;
To the input of the fourth clock signal, the gate is connected to the input terminal of the fourth clock signal, the drain is connected to the source of the sixth transistor, and the source is connected to the second conductive path. The shift register circuit according to claim 1, further comprising a seventh transistor that raises the potential of the second conductive path in response. In response to the input of the fourth clock signal, the gate is connected to the input terminal of the fourth clock signal, the drain is connected to the high potential terminal, and the source is connected to the fourth conductive path. An eighth transistor that raises the potential of the four conductive paths;
In response to an increase in potential of the fourth conductive path, the gate being connected to the fourth conductive path, the drain being connected to the third conductive path and the source being connected to the low potential terminal. A ninth transistor for lowering the potential of the third conductive path;
In response to an increase in potential of the third conductive path, the gate being connected to the third conductive path, the drain being connected to the fourth conductive path and the source being connected to the low potential terminal. The shift register circuit according to claim 2, further comprising a tenth transistor that lowers a potential of the fourth conductive path. In response to an increase in potential of the second conductive path having a gate connected to the second conductive path, a drain connected to the first output terminal, and a source connected to a low potential terminal. An eleventh transistor for lowering the potential of the first output terminal;
In response to an increase in potential of the second conductive path, the gate being connected to the second conductive path, the drain being connected to the second output terminal and the source being connected to the low potential terminal. 4. The shift register circuit according to claim 1, further comprising a twelfth transistor that lowers the potential of the second output terminal. 5.   5. The device according to claim 1, further comprising a third output terminal that outputs the potential of the third conductive path to the shift register circuit of the next stage as an input signal instructing start of operation. A shift register circuit according to any one of the above.   The next-stage shift register circuit having a gate connected to an output terminal of a signal output from the next-stage shift register circuit, a drain connected to the first conductive path, and a source connected to a low potential terminal 6. The shift register circuit according to claim 1, further comprising a thirteenth transistor that drops the potential of the first conductive path in accordance with the potential of the signal output from the first register. .   The potential of the first conductive path according to the potential of the input signal, the gate being connected to the input terminal of the input signal, the drain being connected to the high potential terminal and the source being connected to the first conductive path. The shift register circuit according to claim 1, further comprising a fourteenth transistor for raising the voltage.   The third clock signal is a signal obtained by delaying the phase of the second clock signal by a predetermined amount, and the first clock signal has the second clock signal and the third clock signal. The shift register circuit according to any one of claims 1 to 7, wherein the shift register circuit is a signal having a cycle that is twice the cycle. A driver circuit having the shift register circuit according to any one of claims 1 to 8,
An image display apparatus, comprising: a display panel that displays an image, the light emitting element emitting light according to a signal output from the driver circuit. A driver circuit having the shift register circuit according to any one of claims 1 to 8,
An image display device comprising: a liquid crystal panel that displays an image according to a signal output from the driver circuit.

Images