CN113053319A - Pixel driving circuit, driving method thereof and display device - Google Patents

Abstract

The invention relates to the technical field of display, in particular to a pixel driving circuit, a driving method thereof and a display device, which are used for reducing the power consumption of the pixel driving circuit. A pixel drive circuit comprising: an inverter, a driving sub-circuit, and a light emitting device. The inverter is electrically connected with the input signal end, the first node, the first voltage signal end and the second voltage signal end; the driving sub-circuit is electrically connected with the first node, the third voltage signal end and the second node; the light emitting device is electrically connected with the second node and the fourth voltage signal terminal. The pixel driving circuit, the driving method thereof and the display device are used for image display.

Description

Pixel driving circuit, driving method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a pixel driving circuit, a driving method thereof and a display device.

Background

At present, an OLED (Organic Light Emitting Diode) has been widely used due to its advantages of self-luminescence, fast response speed, low power consumption, and the like.

The luminance of the OLED is in direct proportion to the current density, and therefore, the current density generated by the circuit for driving the OLED in the pixel driving circuit is changed. Taking the circuit structure of 7T1C shown in fig. 1 as an example, by controlling the current density flowing through the control transistor M1, the driving transistor M3 and the control transistor M2, the light-emitting brightness of the OLED can be controlled, and the display of different gray scales of the OLED can be realized.

As a self-Light Emitting device, an LED (Light Emitting Diode) is used, and the OLED in the pixel driving circuit may be replaced with an LED in general.

The relationship between the luminous efficiency of an LED and the current density flowing through the LED is shown in fig. 2. As can be seen from fig. 2, the light emission efficiency of the LED is in direct proportion to the current density at low current densities, i.e., current densities of 0 to J1. That is, when the OLED in the pixel driving circuit is replaced with the LED, the light emitting efficiency of the LED is also decreased when the current density is low. In order to improve the light emission efficiency of the LED, it is necessary to increase the current density flowing through the LED, for example, in the range of J1 to J2.

As shown in fig. 1, since a plurality of transistors (i.e., the driving transistor M3, and the control transistor M1 and the control transistor M2) are disposed in the current path of the LED, when the current density is high, the voltage across the control transistor M1 and the control transistor M2 (the total voltage across the control transistor M1 and the control transistor M2 reaches 2V, for example) and the power consumption are also greatly increased, so that the power consumption of the pixel driving circuit is greatly increased.

Disclosure of Invention

Embodiments of the present invention provide a pixel driving circuit, a driving method thereof, and a display device, which are used to reduce power consumption of the pixel driving circuit.

In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:

an embodiment of the present invention provides a pixel driving circuit, including: an inverter, a driving sub-circuit, and a light emitting device. The inverter is electrically connected with the input signal end, the first node, the first voltage signal end and the second voltage signal end; the inverter is configured to transmit a first voltage signal received at the first voltage signal terminal to the first node or transmit a second voltage signal received at the second voltage signal terminal to the first node in response to an input signal transmitted by the input signal terminal to obtain a driving control signal. The driving sub-circuit is electrically connected with the first node, the third voltage signal end and the second node; the driving sub-circuit is configured to transmit a third voltage signal received at the third voltage signal terminal to the second node under control of a driving control signal from the first node. The light emitting device is electrically connected with the second node and the fourth voltage signal end; the light emitting device is configured to emit light under the action of a third voltage signal from the second node and a fourth voltage signal transmitted by the fourth voltage signal terminal.

The pixel driving circuit provided by the embodiment of the invention can adjust the duty ratio of the obtained driving control signal by adjusting the time length ratio of the high-level signal to the low-level signal in the input signal transmitted by the input signal end through arranging the phase inverter, so that the conduction time length of the driving sub-circuit can be controlled, the time length of the driving current transmitted to the light-emitting device can be controlled, and the light-emitting time length of the light-emitting device can be controlled. That is, the pixel driving circuit can adjust the display time period of a display device to which the pixel driving circuit is applied.

In the pixel driving circuit, the third voltage signal terminal, the driving sub-circuit, the light emitting device, and the fourth voltage signal terminal are sequentially disposed in a current path of the driving current, and no other circuit structure is connected between any two adjacent voltage signal terminals. Therefore, the light-emitting device can keep high luminous efficiency, and the power consumption of the pixel driving circuit can be reduced.

In some embodiments, the input signal is a triangular wave signal.

In some embodiments, the inverter comprises: a first transistor and a second transistor; and/or, the driving sub-circuit comprises: a third transistor. The control electrode of the first transistor is electrically connected with the input signal end, the first electrode of the first transistor is electrically connected with the first voltage signal end, and the second electrode of the first transistor is electrically connected with the second electrode of the second transistor and the first node. The control electrode of the second transistor is electrically connected with the input signal end, and the first electrode of the second transistor is electrically connected with the second voltage signal end. A control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the third voltage signal terminal, and a second electrode of the third transistor is electrically connected to the second node.

In some embodiments, one of the first transistor and the second transistor is of the same type as the third transistor. The other of the first transistor and the second transistor is of a type opposite to that of the third transistor.

In some embodiments, the pixel driving circuit further comprises: an input sub-circuit and a switch sub-circuit. The input sub-circuit is electrically connected with the enable signal end, the input signal end and the third node; the input sub-circuit is configured to transmit an input signal received at the input signal terminal to the third node under control of an enable signal from the enable signal terminal. The switch sub-circuit is electrically connected with the scanning signal end, the data signal end, the third node, the first initial voltage signal end and the fourth node; the switching sub-circuit is configured to transmit a data signal received at the data signal terminal to the third node and transmit a first initial voltage signal received at the first initial voltage signal terminal to the fourth node under control of a scan signal from the scan signal terminal; a pressure difference between the third node and the fourth node is constant; the inverter is electrically connected with the fourth node and is electrically connected with the input signal end sequentially through the switch sub-circuit and the input sub-circuit.

In some embodiments, the input sub-circuit comprises: a fourth transistor; the switch sub-circuit comprises: a fifth transistor, a sixth transistor, and a capacitor. The control electrode of the fourth transistor is electrically connected with the enable signal end, the first electrode of the fourth transistor is electrically connected with the input signal end, and the second electrode of the fourth transistor is electrically connected with the third node. A control electrode of the fifth transistor is electrically connected to the scan signal terminal, a first electrode of the fifth transistor is electrically connected to the data signal terminal, and a second electrode of the fifth transistor is electrically connected to the third node. A control electrode of the sixth transistor is electrically connected to the scan signal terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage signal terminal, and a second electrode of the sixth transistor is electrically connected to the fourth node. A first terminal of the capacitor is electrically connected to the third node and a second terminal of the capacitor is electrically connected to the fourth node. Wherein the inverter is electrically connected to the input signal terminal through the capacitor and the fourth transistor in this order.

In some embodiments, the pixel driving circuit further comprises: the circuit comprises a first potential stabilizing sub-circuit, a second potential stabilizing sub-circuit and a reset sub-circuit. The first potential stabilizing sub-circuit is electrically connected with the enabling signal end, the fourth node and the fifth node; the first potential stabilizing sub-circuit is configured to transmit a signal received at the fourth node to the fifth node and stabilize a voltage of the fifth node under control of an enable signal from the enable signal terminal. The second potential stabilizing sub-circuit is electrically connected with the enabling signal end, the sixth node and the first node; the second potential stabilizing sub-circuit is configured to transmit a signal received at the sixth node to the first node and stabilize a voltage of the first node under control of an enable signal from the enable signal terminal. The reset sub-circuit is electrically connected with the reset signal end, the second initial voltage signal end and the first node; the reset sub-circuit is configured to transmit a second initial voltage signal received at the second initial voltage signal terminal to the first node under control of a reset signal from the reset signal terminal. The inverter is electrically connected to the fifth node and is electrically connected to the fourth node through the first potential stabilizing sub-circuit. The inverter is also electrically connected to the sixth node and to the first node through the second potential stabilization subcircuit.

In some embodiments, the first potential stabilizing sub-circuit includes: a seventh transistor; the second potential stabilizing sub-circuit includes: an eighth transistor; the reset sub-circuit includes: and a ninth transistor. A control electrode of the seventh transistor is electrically connected to the enable signal terminal, a first electrode of the seventh transistor is electrically connected to the fourth node, and a second electrode of the seventh transistor is electrically connected to the fifth node. A control electrode of the eighth transistor is electrically connected to the enable signal terminal, a first electrode of the eighth transistor is electrically connected to the sixth node, and a second electrode of the eighth transistor is electrically connected to the first node. A control electrode of the ninth transistor is electrically connected to the reset signal terminal, a first electrode of the ninth transistor is electrically connected to the second initial voltage signal terminal, and a second electrode of the ninth transistor is electrically connected to the first node. The inverter is electrically connected to the fourth node through the seventh transistor. The inverter is also electrically connected to the first node through the eighth transistor.

Some embodiments of the present invention also provide a driving method of a pixel driving circuit, for driving the pixel driving circuit as described in any one of the above embodiments; the driving method includes: in response to an input signal received at an input signal terminal, an inverter is turned on, and a first voltage signal received at a first voltage signal terminal is transmitted to the first node or a second voltage signal received at a second voltage signal terminal is transmitted to the first node to obtain a driving control signal; in response to a driving control signal from the first node, the driving sub-circuit is turned on, and a third voltage signal received at a third voltage signal terminal is transmitted to the second node; the light emitting device emits light in response to a third voltage signal from the second node and a fourth voltage signal received at a fourth voltage signal terminal.

The advantageous effects that can be achieved by the driving method of the pixel driving circuit provided in some embodiments of the present invention are the same as those that can be achieved by the pixel driving circuit provided in some embodiments described above, and are not described here again.

Some embodiments of the present invention also provide a display device, including: a plurality of pixel drive circuits as described in any one of the embodiments above.

The advantageous effects that can be achieved by the display device provided in some embodiments of the present invention are the same as those that can be achieved by the pixel driving circuit provided in some embodiments described above, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

Fig. 1 is a block diagram of a pixel driving circuit in the prior art;

FIG. 2 is a graph of the relationship between current density and luminous efficiency of a prior art LED;

fig. 3 is a structural diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 4 is a circuit diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 5 is a structural diagram of another pixel driving circuit according to an embodiment of the invention;

FIG. 6 is a circuit diagram of another pixel driving circuit according to an embodiment of the present invention;

fig. 7 is a structural diagram of another pixel driving circuit according to an embodiment of the invention;

fig. 8 is a circuit diagram of another pixel driving circuit according to an embodiment of the invention;

FIG. 9 is a timing diagram of input signals according to an embodiment of the present invention;

FIG. 10 is a timing diagram of the sum of a first initialization voltage signal and an input signal provided by an embodiment of the present invention;

fig. 11 is a timing diagram of a fifth node and a sixth node according to an embodiment of the present invention;

FIG. 12 is a timing control diagram corresponding to the pixel driving circuit shown in FIG. 8 according to an embodiment of the present invention;

fig. 13 is a structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "an example" or "some examples" or the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

As used herein, the term "if" is optionally to be interpreted to mean "when … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined … …" or "if [ stated condition or event ] is detected" is optionally to be construed to mean "upon determination … …" or "in response to determination … …" or "upon detection of [ stated condition or event ] or" in response to detection of [ stated condition or event ] ", depending on the context.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about" or "approximately" includes the stated values as well as average values within an acceptable deviation range for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

The transistors used in the circuit provided in the embodiments of the present invention may be thin film transistors, field effect transistors (e.g., oxide thin film transistors), or other switching devices with the same characteristics, and the thin film transistors are all taken as examples in the embodiments of the present invention for description.

In some embodiments, the control electrode of each transistor employed by the pixel driving circuit is a gate electrode of the transistor, the first electrode is one of a source electrode and a drain electrode of the transistor, and the second electrode is the other of the source electrode and the drain electrode of the transistor. Since the source and the drain of the transistor may be symmetrical in structure, the source and the drain may not be different in structure, that is, the first and the second poles of the transistor in the embodiment of the present invention may not be different in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

In the circuit provided by the embodiment of the present invention, the nodes such as the first node and the second node do not represent actual components, but represent junctions of relevant electrical connections in the circuit diagram, that is, the nodes are equivalent nodes of the junctions of relevant electrical connections in the circuit diagram.

An embodiment of the present invention provides a pixel driving circuit 100, as shown in fig. 3, the pixel driving circuit 100 includes: an inverter 10, a driving sub-circuit 20, and a light emitting device 30.

In some embodiments, as shown in fig. 3 and 4, the inverter 10 is electrically connected to the Input signal terminal Input, the first node N1, the first voltage signal terminal VDD, and the second voltage signal terminal VSS. The inverter 10 is configured to transmit a first voltage signal received at a first voltage signal terminal VDD to the first node N1 or transmit a second voltage signal received at a second voltage signal terminal VSS to the first node N1 in response to an Input signal transmitted by an Input signal terminal Input to obtain a driving control signal.

It should be noted that the first voltage signal terminal VDD is configured to transmit a dc high level signal, and the second voltage signal terminal VSS is configured to transmit a dc low level signal. The voltage value of the first voltage signal is larger than that of the second voltage signal. The voltage value of the first voltage signal is, for example, greater than 0V, and the voltage value of the second voltage signal is, for example, less than 0V.

For example, in the case that the level of the input signal is high level, the inverter 10 may be turned on under the control of the input signal, and transmit the first voltage signal to the first node N1, so as to obtain a dc high level signal as a part of the driving control signal. In the case where the level of the input signal is low, the inverter 10 may be turned on under the control of the input signal, and transmit the second voltage signal to the first node N1, so as to obtain a dc low level signal as another part of the driving control signal.

That is, the driving control signal is composed of a first voltage signal and a second voltage signal, and the driving control signal may be a stable square wave signal (which may also be referred to as a clock signal).

It should be noted that the above "high level" and "low level" are relative terms. Both of which may have a voltage value greater than 0V, or both may have a voltage value less than 0V. For example, the high level voltage value is 10V, and the low level voltage value is 3V.

By providing the inverter 10 and electrically connecting the inverter 10 to the Input signal terminal Input, the first voltage signal terminal VDD, and the second voltage signal terminal VSS, the inverter 10 can be turned on and output the driving control signal no matter whether the level of the Input signal is high level or low level. Moreover, by adjusting the duty ratio of the time duration of the high-level signal and the low-level signal in the input signal, the duty ratio of the time duration of the first voltage signal that is output by the inverter 10 and the time duration of the second voltage signal that is output by the inverter 10 can be adjusted, and further the duty ratio of the time duration of the first voltage signal and the second voltage signal in the obtained driving control signal, that is, the duty ratio of the driving control signal can be adjusted.

In some embodiments, as shown in fig. 3 and 4, the driving sub-circuit 20 is electrically connected to the first node N1, the third voltage signal terminal VDD', and the second node N2. The driving sub-circuit 20 is configured to transmit the third voltage signal received at the third voltage signal terminal VDD' to the second node N2 under the control of the driving control signal from the first node N1.

For example, in a case where the level of the driving control signal is a high level, the driving sub-circuit 20 may be turned on under the control of the driving control signal, and transmit the third voltage signal to the second node N2. In the case where the level of the above-described drive control signal is low level, the drive sub-circuit 20 may be turned off under the control of the drive control signal.

It should be noted that the third voltage signal terminal VDD' is configured to transmit a dc high-level signal. The voltage value of the third voltage signal is, for example, greater than 0V. The voltage value of the third voltage signal may be equal to or different from the voltage value of the first voltage signal.

For example, the electrical connection between the third voltage signal terminal VDD' and the driving sub-circuit 20 is a direct electrical connection, the electrical connection between the driving sub-circuit 20 and the second node N2 is also a direct electrical connection, and no other circuit structure is connected between the above components. With the drive sub-circuit 20 turned on, the third voltage signal may be directly transmitted to the second node N2 through the drive sub-circuit 20.

In some embodiments, as shown in fig. 3 and 4, the light emitting device 30 is electrically connected to the second node N2 and the fourth voltage signal terminal VSS'. The light emitting device 30 is configured to emit light by the third voltage signal from the second node N2 and the fourth voltage signal transmitted from the fourth voltage signal terminal VSS'.

The type of the light emitting device 30 in the present invention includes various types, and the arrangement may be selected according to actual needs. Illustratively, the light emitting device 30 may be an LED. The LED may be, for example, a Micro LED (Micro Light Emitting Diode) or a Mini LED (Mini Light Emitting Diode).

It should be noted that the fourth voltage signal terminal VSS' is configured to transmit a dc low-level signal. And the voltage value of the fourth voltage signal is smaller than that of the third voltage signal. The voltage value of the fourth voltage signal is, for example, less than 0V. The voltage value of the fourth voltage signal may be equal to or different from the voltage value of the second voltage signal.

For example, when the driving sub-circuit 20 is turned on, a voltage difference is formed between the third voltage signal transmitted by the third voltage signal terminal VDD 'and the fourth voltage signal transmitted by the fourth voltage signal terminal VSS', and a current path may be formed between the third voltage signal terminal VDD 'and the fourth voltage signal terminal VSS', so as to generate a driving current with a higher current density. The higher current density of the driving current enables the light emitting device 30 to emit light, and enables the light emitting device 30 to have higher luminous efficiency.

For example, the electrical connection between the second node N2 and the light emitting device 30 is a direct electrical connection, and no other circuit structure is connected therebetween. That is, no other circuit structure is connected between the driving sub-circuit 20 and the light emitting device 30.

Since no other circuit structure is connected between the third voltage signal terminal VDD 'and the driving sub-circuit 20, and no other circuit structure is connected between the driving sub-circuit 20 and the light emitting device 30, it is possible to avoid the cross voltage between the third voltage signal terminal VDD' and the driving sub-circuit 20 and between the driving sub-circuit 20 and the light emitting device 30, and further, it is possible to reduce the power consumption of the pixel driving circuit 100 while maintaining the high light emitting efficiency of the light emitting device 30.

Therefore, by providing the inverter 10, the pixel driving circuit 100 provided in the embodiment of the present invention can adjust the duty ratio of the obtained driving control signal by adjusting the time length ratio of the high level signal and the low level signal in the Input signal transmitted by the Input signal terminal Input, and further can control the time length of the conduction of the driving sub-circuit 20, and control the time length of the driving current transmitted to the light emitting device 30, thereby controlling the light emitting time length of the light emitting device 30. That is, the pixel driving circuit 100 can adjust the display time period of a display device to which the pixel driving circuit 100 is applied.

In the pixel driving circuit 100, the third voltage signal terminal VDD ', the driving sub-circuit 20, the light emitting device 30, and the fourth voltage signal terminal VSS' are sequentially disposed in a current path of the driving current, and any adjacent two are not connected to another circuit structure, so that a voltage across the current path can be prevented from being generated during the light emission of the light emitting device 30 driven by the driving current, and the driving current can have a high circuit density. This can maintain high light emitting efficiency of the light emitting device 30 and reduce power consumption of the pixel driving circuit 100.

In some embodiments, the Input signal transmitted by the Input signal terminal is a triangular wave signal.

The types of the triangular wave signals in the invention comprise various types, and the triangular wave signals can be selected and arranged according to actual needs. For example, the triangular wave signal may be a ramp signal or a sawtooth signal.

The operation of the inverter 10 will be schematically described below by taking a sawtooth wave signal as shown in fig. 11 (a) as an example. The part of the sawtooth wave signal above the X axis is, for example, a high level signal, and the part of the sawtooth wave signal below the X axis is, for example, a low level signal.

For example, as shown in fig. 11, when the level of the sawtooth wave signal is high, the inverter 10 may be turned on under the control of the sawtooth wave signal to output the second voltage signal. When the level of the sawtooth wave signal is low, the inverter 10 may be turned on under the control of the sawtooth wave signal to output the first voltage signal. The first voltage signal and the second voltage signal constitute a drive control signal.

Here, it can be approximately understood that the inverter 10 is provided to convert the input sawtooth wave signal into a drive control signal composed of a first voltage signal and a second voltage signal. The voltage value of the sawtooth wave signal changes along with the change of time, for example, the voltage value increases or decreases along with the increase of time; the driving control signal is a clock signal, and the voltage value is kept constant or basically constant in the corresponding time period.

Thus, the driving sub-circuit 20 can be turned on more stably under the control of the driving control signal, and the third voltage signal can be output to the light emitting device 30 more stably, so that the light emitting device 30 can emit light more stably, and the stability of light emission of the light emitting device 30 is improved. Moreover, by adjusting the duty ratio of the high level signal and the low level signal in the sawtooth wave signal, the duty ratio of the driving control signal can be adjusted, and thus the light emitting duration of the light emitting device 30 can be adjusted.

The following schematically describes the structures of the inverter 10 and the driving sub-circuit 20 included in the pixel driving circuit 100.

In some embodiments, inverter 10 comprises: a first transistor T1 and a second transistor T2; and/or, the driving sub-circuit 20 comprises: a third transistor T3.

Illustratively, the above embodiments include the following three cases: the inverter 10 includes a first transistor T1 and a second transistor T2; the driving sub-circuit 20 includes a third transistor T3; the inverter 10 includes a first transistor T1 and a second transistor T2, and the driving sub-circuit 20 includes a third transistor T3. The present invention is described in detail by taking an example in which the inverter 10 includes the first transistor T1 and the second transistor T2, and the driving sub-circuit 20 includes the third transistor T3.

The types of transistors included in the inverter 10 and the driving sub-circuit 20 in the present invention include various types, and can be selectively set according to actual needs.

In some examples, one of the first transistor T1 and the second transistor T2 is of the same type as the third transistor T3; the other of the first transistor T1 and the second transistor T2 is of the opposite type to the third transistor T3. That is, the first transistor T1 and the second transistor T2 are provided as two transistors of opposite types.

Illustratively, the first transistor T1 is an N-type transistor, the second transistor T2 is a P-type transistor, and the third transistor T3 is an N-type transistor or a P-type transistor.

Illustratively, the first transistor T1 is a P-type transistor, the second transistor T2 is an N-type transistor, and the third transistor T3 is an N-type transistor or a P-type transistor.

The first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors, N-type transistors, and N-type transistors, respectively, as an example, which will be described in detail below.

For example, as shown in fig. 4, a control electrode of the first transistor T1 is electrically connected to the Input signal terminal Input, a first electrode of the first transistor T1 is electrically connected to the first voltage signal terminal VDD, and a second electrode of the first transistor T1 is electrically connected to a second electrode of the second transistor T2 and the first node N1. A control electrode of the second transistor T2 is electrically connected to the Input signal terminal Input, and a first electrode of the second transistor T2 is electrically connected to the second voltage signal terminal VSS.

For example, in the case where the level of the input signal is a low level, the first transistor T1 may be turned on under the control of the input signal, and transmit the first voltage signal to the first node N1 to obtain a part of the driving control signal. In case that the level of the input signal is a high level, the second transistor T2 may be turned on under the control of the input signal, and transmit the second voltage signal to the first node N1 to obtain another portion of the driving control signal.

By providing the first transistor T1 and the second transistor T2 in the inverter 10, it can be realized that the inverter 10 can output a drive control signal regardless of whether the level of an input signal is a high level or a low level. Moreover, by adjusting the duty ratio of the time duration of the high-level signal and the low-level signal in the input signal, the duty ratio of the time duration of the turn-on of the first transistor T1 and the turn-on of the second transistor T2 can be adjusted, and further, the duty ratio of the time duration of the first voltage signal and the second voltage signal in the obtained driving control signal, that is, the duty ratio of the driving control signal is adjusted.

Illustratively, as shown in fig. 4, a control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the third voltage signal terminal VDD', and a second electrode of the third transistor T3 is electrically connected to the second node N2.

For example, in a case where the level of the driving control signal from the first node N1 is a high level, the third transistor T3 may be turned on under the control of the driving control signal, transmit the third voltage signal to the second node N2, and generate a driving current to drive the light emitting device 30 to emit light by a voltage difference between the third voltage signal and the fourth voltage signal.

By adjusting the duty ratio of the driving control signal, the turn-on duration of the third transistor T3 can be controlled, thereby controlling the duration of the driving current flowing through the light emitting device 30, and thus controlling the light emitting duration of the light emitting device 30.

In some embodiments, as shown in fig. 5 and 6, the pixel driving circuit 100 further includes: an input sub-circuit 40 and a switch sub-circuit 50.

In some examples, as shown in fig. 5 and 6, the Input sub-circuit 40 is electrically connected to the enable signal terminal EM, the Input signal terminal Input, and the third node N3. The Input sub-circuit 40 is configured to transmit an Input signal received at the Input signal terminal Input to the third node N3 under control of an enable signal from the enable signal terminal EM.

For example, in the case that the level of the enable signal is high level, the input sub-circuit 40 may be turned on under the control of the enable signal, and transmit the input signal to the third node N3.

By providing the input sub-circuit 40, the input time of the input signal can be controlled in the respective operating phase.

In some examples, as shown in fig. 5 and 6, the switch sub-circuit 50 is electrically connected to the scan signal terminal Gate, the data signal terminal Date, the third node N3, the first initial voltage signal terminal Vin1, and the fourth node N4. The switching sub-circuit 50 is configured to transmit a data signal received at the data signal terminal Date to the third node N3 and transmit a first initial voltage signal received at the first initial voltage signal terminal Vin1 to the fourth node N4 under the control of a scan signal from the scan signal terminal Gate. The pressure difference between the third node N3 and the fourth node N4 is constant.

It should be noted that the first initial voltage signal terminal Vin1 is configured to transmit a dc high-level signal. The voltage value of the first initial voltage signal terminal Vin1 is greater than 0V, for example.

For example, in a case where the level of the scan signal is a high level, the switch sub-circuit 50 may be turned on under the control of the scan signal, transmit the data signal to the third node N3, and transmit the first initial voltage signal to the fourth node N4. This may form a voltage difference between the third node N3 and the fourth node N4, which is a difference between the voltage value of the first initial voltage signal and the voltage value of the data signal.

Since the voltage difference between the third node N3 and the fourth node N4 is constant, the voltage of the fourth node N4 changes when the voltage of the third node N3 changes, and the voltage of the third node N3 and the voltage of the fourth node N4 change by the same amount.

For example, in the case where the voltage value of the third node N3 is increased by 10V, the voltage value of the fourth node N4 is also increased by 10V.

For example, the switch sub-circuit 50 may change the voltage at the fourth node N4 from the sawtooth signal shown in fig. 10 to the sawtooth signal shown in (a) of fig. 11. The part of the sawtooth wave signal above the X axis is, for example, a high level signal, and the part of the sawtooth wave signal below the X axis is, for example, a low level signal.

By providing the switch sub-circuit 50, the voltage of the signal at the third node N3 can be adjusted, and the voltage of the signal at the fourth node N4 can be adjusted accordingly. In this way, the switch sub-circuit 50 can be used to adjust the input signal, i.e. to adjust the time ratio of the high-level signal to the low-level signal in the input signal.

In some examples, as shown in fig. 5 and 6, the inverter 10 is electrically connected to the fourth node N4, and is electrically connected to the Input signal terminal Input through the switch sub-circuit 50 and the Input sub-circuit 40 in sequence. That is, the inverter 10 is indirectly electrically connected to the Input signal terminal Input through the switch sub-circuit 50 and the Input sub-circuit 40, and the Input signal is adjusted by the switch sub-circuit 50 and then transmitted to the inverter 10.

By setting the switch sub-circuit 50, the voltage of the signal received by the inverter 10 (i.e. the input signal adjusted by the switch sub-circuit 50) and the time length ratio of the high level signal to the low level signal can be adjusted, so as to adjust the duty ratio of the driving control signal output by the inverter 10, adjust the on-time length of the driving sub-circuit 20, and control the light emitting time length of the light emitting device 30.

The following schematically describes the structures of the input sub-circuit 40 and the switch sub-circuit 50 included in the pixel driving circuit 100.

In some examples, the input sub-circuit 40 includes: and a fourth transistor T4. The switch sub-circuit 50 includes: a fifth transistor T5, a sixth transistor T6, and a capacitor C.

The types of transistors included in the input sub-circuit 40 and the switch sub-circuit 50 in the present invention include various types, and can be selectively set according to actual needs. Each of the above-described fourth transistor T4, fifth transistor T5, and sixth transistor T6 may be an N-type transistor or a P-type transistor.

The fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type transistors, which will be described in detail below.

Illustratively, as shown in fig. 6, a control electrode of the fourth transistor T4 is electrically connected to the enable signal terminal EM, a first electrode of the fourth transistor T4 is electrically connected to the Input signal terminal Input, and a second electrode of the fourth transistor T4 is electrically connected to the third node N3.

For example, in a case where the level of the enable signal is a high level, the fourth transistor T4 may be turned on under the control of the enable signal, transmitting the input signal to the third node N3.

By controlling the time when the fourth transistor T4 is turned on, the input time of the input signal can be controlled in the corresponding operation phase.

Illustratively, as shown in fig. 6, a control electrode of the fifth transistor T5 is electrically connected to the scan signal terminal Gate, a first electrode of the fifth transistor T5 is electrically connected to the data signal terminal Date, and a second electrode of the fifth transistor T5 is electrically connected to the third node N3.

For example, in case that the level of the scan signal is a high level, the fifth transistor T5 may be turned on under the control of the scan signal, transmitting the data signal to the third node N3.

Illustratively, as shown in fig. 6, a control electrode of the sixth transistor T6 is electrically connected to the scan signal terminal Gate, a first electrode of the sixth transistor T6 is electrically connected to the first initial voltage signal terminal Vin1, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

For example, in case that the level of the scan signal is a high level, the sixth transistor T6 may be turned on under the control of the scan signal, transmitting the first initial voltage signal to the fourth node N4.

Illustratively, as shown in fig. 6, a first terminal of the capacitor C is electrically connected to the third node N3, and a second terminal of the capacitor C is electrically connected to the fourth node N4.

Since the control electrode of the fifth transistor T5 and the control electrode of the sixth transistor T6 are both electrically connected to the scan signal terminal Gate, when the level of the scan signal is high, the fifth transistor T5 and the sixth transistor T6 may be turned on at the same time to charge both ends of the capacitor C, respectively, so that the potential of the first end of the capacitor C (corresponding to the third node N3) is Vdate, and the potential of the second end of the capacitor C (corresponding to the fourth node N4) is Vin 1. The voltage difference across capacitor C is the difference between Vin1 and Vdate.

The voltage difference between the third node N3 and the fourth node N4 can be kept constant due to the bootstrap effect of the capacitor C. That is, the voltage of the fourth node N4 varies with the voltage of the third node N3.

Illustratively, as shown in fig. 6, the inverter 10 is electrically connected to the Input signal terminal Input through the capacitor C and the fourth transistor T4 in this order. That is, the signal received by the inverter 10 is an input signal sequentially acted by the fourth transistor T4 and the capacitor C.

For example, the fifth transistor T5 and the sixth transistor T6 are turned on earlier than the fourth transistor T4. In the case where the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on, the potential of the third node N3 is Vdate, the potential of the fourth node N4 is Vin1, and the voltage difference between the fourth node N4 and the third node N3 is Vin 1-Vdate. When the fourth transistor T4 is turned on, the potential of the third node N3 becomes Vinput. Since the potential before the third node N3 is Vdate, the variation of the potential of the third node N3 at this time is Vinput-Vdate. The potential of the fourth node N4 should also vary by Vinput-Vdate according to the bootstrap effect of the capacitor C, and since the potential before the fourth node N4 is Vin1, the potential of the fourth node N4 becomes Vin1+ Vinput-Vdate.

Illustratively, the input signal is a triangular wave signal, the timing diagram of which is shown in fig. 9. The timing diagram of Vin1+ Vinput is shown in fig. 10, which is ideally located above the X-axis. The timing diagram of Vin1+ Vinput-Vdate is shown in fig. 11 (a), where the part above the X-axis is a high-level signal, for example, and the part below the X-axis is a low-level signal, for example.

Illustratively, as shown in fig. 11, it can be approximately understood that the inverter 10 can convert an input sawtooth wave signal (a signal corresponding to the fifth node N5) into a drive control signal (a signal corresponding to the sixth node N6) composed of VDD 'and VSS'. Wherein, the voltage value (Vin1+ Vinput-Vdate) of the sawtooth wave signal changes along with the change of time, for example, the voltage value increases or decreases along with the increase of time; the driving control signal is a clock signal whose timing chart is shown in fig. 11 (B), and the voltage value is kept constant or substantially constant in the corresponding period.

Wherein, the magnitude of Vin1 and Vinput in Vin1+ Vinput-Vdate is basically unchanged, and the magnitude of Vdate can be adjusted. Therefore, as shown in fig. 11 (a), the magnitude of the potential Vin1+ Vinput-Vdate is determined by Vdata, and the larger the value of Vdata, the more the Vin1+ Vinput-Vdate is located below the X axis, and the smaller the Vin1+ Vinput-Vdate is located above the X axis.

Therefore, by controlling the value of Vdata, the value of Vin1+ Vinput-Vdate above and below the X-axis can be controlled, and the time length ratio of the high-level signal and the low-level signal in Vin1+ Vinput-Vdate (i.e. the input signal adjusted by the switch sub-circuit 50) can be controlled. This allows the duty ratio of the driving control signal to be adjusted to control the on-time ratio of the driving sub-circuit 20, thereby controlling the light emitting time of the light emitting device 30.

In some embodiments, as shown in fig. 7 and 8, the pixel driving circuit 100 further includes: a first potential stabilizing sub-circuit 60, a second potential stabilizing sub-circuit 70, and a reset sub-circuit 80.

In some examples, as shown in fig. 7 and 8, the first potential stabilizing sub-circuit 60 is electrically connected to the enable signal terminal EM, the fourth node N4, and the fifth node N5. The first potential stabilizing sub-circuit 60 is configured to transmit a signal received at the fourth node N4 to the fifth node N5 and stabilize the voltage of the fifth node N5 under the control of an enable signal from the enable signal terminal EM.

For example, in a case where the level of the enable signal is a high level, the first potential stabilizing sub-circuit 60 may be turned on under the control of the enable signal, transmit the signal received at the fourth node N4 to the fifth node N5, and make the signal transmitted to the fifth node N5 stable.

In some examples, as shown in fig. 7 and 8, the second potential stabilizing sub-circuit 70 is electrically connected to the enable signal terminal EM, the sixth node N6, and the first node N1. The second potential stabilizing sub-circuit 70 is configured to transmit a signal received at the sixth node N6 to the first node N1 and stabilize the voltage of the first node N1 under the control of an enable signal from the enable signal terminal EM.

For example, in a case where the level of the enable signal is a high level, the second potential stabilizing sub-circuit 70 may be turned on under the control of the enable signal, transmit the signal received at the sixth node N6 to the first node N1, and make the signal transmitted to the first node N1 more stable.

By providing the first potential stabilizing sub-circuit 60 and the second potential stabilizing sub-circuit 70, the signal received at the fourth node N4 can be stably transmitted to the fifth node N5, the signal received at the sixth node N6 can be stably transmitted to the first node N1, and the stability of the voltages at the fifth node N5 and the first node N1 can be ensured.

In some examples, as shown in fig. 7 and 8, the Reset sub-circuit 80 is electrically connected to the Reset signal terminal Reset, the second initial voltage signal terminal Vin2, and the first node N1. The Reset sub-circuit 80 is configured to transmit the second initial voltage signal received at the second initial voltage signal terminal Vin2 to the first node N1 under the control of a Reset signal from the Reset signal terminal Reset.

For example, in a case where the level of the reset signal is a high level, the reset sub-circuit 80 may be turned on under the control of the reset signal, transmit the second initial voltage signal to the first node N1, and reset the first node N1.

It should be noted that the second initial voltage signal terminal Vin2 is configured to transmit a dc low-level signal. And the voltage value of the second initial voltage signal is smaller than that of the first initial voltage signal. The voltage value of the second initial voltage signal terminal Vin2 is less than 0V, for example.

Through setting up the sub-circuit 80 that resets, can transmit second initial voltage signal to first node N1, reset first node N1, and then reset drive sub-circuit 20, be favorable to deleting the remaining signal of telecommunication in the last frame image display to can make drive sub-circuit 20 keep the off-state, avoid the mistake to open.

In some examples, as shown in fig. 7 and 8, the inverter 10 is electrically connected to the fifth node N5, and is electrically connected to the fourth node N4 through the first potential stabilizing sub-circuit 60. That is, the inverter 10 is indirectly electrically connected to the switch sub-circuit 50 through the first potential stabilizing sub-circuit 60. The input signal received by the inverter 10 and adjusted by the switching sub-circuit 50 can be a more stable signal.

In some examples, as shown in fig. 7 and 8, the inverter 10 is also electrically connected to the sixth node N6, and is electrically connected to the first node N1 through the second potential stabilizing sub-circuit 70. That is, the inverter 10 is indirectly electrically connected to the driving sub-circuit 20 through the second potential stabilizing sub-circuit 70. The signal received by the driving sub-circuit 20 via the second potential stabilizing sub-circuit 70 may be a more stable signal.

The following schematically describes the configurations of the first potential stabilizing sub-circuit 60, the second potential stabilizing sub-circuit 70, and the reset sub-circuit 80 included in the pixel driving circuit 100.

In some examples, the first potential stabilizing sub-circuit 60 includes: and a seventh transistor T7. The second potential stabilizing sub-circuit 70 includes: and an eighth transistor T8. The reset sub-circuit 80 includes: and a ninth transistor T9.

The types of transistors included in the first potential stabilizing sub-circuit 60, the second potential stabilizing sub-circuit 70, and the reset sub-circuit 80 in the present invention include various types, and can be selectively set according to actual needs. Each of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 described above may be an N-type transistor or a P-type transistor.

The seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all N-type transistors, which will be described in detail below.

Illustratively, as shown in fig. 8, a control electrode of the seventh transistor T7 is electrically connected to the enable signal terminal EM, a first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and a second electrode of the seventh transistor T7 is electrically connected to the fifth node N5.

For example, in the case where the level of the enable signal is a high level, the seventh transistor T7 may be turned on under the control of the enable signal, transmit the signal received at the fourth node N4 to the fifth node N5, and stabilize the signal.

Illustratively, as shown in fig. 8, a control electrode of the eighth transistor T8 is electrically connected to the enable signal terminal EM, a first electrode of the eighth transistor T8 is electrically connected to the sixth node N6, and a second electrode of the eighth transistor T8 is electrically connected to the first node N1.

For example, in the case where the level of the enable signal is a high level, the eighth transistor T8 may be turned on under the control of the enable signal, transmit the signal received at the sixth node N6 to the first node N1, and stabilize the signal.

Illustratively, as shown in fig. 8, a control electrode of the ninth transistor T9 is electrically connected to the Reset signal terminal Reset, a first electrode of the ninth transistor T9 is electrically connected to the second initial voltage signal terminal Vin2, and a second electrode of the ninth transistor T9 is electrically connected to the first node N1.

For example, in the case where the level of the reset signal is a high level, the ninth transistor T9 may be turned on under the control of the reset signal to transmit the second initial voltage signal to the first node N1 for resetting the first node N1.

Illustratively, as shown in fig. 8, the inverter 10 is electrically connected to the fourth node N4 through a seventh transistor T7. That is, the signal received by the inverter 10 is an input signal sequentially passing through the fourth transistor T4, the capacitor C, and the seventh transistor T7.

Illustratively, as shown in fig. 8, the inverter 10 is also electrically connected to the first node N1 through an eighth transistor T8. That is, the driving control signal received by the driving sub-circuit 20 is the driving control signal acted by the eighth transistor T8.

The pixel driving circuit 100 as described above and the prior art as shown in fig. 1 are provided with two scanning signal terminals Gate and one data signal terminal Date. That is, the present invention does not need to add an additional scan signal terminal Gate and a data signal terminal Date, so that the structure of the pixel driving circuit 100 is simple, and the manufacturing cost of the pixel driving circuit 100 is reduced.

The embodiment of the present invention further provides a driving method of the pixel driving circuit 100, which is used for driving the pixel driving circuit 100 according to any one of the above embodiments.

Taking the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 as N-type transistors, taking the first transistor T1 as a P-type transistor as an example, and taking the pixel driving circuit 100 shown in fig. 8 as an example in combination with the timing diagram of each signal terminal shown in fig. 12, the operation process of the pixel driving circuit 100 in one frame of image will be described in detail

Wherein, an image frame includes a first stage t1, a second stage t2 and a third stage t 3; in an image frame, the driving method includes:

in the first phase T1, in response to the Reset signal received at the Reset signal terminal Reset, the Reset sub-circuit 80 is turned on, the ninth transistor T9 is turned on, the second initial voltage signal received at the second initial voltage signal terminal Vin2 is transmitted to the first node N1, and the first node N1 is Reset. Meanwhile, the second initial voltage signal is transmitted to the gate of the third transistor T3 through the first node N1, and the third transistor T3 is turned off, so that the third transistor T3 is guaranteed to be turned off at a corresponding stage.

In the second stage T2, in response to the scan signal received at the scan signal terminal Gate, the switch sub-circuit 50 is turned on, the fifth transistor T5 and the sixth transistor T6 are both turned on, the fifth transistor T5 transmits the data signal received at the data signal terminal Date to the third node N3, and the sixth transistor T6 transmits the first initial voltage signal received at the first initial voltage signal terminal Vin1 to the fourth node N4.

At this time, both ends of the capacitor C are charged, respectively, the potential of the third node N3 is Vdata, and the potential of the fourth node N4 is Vin1, thereby completing data writing.

A third stage T3 in which the Input sub-circuit 40 is turned on in response to the enable signal received at the enable signal terminal EM, the fourth transistor T4 is turned on, and the Input signal received at the Input signal terminal Input is transmitted to the third node N3; the potential of the third node N3 becomes Vinput. Since the potential before the third node N3 is Vdate, the variation of the potential of the third node N3 at this time is Vinput-Vdate; the potential of the fourth node N4 should also vary by Vinput-Vdate according to the bootstrap effect of the capacitor C, and since the potential before the fourth node N4 is Vin1, the potential of the fourth node N4 becomes Vin1+ Vinput-Vdate.

In response to the enable signal received at the enable signal terminal EM, the first potential stabilizing sub-circuit 60 is turned on, the seventh transistor T7 is turned on, transmits the signal received at the fourth node N4 to the fifth node N5, and stabilizes the voltage of the fifth node N5; that is, the seventh transistor T7 transmits the potential of Vin1+ Vinput-Vdate of the fourth node N4 to the fifth node N5, and the potential of the fifth node N5 is Vin1+ Vinput-Vdate.

In response to the Input signal received at the Input signal terminal Input, i.e., the signal of the fifth node N5, the inverter 10 is turned on, the first transistor T1 or the second transistor T2 is turned on, the first transistor T1 transmits the first voltage signal received at the first voltage signal terminal VDD to the sixth node N6, or the second transistor T2 transmits the second voltage signal received at the second voltage signal terminal VSS to the sixth node N6 to derive the driving control signal.

In response to the enable signal received at the enable signal terminal EM, the second potential stabilizing sub-circuit 70 is turned on, the eighth transistor T8 is turned on, transmits the signal received at the sixth node N6 to the first node N1, and stabilizes the voltage of the first node N1; that is, the eighth transistor T8 transmits the driving control signal of the sixth node N6 to the first node N1.

In response to the driving control signal from the first node N1, the driving sub-circuit 20 is turned on, the third transistor T3 is turned on, and the third voltage signal received at the third voltage signal terminal VDD' is transmitted to the second node N2.

The light emitting device 30 emits light in response to the third voltage signal from the second node N2 and the fourth voltage signal received at the fourth voltage signal terminal VSS ', i.e., a current path is formed between the third voltage signal terminal VDD ' and the fourth voltage signal terminal VSS '.

The advantageous effects that can be achieved by the driving method of the pixel driving circuit 100 provided in some embodiments of the present invention are the same as those that can be achieved by the pixel driving circuit 100 provided in some embodiments described above, and are not described herein again.

An embodiment of the present invention further provides a display device 1000, as shown in fig. 13, the display device 1000 includes: a plurality of pixel drive circuits 100 as described in any of the embodiments above.

In some embodiments, as shown in fig. 13, the display device 1000 further includes: a substrate 200. The pixel driving circuits 100 are disposed on the substrate 200.

The pixel driving circuits 100 are arranged in a matrix on the substrate 200 in this embodiment.

Based on this, for example, as shown in fig. 13, the display device 1000 may further include a plurality of gate lines GL and a plurality of data lines DL disposed at one side of the substrate. The gate lines GL extend along, for example, the horizontal direction X axis, and the data lines DL extend along, for example, the vertical direction Y axis. The pixel driving circuits 100 in the same row may be connected to a gate line GL, and the pixel driving circuits 100 in the same column may be connected to a data line DL.

It should be noted that the specific form of the display device 1000 is not limited in the embodiments of the present invention, and the display device 1000 includes various forms, such as a mobile phone, a tablet computer, a notebook, a Personal Digital Assistant (PDA), a vehicle-mounted computer, and the like.

The advantageous effects that can be achieved by the display device 1000 according to some embodiments of the present invention are the same as those that can be achieved by the pixel driving circuit 100 according to some embodiments, and are not described herein again.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art will appreciate that changes or substitutions within the technical scope of the present disclosure are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A pixel driving circuit, comprising:

the inverter is electrically connected with the input signal end, the first node, the first voltage signal end and the second voltage signal end; the inverter is configured to transmit a first voltage signal received at the first voltage signal terminal to the first node or transmit a second voltage signal received at the second voltage signal terminal to the first node in response to an input signal transmitted by the input signal terminal to obtain a driving control signal;

the driving sub-circuit is electrically connected with the first node, the third voltage signal end and the second node; the drive sub-circuit is configured to transmit a third voltage signal received at the third voltage signal terminal to the second node under control of a drive control signal from the first node; and the number of the first and second groups,

the light-emitting device is electrically connected with the second node and the fourth voltage signal end; the light emitting device is configured to emit light under the action of a third voltage signal from the second node and a fourth voltage signal transmitted by the fourth voltage signal terminal.

2. The pixel driving circuit according to claim 1,

the input signal is a triangular wave signal.

3. The pixel driving circuit according to claim 1,

the inverter includes: a first transistor and a second transistor;

a control electrode of the first transistor is electrically connected with the input signal end, a first electrode of the first transistor is electrically connected with the first voltage signal end, and a second electrode of the first transistor is electrically connected with a second electrode of the second transistor and the first node;

the control electrode of the second transistor is electrically connected with the input signal end, and the first electrode of the second transistor is electrically connected with the second voltage signal end;

and/or the presence of a gas in the gas,

the driving sub-circuit includes: a third transistor;

a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the third voltage signal terminal, and a second electrode of the third transistor is electrically connected to the second node.

4. The pixel driving circuit according to claim 3,

a type of one of the first transistor and the second transistor is the same as a type of the third transistor;

the other of the first transistor and the second transistor is of a type opposite to that of the third transistor.

5. The pixel driving circuit according to any one of claims 1 to 4,

the pixel driving circuit further includes:

the input sub-circuit is electrically connected with an enable signal end, the input signal end and the third node; the input sub-circuit is configured to transmit an input signal received at the input signal terminal to the third node under control of an enable signal from the enable signal terminal; and the number of the first and second groups,

the switch sub-circuit is electrically connected with the scanning signal end, the data signal end, the third node, the first initial voltage signal end and the fourth node; the switching sub-circuit is configured to transmit a data signal received at the data signal terminal to the third node and transmit a first initial voltage signal received at the first initial voltage signal terminal to the fourth node under control of a scan signal from the scan signal terminal; a pressure difference between the third node and the fourth node is constant;

the inverter is electrically connected with the fourth node and is electrically connected with the input signal end sequentially through the switch sub-circuit and the input sub-circuit.

6. The pixel driving circuit according to claim 5,

the input sub-circuit includes: a fourth transistor;

a control electrode of the fourth transistor is electrically connected with the enable signal end, a first electrode of the fourth transistor is electrically connected with the input signal end, and a second electrode of the fourth transistor is electrically connected with the third node;

the switch sub-circuit comprises: a fifth transistor, a sixth transistor, and a capacitor;

a control electrode of the fifth transistor is electrically connected with the scanning signal end, a first electrode of the fifth transistor is electrically connected with the data signal end, and a second electrode of the fifth transistor is electrically connected with the third node;

a control electrode of the sixth transistor is electrically connected to the scan signal terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage signal terminal, and a second electrode of the sixth transistor is electrically connected to the fourth node;

a first terminal of the capacitor is electrically connected to the third node, and a second terminal of the capacitor is electrically connected to the fourth node;

wherein the inverter is electrically connected to the input signal terminal through the capacitor and the fourth transistor in this order.

7. The pixel driving circuit according to claim 6,

the pixel driving circuit further includes:

a first potential stabilizing sub-circuit electrically connected to the enable signal terminal, the fourth node, and the fifth node; the first potential stabilizing sub-circuit is configured to transmit a signal received at the fourth node to the fifth node and stabilize a voltage of the fifth node under control of an enable signal from the enable signal terminal;

the second potential stabilizing sub-circuit is electrically connected with the enable signal end, the sixth node and the first node; the second potential stabilizing sub-circuit is configured to transmit a signal received at the sixth node to the first node and stabilize a voltage of the first node under control of an enable signal from the enable signal terminal; and the number of the first and second groups,

the reset sub-circuit is electrically connected with a reset signal end, a second initial voltage signal end and the first node; the reset sub-circuit is configured to transmit a second initial voltage signal received at the second initial voltage signal terminal to the first node under control of a reset signal from the reset signal terminal;

the inverter is electrically connected with the fifth node and is electrically connected with the fourth node through the first potential stabilizing sub-circuit;

the inverter is also electrically connected to the sixth node and to the first node through the second potential stabilization subcircuit.

8. The pixel driving circuit according to claim 7,

the first potential stabilizing sub-circuit includes: a seventh transistor;

a control electrode of the seventh transistor is electrically connected with the enable signal terminal, a first electrode of the seventh transistor is electrically connected with the fourth node, and a second electrode of the seventh transistor is electrically connected with the fifth node;

the second potential stabilizing sub-circuit includes: an eighth transistor;

a control electrode of the eighth transistor is electrically connected with the enable signal terminal, a first electrode of the eighth transistor is electrically connected with the sixth node, and a second electrode of the eighth transistor is electrically connected with the first node;

the reset sub-circuit includes: a ninth transistor;

a control electrode of the ninth transistor is electrically connected with the reset signal end, a first electrode of the ninth transistor is electrically connected with the second initial voltage signal end, and a second electrode of the ninth transistor is electrically connected with the first node;

the inverter is electrically connected to the fourth node through the seventh transistor;

the inverter is also electrically connected to the first node through the eighth transistor.

9. A method of driving a pixel drive circuit, for driving a pixel drive circuit as claimed in any one of claims 1 to 8; the driving method includes:

in response to an input signal received at an input signal terminal, an inverter is turned on, and a first voltage signal received at a first voltage signal terminal is transmitted to the first node or a second voltage signal received at a second voltage signal terminal is transmitted to the first node to obtain a driving control signal;

in response to a driving control signal from the first node, the driving sub-circuit is turned on, and a third voltage signal received at a third voltage signal terminal is transmitted to the second node;

the light emitting device emits light in response to a third voltage signal from the second node and a fourth voltage signal received at a fourth voltage signal terminal.

10. A display device, characterized in that the display device comprises: a plurality of pixel drive circuits as claimed in any one of claims 1 to 8.

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