CN111462679A - Pixel driving circuit, driving method thereof and display panel - Google Patents

Pixel driving circuit, driving method thereof and display panel Download PDF

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Publication number
CN111462679A
CN111462679A CN202010298984.1A CN202010298984A CN111462679A CN 111462679 A CN111462679 A CN 111462679A CN 202010298984 A CN202010298984 A CN 202010298984A CN 111462679 A CN111462679 A CN 111462679A
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China
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transistor
unit
node
pole
signal
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CN202010298984.1A
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Chinese (zh)
Inventor
岳晗
刘冬妮
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BOE Technology Group Co Ltd
Zhejiang Luyuan Electric Vehicle Co Ltd
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Zhejiang Luyuan Electric Vehicle Co Ltd
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Priority to CN202010298984.1A priority Critical patent/CN111462679A/en
Publication of CN111462679A publication Critical patent/CN111462679A/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Abstract

The invention provides a pixel driving circuit, a driving method thereof and a display panel, belongs to the technical field of display, and can at least partially solve the problem of low adjustment precision of the pixel driving circuit of the conventional organic light-emitting diode display device on the adjustment mode of the light-emitting duration. A pixel drive circuit of the present invention includes: the device comprises a driving unit, a light-emitting unit, a storage unit, a writing compensation unit, a current control unit, a duration control unit and an inversion unit; the writing compensation unit is used for writing the data signal and the compensation data of the data line end into the driving unit through the adjustment of the storage unit; a current control unit for controlling the magnitude of the current flowing through the light emitting unit by controlling the driving unit; the time length control unit is used for controlling the light emitting time length of the light emitting unit according to signals of the first data line end and the first grid line end; and the inverting unit is used for adjusting the control of the time length control unit on the light emitting time length of the light emitting unit.

Description

Pixel driving circuit, driving method thereof and display panel
Technical Field
The invention belongs to the technical field of display, and particularly relates to a pixel driving circuit, a driving method thereof and a display panel.
Background
Micro light emitting diode display devices, such as Micro-L ED display devices, have advantages of low driving voltage, long life span, wide temperature resistance, and the like, compared to organic light emitting diode (O L ED) display devices, and thus, the Micro light emitting diode display devices are receiving more and more attention.
In a pixel driving circuit of a Micro-L ED display device in the prior art, the display gray scale of a display element is controlled by controlling the driving current and the light emitting time of the display element.
However, due to the nature of the transistor in the light emission period control unit, the adjustment precision of the adjustment manner of the light emission period implemented in the above manner is low, which is not favorable for accurately controlling the light emission period.
Disclosure of Invention
The invention at least partially solves the problem of low adjustment precision of the adjustment mode of the light-emitting duration by the pixel drive circuit of the existing organic light-emitting diode display device, and provides the pixel drive circuit with high adjustment precision of the adjustment mode of the light-emitting duration.
The technical scheme adopted for solving the technical problem of the invention is a pixel driving circuit, which comprises: the device comprises a driving unit, a light-emitting unit, a storage unit, a writing compensation unit, a current control unit, a duration control unit and an inversion unit;
the driving unit is used for driving the light-emitting unit to emit light;
the first end of the storage unit is connected with a first voltage end, and the second end of the storage unit is connected with a first node;
the writing compensation unit is used for writing the data signal and the compensation data of a data line end into the driving unit through the adjustment of the storage unit;
the current control unit is used for controlling the current flowing through the light-emitting unit by controlling the driving unit;
the time length control unit is used for controlling the light emitting time length of the light emitting unit according to signals of the first data line end and the first grid line end;
and the phase inversion unit is used for adjusting the control of the time length control unit on the light emitting time length of the light emitting unit.
Further preferably, the inverting unit includes: a first transistor, wherein the grid electrode of the first transistor is connected with the second node, the first pole of the first transistor is connected with the second voltage end, and the second pole of the first transistor is connected with the third node; and a second transistor, wherein a gate of the second transistor is connected to the second node, a first pole of the second transistor is connected to the third node, a second pole of the second transistor is connected to the third voltage terminal, one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.
It is further preferred that the inverting unit comprises a cascade of at least two inverting subunits, each of the inverting subunits comprising: the first electrode of the first transistor is connected with the second voltage end; the first pole of the second transistor is connected with the second pole of the first transistor, the second pole of the second transistor is connected with the third voltage end, the grid electrodes of the first transistor and the second transistor in each inverting subunit are connected with the second pole of the first transistor in the previous inverting subunit, the grid electrodes of the first transistor and the second transistor in the first inverting subunit are connected with the second node, and the second pole of the first transistor in the last inverting subunit is connected with the third node.
Further preferably, the write compensation unit includes: a third transistor, wherein the grid electrode of the third transistor is connected with a second grid line end, the first pole of the third transistor is connected with the fourth node, and the second pole of the third transistor is connected with a second data line end; and the grid electrode of the fourth transistor is connected with the second grid line end, the first pole of the fourth transistor is connected with the first node, and the second pole of the fourth transistor is connected with the fifth node.
Further preferably, the driving unit includes: and a gate of the fifth transistor is connected to the first node, a first pole of the fifth transistor is connected to the fourth node, and a second pole of the fifth transistor is connected to the fifth node.
Further preferably, the current control unit includes: a sixth transistor, having a gate connected to the signal terminal, a first terminal connected to the first voltage terminal, and a second terminal connected to the fourth node; and a seventh transistor having a gate connected to the signal terminal and a first electrode connected to the fifth node.
Further preferably, the storage unit includes: the first pole of the first capacitor is connected with the first voltage end, and the second pole of the first capacitor is connected with the first node.
Further preferably, the duration control unit includes: a gate of the eighth transistor is connected with the first gate terminal, a first pole of the eighth transistor is connected with the first data terminal, and the first pole of the eighth transistor is connected with the second node; a first pole of the second capacitor is connected with the third node, and a second pole of the second capacitor is connected with the fourth voltage end; and a ninth transistor having a gate connected to the third node, a first electrode connected to the second electrode of the seventh transistor, and a second electrode connected to the light emitting unit.
Further preferably, the pixel driving circuit further includes: and the reset unit is used for adjusting the voltage of the first node through signals of a fifth voltage end and a reset end, and comprises a tenth transistor, wherein the grid electrode of the tenth transistor is connected with the reset end, the first pole of the tenth transistor is connected with the first node, and the first pole of the tenth transistor is connected with the fifth voltage end.
The technical scheme adopted for solving the technical problem of the invention is a pixel driving method, based on the pixel driving circuit, the pixel driving method comprises the following steps:
in a first data writing phase, the writing compensation unit writes a second data signal and compensation data of a second data line end into the driving unit through the adjustment of the storage unit;
in a second data writing phase, the duration control unit writes the first data signal of the first data line end into the second node according to the signal of the first grid line end;
in a display phase, the current control unit controls the magnitude of current flowing through the light emitting unit by controlling the driving unit; the time length control unit controls the light emitting time length of the light emitting unit according to signals of the first data line end and the first grid line end, and the inverting unit adjusts the control of the time length control unit on the light emitting time length of the light emitting unit.
Further preferably, the pixel driving method specifically includes: a reset stage, in which a reset signal is input to the fifth voltage terminal, a turn-on signal is input to the reset terminal, and a turn-off signal is input to the first gate terminal, the second gate terminal and the signal terminal; in the first data writing stage, a second data line number is input to the second data line end, a conducting signal is input to the second grid line end, and a closing signal is input to the reset end, the signal end and the first grid line end; in the second data writing stage, a first data line number is input to the first data line end, a conducting signal is input to the first grid line end, and a closing signal is input to the reset end, the signal end and the second grid line end; and a display stage, namely inputting a display signal to the first voltage end, inputting a duration control signal to the fourth voltage end, inputting a conducting signal to the signal end, and inputting a closing signal to the reset end, the first grid line end and the second grid line end.
The technical scheme adopted for solving the technical problem of the invention is that the display panel comprises a plurality of pixel driving circuits, wherein the pixel driving circuits are the pixel driving circuits.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1a is a schematic diagram of a conventional pixel driving circuit;
fig. 1b is a schematic diagram of a ninth transistor in a conventional pixel driving circuit turned off after a delay;
FIG. 2 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a pixel driving circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a ninth transistor of a pixel driving circuit according to an embodiment of the present invention being normally turned off;
wherein the reference numerals are: 1. a drive unit; 2. a light emitting unit; 3. a storage unit; 4. writing a compensation unit; 5. a current control unit; 6. a duration control unit; 7. an inverting unit; 8. a reset unit; GateT and a first grid line end; GateI and a second grid line end; a DataT and a first data line end; a DataI and a second data line end; EM, a signal terminal; reset, Reset terminal; VDD, a first voltage terminal; VDD1, second voltage terminal; VSS1, a third voltage terminal; common, fourth voltage terminal; initial, fifth voltage terminal; VSS, sixth voltage terminal; t1, a first transistor; t2, a second transistor; t3, a third transistor; t4, a fourth transistor; t5, a fifth transistor; t6, a sixth transistor; t7, a seventh transistor; t8, an eighth transistor; t9, a ninth transistor; t10, tenth transistor; n1, first node; n2, a second node; n3, third node; n4, fourth node; n5, fifth node; c1, a first capacitance; c2, a second capacitor; t1, reset phase; t2, a first data writing phase; t3, second data writing phase; t4, display phase.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Example 1:
as shown in fig. 1a to fig. 6, the present embodiment provides a pixel driving circuit, including: the device comprises a driving unit 1, a light-emitting unit 2, a storage unit 3, a writing compensation unit 4, a current control unit 5, a duration control unit 6 and an inversion unit 7;
a driving unit 1 for driving the light emitting unit 2 to emit light;
the first terminal of the memory cell 3 is connected to the first voltage terminal VDD, and the second terminal thereof is connected to the first node N1;
a write compensation unit 4 for writing the data signal of the data line end and the compensation data to the drive unit 1 by the adjustment of the storage unit 3;
a current control unit 5 for controlling the magnitude of the current flowing through the light emitting unit 2 by controlling the driving unit 1;
a duration control unit 6, configured to control the light emitting duration of the light emitting unit 2 according to signals of the first data line terminal DataT and the first gate line terminal GateT;
and an inverting unit 7 for adjusting control of the light emitting period of the light emitting unit 2 by the period control unit 6.
In addition, the light Emitting unit 2 in the present embodiment may be a current-driven light Emitting device including a Micro-L ED (Micro L lighting Diode) or an O L ED (Organic L lighting Diode) in the prior art, and in the present embodiment, the Micro-L ED is taken as an example for explanation.
In the pixel driving circuit of the present embodiment, the period control unit 6 can more accurately control the light emission period of the light emitting unit 2 by providing the inversion unit 7, thereby improving the performance of the pixel driving circuit.
Specifically, as shown in fig. 2, in one case, the inverting unit 7 includes: a first transistor T1 having a gate connected to the second node N2, a first pole connected to the second voltage terminal VDD1, and a second pole connected to the third node N3; a second transistor T2 having a gate connected to the second node N2, a first electrode connected to the third node N3, a second electrode connected to the third voltage terminal VSS1, one of the first transistor T1 and the second transistor T2 being an N-type transistor, and the other being a P-type transistor.
As shown in fig. 3 and 4, alternatively, the inverting unit 7 comprises at least two inverting subunits in cascade, each inverting subunit comprising: a first transistor T1 and a second transistor T2, a first pole of the first transistor T1 being connected to a second voltage terminal VDD 1; a first pole of the second transistor T2 is connected to a second pole of the first transistor T1, a second pole of the second transistor T2 is connected to the third voltage terminal VSS1, gates of the first transistor T1 and the second transistor T2 in each inverting subunit are connected to a second pole of the first transistor T1 in the previous inverting subunit, gates of the first transistor T1 and the second transistor T2 in the first inverting subunit are connected to the second node N2, and a second pole of the first transistor T1 in the last inverting subunit is connected to the third node.
The write compensation unit 4 includes: a third transistor T3 having a gate connected to the second gate line terminal GateI, a first pole connected to the fourth node N4, and a second pole connected to the second data line terminal DataI; a fourth transistor T4 has a gate connected to the second gate line terminal GateI, a first electrode connected to the first node N1, and a second electrode connected to the fifth node N5.
The drive unit 1 includes: the fifth transistor T5 has a gate connected to the first node N1, a first pole connected to the fourth node N4, and a second pole connected to the fifth node N5.
The current control unit 5 includes: a sixth transistor T6 having a gate connected to the signal terminal EM, a first terminal connected to the first voltage terminal VDD, and a second terminal connected to the fourth node N4; the seventh transistor T7 has a gate connected to the signal terminal EM and a first pole connected to the fifth node N5.
The storage unit 3 includes: the first terminal of the first capacitor C1 is connected to the first voltage terminal VDD, and the second terminal thereof is connected to the first node N1.
The duration control unit 6 includes: an eighth transistor T8 having a gate connected to the first gate line terminal GateT, a first pole connected to the first data line terminal DataT, and a first pole connected to the second node N2; a second capacitor C2, having a first electrode connected to the third node N3 and a second electrode connected to the fourth voltage terminal Common; the ninth transistor T9 has a gate connected to the third node N3, a first electrode connected to the second electrode of the seventh transistor T7, and a second electrode connected to the light emitting unit 2.
The pixel driving circuit of the present embodiment further includes: the Reset unit 8 is configured to adjust a voltage of the first node N1 according to signals of a fifth voltage terminal Initial and a Reset terminal Reset, and the Reset unit 8 includes a tenth transistor T10 having a gate connected to the Reset terminal Reset, a first pole connected to the first node N1, and a first pole connected to the fifth voltage terminal Initial.
Preferably, all the transistors except the first transistor T1 and the second transistor T2 are N-type transistors; alternatively, all transistors are P-type transistors.
It should be noted that, in the prior art, as shown in fig. 1a and fig. 1b, a process of controlling the light emitting duration of the light emitting unit 2 is as follows: under the action of the second capacitor C2, the voltage of the gate of the ninth transistor T9 is changed by the change of the voltage of the fourth voltage terminal Common, so as to control the on or off of the ninth transistor T9, and further control the light emitting duration of the light emitting unit 2. However, since the transistor transfer characteristic curve is relatively gentle due to the manufacturing process of the transistor, when the turn-off voltage is input to the gate of the ninth transistor T9, the ninth transistor T9 cannot be turned off in time, and a phenomenon of delayed turn-off (tail-tilting phenomenon) occurs, which results in a problem that the adjustment accuracy of the pixel driving circuit for the adjustment mode of the light emitting duration is low.
In fact, as shown in fig. 1b, due to the non-ideal state of the transistor, near the threshold voltage Vth, instead of being fully on or off, this voltage is in an inactive state, defined as Δ Vfail. The accuracy of the duration control unit 6 must be greater than Δ Vfail to improve the control accuracy.
In the pixel driving circuit of this embodiment, the first transistor T1 and the second transistor T2 are alternately turned on to form a pulse voltage in the process of increasing or decreasing the voltage of the fourth voltage terminal Common, so that a phenomenon (tail-tilting phenomenon) that the ninth transistor T9 is turned off in time and is turned off later can be avoided, that is, the duration control unit 6 can more accurately control the light-emitting duration of the light-emitting unit 2 by providing the inverting unit 7, thereby improving the performance of the pixel driving circuit.
Example 2:
as shown in fig. 1a to 6, the present embodiment provides a pixel driving method, based on the pixel driving circuit of embodiment 1, the pixel driving method includes:
in the first data writing phase t2, the write compensation unit 4 writes the second data signal of the second data line terminal DataI and the compensation data to the drive unit 1 by the adjustment of the storage unit 3.
In the second data writing phase t3, the duration control unit 6 writes the first data signal of the first data line end DataT into the second node N2 according to the signal of the first gate line end GateT.
In the display period t4, the current control unit 5 controls the magnitude of the current flowing through the light emitting unit 2 by controlling the driving unit 1; the time length control unit 6 controls the light emitting time length of the light emitting unit 2 according to the signals of the first data line end DataT and the first grid line end GateT, and the inverting unit 7 adjusts the control of the time length control unit 6 on the light emitting time length of the light emitting unit 2.
Specifically, in the method, a first voltage terminal VDD is used for providing a working voltage, and a sixth voltage terminal VSS is used for providing a reference voltage; the method specifically comprises the following steps:
s11 and a Reset period t1, the Reset signal is input to the fifth voltage terminal Initial, the on signal is input to the Reset terminal Reset, and the off signal is input to the first gate line terminal gate, the second gate line terminal gate i and the signal terminal EM.
The on signal refers to a signal that can turn on the transistor when applied to the gate of the transistor, and the off signal refers to a signal that can turn off the transistor when applied to the gate of the transistor.
It should be noted that, in the following description, all the transistors except the first transistor T1 and the second transistor T2 are P-type transistors, so that the on signal is a low level signal and the off signal is a high level signal.
As shown in fig. 2 to 5, in this stage, that is, a high level is input to the first gate line terminal gate, so that the eighth transistor T8 is turned off; a high level is input to the second gate line terminal GateI so that the third transistor T3 and the fourth transistor T4 are turned off; a high level is input to the signal terminal EM so that the sixth transistor T6 and the seventh transistor T7 are turned off. When a low level is input to the Reset terminal Reset, the tenth transistor T10 is turned on, and the Reset signal of the fifth voltage terminal Initial is written into the first node N1, thereby causing the Initial signal to be written into the first capacitor C1.
S12, the first data write phase t2, the second data signal is input to the second data line terminal DataI, the on signal is input to the second gate line terminal GateI, and the off signal is input to the Reset terminal Reset, the signal terminal EM, and the first gate line terminal GateT.
As shown in fig. 2 to 5, in this stage, that is, a high level is input to the Reset terminal Reset, so that the tenth transistor T10 is turned off; a high level is input to the first gate line terminal GateT so that the eighth transistor T8 is turned off; a high level is input to the signal terminal EM so that the sixth transistor T6 and the seventh transistor T7 are turned off. A low level is input to the second gate line terminal GateI, and the third transistor T3 and the fourth transistor T4 are turned on. The fifth transistor T5 is turned on by the first capacitor C1, so that when the third transistor T3 and the fourth transistor T4 are turned on, the second data signal at the second data line end DataI is sequentially written into the first node N1 through the third transistor T3, the fifth transistor T5 and the fourth transistor T4, and the compensation data is also written into the first node N1, that is, stored into the first capacitor C1.
S13 and a second data writing phase t3, the first data line number is input to the first data line terminal DataT, the on signal is input to the first gate line terminal GateT, and the off signal is input to the Reset terminal Reset, the signal terminal EM, and the second gate line terminal GateI.
As shown in fig. 2 to 5, in this stage, that is, a high level is input to the Reset terminal Reset, so that the tenth transistor T10 is turned off; a high level is input to the second gate line terminal GateI so that the third transistor T3 and the fourth transistor T4 are turned off; a high level is input to the signal terminal EM so that the sixth transistor T6 and the seventh transistor T7 are turned off. The low level is input to the first gate line terminal GateT so that the eighth transistor T8 is turned on, and the first data signal of the first data line terminal DataT is written into the second node N2, i.e., stored into the second capacitor C2, through the eighth transistor T8.
S14 and a display period t4, the display signal is input to the first voltage terminal VDD, the duration control signal is input to the fourth voltage terminal Common, the on signal is input to the signal terminal EM, and the off signal is input to the Reset terminal Reset, the first gate line terminal gate, and the second gate line terminal gate i.
As shown in fig. 2 to 5, in this stage, that is, a high level is input to the Reset terminal Reset, so that the tenth transistor T10 is turned off; a high level is input to the first gate line terminal GateT so that the eighth transistor T8 is turned off; a high level is input to the second gate line terminal GateI so that the third transistor T3 and the fourth transistor T4 are turned off. A low level is input to the signal terminal EM so that the sixth transistor T6 and the seventeenth transistor are turned on. The fifth transistor T5 is kept turned on by the first capacitor C1. And due to the second capacitor C2, the first transistor T1 or the second transistor T2 in the inverting unit 7 is turned on to turn on the ninth transistor T9. Accordingly, the display signal of the first voltage terminal VDD is finally written to the light emitting unit 2 through the sixth transistor T6, the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 in sequence, so that the light emitting unit 2 normally emits light.
It should be noted that, at this stage, the inverting unit 7 reads the second data signal in the second capacitor C2 to make the first transistor T1 and the second transistor T2 turn on alternately to form a pulse voltage, so as to avoid a phenomenon (tail-warp phenomenon) that the ninth transistor T9 cannot turn off in time and turn off later, that is, by setting the inverting unit 7, the duration control unit 6 can control the lighting duration of the lighting unit 2 more accurately, thereby improving the performance of the pixel driving circuit.
Example 3:
the present embodiment provides a display panel, which includes a plurality of pixel driving circuits, wherein the pixel driving circuits are the pixel driving circuits described above.
Specifically, the display panel can be any product or component with a display function, such as a Micro-light emitting diode (Micro-L ED) display panel, an organic light emitting diode (O L ED) display panel, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (12)

1. A pixel driving circuit, comprising: the device comprises a driving unit, a light-emitting unit, a storage unit, a writing compensation unit, a current control unit, a duration control unit and an inversion unit;
the driving unit is used for driving the light-emitting unit to emit light;
the first end of the storage unit is connected with a first voltage end, and the second end of the storage unit is connected with a first node;
the writing compensation unit is used for writing the data signal and the compensation data of a data line end into the driving unit through the adjustment of the storage unit;
the current control unit is used for controlling the current flowing through the light-emitting unit by controlling the driving unit;
the time length control unit is used for controlling the light emitting time length of the light emitting unit according to signals of the first data line end and the first grid line end;
and the phase inversion unit is used for adjusting the control of the time length control unit on the light emitting time length of the light emitting unit.
2. The pixel driving circuit according to claim 1, wherein the inverting unit includes:
a first transistor, wherein the grid electrode of the first transistor is connected with the second node, the first pole of the first transistor is connected with the second voltage end, and the second pole of the first transistor is connected with the third node;
and a second transistor, wherein a gate of the second transistor is connected to the second node, a first pole of the second transistor is connected to the third node, a second pole of the second transistor is connected to the third voltage terminal, one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.
3. The pixel driving circuit according to claim 1, wherein the inverting unit comprises a cascade of at least two inverting subunits, each of the inverting subunits comprising: the first electrode of the first transistor is connected with the second voltage end; the first pole of the second transistor is connected with the second pole of the first transistor, the second pole of the second transistor is connected with the third voltage end, the grid electrodes of the first transistor and the second transistor in each inverting subunit are connected with the second pole of the first transistor in the previous inverting subunit, the grid electrodes of the first transistor and the second transistor in the first inverting subunit are connected with the second node, and the second pole of the first transistor in the last inverting subunit is connected with the third node.
4. The pixel driving circuit according to claim 2 or 3, wherein the write compensation unit comprises:
a third transistor, wherein the grid electrode of the third transistor is connected with a second grid line end, the first pole of the third transistor is connected with the fourth node, and the second pole of the third transistor is connected with a second data line end;
and the grid electrode of the fourth transistor is connected with the second grid line end, the first pole of the fourth transistor is connected with the first node, and the second pole of the fourth transistor is connected with the fifth node.
5. The pixel driving circuit according to claim 4, wherein the driving unit comprises: and a gate of the fifth transistor is connected to the first node, a first pole of the fifth transistor is connected to the fourth node, and a second pole of the fifth transistor is connected to the fifth node.
6. The pixel driving circuit according to claim 5, wherein the current control unit comprises:
a sixth transistor, having a gate connected to the signal terminal, a first terminal connected to the first voltage terminal, and a second terminal connected to the fourth node;
and a seventh transistor having a gate connected to the signal terminal and a first electrode connected to the fifth node.
7. The pixel driving circuit according to claim 6, wherein the storage unit comprises: the first pole of the first capacitor is connected with the first voltage end, and the second pole of the first capacitor is connected with the first node.
8. The pixel driving circuit according to claim 7, wherein the duration control unit comprises:
a gate of the eighth transistor is connected with the first gate terminal, a first pole of the eighth transistor is connected with the first data terminal, and the first pole of the eighth transistor is connected with the second node;
a first pole of the second capacitor is connected with the third node, and a second pole of the second capacitor is connected with the fourth voltage end;
and a ninth transistor having a gate connected to the third node, a first electrode connected to the second electrode of the seventh transistor, and a second electrode connected to the light emitting unit.
9. The pixel driving circuit according to claim 8, further comprising: and the reset unit is used for adjusting the voltage of the first node through signals of a fifth voltage end and a reset end, and comprises a tenth transistor, wherein the grid electrode of the tenth transistor is connected with the reset end, the first pole of the tenth transistor is connected with the first node, and the first pole of the tenth transistor is connected with the fifth voltage end.
10. A pixel driving method according to the pixel driving circuit of any one of claims 1 to 9, the pixel driving method comprising:
in a first data writing phase, the writing compensation unit writes a second data signal and compensation data of a second data line end into the driving unit through the adjustment of the storage unit;
in a second data writing phase, the duration control unit writes the first data signal of the first data line end into the second node according to the signal of the first grid line end;
in a display phase, the current control unit controls the magnitude of current flowing through the light emitting unit by controlling the driving unit; the time length control unit controls the light emitting time length of the light emitting unit according to signals of the first data line end and the first grid line end, and the inverting unit adjusts the control of the time length control unit on the light emitting time length of the light emitting unit.
11. The pixel driving method according to claim 10, wherein the pixel driving circuit is the pixel driving circuit according to claim 9, and the pixel driving method specifically comprises:
a reset stage, in which a reset signal is input to the fifth voltage terminal, a turn-on signal is input to the reset terminal, and a turn-off signal is input to the first gate terminal, the second gate terminal and the signal terminal;
in the first data writing stage, a second data line number is input to the second data line end, a conducting signal is input to the second grid line end, and a closing signal is input to the reset end, the signal end and the first grid line end;
in the second data writing stage, a first data line number is input to the first data line end, a conducting signal is input to the first grid line end, and a closing signal is input to the reset end, the signal end and the second grid line end;
and a display stage, namely inputting a display signal to the first voltage end, inputting a duration control signal to the fourth voltage end, inputting a conducting signal to the signal end, and inputting a closing signal to the reset end, the first grid line end and the second grid line end.
12. A display panel comprising a plurality of pixel driving circuits, the pixel driving circuits being the pixel driving circuits according to any one of claims 1 to 9.
CN202010298984.1A 2020-04-16 2020-04-16 Pixel driving circuit, driving method thereof and display panel Pending CN111462679A (en)

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