KR102262863B1 - Gate driver ic, gate driving method, display panel, and display device - Google Patents

Abstract

The present embodiments relate to a gate driving method, a gate driver integrated circuit, a display panel, and a display device capable of enabling gate driving using only a small number of gate control signals and thereby reducing the bezel size of a display panel. will be.

Description

Gate driver integrated circuit, gate driving method, display panel and display device {GATE DRIVER IC, GATE DRIVING METHOD, DISPLAY PANEL, AND DISPLAY DEVICE}

The present embodiments relate to a gate driver integrated circuit, a gate driving method, a display panel, and a display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display device, a plasma display device, and an organic light emitting display device ( Various display devices such as Organic Light Emitting Display Device) are being used.

Such a display device includes a display panel in which data lines and gate lines are disposed and subpixels are disposed, at least one source driver integrated circuit driving data lines, and at least one gate driver integrated circuit driving gate lines sequentially. circuits, etc.

The timing controller controls gate driving timing by supplying a gate control signal to each gate driver integrated circuit so that each gate driver integrated circuit can drive the gate lines.

Accordingly, each gate driver integrated circuit receives a plurality of gate control signals for controlling gate driving timing from a timing controller, generates scan signals, and sequentially outputs the scan signals to the gate lines, thereby driving the gate lines.

As described above, since the timing controller controls the gate driving timing and each gate driver integrated circuit uses several gate control signals to drive the gate lines, the structure and processing method of the timing controller and the gate driver integrated circuit are different. There is a problem in that it becomes complicated and the throughput increases.

In addition, since gate driving timing control and gate driving are performed using multiple gate control signals, multiple gate control signal lines for transmitting multiple gate control signals to each gate driver integrated circuit must be disposed on the display panel. Therefore, the signal line structure of the display panel may be complicated, the process of the display panel may also be complicated, and the bezel area of the display panel on which a plurality of gate control signal lines are disposed is bound to increase.

It is an object of the present embodiments to provide a gate driving method, a gate driver integrated circuit, a display panel, and a display device that enable gate driving timing control and gate driving using only a small number of gate control signals.

Another object of the present exemplary embodiments is to provide a display panel and a display device in which only as few gate control signal lines as possible are disposed.

Another object of the present embodiments is to provide a gate driving method capable of reducing the size (width) of a bezel region in a display panel, and a gate driver integrated circuit, a display panel, and a display device for the same.

In one embodiment, the gate start pulse and the clock and masking pulse are received, and the on/off of the corresponding gate line is determined based on the gate start pulse, the clock and masking pulse, and the pulse in which the clock and masking pulse is inverted. A shift register that generates and outputs a logic signal, a level shifter circuit that converts and outputs the voltage level of the logic signal output from the shift register, and a buffer that outputs the logic signal output from the level shifter circuit as a scan signal to the corresponding gate line A gate driver integrated circuit including a circuit may be provided.

Another embodiment is a method for driving a gate of a gate driver integrated circuit, comprising the steps of receiving a gate start pulse and a clock and masking pulse, and shifting the gate start pulse to a clock and masking pulse to invert the clock and masking pulse It is possible to provide a gate driving method comprising the steps of generating a logic signal by adjusting the length of the output section, converting the voltage level of the logic signal, and outputting the converted logic signal as a scan signal.

Another embodiment provides a display panel in which a plurality of data lines and a plurality of gate lines are disposed, at least one source driver integrated circuit driving the plurality of data lines, and at least one gate driver integrated circuit driving the plurality of gate lines A display device including a circuit may be provided.

In such a display device, each gate driver integrated circuit receives a gate start pulse and a clock and masking pulse, and turns on the corresponding gate line based on the gate start pulse, the clock and masking pulse, and the pulse in which the clock and masking pulse is inverted. - A shift register that generates and outputs a logic signal for determining OFF, a level shifter circuit that converts and outputs the voltage level of the logic signal output from the shift register, and a logic signal output from the level shifter circuit as a scan signal A buffer circuit outputting to the gate line may be included.

Another embodiment provides a plurality of data lines arranged in a first direction, a plurality of gate lines arranged in a second direction, and a gate start pulse line for transmitting a gate start pulse to at least one gate driver integrated circuit; A display panel including a clock and masking pulse line that transmits a clock and masking pulse to at least one gate driver integrated circuit may be provided.

The scan signal output to the plurality of gate lines disposed on the display panel may be a signal generated based on a gate start pulse, a clock and masking pulse, and a pulse in which the clock and masking pulse is inverted.

According to the present exemplary embodiments as described above, it is possible to provide a gate driving method, a gate driver integrated circuit, a display panel, and a display device that enable gate driving timing control and gate driving using only a small number of gate control signals.

According to the present embodiments, it is possible to provide a display panel and a display device in which only as few gate control signal lines are disposed as possible for gate driving timing control.

According to the present embodiments, it is possible to provide a gate driving method capable of reducing the size (width) of a bezel region in a display panel, and a gate driver integrated circuit, a display panel, and a display device for the same.

1 is a schematic system configuration diagram of a display device according to the present exemplary embodiment.
2 is a block diagram of a gate driver integrated circuit according to the present embodiments.
3 to 5 are diagrams illustrating circuit diagrams of the gate driver integrated circuit according to the present exemplary embodiment.
6 is a diagram illustrating input pulses and output signals of the gate driver integrated circuit shown in FIGS. 3 to 5 .
7 is a view illustrating a display panel in which gate control signal lines for supplying gate control signals to the gate driver integrated circuits shown in FIGS. 3 to 5 are disposed.
8 is a diagram illustrating another circuit diagram of the gate driver integrated circuit according to the present exemplary embodiment.
FIG. 9 is a diagram illustrating input pulses and output signals of the gate driver integrated circuit shown in FIG. 8 .
FIG. 10 is a view illustrating a display panel in which gate control signal lines for supplying a gate control signal to the gate driver integrated circuit shown in FIG. 8 are disposed.
11 is a flowchart of a gate driving method according to the present exemplary embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When a component is described as being “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a schematic system configuration diagram of a display device 100 according to the present exemplary embodiment.

Referring to FIG. 1 , in the display device 100 according to the present exemplary embodiments, a plurality of data lines DL are disposed in a first direction and a plurality of gate lines GL may be different from the first direction. The display panel 110 is arranged in two directions and a plurality of subpixels are arranged in a matrix type, a data driver 120 that drives a plurality of data lines DL, and a gate driver that drives a plurality of gate lines ( 130 , and a timing controller 140 for controlling the data driver 120 and the gate driver 130 .

The data driver 120 drives the plurality of data lines by supplying data voltages to the plurality of data lines. Here, the data driver 120 is also referred to as a “source driver”.

The gate driver 130 sequentially drives the plurality of gate lines by sequentially supplying scan signals to the plurality of gate lines. Here, the gate driver 130 is also referred to as a “scan driver”.

The timing controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130 .

The timing controller 140 starts scanning according to the timing implemented in each frame, converts input image data input from the outside to match the data signal format used by the data driver 120 , and outputs the converted image data. and control the data operation at an appropriate time according to the scan.

The gate driver 130 sequentially drives the plurality of gate lines by sequentially supplying a scan signal of an on voltage or an off voltage to the plurality of gate lines under the control of the timing controller 140 . .

The gate driver 130 may be positioned on only one side of the display panel 110 , as shown in FIG. 1 , or, in some cases, on both sides, according to a gate driving method and a display panel design method.

Also, the gate driver 130 may include at least one gate driver integrated circuit (GDIC).

In addition, the one or more gate driver integrated circuits (GDIC) included in the gate driver 130 may include bonding pads of the display panel 110 using a tape automated bonding (TAB) method or a chip-on-glass (COG) method. It may be connected to a bonding pad or implemented as a GIP (Gate In Panel) type and disposed directly on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases.

Each of the one or more gate driver integrated circuits included in the gate driver 130 may include a shift register, a level shifter, an output buffer, and the like.

When a specific gate line is opened, the data driver 120 converts the image data received from the timing controller 140 into an analog data voltage and supplies it to the data lines, thereby driving a plurality of data lines.

The data driver 120 may drive a plurality of data lines including at least one source driver integrated circuit (SDIC).

At least one source driver integrated circuit (SDIC) included in the data driver 120 may be configured as a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method. It may be connected to the bonding pad) or directly disposed on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases.

Each source driver integrated circuit (SDIC) included in the data driver 120 may include a logic unit including a shift register, a latch circuit, and the like, a digital analog converter (DAC), an output butter, and the like. In some cases, a sensing unit for sensing the characteristics of the sub-pixel (e.g., the threshold voltage and mobility of the driving transistor, the threshold voltage of the organic light emitting diode, the luminance of the sub-pixel, etc.) sensor) may be further included.

In addition, each source driver integrated circuit SDIC included in the data driver 120 may be implemented in a Chip On Film (COF) method.

In this case, one end of each source driver integrated circuit is bonded to at least one source printed circuit board, and the other end is bonded to the display panel 110 .

Meanwhile, the timing controller 140 includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, a clock signal (CLK), etc. together with the input image data. Receives various timing signals from an external (eg, host system).

The timing controller 140 converts input image data input from the outside to match the data signal format used by the data driver 120 and outputs the converted image data, as well as the data driver 120 and the gate driver 130 . ), the data driver 120 and the gate driver 130 receive timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal to generate various control signals. ) is output.

For example, the timing controller 140 outputs various gate control signals (GCS) to control the gate driver 130 , that is, to control the gate driving. Such a gate control signal GCS will be described in more detail with reference to FIG. 2 .

In addition, the timing controller 140 controls the data driver 120 , a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Source). Various data control signals (DCS: Data Control Signal) including output enable) are output.

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits SDIC constituting the data driver 120 . The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source driver integrated circuits SDIC. The source output enable signal SOE controls the output timing of the data driver 120 .

Referring to FIG. 1 , the timing controller 140 includes at least one source printed circuit board to which at least one source driver integrated circuit (SDIC) is bonded and a flexible flat cable (FFC) or flexible printed circuit (FPC). : It can be arranged on a Control Printed Circuit Board connected through a connection medium such as a Flexible Printed Circuit.

A power controller (not shown) for supplying various voltages or currents to the display panel 110 , the data driver 120 , the gate driver 130 , or controlling various voltages or currents to be supplied is further disposed on the control printed circuit board can be Such a power controller is also referred to as a power management integrated circuit (PMIC).

The at least one source printed circuit board and the control printed circuit board mentioned above may be a single printed circuit board.

The display device 100 according to the present embodiments may be, for example, one of a liquid crystal display device, a plasma display device, an organic light emitting display device, and the like. can

In the display device 100 , circuit elements such as a transistor and a capacitor may be disposed in each of the plurality of sub-pixels disposed on the display panel 110 .

For example, when the display panel 110 is an organic light emitting display panel, each sub-pixel may include circuit elements such as an organic light emitting diode (OLED), two or more transistors, and at least one capacitor. have.

The type and number of circuit elements constituting each sub-pixel may be variously determined according to a provided function and a design method.

2 is a block diagram of each gate driver integrated circuit (GDIC) according to the present exemplary embodiment.

Referring to FIG. 2 , the timing controller 140 supplies the gate control signal GCS to the gate driver integrated circuit GDIC.

Referring to FIG. 2 , the gate driver integrated circuit GDIC generates a scan signal using the gate control signal GCS supplied from the timing controller 140 and outputs the scan signal to the gate lines.

Referring to FIG. 2 , in order to control the gate driving timing, the gate control signal GCS supplied from the timing controller 140 to the gate driver integrated circuit GDIC includes a gate start pulse (GSP) and a clock. and a Clock and Masking Pulse (CMP).

Here, the gate start pulse GSP is a signal instructing the start of gate driving for one frame.

The clock and masking pulse (CMP) has a role of controlling the shift timing of the scan signal (this is also referred to as a "shift clock pulse role") and a role of controlling an output period (this is a "masking role") (also called "gate output enable role")) is a functionally integrated signal.

Referring to FIG. 2 , each gate driver integrated circuit GDIC according to the present embodiments includes a shift register 210 , a level shifter circuit 220 , and a buffer circuit 230 . and the like.

Referring to FIG. 2 , the shift register 210 receives a gate start pulse GSP and a clock and masking pulse CMP from the timing controller 140 , and receives a gate start pulse GSP and a clock and masking pulse CMP ) and a pulse in which a clock and masking pulse (CMP) is inverted, a logic signal for determining the on-off of the corresponding gate line is generated for each gate line. can be printed out.

Since the shift register 210 only needs to determine a logic state to determine whether the corresponding gate line is On or Off, a high voltage is not required. Accordingly, the logic signal has a low voltage logic level (eg, low level: 3V, high level: 5V).

Referring to FIG. 2 , the level shifter circuit 220 sets the voltage level of the logic signal output from the shift register 210 for each gate line to turn on/off the transistor electrically connected to the corresponding gate line. You can convert it to a level and output it.

Here, the transistor is a transistor in each sub-pixel included in the same sub-pixel row, and is turned on or turned on by a scan signal applied to the gate node through the corresponding gate line. It can be turned off (Turn-Off).

The level shifter circuit 220 converts the voltage level of the logic signal output from the shift register 210 into a voltage level necessary to actually turn the transistor on or off.

Accordingly, the level shift circuit 220 converts the input logic signal into a high-level gate voltage VGH greater than or equal to a specific voltage (eg, 20V) and a low-level gate voltage VGL that is less than or equal to a specific voltage (eg, -5V). do.

When the gate line is directly driven using the logic signal output from the level shifter circuit 220 as a scan signal, the driving force may be insufficient.

Accordingly, the buffer circuit 230 serves to increase the driving force.

Referring to FIG. 2 , the buffer circuit 230 increases the driving force of the logic signal output from the level shifter circuit 220 enough to drive the corresponding gate line, and the logic signal Gout 1 for each gate line whose driving force is increased. , ... , Gout n) can be output to the corresponding gate line. At this time, the logic signals Gout 1 , ... , Gout n output to each gate line correspond to a scan signal for each gate line.

Meanwhile, for the gate driving, three types of gate driving timing control including the start of the gate driving, the shift timing of the scan signal, and the output timing (output length) of the scan signal are required.

Accordingly, in general, three gate control signals have been separately used for controlling the three gate driving timings.

Accordingly, in general, the timing controller 140 needs to supply three gate control signals for controlling three gate driving timings to each gate driver integrated circuit GDIC. In addition, the gate driver integrated circuit (GDIC) must generate a scan signal through complex processing using three types of gate control signals. In addition, for the supply of the three gate control signals, at least three signal lines are required.

If a modified gate driving such as odd/even gate driving is performed, more than three gate control signals and signal lines are required.

As described above, in general, since many types, a large number of gate control signals and many gate control signal lines are used, the timing controller 140 and the gate driver integrated circuit (GDIC) are complicated, and the display panel 110 is The design also becomes more complex. In particular, since a large number of gate control signal lines must be disposed on the display panel 110 , there is also a problem in that the bezel area (non-image display area) of the display panel 110 becomes large.

In contrast, in the case of the gate driving according to the present embodiments, for controlling the three gate driving timings, the gate start pulse (GSP) for controlling the start timing of the gate driving without using the three gate control signals , which can simultaneously control shift timing and output timing (output length), and uses only two gate control signals including a clock and masking pulse (CMP).

Accordingly, according to the present embodiments, structures and processing methods of the timing controller 140 and the gate driver integrated circuit (GDIC) are simplified in relation to gate timing control and gate driving, and the timing controller 140 and the gate driver are integrated. The throughput of the circuit GDIC may also be reduced.

In addition, as the number of gate control signals is reduced, the number of gate control signal lines may also be reduced, thereby simplifying the design of the display panel 110 . In particular, since a smaller number of gate control signal lines can be disposed on the display panel 110 than before, the bezel area (non-image display area) of the display panel 110 can be significantly reduced.

Examples of implementations of the gate driver integrated circuit (GDIC) described above will be described below with reference to FIGS. 3 to 10 .

3 to 5 are diagrams illustrating circuit diagrams of a gate driver integrated circuit (GDIC) according to the present exemplary embodiment.

3 is an exemplary diagram of a circuit diagram of the gate driver integrated circuit (GDIC) shown in FIG. 2, and FIG. 4 is a first and second scan signal Gout 1 and Gout 2 for generating the first and second scan signals Gout 1 in the circuit diagram of FIG. It is a diagram showing in detail the part corresponding to step 2, and FIG. 5 is a diagram showing a part of the circuit diagram of FIG. 3 as a logic circuit.

In FIG. 3, when one gate driver integrated circuit (GDIC) generates and outputs eight or more scan signals Gout 1, ... , Gout 8, ... (that is, in FIG. 2 , n is 8 or more), only a portion for generating and outputting eight scan signals (Gout 1, ..., Gout 8) is illustrated by way of example.

Each step to be mentioned below corresponds to a scan signal. That is, the first step, the second step, the third step, the fourth step, the fifth step, the sixth step, the seventh step, and the eighth step are the first scan signal Gout 1 and the second scan signal Gout 2 ), a third scan signal (Gout 3), a fourth scan signal (Gout 4), a fifth scan signal (Gout 5), a sixth scan signal (Gout 6), a seventh scan signal (Gout 7), and an eighth scan signal (Gout 7) It corresponds to the signal Gout 8, respectively.

3 and 4 , the shift register 210 may include a shift circuit unit 211 and a masking circuit unit 212 .

The shift circuit unit 211 may include a plurality of shift circuits SC 1 , SC 2 , ... including a first input terminal IN1 , a second input terminal IN2 , and an output terminal OUT.

The masking circuit unit 212 may include a plurality of masking circuits MC 1 , MC 2 , ... including a first input terminal IN1 , a second input terminal IN2 , and an output terminal OUT.

Here, the plurality of masking circuits MC 1 , MC 2 , ... may correspond to the plurality of shift circuits SC 1 , SC 2 , ... .

3 and 4, the level shifter circuit 220 includes a plurality of level shifters including a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, and an output terminal OUT. LS 1, LS 2, ...) and the like.

Here, the plurality of level shifters LS 1 , LS 2 , ... may correspond to the plurality of masking circuits MC 1 , MC 2 , ... .

3 and 4, the buffer circuit 230 unit, a plurality of level shifters (LS 1, LS 2, ...) and a plurality of buffers (BUF 1, BUF 2, ...) corresponding to each other, etc. may include.

Below, the above-described configurations will be described in more detail.

3 and 4 , each of the plurality of shift circuits SC 1 , SC 2 , ... , includes a first input terminal IN1 receiving a clock and masking pulse CMP, and a gate start pulse GSP. ) or the second input terminal IN2 receiving the output signal of the shift circuit of the previous stage, the second input terminal IN2 of the shift circuit of the next stage, and the first input terminal IN1 of the masking circuit corresponding to the current stage. It may include an output terminal (OUT).

For example, the shift circuit SC 1 of the first stage receives the clock and masking pulse CMP through the first input terminal IN1 and receives the gate start pulse GSP through the second input terminal IN2. It receives an input and outputs an output signal to the second input terminal IN2 of the shift circuit SC 2 of the second stage, which is the next stage, through the output stage OUT, and at the same time, a masking circuit corresponding to the first stage, which is the current stage. An output signal is output to the first input terminal IN1 of (MC 1).

As another example, the shift circuit SC 2 of the second stage receives the clock and masking pulse CMP through the first input terminal IN1 and receives the first stage, which is the previous stage, through the second input terminal IN2 . receives the output signal of the shift circuit SC 1 of , and outputs the output signal to the second input terminal IN2 of the shift circuit SC 3 of the third stage, which is the next stage, through the output terminal OUT, and at the same time, An output signal is output to the first input terminal IN1 of the corresponding masking circuit MC 2 in the second stage, which is the current stage.

3 and 4 , each of the plurality of masking circuits MC 1 , MC 2 , ... , includes a first input terminal IN1 connected to an output terminal OUT of a corresponding shift circuit, and a clock and masking pulse. The CMP may include a second input terminal IN2 receiving an inverted pulse, and an output terminal OUT connected to a first input terminal IN1 of a corresponding level shifter.

For example, the masking circuit MC 1 of the first stage receives an output signal output from the output terminal OUT of the corresponding shift circuit SC 1 through the first input terminal IN1, and receives the second input terminal Through IN2, a pulse in which the clock and masking pulse CMP is inverted is received, and through the output terminal OUT, an output signal is output to the first input terminal IN1 of the corresponding level shifter LS1. .

As another example, the masking circuit MC 2 of the second stage receives the output signal output from the output terminal OUT of the corresponding shift circuit SC 2 through the first input terminal IN1, and the second Through the input terminal IN2, a pulse in which the clock and masking pulse CMP is inverted is input, and an output signal is output to the first input terminal IN1 of the corresponding level shifter LS 2 through the output terminal OUT. do.

Meanwhile, as shown in FIGS. 3 and 4 , the gate driver integrated circuit GDIC may further include at least one inverter circuit IVC for inverting the clock and masking pulse CMP.

Here, the inverter circuit IVC is included in the gate driver integrated circuit GDIC, and may be included inside or outside the shift register 210 .

The inverter circuit IVC may be implemented as, for example, a NOT gate.

As described above, by inverting the clock and masking pulse (CMP) through the inverter circuit (IVC), the clock and masking pulse (CMP) serves to control the output period, that is, the “masking role” Alternatively, it allows you to "act as a gate output enable".

That is, the pulse in which the clock and masking pulse CMP is inverted may play a role of controlling an output period, that is, a “masking role” or a “gate output enable role”.

In contrast, the non-inverted clock and masking pulse CMP may serve to control shift timing of the scan signal, that is, to serve as a “shift clock pulse”.

3 and 4 , each of the plurality of level shifters LS 1 , LS 2 , ... has a first input terminal IN1 connected to an output terminal OUT of a corresponding masking circuit, and a high level gate voltage. It may include a second input terminal IN2 to which VGH is applied, a third input terminal IN3 to which a low-level gate voltage VGL is applied, and an output terminal OUT connected to a corresponding buffer.

For example, the level shifter LS 1 of the first stage receives an output signal (logic signal) output from the output terminal OUT of the corresponding masking circuit MC 1 through the first input terminal IN1 , , through the second input terminal IN2 and the third input terminal IN3, the high-level gate voltage VGH and the low-level gate voltage VGL for voltage level conversion are respectively received, and through the output terminal OUT, the corresponding The output signal is output to the buffer (BUF 1) that is used.

As another example, the level shifter LS 2 of the second stage inputs an output signal (logic signal) output from the output terminal OUT of the corresponding masking circuit MC 2 through the first input terminal IN1 . and receives the high-level gate voltage VGH and the low-level gate voltage VGL for voltage level conversion through the second input terminal IN2 and the third input terminal IN3, respectively, and through the output terminal OUT, An output signal is output to the corresponding buffer BUF 2 .

As described above, by implementing each gate driver integrated circuit GDIC, gate lines can be driven using only two gate control signals GSP and CMP. Accordingly, a structure and a processing method may be simpler than that of a conventional gate driver integrated circuit (GDIC) that drives gate lines using three gate control signals.

Meanwhile, as shown in FIG. 5 , each of the plurality of shift circuits SC 1 , SC 2 , ... may be implemented including flip-flops. Also, as shown in FIG. 5 , each of the plurality of masking circuits MC 1 , MC 2 , ... may be implemented including an AND gate.

5, a plurality of shift circuits (SC 1, SC 2, ...) and a plurality of masking circuits (MC 1, MC 2, ...) included in the shift register 210 are simple digital By implementing the logic circuit (Digital Logic Circuit), the structure and processing method of the gate driver integrated circuit (GDIC) may be made simple, and an accurate internal operation of the gate driver integrated circuit (GDIC) may be made possible.

Meanwhile, referring to FIGS. 3 to 5 , a plurality of shift circuits SC 1 , SC 2 , ... that may be implemented including a plurality of flip-flops FF 1 , FF 2 , ... , respectively , when the gate start pulse GSP input to the second input terminal IN2 or the output signal of the shift circuit of the previous stage is at a high level, the clock and masking pulse CMP input to the first input terminal IN1 is high When rising to a level, the high level output signal may be output through the output terminal OUT to the second input terminal IN2 of the shift circuit of the next stage and the first input terminal IN1 of the masking circuit corresponding to the current stage.

As described above, each of a plurality of shift circuits SC 1 , SC 2 , ... that may be implemented including a plurality of flip-flops FF 1 , FF 2 , ... is a gate start pulse ( GSP) or the output signal of the shift circuit of the previous stage, and the clock and masking pulse (CMP) may be used to control the shift timing of the scan signal. That is, each of the plurality of shift circuits SC 1 , SC 2 , ... may sequentially shift the gate start pulse GSP or the output signal of the shift circuit of the previous stage to the clock and masking pulse CMP. .

3 to 5, each of a plurality of masking circuits (MC 1, MC 2, ...) that can be implemented including a plurality of AND gates (AG 1, AG 2, ...) is the first The signal level of the signal input to the first input terminal IN1 (ie, the output signal of the corresponding shift circuit) and the signal input to the second input terminal IN2 (ie, the pulse in which the clock and masking pulse CMP is inverted) Accordingly, a high-level or low-level output signal may be output as a “logic signal” to the first input terminal IN1 of the corresponding level shifter. Here, the logic signal is an output signal output from the shift register 210 .

As described above, each of the plurality of masking circuits MC 1 , MC 2 , ... , which may be implemented including a plurality of AND gates AG 1 , AG 2 , ... , the second input terminal IN2 ), the signal input through the first input terminal IN1 (that is, the output signal of the corresponding shift circuit) is masked using a pulse in which the clock and masking pulse CMP is inverted, and the scan signal is output. You can adjust the length (Period).

In FIG. 6 , m1, m2, m3, and m4 are masked and correspond to portions dropped to a low level.

3 to 5, each of the plurality of level shifters LS 1, LS 2, ... receives the output signal of the corresponding masking circuit as a logic signal through the first input terminal IN1, Based on the high-level gate voltage VGH and the low-level gate voltage VGL input through the second input terminal IN2 and the third input terminal IN3 , the logic signal output from the shift register 210 (ie, a plurality of The voltage level of the masking circuit (the output signal of MC 1, MC 2, ...) is converted to a voltage level that can actually turn on or off the transistor connected to the corresponding gate line, and the voltage level is converted. The logic signal is output to the corresponding buffer through the output terminal (OUT).

As described above, through each of the plurality of level shifters LS 1 , LS 2 , ... included in the level shifter circuit 220 , turn-on or turn-off of the transistor connected to the corresponding gate line is possible. can do it

As described above, the logic signal whose voltage level is converted through each of the plurality of level shifters LS 1 , LS 2 , ... included in the level shifter circuit 220 is transmitted to the corresponding gate line through a corresponding buffer. has the driving force to drive it.

3 to 5 , the plurality of buffers BUF 1 , BUF 2 , ... , included in the buffer circuit 230 improves the driving force of the logic signals to thereby increase the scan signals Gout 1 , Gout 2 , ... ) as output.

The input pulses GSP and CMP of the gate driver integrated circuit GDIC and the scan signals Gout 1, Gout 2, ... , which are output signals of the gate driver integrated circuit GDIC, are shown in FIG. like a bar

FIG. 7 illustrates the display panel 110 on which gate control signal lines 710 and 720 for supplying gate control signals GSP and CMP to the gate driver integrated circuit GDIC shown in FIGS. 3 to 5 are disposed. It is a drawing.

In FIG. 7 , the display device 100 includes K gate driver integrated circuits (GDIC #1, ... , GDIC #K, and K is a natural number greater than or equal to 1), and K gate driver integrated circuits GDIC #1, ..., GDIC #K) each outputs n scan signals to n gate lines (GL #K-1, ..., GL #Kn, K is a natural number greater than or equal to 1).

Referring to FIG. 7 , two gate control signals, ie, a gate start pulse (GSP) and a clock and masking pulse (CMP), are transmitted from the timing controller 140 to K gate driver integrated circuits (GDIC #1, ... , GDIC #K), two gate control signal lines 710 and 720 may be disposed in the image non-display area of the display panel 100 .

The two gate control signal lines are a gate start pulse line 710 that transmits a gate start pulse (GSP) to the K gate driver integrated circuits (GDIC #1, ... , GDIC #K), and a clock and masking line. It includes a clock and masking pulse line 720 that transmits the pulses CMP to the K gate driver integrated circuits (GDIC #1, ..., GDIC #K).

As described above, since the gate line is driven using only the two gate control signals GSP and CMP, the number of gate control signal lines that must be disposed on the display panel 110 can be significantly reduced. Accordingly, the width (size) of the region (the bezel region) in which the gate control signal lines are disposed in the display panel 110 can be greatly reduced.

8 is a diagram illustrating another circuit diagram of a gate driver integrated circuit (GDIC) according to the present exemplary embodiment.

8 shows a process and configuration of generating a scan signal for driving odd-numbered gate lines and a process and configuration of generating a scan signal for driving even-numbered gate lines, unlike the gate driver integrated circuit (GDIC) of FIG. 5 . This is a circuit diagram of the separated gate driver integrated circuit (GDIC).

Referring to FIG. 8 , the shift register 210 included in the gate driver integrated circuit GDIC according to the present exemplary embodiments may include a first shift register 210A and a second shift register 210B.

Referring to FIG. 8 , the first shift register 210A receives the first gate start pulse GSP A and the first clock and masking pulse CMP A, and transmits the scan signal Gout 1 to the odd-numbered gate line. It generates logic signals to output Gout 3, Gout 5, Gout 7, ... ).

The first shift register 210A is a plurality of shift circuits SC 1 , SC 3 , SC 5 that may be implemented as a plurality of flip-flops FF 1 , FF 3 , FF 5 , FF 7 , ... . , SC 7, ... ) including a first shift circuit unit 211A, and a plurality of masking circuits that can be implemented with a plurality of AND gates AG 1, AG 3, AG 5, AG 7, ... (MC 1, MC 3, MC 5, MC 7, ... ) may include a first masking circuit unit 212A included.

The structure and operation method of the first shift register 210A are the same as the structure and operation method of the shift register 210 described with reference to FIGS. 3 to 6 .

The second shift register 210B receives the second gate start pulse GSP B and the second clock and masking pulse CMP B, and sends scan signals Gout 2, Gout 4, Gout 6, A logic signal to output Gout 8, ... ) can be generated.

The second shift register 210B is a plurality of shift circuits SC 2 , SC 4 , SC 6 that may be implemented as a plurality of flip-flops FF 2 , FF 4 , FF 6 , FF 8 , ... . , SC 8, ... ) including a second shift circuit unit 211B, and a plurality of AND gates AG 2, AG 4, AG 6, AG 7, ... (MC 2 , MC 4 , MC 6 , MC 8 , ... ) may include a second masking circuit unit 212B.

The structure and operation method of the second shift register 210B are the same as the structure and operation method of the shift register 210 described with reference to FIGS. 3 to 6 .

Referring to FIG. 8 , the level shifter circuit 220 includes a first level shifter circuit 220A corresponding to the first shift register 210A and a second level shifter circuit 220A corresponding to the second shift register 210B. 220B).

The first level shifter circuit 220A may include a plurality of level shifters LS 1 , LS 3 , LS 5 , LS 7 , ... , and the second level shifter circuit 220B may include a plurality of level shifters LS 1 , LS 3 , LS 5 , LS 7 , ... It may include shifters LS 2 , LS 4 , LS 6 , LS 8 , ... .

The structure and operation method of each of the first level shifter circuit 220A and the second level shifter circuit 220B are the same as the structure and operation method of the level shifter circuit 220 described with reference to FIGS. 3 to 6 .

Referring to FIG. 8 , the buffer circuit 230 includes a first buffer circuit 230A corresponding to the first level shifter circuit 220A, and a second buffer circuit 230B corresponding to the second level shifter circuit 220B. ) may be included.

The first buffer circuit 230A includes a plurality of buffers BUF 1 , BUF 3 , BUF 5 , BUF 7 , ... that are electrically connected to each other to correspond to odd-numbered gate lines.

The plurality of buffers BUF 1 , BUF 3 , BUF 5 , BUF 7 , ... , included in the first buffer circuit 230A, are odd-numbered gate lines to transmit scan signals Gout 1 , Gout 3 , Gout 5 . , Gout 7, ... ) are output sequentially.

Scan signals Gout 1, Gout 3, Gout 5 output by improving driving force by the plurality of buffers BUF 1, BUF 3, BUF 5, BUF 7, ... , included in the first buffer circuit 230A , Gout 7, ... ) are as shown in FIG. 9 .

In FIG. 9 , m1 , m3 , and m5 correspond to portions in which the first clock and masking pulse CMP A is masked by an inverted pulse and dropped to a low level.

The second buffer circuit 230B includes a plurality of buffers BUF 2 , BUF 4 , BUF 6 , BUF 8 , ... that are electrically connected to each other to correspond to the even-numbered gate lines.

The plurality of buffers BUF 2 , BUF 4 , BUF 6 , BUF 8 , ... , included in the second buffer circuit 230B, transmits scan signals Gout 2 , Gout 4 , Gout 6 to even-numbered gate lines. , Gout 8, ... ) are output sequentially.

Scan signals Gout 2, Gout 4, Gout 6 output by improving driving force by the plurality of buffers BUF 2, BUF 4, BUF 6, BUF 8, ... , included in the second buffer circuit 230B , Gout 8, ... ) are as shown in FIG. 9 .

In FIG. 9 , m2, m4, and m6 correspond to portions in which the second clock and masking pulse CMP B is masked by an inverted pulse and dropped to a low level.

Referring to FIG. 8 , the gate driver integrated circuit (GDIC) includes an ODD gate driving part driving an odd-numbered gate line and an EVEN gate driving part driving an even-numbered gate line. ) can be divided into

In the gate driver integrated circuit (GDIC), the ODD gate driving part and the EVEN gate driving part may operate independently of each other. Accordingly, the ODD gate driving part may be viewed as one gate driver integrated circuit, and the EVEN gate driving part may be viewed as another gate driver integrated circuit.

The ODD gate driving part includes a first shift register 210A including a first shift circuit unit 211A and a first masking circuit unit 212A, a first level shifter circuit 220A, and a first buffer circuit 230A. and a first inverter circuit IVC A.

The EVEN gate driving part includes a second shift register 210B including a second shift circuit unit 211B and a second masking circuit unit 212B, a second level shifter circuit 220B, and a second buffer circuit 230B. and a second inverter circuit IVC B.

When the circuit of the gate driver integrated circuit (GDIC) as shown in FIG. 8 is used, efficient independent driving of odd-numbered gate lines and even-numbered gate lines may be enabled.

FIG. 10 shows gate control signal lines 710A, 710B, 720A, and 720B for supplying gate control signals GSP A, GSP B, CMP A, and CMP B to the gate driver integrated circuit GDIC shown in FIG. 8 . It is a view showing the arranged display panel 110 .

In FIG. 10 , the display device 100 includes K gate driver integrated circuits (GDIC #1, ... , GDIC #K, K is a natural number greater than or equal to 1), and K gate driver integrated circuits (GDIC #1, GDIC #1, ..., GDIC #K) each outputs n scan signals to n gate lines (GL #K-1, ..., GL #Kn, K is a natural number greater than or equal to 1).

Referring to FIG. 10 , two gate control signals, ie, first and second gate start pulses GSP A and GSP B and first and second clock and masking pulses CMP A and CMP B, are transmitted to the timing controller 140 . ) to the K gate driver integrated circuits (GDIC #1, ... , GDIC #K), four gate control signal lines (710A, 710B, 720A, 720B) that can be transferred to the image ratio of the display panel 100 It may be disposed in the display area.

Referring to FIG. 10 , for ODD gate driving timing control, a first gate start pulse line 710A transmitting a first gate start pulse GSP A and a first clock and masking pulse CMP A are provided A first clock and masking pulse line 720A is required.

Referring to FIG. 10 , for EVEN gate driving timing control, a second gate start pulse line 710B transmitting a second gate start pulse GSP B, and a second clock and masking pulse CMP B A second clock and masking pulse line 720B is required.

In the case of ODD gate driving and EVEN gate driving, conventionally, three gate control signal lines for transmitting three gate control signals for ODD gate driving timing control, and three gate control signals for EVEN gate driving timing control A total of six gate control signal lines are required by adding three gate control signal lines that transmit signals, but only four gate control signal lines are required in total according to the present embodiments.

As described above, since the number of gate control signal lines that must be arranged on the display panel 110 can be reduced, the width (size) of the region (bezel region) where the gate control signal lines are arranged on the display panel 110 can be greatly reduced. can

Hereinafter, the gate driving method described above will be briefly described again with reference to FIG. 11 .

11 is a flowchart of a gate driving method according to the present exemplary embodiments.

Referring to FIG. 11 , the gate driving method of the gate driver integrated circuit (GDIC) according to the present exemplary embodiments includes receiving a gate start pulse (GSP) and a clock and masking pulse (CMP) from the timing controller 140 ( S1110) and a logic signal by shifting the gate start pulse (GSP) to a clock and masking pulse (CMP) and adjusting the length of the output section (Period) with a pulse (CMP') in which the clock and masking pulse (CMP) is inverted step S1120, and converting the voltage level of the logic signal into voltage levels VGH and VGL capable of turning on or off the transistor in the subpixel electrically connected to the corresponding gate line (S1130) ) and outputting the logic signal in which the voltage level is converted as a scan signal (S1140), and the like.

When the gate driving method according to the present exemplary embodiments is used, only two gate control signals GSP and CMP may be used to generate a gate driving timing control and a scan signal for gate driving.

Accordingly, the structure and processing method of the timing controller 140 and the gate driver integrated circuit GDIC may be simplified, and the throughput of the timing controller 140 and the gate driver integrated circuit GDIC may also be reduced.

In addition, since the number of gate control signals can be reduced, the design of the display panel 110 can be simplified. In particular, since a smaller number of gate control signal lines can be disposed on the display panel 110 than before, the bezel area (non-image display area) of the display panel 110 can be significantly reduced.

According to the present exemplary embodiments as described above, the gate driving method, the gate driver integrated circuit (GDIC), the display panel 110 and the display device enabling gate driving timing control and gate driving using only a small number of gate control signals. (100) can be provided.

According to the present exemplary embodiments, it is possible to provide the display panel 110 and the display device 100 in which only as few gate control signal lines are disposed as possible for gate driving timing control.

According to the present exemplary embodiments, a method for driving a gate capable of reducing the size (width) of a bezel region in the display panel 110 and a gate driver integrated circuit (GDIC) for the same, the display panel 110 , and the display device 100 . ) can be provided.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine the configuration within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: data driving unit
130: gate driver
140: timing controller

Claims (11)

A logic signal for receiving a gate start pulse and a clock and masking pulse and determining on/off of a corresponding gate line based on the gate start pulse, the clock and masking pulse, and a pulse in which the clock and masking pulse is inverted a shift register for generating and outputting ;
a level shifter circuit that converts and outputs the voltage level of the logic signal output from the shift register; and
a buffer circuit for outputting the logic signal output from the level shifter circuit as a scan signal to a corresponding gate line;
The shift register includes a first shift register receiving a first gate start pulse and a plurality of first clock and masking pulses and generating a logic signal for outputting a scan signal to each of the plurality of odd-numbered gate lines; a second shift register receiving a gate start pulse and a plurality of second clock and masking pulses and generating a logic signal for outputting a scan signal to each of the plurality of even-numbered gate lines;
the level shifter circuit includes a first level shifter circuit corresponding to the first shift register and a second level shifter circuit corresponding to the second shift register;
the buffer circuit includes a first buffer circuit corresponding to the first level shifter circuit and a second buffer circuit corresponding to the second level shifter circuit;
The first gate start pulse rises at a first rising timing and falls at a first falling timing, and includes a first high level section having a first pulse width, the second gate start pulse rises at a second rising timing, and a second high-level section that is polled at a second polling timing and has a second pulse width;
Each of the plurality of first clock and masking pulses has the same pulse width as each other, but has a smaller pulse width than the first pulse width of the first gate start pulse, and each of the plurality of second clock and masking pulses has the second having a pulse width smaller than the second pulse width of the gate start pulse;
a pulse width of each of the plurality of second clock and masking pulses is equal to a pulse width of each of the plurality of first clock and masking pulses;
An interval between the plurality of first clock and masking pulses is the same as the first pulse width of the first gate start pulse, and an interval between the plurality of second clock and masking pulses is the second of the second gate start pulse. equal to the pulse width,
the second pulse width of the second high level section of the second gate start pulse is the same as the first pulse width of the first high level section of the first gate start pulse;
The second rising timing of the second high level section of the second gate start pulse is the same as the first rising timing of the first high level section of the first gate start pulse, but the plurality of second clocks and The rising timing of the second clock and masking pulse overlapping the second gate start pulse among the masking pulses is the rising timing of the first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses different from,
The second falling timing of the second high level section of the second gate start pulse is the same as the first falling timing of the first high level section of the first gate start pulse, but the plurality of second clocks and The falling timing of the second clock and masking pulse overlapping the second gate start pulse among the masking pulses is the falling timing of the first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses different from,
When a first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses is polled, a second gate start pulse of the plurality of second clock and masking pulses overlaps with the second gate start pulse Gate driver integrated circuit with two clock and masking pulses rising simultaneously. According to claim 1,
The shift register is
A plurality of shift circuits including a first input terminal, a second input terminal, and an output terminal;
A first input terminal, a second input terminal, and an output terminal are included, and a plurality of masking circuits corresponding to the plurality of shift circuits are included,
The level shifter circuit is
and a plurality of level shifters corresponding to the plurality of masking circuits including a first input terminal, a second input terminal, a third input terminal, and an output terminal,
The buffer circuit is
and a plurality of buffers corresponding to the plurality of level shifters,
Each of the plurality of shift circuits,
A first input terminal receiving the clock and masking pulse, a second input terminal receiving the gate start pulse or an output signal of a shift circuit of a previous stage, a second input terminal of the shift circuit of the next stage, and masking corresponding to the current stage an output terminal connected to the first input terminal of the circuit;
Each of the plurality of masking circuits,
A first input terminal connected to an output terminal of a corresponding shift circuit, a second input terminal receiving a pulse in which the clock and masking pulse is inverted, and an output terminal connected to a first input terminal of a corresponding level shifter,
Each of the plurality of level shifters,
A gate driver integrated circuit including a first input terminal connected to an output terminal of a corresponding masking circuit, a second input terminal to which a high level gate voltage is applied, a third input terminal to which a low level gate voltage is applied, and an output terminal connected to a corresponding buffer. . 3. The method of claim 2,
Each of the plurality of shift circuits,
When the gate start pulse input to the second input terminal or the output signal of the shift circuit of the previous stage is at a high level, when the clock and masking pulse input to the first input terminal rises to a high level,
A gate driver integrated circuit for outputting a high-level output signal through an output terminal to a second input terminal of a shift circuit of a next stage and a first input terminal of a masking circuit corresponding to a current stage. 3. The method of claim 2,
Each of the plurality of masking circuits,
A gate driver integrated circuit for outputting a high-level or low-level output signal as the logic signal to a first input terminal of a corresponding level shifter according to signal levels of a signal input to a first input terminal and a signal input to a second input terminal. 3. The method of claim 2,
Each of the plurality of level shifters,
The output signal of the corresponding masking circuit is received as the logic signal through a first input terminal, and the voltage level of the logic signal is based on the high-level gate voltage and the low-level gate voltage input through the second input terminal and the third input terminal. A gate driver integrated circuit that converts and outputs to the corresponding buffer through the output stage. 3. The method of claim 2,
Each of the plurality of shift circuits is implemented to include a flip-flop, and each of the plurality of masking circuits is implemented to include an AND gate. delete According to claim 1,
The gate driver integrated circuit further comprising at least one inverter circuit for inverting the clock and masking pulse. A method for driving a gate of a gate driver integrated circuit, the method comprising:
receiving, by the shift register, a gate start pulse and a clock and masking pulse;
generating, by the shift register, a logic signal by shifting the gate start pulse to the clock and masking pulse and adjusting the length of an output section with a pulse in which the clock and masking pulse is inverted;
converting the voltage level of the logic signal by a level shifter circuit; and
a buffer circuit outputting the converted logic signal as a scan signal,
The shift register includes a first shift register receiving a first gate start pulse and a plurality of first clock and masking pulses and generating a logic signal for outputting a scan signal to each of the plurality of odd-numbered gate lines; a second shift register receiving a gate start pulse and a plurality of second clock and masking pulses and generating a logic signal for outputting a scan signal to each of the plurality of even-numbered gate lines;
the level shifter circuit includes a first level shifter circuit corresponding to the first shift register and a second level shifter circuit corresponding to the second shift register;
the buffer circuit includes a first buffer circuit corresponding to the first level shifter circuit and a second buffer circuit corresponding to the second level shifter circuit;
The first gate start pulse rises at a first rising timing and falls at a first falling timing, and includes a first high level section having a first pulse width, the second gate start pulse rises at a second rising timing, and a second high-level section that is polled at a second polling timing and has a second pulse width;
Each of the plurality of first clock and masking pulses has the same pulse width as each other, but has a smaller pulse width than the first pulse width of the first gate start pulse, and each of the plurality of second clock and masking pulses has the second having a pulse width smaller than the second pulse width of the gate start pulse;
a pulse width of each of the plurality of second clock and masking pulses is equal to a pulse width of each of the plurality of first clock and masking pulses;
An interval between the plurality of first clock and masking pulses is the same as the first pulse width of the first gate start pulse, and an interval between the plurality of second clock and masking pulses is the second of the second gate start pulse. equal to the pulse width,
the second pulse width of the second high level section of the second gate start pulse is the same as the first pulse width of the first high level section of the first gate start pulse;
The second rising timing of the second high level section of the second gate start pulse is the same as the first rising timing of the first high level section of the first gate start pulse, but the plurality of second clocks and The rising timing of the second clock and masking pulse overlapping the second gate start pulse among the masking pulses is the rising timing of the first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses different from,
The second falling timing of the second high level section of the second gate start pulse is the same as the first falling timing of the first high level section of the first gate start pulse, but the plurality of second clocks and The falling timing of the second clock and masking pulse overlapping the second gate start pulse among the masking pulses is the falling timing of the first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses different from,
When a first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses is polled, a second gate start pulse of the plurality of second clock and masking pulses overlaps with the second gate start pulse A gate driving method in which two clocks and masking pulses rise simultaneously. a display panel on which a plurality of data lines and a plurality of gate lines are disposed;
at least one source driver integrated circuit for driving the plurality of data lines; and
at least one gate driver integrated circuit for driving the plurality of gate lines;
Each of the gate driver integrated circuits,
A logic signal for receiving a gate start pulse and a clock and masking pulse and determining on/off of a corresponding gate line based on the gate start pulse, the clock and masking pulse, and a pulse in which the clock and masking pulse is inverted a shift register for generating and outputting ;
a level shifter circuit that converts and outputs the voltage level of the logic signal output from the shift register; and
a buffer circuit for outputting the logic signal output from the level shifter circuit as a scan signal to a corresponding gate line;
The shift register includes a first shift register receiving a first gate start pulse and a plurality of first clock and masking pulses and generating a logic signal for outputting a scan signal to each of the plurality of odd-numbered gate lines; a second shift register receiving a gate start pulse and a plurality of second clock and masking pulses and generating a logic signal for outputting a scan signal to each of the plurality of even-numbered gate lines;
the level shifter circuit includes a first level shifter circuit corresponding to the first shift register and a second level shifter circuit corresponding to the second shift register;
the buffer circuit includes a first buffer circuit corresponding to the first level shifter circuit and a second buffer circuit corresponding to the second level shifter circuit;
The first gate start pulse rises at a first rising timing and falls at a first falling timing, and includes a first high level section having a first pulse width, the second gate start pulse rises at a second rising timing, and a second high-level section that is polled at a second polling timing and has a second pulse width;
Each of the plurality of first clock and masking pulses has the same pulse width as each other, but has a smaller pulse width than the first pulse width of the first gate start pulse, and each of the plurality of second clock and masking pulses has the second having a pulse width smaller than the second pulse width of the gate start pulse;
a pulse width of each of the plurality of second clock and masking pulses is equal to a pulse width of each of the plurality of first clock and masking pulses;
An interval between the plurality of first clock and masking pulses is the same as the first pulse width of the first gate start pulse, and an interval between the plurality of second clock and masking pulses is the second of the second gate start pulse. equal to the pulse width,
The second pulse width of the second high level section of the second gate start pulse is the same as the first pulse width of the first high level section of the first gate start pulse,
The second rising timing of the second high level section of the second gate start pulse is the same as the first rising timing of the first high level section of the first gate start pulse, but the plurality of second clocks and The rising timing of the second clock and masking pulse overlapping the second gate start pulse among the masking pulses is the rising timing of the first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses different from,
The second falling timing of the second high level section of the second gate start pulse is the same as the first falling timing of the first high level section of the first gate start pulse, but the plurality of second clocks and The falling timing of the second clock and masking pulse overlapping the second gate start pulse among the masking pulses is the falling timing of the first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses different from,
When a first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses is polled, a second gate start pulse of the plurality of second clock and masking pulses overlaps with the second gate start pulse A display device in which two clocks and masking pulses rise simultaneously. a plurality of data lines arranged in a first direction;
a plurality of gate lines arranged in a second direction;
a gate start pulse line for transmitting the first gate start pulse and the second gate start pulse to at least one gate driver integrated circuit; and
a clock and masking pulse line for transmitting a plurality of first clock and masking pulses and a plurality of second clock and masking pulses to the at least one gate driver integrated circuit;
A scan signal output to each of a plurality of odd-numbered gate lines among the plurality of gate lines is applied to a pulse in which the first gate start pulse, the first clock and masking pulse, and the first clock and masking pulse are inverted. created on the basis of
The scan signal output to each of the plurality of even-numbered gate lines among the plurality of gate lines is applied to a pulse in which the second gate start pulse, the second clock and masking pulse, and the second clock and masking pulse are inverted. created on the basis of
The first gate start pulse rises at a first rising timing and falls at a first falling timing, and includes a first high level section having a first pulse width, the second gate start pulse rises at a second rising timing, and a second high-level section that is polled at a second polling timing and has a second pulse width;
Each of the plurality of first clock and masking pulses has the same pulse width as each other, but has a smaller pulse width than the first pulse width of the first gate start pulse, and each of the plurality of second clock and masking pulses has the second having a pulse width smaller than the second pulse width of the gate start pulse;
a pulse width of each of the plurality of second clock and masking pulses is equal to a pulse width of each of the plurality of first clock and masking pulses;
An interval between the plurality of first clock and masking pulses is the same as the first pulse width of the first gate start pulse, and an interval between the plurality of second clock and masking pulses is the second of the second gate start pulse. equal to the pulse width,
the second pulse width of the second high level section of the second gate start pulse is the same as the first pulse width of the first high level section of the first gate start pulse;
The second rising timing of the second high level section of the second gate start pulse is the same as the first rising timing of the first high level section of the first gate start pulse, but the plurality of second clocks and The rising timing of the second clock and masking pulse overlapping the second gate start pulse among the masking pulses is the rising timing of the first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses different from,
The second falling timing of the second high level section of the second gate start pulse is the same as the first falling timing of the first high level section of the first gate start pulse, but the plurality of second clocks and The falling timing of the second clock and masking pulse overlapping the second gate start pulse among the masking pulses is the falling timing of the first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses different from,
When a first clock and masking pulse overlapping the first gate start pulse among the plurality of first clock and masking pulses is polled, a second gate start pulse of the plurality of second clock and masking pulses overlaps with the second gate start pulse A display panel in which 2 clocks and masking pulses rise at the same time.

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