KR102067243B1 - Display device, gate driver, and panel - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driver, a panel, and a display device that have a simple circuit structure and enable efficient gate driving even when generating only a small number of clock signals.

Description

DISPLAY DEVICE, GATE DRIVER, AND PANEL}

The present invention relates to a display device, a gate driver and a panel.

Conventional display devices include a panel formed by crossing gate lines and data lines, a gate driver for driving gate lines formed in the panel, a data driver for driving data lines formed in the panel, a gate driver and a data driver. And a timing controller for controlling the drive timing of the same.

On the other hand, in such a conventional display device, since the gate driver generates and uses a large number of clock signals to sequentially supply scan signals to the gate lines, the circuit is inevitably complicated, and the signal wiring for transmitting the clock signals is complicated. There is a problem that the area also has to be so large.

Due to these problems, the conventional gate driver and its driving method are a major obstacle in manufacturing the narrow bezel panel. In particular, the narrow bezel (Narrow Bezel) can cause a big problem in the production of a panel for a mobile terminal, which is the most important factor, such as product value.

In this background, it is an object of the present invention to provide a gate driver, a panel, and a display device that have a simple circuit structure and enable efficient gate driving even when generating only a small number of clock signals.

Another object of the present invention is to provide a gate driver, a panel, and a display device, which can further reduce the size of a bezel through efficient gate driving using a single feeding method.

In addition, another object of the present invention, by using a dummy clock signal having a low sensitivity to the RC delay, it is possible to efficiently drive the gate while generating only a small number of clock signals than the number of clock signals required for gate driving Therefore, it is not necessary to increase the line width in order to reduce the wiring resistance, so that the signal wiring design area in the panel can be reduced. As a result, the gate driver, the panel, and the display device, which enable the narrow bezel, can be further reduced. To provide.

In addition, another object of the present invention, it is possible to simplify the logic block according to the clock signal generation by enabling efficient gate driving even if only a small number of clock signals than the number of clock signals required for the gate driving The present invention provides a gate driver, a panel, and a display device.

In order to achieve the above object, in one aspect, the present invention, a panel formed by crossing the gate line and the data line; And a gate driver sequentially supplying scan signals to the gate lines based on the input x clock signals and y dummy clock signals.

In another aspect, the present invention, the data line formed in one direction; Gate lines formed to intersect the data lines; And formed on the first side of the inactive region or on the first side and the second side, and sequentially supplying scan signals to the gate lines based on the input x clock signals and y dummy clock signals. Provided is a panel comprising gate drive integrated circuits.

In still another aspect, the present invention includes a plurality of gate drive integrated circuits sequentially supplying scan signals to the gate lines based on the input x clock signals and y dummy clock signals. Each of the drive integrated circuits receives one or more dummy clock signals of y dummy clock signals, and one or more dummy clock signals input to each of the plurality of gate drive integrated circuits are part of the x clock signals or the x clocks. A gate driver is provided which has the same on-off timing with some of the signals.

As described above, the present invention has the effect of providing a gate driver, a panel, and a display device having a simple circuit structure and enabling efficient gate driving even when generating only a small number of clock signals.

In addition, according to the present invention, there is an effect of providing a gate driver, a panel, and a display device capable of further reducing the size of the bezel through the efficient gate driving of the single feeding method.

In addition, according to the present invention, by using a dummy clock signal having a small sensitivity to the RC delay, it is possible to efficiently drive the gate even if only a small number of clock signals are required for the gate driving. It is not necessary to increase the line width in order to reduce the resistance, thereby reducing the area of signal wiring design in the panel, thereby providing a gate driver that enables the narrow bezel even more, and an effect of providing the panel and the display device. There is.

In addition, according to the present invention, a gate driver capable of simplifying a logic block according to clock signal generation by enabling efficient gate driving even by generating fewer clock signals than the number of clock signals required for gate driving. And a panel and a display device.

1 is a schematic system configuration diagram of a display device for applying embodiments.
2 is a diagram illustrating clock signal generation according to an exemplary embodiment.
3 illustrates gate drive integrated circuits formed in a panel according to an exemplary embodiment.
4 is a diagram illustrating a clock signal according to an exemplary embodiment.
5 is a circuit diagram illustrating a gate drive integrated circuit formed in a panel according to an exemplary embodiment.
6A to 6I are diagrams for describing an operating procedure of a gate drive integrated circuit formed in a panel, according to an exemplary embodiment.
FIG. 7 illustrates a narrow bezel effect of a panel according to an embodiment.
8 is a view showing a panel according to another embodiment.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are shown in different drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the component of this invention, terms, such as 1st, 2nd, A, B, (a), (b), can be used. These terms are only to distinguish the components from other components, and the terms are not limited in nature, order, order, or number of the components. If a component is described as being "connected", "coupled" or "connected" to another component, that component may be directly connected to or connected to that other component, but between components It is to be understood that the elements may be "interposed" or each component may be "connected", "coupled" or "connected" through other components.

1 is a schematic system configuration diagram of a display device 100 for applying embodiments.

Referring to FIG. 1, the display device 100 for applying the embodiments includes a panel 110 formed by crossing gate lines GL1 to GLn and data lines DL1 to DLm, and a panel 110. A gate driver 120 for driving the gate lines formed in the gate line, a data driver 130 for driving the data lines formed in the panel 110, and driving timings of the gate driver 120 and the data driver 130. Timing controller 140 or the like.

In the panel 110, the pixels P are defined by crossing the gate lines GL1 to GLn and the data lines DL1 to DLm.

The gate driver 120 drives the gate lines GL1 to GLn by sequentially supplying scan signals to the gate lines GL1 to GLn. For this purpose, x (x is a natural number of two or more) clock signals and The y dummy clock signals are input, and the scan signals are sequentially supplied to the gate lines GL1 to GLn based on the input x clock signals and the y dummy clock signals.

The x clock signals mentioned above may be generated by a level shifter. The clock signal generation of the level shifter will be described with reference to FIG. 2.

The display device 100 of FIG. 1 may be, for example, a liquid crystal display (LCD) or an organic light-emitting diode (OLED), but is not limited thereto. 110, the gate driver 120, the data driver 130, the timing controller 140, and the like, and the gate driver 120 only uses the clock signal to drive the gate lines GL1 to GLn. The display device may be of any type.

In addition, the display device 100 of FIG. 1 may be, for example, a display device of a mobile terminal in which a narrow bezel is an important factor.

2 is a diagram illustrating clock signal generation according to an exemplary embodiment.

Referring to FIG. 2, the level shifter 200 is based on the clock information CLOCK input from the timing controller 140 and the high level voltage VGH and the low level voltage VGL supplied from the power supply 210. X clock signals CLK 1, CLK 2, CKL 3, CLK 4, ..., CLK x are generated.

The level shifter 200 outputs the generated x clock signals CLK 1 to CLK x to the gate driver 120 for driving x phases, and includes all or all of the x clock signals CLK 1 to CLK x. Some of the dummy clock signals D-CLK 1, D-CLK 2,..., And D-CLK y are further output to the gate driver 120.

The level shifter 200 may be, for example, included in the data driver 130 or may be formed on a printed circuit board (PCB) connected through the panel 110 and the data driver 130. The present invention is not limited thereto, and may be formed or positioned anywhere besides the gate driver 120.

The dummy clock signal number y may be equal to the clock signal number x or may be smaller than the clock signal number x. That is, the number of dummy clock signals y may be equal to or less than the number of clock signals x.

As mentioned above, the y dummy clock signals D-CLK 1 to D-CLK y may be all or part of the x clock signals CLK 1 to CLK x. That is, the y dummy clock signals D-CLK 1 to D-CLK y are not generated by the level shifter 200, but instead of the total of x clock signals CLK 1 to CLK x actually generated or Some may be reused signals.

The gate driver 120 may include a plurality of gate drive ICs that are directly formed in the panel 110 and sequentially supply scan signals to the gate lines.

Here, the gate drive integrated circuit formed directly on the panel 110 may be referred to as a "GIP (Gate Drive IC in Panel)".

As described above, the plurality of gate drive integrated circuits included in the gate driver 120 may be directly formed in the panel 110, but the present disclosure is not limited thereto, and the panel may be formed through a tape carrier package (TCP). 110 may be connected.

Meanwhile, each of the plurality of gate drive integrated circuits may receive two clock signals among the x clock signals and one dummy clock signal among the y dummy clock signals.

One of two clock signals input to each of the plurality of gate drive integrated circuits is a first clock signal for outputting a scan signal, and the other one is a second clock signal whose on-off timing is opposite to the first clock signal.

In addition, one dummy clock signal input to each of the plurality of gate drive integrated circuits is a signal that is already turned on when the first clock signal input to the corresponding gate drive integrated circuit is turned on.

One dummy clock signal input to each of the plurality of gate drive integrated circuits may be one of the x clock signals or a signal having the same on-off timing with one of the x clock signals.

On the other hand, each of the plurality of gate drive integrated circuits is turned on by the voltage applied to the gate and outputs the high level voltage VGH to the voltage output terminal in response to the application of the first clock signal to thereby output the scan signal Vout to the corresponding gate line. A first transistor that is turned on by a pull-up transistor supplied to the gate and a dummy clock signal applied to the gate and supplies a low level voltage VGL to a Q node corresponding to the gate of the pull-up transistor And a second transistor that is turned on by the second clock signal applied to the gate and applies a low level voltage VGL to the voltage output terminal of the pull-up transistor.

The circuit configuration of each gate drive integrated circuit and the use of the clock signal and the dummy clock signal of each gate drive integrated circuit will be described in more detail with reference to FIG. 5.

Hereinafter, the panel 110, the gate driver 120, the gate drive integrated circuit, etc. according to the exemplary embodiment briefly described above will be described in more detail.

However, in the following description, a case where the gate drive integrated circuits are driven in a four-phase single-feeding scheme is described, for example, when the number of clock signals x is four and the number of dummy clock signals y is four. The gate drive integrated circuits are described as being directly formed on the first side and the second side of the panel 110.

3 illustrates gate drive integrated circuits formed in the panel 110, according to an exemplary embodiment.

Referring to FIG. 3, the gate driver 120 may be formed on the first side and the second side of the panel 110. That is, the plurality of gate drive integrated circuits GIP 1, GIP 2,... Included in the gate driver 120 may be formed on the first side and the second side of the panel 110.

On the other hand, the formation position of the plurality of gate drive integrated circuits (GIP 1, GIP 2, ...), as described above may be formed on both the first side and the second side of the panel 110, as shown in FIG. The present invention is not limited thereto and may be formed only on the first side of the panel 110 as shown in FIG. 8.

Referring to FIG. 3, the gate driver 120a formed on the first side of the panel 110 includes GIP 1, GIP 3, GIP 5, GIP 7,..., And the like. The gate driver 120B formed on the side includes GIP 2, GIP 4, GIP 6, GIP 8,...

An area in which the plurality of gate drive integrated circuits GIP 1, GIP 2,..., Are formed in the panel 110 is an active area 310 in which an image is displayed in the panel 110 as shown in FIG. 3. An inactive area corresponding to an outer area of the area.

Meanwhile, referring to FIG. 3, each of the plurality of gate drive integrated circuits GIP 1, GIP 2,..., Corresponds to one gate line GL. That is, each gate drive integrated circuit supplies a scan signal to one gate line GL.

In this case, the number of gate drive integrated circuits is equal to the number of gate lines.

As described above, a method in which each gate drive integrated circuit supplies one scan line to one gate line GL to drive one gate line GL is referred to as a “single feeding method”.

The plurality of gate drive integrated circuits GIP 1, GIP 2,..., Driving the gate lines by receiving the x clock signals, may be driven by the x-phase single feeding method. In the case illustrated in FIG. 3, the plurality of gate drive integrated circuits GIP 1, GIP 2,... Are driven in a four-phase single feeding scheme.

As mentioned above, the four-phase single method compares the size and number of gate drive integrated circuits with the four-phase double feeding method in which two gate drive integrated circuits on both sides simultaneously supply a scan signal to one gate line. This can be reduced, which has a greater advantage in implementing narrow bezels. This advantage is described again later with reference to FIG. 7.

As shown in FIG. 3, when the plurality of gate drive integrated circuits are divided and formed on the first side and the second side of the panel 110, the four clock signals CLK 1, CLK 2, CKL 3, and CLK 4 may be divided into the first and second gate signals. Gate drive integrated circuits (GIP 1, GIP 3, GIP 5, GIP 7, ...) formed on the side and gate drive integrated circuits (GIP 2, GIP 4, GIP 6, GIP 8, ... formed on the second side The input is divided into).

That is, among the four clock signals CLK 1, CLK 2, CKL 3 and CLK 4, CLK 1 and CLK 3 are the gate drive integrated circuits GIP 1, GIP 3, GIP 5, GIP 7, .. Of the four clock signals CLK 1, CLK 2, CKL 3, and CLK 4, the gate drive integrated circuits GIP 2, GIP 4, and GIP 6 formed on the second side. , GIP 8, ...).

In addition, the four dummy clock signals D-CLK 1, D-CLK 2, D-CKL 3, and D-CLK 4 are gate drive integrated circuits GIP 1, GIP 3, GIP 5, and GIP 7 formed on the first side. , ...) and gate drive integrated circuits GIP 2, GIP 4, GIP 6, GIP 8, ... formed on the second side.

That is, among the four dummy clock signals D-CLK 1, D-CLK 2, D-CKL 3, and D-CLK 4, D-CLK 2 and D-CLK 4 are gate drive integrated circuits (GIP) formed on the first side. 1, GIP 3, GIP 5, GIP 7, ...), and D- out of four dummy clock signals (D-CLK 1, D-CLK 2, D-CKL 3, D-CLK 4). The CLK 1 and the D-CLK 3 may be input to the gate drive integrated circuits GIP 2, GIP 4, GIP 6, GIP 8,... Formed on the second side.

In the following, the clock signal input relationship from the gate drive integrated circuit perspective will be described again.

The gate drive integrated circuits GIP 1, GIP 3, GIP 5, GIP 7, ... formed on the first side of the panel 110 may use CLK 1, D-CLK 2, CLK 3, and D-CLK 4. The scan signal is supplied to the corresponding gate lines GL1, GL3, GL5, GL7, ....

For example, GIP 1 supplies Vout (1) to the corresponding gate line GL1 as a scan signal using CLK 1, and GIP 3 supplies Vout (3) as a scan signal using CLK 3 to the corresponding gate line ( GIP 5 supplies Vout (5) to the corresponding gate line GL5 as a scan signal using CLK 5, and GIP 7 supplies Vout (7) as a scan signal using CLK 7 to the corresponding gate. Supply to line GL7.

The gate drive integrated circuits GIP 2, GIP 4, GIP 6, GIP 8,... Formed on the second side of the panel 110 are D-CLK 1, CLK 2, D-CLK 3, and CLK 4. The scan signal is supplied to the corresponding gate lines GL2, GL4, GL6, GL8, ... using.

For example, GIP 2 supplies Vout (2) to the corresponding gate line GL2 as a scan signal using CLK 2, and GIP 4 supplies Vout (4) as a scan signal using CLK 4 to the corresponding gate line ( GIP 6 supplies Vout (6) to the corresponding gate line GL6 as a scan signal using CLK 6, and GIP 8 supplies Vout (8) as a scan signal using CLK 8 to the corresponding gate. Supply to line GL8.

Meanwhile, the dummy clock signals D-CLK 2 and D-CLK 4 input to the gate drive integrated circuits GIP 1, GIP 3, GIP 5, GIP 7, ... formed on the first side of the panel 110. Are clock signals CLK 2 and CLK 4 input to the gate drive integrated circuits GIP 2, GIP 4, GIP 6, GIP 8,... Formed on the second side of the panel 110.

That is, after four clock signals CLK 1 to CLK 4 are generated by the level shifter 200, the gate drive integrated circuits GIP 2 and GIP 4 are formed on the second side of the panel 110 by CLK 2 and CLK 4. , GIP 6, GIP 8, ...), and also to gate drive integrated circuits GIP 1, GIP 3, GIP 5, GIP 7, ... formed on the first side of the panel 110. Will be.

Here, the gate drive integrated circuit formed on the first side of the panel 110 together with the gate drive integrated circuits GIP 2, GIP 4, GIP 6, GIP 8,... Formed on the second side of the panel 110. (GIP 1, GIP 3, GIP 5, GIP 7, ...) gate drive integrated circuits (GIP 1, GIP 3, GIP 5, CLK 2 and CLK 4 input to the first side of the panel 110) It becomes a dummy clock signal in GIP 7, ...).

In addition, the dummy clock signals D-CLK 1 and D-CLK 3 input to the gate drive integrated circuits GIP 2, GIP 4, GIP 6, GIP 8,... The clock signals CLK 1 and CLK 3 are input to the gate drive integrated circuits GIP 1, GIP 3, GIP 5, GIP 7,.

That is, after four clock signals CLK 1 to CLK 4 are generated in the level shifter 200, the gate drive integrated circuits GIP 1 and GIP 3 in which CLK 1 and CLK 3 are formed on the first side of the panel 110 are generated. , GIP 5, GIP 7, ...), and at the same time as the gate drive integrated circuits GIP 2, GIP 4, GIP 6, GIP 8, ... formed on the second side of the panel 110. Will be.

Here, the gate drive integrated circuit formed on the second side of the panel 110 together with the gate drive integrated circuits GIP 1, GIP 3, GIP 5, GIP 6,... Formed on the first side of the panel 110. (GIP 2, GIP 4, GIP 6, GIP 8, ...) CLK 1 and CLK 3 input to the gate drive integrated circuit formed on the second side of the panel 110 (GIP 2, GIP 4, GIP 6, It becomes a dummy clock signal in GIP 8, ...).

The four-phase single feeding method according to an embodiment uses eight clock signals in the same manner as the general eight-phase single feeding method. However, the four-phase feeding method according to an embodiment generates eight clock signals unlike the general eight-phase single feeding method that generates eight clock signals CLK 1, CLK 2,... CLK 8. Instead, only four clock signals CLK 1 to CLK 4 are generated, and the remaining four clock signals are the four clock signals CLK 1 to CLK 4 actually generated by the level shifter 200. -CLK 1 to D-CLK 4) Reused signal.

Therefore, according to an embodiment, since the number of clock signals that should be actually generated can be reduced, the number of logic blocks in the level shifter 200 which is a clock signal generation configuration can be reduced and Simple.

In addition, the four dummy clock signals D-CLK 1 to D-CLK 4 in the four-phase single-feeding method according to an embodiment may include general clock signals CLK 1 to CLK 4 that may become scan signal output voltages. Since it only needs to be on when it is turned on, the sensitivity to the RC delay is very low compared to the general clock signals CLK 1 to CLK 4.

Therefore, when designing signal wiring for transferring the dummy clock signals D-CLK 1 to D-CLK 4, it is not necessary to increase the line width in order to reduce the wiring resistance.

In other words, instead of using the general clock signal for the scan signal output, since the dummy clock signal (D-CLK 1 to D-CLK 4) with low sensitivity to RC delay is used, all eight clock signals are actually used. Compared to the typical eight-phase single feeding method that must be generated, the signal wiring design area can be reduced.

This reduction in signal wiring design area is very helpful in implementing narrow bezels.

The effect according to this embodiment will be even greater when the narrow bezel is applied to the display of the mobile terminal, which is the most important factor.

As illustrated in FIG. 3, four clock signals CLK 1, CLK 2, CLK 3, which are input to a plurality of gate drive integrated circuits GIP 1, GIP 2,... CLK 4) is illustrated in FIG. 4 to explain the on-off timing relationship between the four clock signals CLK 1, CLK 2, CLK 3, and CLK 4.

4 is a diagram illustrating a clock signal according to an exemplary embodiment.

Referring to FIG. 4, the level shifter 200 is based on the clock information CLOCK input from the timing controller 140 and the high level voltage VGH and the low level voltage VGL supplied from the power supply 210. To generate four clock signals (CLK 1, CLK 2, CKL 3, CLK 4).

The level shifter 200 outputs the generated x clock signals CLK 1 to CLK 4 to the gate driver 120 for driving as a four-phase single, as well as four clock signals CLK 1 to CLK. Reusing 4) further outputs four dummy clock signals D-CLK 1, D-CLK 2, D-CLK 3, and D-CLK 4 to the gate driver 120.

Of the four clock signals CLK 1, CLK 2, CKL 3, and CLK 4 generated by the level shifter 200, the timing at which the CLK 1 and the CLK 3 are turned on and off is opposite, and the CLK 2 and the CLK 4 are also turned off. The clock signals are opposite in timing.

In addition, CLK 1 and CLK 2 are delayed clock signals, and any one of CLK 1 and CLK 2 is delayed by a predetermined time compared to the other one, and when one is turned on, the other is already on. When one is off, the other is already off. The same is true for CLK 2 and CLK 3, CLK 3 and CLK 4, and CLK 4 and CLK 1.

As illustrated in FIG. 3, CLK 1 and CLK 3 of the four clock signals CLK 1, CLK 2, CKL 3 and CLK 4 are formed on the first side of the panel 110 among the plurality of gate drive integrated circuits. It is input to the drive integrated circuits GIP 1, GIP 3, .... Also, among the four clock signals CLK 1, CLK 2, CKL 3, and CLK 4, CLK 2 and CLK 4 are formed on the second side of the panel 110 among the gate drive integrated circuits GIP 2. , GIP 4, ....)

On the other hand, the clock signals that can be input to the gate drive integrated circuits GIP 1, GIP 3,... Formed on the first side of the panel 110 have opposite on / off timings based on any one of the clock signals. Must include a clock signal. In other words, CLK 1 and CLK 3 are clock signals having the opposite relationship.

In addition, the clock signals input to the gate drive integrated circuits GIP 1, GIP 3,... Formed on the first side of the panel 110 may be turned on based on any one of the clock signals. At this time, the clock signal which is already on should be present.

To this end, in one embodiment, as a clock signal having a delay relationship with CLK 1 and CLK 3 input to the gate drive integrated circuits GIP 1, GIP 3,... Formed on the first side of the panel 110. The dummy clock signals (D-CLK 2 and D-CLK 4) using CLK 2 and CLK 4 are used.

That is, the gate drive integrated circuits GIP 1, GIP 3, ... formed on the first side of the panel 110 include CLK 1 and CLK 3 and two dummy clock signals D-CLK 2 and D-. CLK 4 is entered.

Similarly, the clock signals that can be input to the gate drive integrated circuits GIP 2, GIP 2,... Formed on the second side of the panel 110 have opposite on-off timings based on any one of the clock signals. Must include a clock signal. In other words, CLK 2 and CLK 4 are clock signals having the opposite relationship.

In addition, the clock signals input to the gate drive integrated circuits GIP 2, GIP 4,... Formed on the second side of the panel 110 may be turned on based on any one of the clock signals. At this time, the clock signal which is already on should be present.

To this end, in one embodiment, as a clock signal having a delay relationship with CLK 2 and CLK 2 input to the gate drive integrated circuits GIP 2, GIP 2,... Formed on the second side of the panel 110. The dummy clock signals (D-CLK 1 and D-CLK 3) using CLK 1 and CLK 3 are used.

In other words, the gate drive integrated circuits GIP 2, GIP 4,... Formed on the second side of the panel 110 include CLK 2 and CLK 4 and two dummy clock signals D-CLK 1 and D-. CLK 3 is entered.

The plurality of gate drive integrated circuits GIP 1, GIP 2,... Illustrated in FIG. 3 operate in the same manner. Hereinafter, a circuit configuration of a gate drive integrated circuit (GIP) will be described in more detail with reference to FIG. 5, and an operation method thereof will be described with reference to FIGS. 6A to 6I.

5 is a circuit diagram illustrating a gate drive integrated circuit (GIP) formed in the panel 110 according to an embodiment.

Referring to FIG. 5, the gate drive integrated circuit GIP N of the Nth stage receives the CLK 1 and supplies the output voltage Vout (N) corresponding thereto to the first side that supplies the Nth gate line GL (N). One of the formed gate drive integrated circuits GIP 1, GIP 3,...

As shown in FIG. 5, since the gate drive integrated circuit GIP of the Nth stage receives CLK 1 as a clock signal (first clock signal) for outputting a scan signal, the on-off timing of CLK 1 is reversed. CLK 3 is further input, and CLK 4, which is already on at the timing when CLK 1 is turned on, is further input as the dummy clock signal D-CLK 4.

In addition, as shown in FIG. 5, the N-th stage gate drive integrated circuit GIP N has seven transistors (T6, T3C, T3N, T3R, T7C, and T7D) for driving in a four-phase single feeding scheme. And one capacitor Cout, and as described above, in addition to receiving two clock signals CLK 1 and CLK 4 and one dummy clock signal D-CLK 4, three other The stage output values Vout (N-2), Vout (N-1), and Vout (N + 2) are further input.

Among the output values Vout (N-2), Vout (N + 2), and Vout (N-1) of the other three stages to which the gate drive integrated circuit GIP N of the Nth stage is input, Vout (N− 1) means the output voltage at the N-2th stage that is 2 horizontal periods (2H) earlier than the current Nth stage, and Vout (N-2) is 1 horizontal period (1H) than the current Nth stage. Is the output voltage at the N-th stage earlier, and Vout (N + 2) is the output voltage at the N + 2-th stage slower by 2 horizontal periods (2H) than the current N-th stage. .

On the other hand, with respect to the representation of the clock signal of FIG. 5, when considering the order of the stages, CLK 1 is input to the gate drive integrated circuit GIP N of the Nth stage as a first clock signal (main clock signal). CLK (N), and CLK 2 is represented as CLK (N + 1) in the sense that it is input as the first clock signal (main clock signal) to the gate drive integrated circuit GIP N + 1 of the N + 1th stage. CLK 3 is represented as CLK (N + 2) in the sense that it is input to the gate drive integrated circuit GIP N + 2 of the N + 2th stage as the first clock signal (main clock signal), and CLK 4 is It can be expressed as CLK (N-1) in the sense that it is input as the first clock signal (main clock signal) to the gate drive integrated circuit GIP N-1 of the N-1 (or N + 3) th stage.

A connection structure between transistors in the gate drive integrated circuit GIP N of the Nth stage illustrated in FIG. 5 will be briefly described.

When the gate of the pull-up transistor T6 is connected to the Q node, and the drain is connected to the first clock signal supply terminal supplying CLK 1, which is the first clock signal for outputting the scan signal, the source outputs Vout (N) as a scan signal. Are respectively connected to the scan signal output terminal.

Between the gate and the source of the pull-up transistor T6 is a capacitor (Cout) that is involved in the voltage change of the Q node while repeatedly charging and discharging.

The gate and the drain of the transistor T7D are simultaneously connected to the scan signal output terminal and the source is connected to the first clock signal supply terminal.

A gate of the transistor T7C is connected to a second clock signal supply terminal for supplying a second clock signal CLK 3 that is opposite to the first clock signal CLK 1 and the on-off timing, and the drain and the source are connected to the scan signal output terminal and the ground voltage VSS Are connected to the base voltage supply terminal for supplying

The gate and the drain of the transistor T1 are simultaneously connected with the N-2th stage output voltage supply terminal for supplying the output voltage Vout (N-2) in the N-2th stage, and the source is connected to the Q node.

The gate of transistor T3N is connected to the N + 2th stage output voltage supply which supplies the output voltage Vout (N + 2) of the N + 2th stage, the drain is connected to the Q node, and the source is connected to the ground voltage supply. .

A gate of the transistor T3R is connected to a reset signal supply terminal for supplying a reset signal (Reset), a drain is connected to a Q node, and a source is connected to a base voltage supply terminal.

The gate of the transistor T3C is connected to a dummy clock signal supply terminal for supplying the same dummy clock signal D-CLK 4 as CLK 4 (CLK (N-1)), a drain is connected to a Q node, and a source is an N-1 th stage. It is connected to the N-th stage output voltage supply terminal for supplying the output voltage Vout (N-1) of.

The gate drive integrated circuit (GIP) illustrated in FIG. 5 is merely an example for convenience of description, and is not limited thereto. One or more of the x clock signals and one or more of the y dummy clock signals may be used. As long as it is possible to receive another stage output value and output an output voltage as a scan signal to the corresponding gate line, the circuit can be configured in any circuit form.

An operation procedure of the gate drive integrated circuit GIP of the Nth stage described with reference to FIG. 5 will be described with reference to FIGS. 6A through 6I.

6A through 6I are diagrams for describing an operating procedure of a gate drive integrated circuit formed in the panel 110, according to an exemplary embodiment.

In each of Figs. 6A to 6I, for each operation procedure, the state of the gate drive integrated circuit GIP N of the Nth stage of Fig. 5 and the signal timing diagram (block display portion) are shown together.

In the following description, for convenience of description, considering the stage stages, CLK 1, CLK 2, CLK 3, and CLK 4 are replaced with CLK (N), CLK (N + 1), CLK (N + 2) and CLK ( It also describes as N-1), respectively. In addition, since the gate drive integrated circuit GIP N of the Nth stage receives CLK 1 as the first clock signal that is involved in the scan signal output, the CLK 4 that is already on at the timing when the CLK 1 is turned on, that is, CLK (N-1) is the dummy clock signal of the gate drive integrated circuit GIP N of the Nth stage.

In the operating step of FIG. 6A, the transistor T3R is turned on by the reset signal Reset to maintain the voltage of the Q node at a low level voltage (VGL = VSS). At this time, the voltage Vout (N) of the scan signal output terminal is the low level voltage VGL.

Next, in the operation step of FIG. 6B, the output voltage Vout (N-2) of the N-th stage is changed to the high level voltage VGH, whereby the transistor T1 is turned on, and accordingly, Q The voltage at the node changes to the high level voltage (VGH).

At this time, CLK 3, that is, CLK (N + 2), also changes to the high level voltage VGH. As a result, the transistor T7C is turned on, and the low level voltage VGL supplied from the base voltage supply terminal VSS is supplied to the scan signal output terminal, whereby Vout (N) is maintained at the low level voltage VGL. do.

In the operating step of FIG. 6B, a constant potential difference ΔV = VGH-VGL is generated across the capacitor Cout connected between the gate and the source of the transistor T6, thereby charging the capacitor Cout.

Next, in the operation step of FIG. 6C, CLK (N-1), that is, CLK 4, which serves as a dummy clock signal in the gate drive integrated circuit of the N-th stage, is changed to the high level voltage VGH, and N-1 The output voltage Vout (N-1) at the first stage is changed to the high level voltage VGH, so that the transistor T3C is turned on.

At this time, the transistor T1 is still turned on, and the voltage at the Q node is kept at the high level voltage VGH.

At this time, the transistor T7C is also continuously turned on, whereby Vout (N) is kept at the low level voltage VGL.

In the operating step of FIG. 6C, a constant potential difference ΔV = VGH-VGL is continuously maintained at both ends of the capacitor Cout.

Next, in the operation step of FIG. 6D, CLK 1, which is the first clock signal CLK (N) directly related to the scan signal output in the Nth stage, is changed to the high level voltage VGH. As a result, the transistor T6 which has already satisfied the turn-on condition in the previous stage is turned on as a ratio.

As a result, the voltage Vout (N) of the scan signal output terminal is changed to the high level voltage VGH, and Vout (N) of the high level voltage VGH is output as the scan signal to the Nth gate line GL (N).

In this way, as the voltage Vout (N) of the scan signal output terminal is changed to the high level voltage VGH, the voltage at the Q node becomes high to maintain the constant potential difference (ΔV = VGH-VGL) of the capacitor Cout. Boosted further by the level voltage VGH.

In the operation step of FIG. 6D, CLK 1, which is CLK (N) and CLK 3, which is the opposite of on-off timing, is turned to low level voltage VGL, so that transistor T7C is turned off. The voltage Vout (N) of the scan signal output terminal may be changed to the high level voltage VGH.

In addition, in the operation step of FIG. 6D, the dummy clock signal CLK (N-1) maintains the high level voltage VGH and the output voltage Vout (N-1) in the N-1th stage is the high level voltage VGH. ), The transistor T3C remains turned on.

Next, in the operation step of FIG. 6E, CLK (N-1), which is CLK 4 serving as the dummy clock signal D-CLK 4, is changed to the low level voltage VGL, and output transfer of the N-1 st stage is performed. Change to the low level voltage (VGL). As a result, the transistor T3C is turned off.

At this time, since CLK 1, which is CLK (N), continues to be the high level voltage VGH, the voltage of the Q node and the boosted voltage are maintained, and the voltage Vout (N) of the scan signal output terminal is also maintained at the high level voltage VGH. Thus, Vout (N) of the high level voltage VGH is continuously output as a scan signal to the Nth gate line GL (N).

Next, in the operation step of FIG. 6F, the output voltage Vout (N + 2) of the N + 2th stage is changed to the high level voltage VGH, and the transistor T3N is turned on.

Accordingly, the low level voltage VGL, which is the base voltage VSS supplied from the base voltage supply terminal, is supplied to the Q node, and the voltage of the Q node is boosted from the boosted voltage 2 * VGH to the low level voltage VGL. It is reset.

At this time, CLK 1, which is CLK (N), changes to the low level voltage VGL, and the transistor T6 is turned off.

At this time, CLK 3, which is CLK (N + 2), is changed to the high level voltage VGH, and the transistor T7C is turned on, and the low level voltage VGL supplied from the base voltage supply terminal is supplied to the scan signal output terminal. Accordingly, the voltage at the scan signal output terminal is reset to the low level voltage VGL.

In this operating step of FIG. 6F, the capacitor Cout is discharged.

Next, in the operation step of Fig. 6G, CLK (N-1), which is CLK 4 serving as the dummy clock signal D-CLK 4, is changed to the high level voltage VGH, so that the transistor T3C is turned on and the low level is turned on. Vout (N-1), which is the voltage VGL, is applied to the Q node. Accordingly, the Q node is maintained at the low level voltage VGL.

At this time, CLK 3, which is CLK (N + 2), is maintained at the high level voltage VGH, and the transistor T7C is continuously turned on, thereby causing the low level voltage VGL supplied from the base voltage supply terminal. The scan signal is continuously supplied to the output terminal. That is, the voltage at the scan signal output terminal is kept at the low level voltage VGL.

Next, in the operation step of FIG. 6H, the dummy clock signal CLK (N-1) maintains the high level voltage VGH and the output voltage Vout (N-1) in the N-1th stage is the low level voltage. While maintaining (VGL), the low level voltage (VGL) is supplied to the Q node by the transistor T3C. As a result, the Q node maintains the low level voltage VGL.

At this time, the CLK (N + 2) is changed from the high level voltage VGH to the low level voltage VGL so that the transistor T7C is turned off.

Next, in the operating step of FIG. 6I, CLK (N + 2) is changed from the low level voltage VGL to the high level voltage VGH so that transistor T7C is turned on, thereby reducing the voltage Vout (N) of the scan signal output terminal. It is induced to low level voltage (VGL).

FIG. 7 illustrates a narrow bezel effect of the panel 110, according to an exemplary embodiment.

FIG. 7 is a view for explaining an effect of reducing the size of a bezel as a plurality of gate drive integrated circuits included in the gate driver 120 are driven by a single feeding method. Referring to FIG. FIG. 7 is a diagram illustrating a case in which scan signals Vout (1) and Vout (2) are supplied to two pixels P1 and P2 by a double feeding method, and FIG. 7B illustrates two pixels. The figure shows a case where scan signals Vout (1) and Vout (2) are supplied to P1 and P2 in a single feeding manner.

Referring to FIG. 7A, two gate drive integrated circuits GIP 1 and GIP 1 ′ connected to the first gate line GL1 formed on the panel 110 and formed on the panel 110 are double fed. In this way, the scan signal Vout (1) is simultaneously supplied to the P1 pixel from both sides via the first gate line GL1. In addition, referring to FIG. 7A, two gate drive integrated circuits GIP 2 and GIP 2 ′ connected to the second gate line GL2 formed on the panel 110 and formed on the panel 110 may be provided. Since it is driven by the double feeding method, the scan signal Vout (2) is simultaneously supplied to the P2 pixel on both sides via the second gate line GL2.

When the gate drive integrated circuit driven in the double feeding method is formed in the panel 110 as shown in FIG. 7A, the length La of one gate drive integrated circuit is greater than the pixel length Lp of one pixel. It should not be large (La≤Lp).

The reason for such a structure is that the gate drive integrated circuits GIP 1 and GIP 1 'for supplying the scan signal Vout 1 to the P1 pixel must be formed on both sides (the first side and the second side), and P2 This is because the gate drive integrated circuits GIP 2 and GIP 2 'for supplying the scan signal Vout 2 to the pixels must also be formed on both sides (the first side and the second side).

Referring to FIG. 7A, the width Wa of each of the gate drive integrated circuits GIP 1, GIP 1 ′, GIP 2, and GIP 2 ′, which is driven by the double feeding method, is each gate drive integrated circuit GIP. 1, GIP 1 ′, GIP 2, GIP 2 ′).

Meanwhile, referring to FIG. 7B, one gate drive integrated circuit GIP 1 connected to the first gate line GL1 formed on the panel 110 and the left side (first side) is formed on the panel 110. Because of driving in a single feeding method, the scan signal Vout (1) is supplied to the P1 pixel from the left through the first gate line GL1. In addition, referring to FIG. 7B, one gate drive integrated circuit GIP 2 connected to the second gate line GL2 formed on the panel 110 and the right side (second side) formed on the panel 110 may be provided. Since the driving is performed by the single feeding method, the scan signal Vout (2) is supplied to the P2 pixel from the right through the second gate line GL2.

When the gate drive integrated circuit driving in the single feeding method is formed in the panel 110 as shown in FIG. 7B, the length L of one gate drive integrated circuit is equal to or greater than the pixel length Lp and the pixel length ( Lp) may be 2 times or less (Lp ≦ L ≦ 2Lp).

The reason for such a structure is that the gate drive integrated circuit GIP 1 for supplying the scan signal Vout 1 to the P1 pixel may be formed only on the left side (first side), and the scan signal Vout 2 is applied to the P2 pixel. This is because the gate drive integrated circuit GIP 2 to be supplied may be formed only on the right side (second side).

Referring to FIG. 7B, the width W of each of the gate drive integrated circuits GIP 1 and GIP 2 driven by the single feeding method is the length of each gate drive integrated circuit GIP 1 and GIP 2. Is determined to correspond to L).

That is, referring to FIG. 7B, the width W of each of the plurality of gate drive integrated circuits GIP 1 and GIP 2 is equal to the length L of each of the plurality of gate drive integrated circuits GIP 1 and GIP 2. ) May be correspondingly narrower as the pixel length Lp becomes longer.

FIG. 7A illustrates a structure in which a double-feeding gate drive integrated circuit is formed in the panel 110, and FIG. 7 illustrates a structure in which a single-feeding gate drive integrated circuit is formed in the panel 110. Comparing b), the single feeding gate drive integrated circuit shown in FIG. 7B is longer in the vertical direction than the double feeding gate drive integrated circuit shown in FIG. It can be formed (L> La).

As such, the single-feeding gate drive integrated circuit shown in FIG. 7B is formed longer in the vertical direction than the double-feeding gate drive integrated circuit shown in FIG. There is room for shorter widths (W <Wa).

Accordingly, as shown in FIG. 7B, a single-feeding gate drive integrated circuit is formed in the panel 110, thereby providing the double-feeding gate drive integrated circuit shown in FIG. 7A. In comparison, the bezel of each of the first side and the second side can be reduced by ΔW (= Wa-W).

That is, as shown in FIG. 7B, by forming a single-feeding gate drive integrated circuit in the panel 110, an effect of providing a narrow bezel may be further improved.

Meanwhile, as illustrated in FIG. 3, the plurality of gate drive integrated circuits may be formed on both sides (the first side and the second side) of the panel 110, but the first side and the first side of the panel 110 may be formed. It may be formed only on one side of the two sides.

A case where a plurality of gate drive integrated circuits are formed only on one side of the panel 110 is illustrated in FIG. 8 as another embodiment.

8 illustrates a panel 110 according to another embodiment.

Referring to FIG. 8, a plurality of gate drive integrated circuits GIP 1, GIP 2, GIP 3, GIP 4, GIP 5, GIP 6, GIP 7, GIP 8,. It is formed only on the first side of the inactive region, which is an outer region of the active region 810 of the panel 110.

Referring to FIG. 8, when the clock signal number x is 4 and the dummy clock signal number y is 4, the plurality of gate drive integrated circuits GIP 1, GIP 2, and GIP 3, which are formed only on the first side of the panel 110, may be used. GIP 4, GIP 5, GIP 6, GIP 7, GIP 8, ...) receive CLK 1, CLK 2, CLK 3 and CLK 4 sequentially one by one as the first clock signal associated with the scan signal output.

Each of the plurality of gate drive integrated circuits (GIP 1, GIP 2, GIP 3, GIP 4, GIP 5, GIP 6, GIP 7, GIP 8, ...) may use CLK 1, CLK 2, CLK 3 and CLK 4 In addition to being sequentially input one by one as the first clock signal related to the scan signal output, a second clock signal whose on-off timing is opposite to that of the received first clock signal is further added from among CLK 1, CLK 2, CLK 3, and CLK 4. Receive input.

In addition, each of the plurality of gate drive integrated circuits GIP 1, GIP 2, GIP 3, GIP 4, GIP 5, GIP 6, GIP 7, GIP 8,..., The first clock signal received is turned on. At this time, a clock signal which is already turned on among CLK 1, CLK 2, CLK 3 and CLK 4 is further input as a dummy clock signal.

For example, the gate drive integrated circuit GIP 1 of the first stage connected to the first gate line GL 1 receives CLK 1 as a first clock signal, and the on-off timing of the CLK 1 is opposite to that shown in FIG. 4. CLK 3 is further input as the second clock signal. In addition, GIP 1 receives CLK 4, which is already on when CLK 1 is turned on, as a dummy clock signal.

Generalizing to the N-th gate line GL N, the gate drive integrated circuit GIP N of the N-th stage connected to the N-th gate line GL N receives CLK (N) as the first clock signal and is turned on and off with CLK (N). CLK (N + 2) whose timing is reversed is further input as the second clock signal. In addition, GIP N further receives CLK (N-1), which is already on when CLK (N) is turned on, as a dummy clock signal.

The circuit structure of each of the gate drive integrated circuits formed in the panel 110 according to another embodiment of FIG. 8 may be the same as that of FIG. 5, and the driving operation thereof is the same as the operation procedure described with reference to FIGS. 6A to 6I. The same can be done.

As described above, the present invention has the effect of providing a gate driver, a panel, and a display device having a simple circuit structure and enabling efficient gate driving even when generating only a small number of clock signals.

In addition, according to the present invention, there is an effect of providing a gate driver, a panel, and a display device capable of further reducing the size of the bezel through the efficient gate driving of the single feeding method.

In addition, according to the present invention, by using a dummy clock signal having a small sensitivity to the RC delay, it is possible to efficiently drive the gate even if only a small number of clock signals are required for the gate driving. It is not necessary to increase the line width in order to reduce the resistance, thereby reducing the area of signal wiring design in the panel, thereby providing a gate driver that enables the narrow bezel even more, and an effect of providing the panel and the display device. There is.

In addition, according to the present invention, a gate driver capable of simplifying a logic block according to clock signal generation by enabling efficient gate driving even by generating fewer clock signals than the number of clock signals required for gate driving. And a panel and a display device.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may combine the configurations without departing from the essential characteristics of the present invention. Various modifications and variations may be made, including separation, substitution, and alteration. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the present invention.

100: display device
110: panel
120: gate driver
130: data driver
140: timing controller
200: level shifter

Claims (13)

A panel formed by crossing gate lines and data lines; And
a level shifter for generating x clock signals, the x clock signals input from the level shifter, and y dummy clock signals reused in whole or part of the x clock signals without being generated from the level shifter; And a gate driver sequentially supplying scan signals to the gate lines. The method of claim 1,
And y is less than or equal to two, which is a natural number of two or more. delete The method of claim 1,
The gate driver,
And a plurality of gate drive integrated circuits formed directly on the panel and sequentially supplying scan signals to the gate lines. The method of claim 4, wherein
The plurality of gate drive integrated circuits,
A display device formed on the first side of the panel or formed on the first and second sides and driven in an x-phase single feeding manner. The method of claim 5,
When the plurality of gate drive integrated circuits are formed on the first side and the second side of the panel,
A length of each of the plurality of gate drive integrated circuits is greater than or equal to a pixel length and less than or equal to twice the length of the pixel,
And a width of each of the plurality of gate drive integrated circuits is correspondingly narrow as the length of each of the plurality of gate drive integrated circuits is longer than the pixel length. The method of claim 4, wherein
When the plurality of gate drive integrated circuits are divided and formed on the first side and the second side of the panel,
The x clock signals are divided and input into a gate drive integrated circuit formed on the first side and a gate drive integrated circuit formed on the second side,
And the y dummy clock signals are input to the gate drive integrated circuit formed on the first side and the gate drive integrated circuit formed on the second side. The method of claim 7, wherein
The dummy clock signal input to the gate drive integrated circuit formed on the first side is the same as the clock signal input to the gate drive integrated circuit formed on the second side,
And a dummy clock signal input to the gate drive integrated circuit formed on the second side is the same as a clock signal input to the gate drive integrated circuit formed on the first side. The method of claim 1,
Each of the plurality of gate drive integrated circuits,
Receiving two clock signals of the x clock signals and one dummy clock signal of the y dummy clock signals,
One of the two clock signals is a first clock signal for outputting a scan signal, and the other one is a second clock signal in which on-off is opposite to the first clock signal.
And the one dummy clock signal is a dummy clock signal which is already turned on when the first clock signal is turned on. The method of claim 9,
Each of the plurality of gate drive integrated circuits,
A pull-up transistor which is turned on by a voltage applied to a gate and outputs a high level voltage to a voltage output terminal according to the application of the first clock signal to supply the scan signal to a corresponding gate line;
A transistor turned on by the one dummy clock signal applied to a gate to supply a low level voltage to a Q node corresponding to the gate of the pull-up transistor;
And a transistor turned on by the second clock signal applied to a gate to apply a low level voltage to the voltage output terminal of the pull-up transistor. The method of claim 1,
The level shifter generates the x clock signals based on clock information input from a timing controller and a high level voltage and a low level voltage supplied from a power supply unit.
And a display device for outputting the x clock signals to the gate driver for driving the x phases. Data lines formed in one direction;
Gate lines formed to intersect the data lines; And
The x clock signals are formed on the first side of the inactive region or on the first side and the second side, and are not generated from the x clock signals and the level shifters input from a level shifter for generating x clock signals. And gate drive integrated circuits sequentially supplying scan signals to the gate lines based on y dummy clock signals reusing all or part of a clock signal.
delete

Images