KR20150042312A - Display device, gate driver, and panel - Google Patents

Abstract

The present invention relates to a gate driver which enables the efficient operation of a gate using a simple circuit structure and a small number of a clock signal, and a panel and a display device for the same. To achieve this, the display device comprises: a panel with gate lines and data lines alternatively formed; and the gate driver to consecutively supply a scan signal to the gate lines based on x number of clock signals and y number of dummy clock signals inputted.

Description

DISPLAY DEVICE, GATE DRIVER, AND PANEL Technical Field [1] The present invention relates to a display device,

The present invention relates to a display device, a gate driver and a panel.

The conventional display device includes a panel formed by intersecting gate lines and data lines, a gate driver for driving gate lines formed on the panel, a data driver for driving data lines formed on the panel, And a timing controller for controlling the driving timing of the driving signal.

On the other hand, in such a conventional display device, since the gate driver sequentially generates and uses a large number of clock signals to supply the scan signals to the gate lines, the circuit becomes complicated and the number of signal lines There is a problem that the area also becomes large.

Due to these problems, the conventional gate driver and the driving method thereof are a great obstacle in manufacturing a panel of a low-bezel. In particular, Narrow Bezel can cause a serious problem in manufacturing panels for mobile terminals, which are important factors for product value and the like.

In view of the foregoing, it is an object of the present invention to provide a gate driver having a simple circuit structure and capable of efficient gate driving even when only a small number of clock signals are generated, and its panel and display device.

It is another object of the present invention to provide a gate driver capable of further reducing the size of the bezel through efficient gate driving in a single feeding mode, and a panel and a display device thereof.

It is still another object of the present invention to provide a method and apparatus for generating a clock signal having a smaller sensitivity to RC delay than a clock signal used for gate driving, Therefore, there is no need to increase the line width in order to reduce the wiring resistance, thereby reducing the signal wiring design area in the panel, thereby making it possible to further make the narrow bezel, and the panel and the display device .

It is still another object of the present invention to provide a semiconductor memory device capable of efficiently performing gate driving even when only a fewer number of clock signals are generated than the number of clock signals required for gate driving, And a panel and a display device.

In order to achieve the above-mentioned object, in one aspect, the present invention provides a liquid crystal display comprising: a panel formed by intersecting gate lines and data lines; And a gate driver sequentially supplying a scan signal to the gate lines based on the input x clock signals and the y dummy clock signals.

In another aspect, the present invention provides a liquid crystal display device including data lines formed in one direction; Gate lines intersecting with the data lines; And a scan driver for sequentially supplying scan signals to the gate lines based on the input x clock signals and the y dummy clock signals, the scan signal being formed on the first side of the inactive area or formed on the first side and the second side, And gate drive integrated circuits.

In another aspect, the present invention includes a plurality of gate drive integrated circuits sequentially supplying a scan signal to the gate lines based on input x clock signals and y dummy clock signals, Each of the drive integrated circuits receives one or more dummy clock signals of y dummy clock signals, and one or more dummy clock signals input to each of the plurality of gate drive integrated circuits is part of the x clock signals, And the on-off timing is the same as a part of the signal.

As described above, according to the present invention, it is possible to provide a gate driver that has a simple circuit structure and enables efficient gate driving even when only a small number of clock signals are generated, and its panel and display device.

Further, according to the present invention, it is possible to provide a gate driver capable of further reducing the size of the bezel through efficient gate driving of the single feeding type, and its panel and display device.

In addition, according to the present invention, by using a dummy clock signal having a small sensitivity to RC delay, it is possible to efficiently perform gate driving even when only a smaller number of clock signals are generated than the required number of clock signals for gate driving, There is no need to increase the line width in order to reduce the resistance, thereby reducing the signal wiring design area in the panel, thereby making it possible to further make the narrow bezel, and an effect of providing the panel and the display device .

In addition, according to the present invention, a gate driver capable of simplifying a logic block according to a clock signal generation by enabling efficient gate driving even when generating only a fewer number of clock signals than a necessary number of clock signals for gate driving And a panel and a display device therefor.

1 is a schematic system configuration diagram of a display device for applying embodiments.
2 is a diagram illustrating clock signal generation according to one embodiment.
3 is a diagram illustrating gate drive integrated circuits formed in a panel according to one embodiment.
4 is a diagram illustrating a clock signal according to an embodiment.
5 is a circuit configuration diagram of a gate drive integrated circuit formed on a panel according to an embodiment.
6A to 6I are diagrams for explaining operation procedures of a gate drive integrated circuit formed on a panel according to an embodiment.
7 is a view for explaining a Narrow Bezel effect of a panel according to an embodiment.
8 is a view showing a panel according to another embodiment.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a schematic system configuration diagram of a display device 100 for applying embodiments.

1, a display device 100 according to an embodiment of the present invention includes a panel 110 formed by intersecting gate lines GL1 through GLn and data lines DL1 through DLm, A data driver 130 for driving the data lines formed on the panel 110 and a gate driver 120 for driving the gate drivers 120 and the data driver 130. [ A timing controller 140 and the like.

Each pixel (P) is defined in the panel 110 by intersecting the gate lines GL1 to GLn and the data lines DL1 to DLm.

The gate driver 120 drives the gate lines GL1 to GLn by sequentially supplying a scan signal to the gate lines GL1 to GLn. To this end, x (x is a natural number of 2 or more) y dummy clock signals, and sequentially supplies the scan signals to the gate lines GL1 to GLn based on the input x clock signals and the y dummy clock signals.

The above-mentioned x clock signals can be generated in a level shifter. The generation of the clock signal of this level shifter will be described with reference to FIG.

1 may be, for example, a liquid crystal display (LCD) or an organic light-emitting diode (OLED), and the present invention is not limited thereto, A gate driver 120, a data driver 130 and a timing controller 140. The gate driver 120 uses a clock signal to drive the gate lines GL1 to GLn It may be any type of display device.

In addition, the display device 100 of FIG. 1 may be a display device of a mobile terminal, for example, a narrow bezel as an important factor.

2 is a diagram illustrating clock signal generation according to one embodiment.

2, the level shifter 200 generates a level shifter 200 based on the clock information CLOCK input from the timing controller 140 and the high level voltage VGH and the low level voltage VGL supplied from the power supply unit 210 Thereby generating x clock signals CLK 1, CLK 2, CKL 3, CLK 4, ..., CLK x.

The level shifter 200 outputs the generated x clock signals CLK 1 to CLK x to the gate driver 120 driving the x-phase clock signal CLK 1 to CLK x, (D-CLK1, D-CLK2, ..., D-CLK y) to the gate driver 120 as shown in FIG.

The level shifter 200 may be included in the data driver 130 or may be formed on a printed circuit board (PCB) connected through the panel 110 and the data driver 130, But may be formed or positioned anywhere other than the gate driver 120, without limitation.

On the other hand, the dummy clock signal number y may be equal to or smaller than the clock signal number x. That is, the number of dummy clock signals y may be equal to or less than the number x of clock signals.

As mentioned above, the y dummy clock signals (D-CLK 1 to D-CLK y) may be all or part of x clock signals (CLK 1 to CLK x). That is, the y dummy clock signals (D-CLK 1 to D-CLK y) are not generated by the level shifter 200, but instead are generated by the entire x clock signals (CLK 1 to CLK x) Some may be reused signals.

The gate driver 120 may include a plurality of gate drive ICs directly formed on the panel 110 to sequentially supply scan signals to the gate lines.

Here, the gate drive integrated circuit formed directly on the panel 110 is also referred to as "GIP (Gate Drive IC in Panel) ".

As described above, the plurality of gate drive integrated circuits included in the gate driver 120 may be formed directly on the panel 110, but the present invention is not limited thereto. For example, the gate driver integrated circuit may be formed on the panel 110 through a tape carrier package (TCP) 110).

On the other hand, each of the plurality of gate drive integrated circuits can receive two clock signals of x clock signals and one dummy clock signal of y dummy clock signals.

One of the two clock signals input to each of the plurality of gate drive integrated circuits is a first clock signal for outputting a scan signal and the other is a second clock signal having an on / off timing opposite to that of the first clock signal.

One dummy clock signal input to each of the plurality of gate drive integrated circuits is a signal that is already turned on when the first clock signal input to the gate drive integrated circuit is turned on.

One dummy clock signal input to each of the plurality of gate drive integrated circuits may be one of x clock signals or a signal having the same on / off timing with one of x clock signals.

On the other hand, each of the plurality of gate drive integrated circuits is turned on by the voltage applied to the gate and outputs a high level voltage (VGH) to the voltage output terminal in accordance with the application of the first clock signal, A first transistor (PMOS) which is turned on by one dummy clock signal applied to a gate and supplies a low level voltage (VGL) to a Q node corresponding to a gate of the pull-up transistor, And a second transistor which is turned on by the second clock signal applied to the gate and applies a low level voltage VGL to the voltage output terminal of the pull-up transistor.

The circuit configuration of each gate drive integrated circuit and the use of the clock signal and dummy clock signal of each gate drive integrated circuit will be described in more detail with reference to FIG.

Hereinafter, the panel 110, the gate driver 120, the gate drive integrated circuit, and the like according to the embodiment briefly described above will be described in more detail.

Hereinafter, the case where the gate drive integrated circuits are driven in the four-phase single feeding mode will be described as a case where the number of clock signals x is 4 and the number of dummy clock signals y is 4, for example. And gate drive integrated circuits are formed directly on the first side and the second side of the panel 110. [

3 is a diagram illustrating gate drive integrated circuits formed in panel 110 according to one embodiment.

Referring to FIG. 3, a gate driver 120 may be formed on the first side and the second side of the panel 110. That is, a plurality of gate drive integrated circuits (GIP 1, GIP 2, ...) included in the gate driver 120 may be formed on the first side and the second side of the panel 110.

On the other hand, the formation positions of the plurality of gate drive integrated circuits (GIP1, GIP2, ...) may be formed on both the first side and the second side of the panel 110 as shown in Fig. 3, But it is not limited thereto and may be formed only on the first side of the panel 110 as shown in Fig.

3, the gate driver 120a formed on the first side of the panel 110 includes GIP 1, GIP 3, GIP 5, GIP 7, The gate driver 120B formed on the side of the gate driver 120 includes GIP2, GIP4, GIP6, GIP8, and so on.

The area where the plurality of gate drive ICs GIP1, GIP2, ... are formed in the panel 110 includes an active area 310 (Active) in which an image is displayed in the panel 110, Area).

Referring to FIG. 3, each of the gate drive ICs GIP 1, GIP 2,... Corresponds to one gate line GL. That is, each gate drive integrated circuit supplies a scan signal to one gate line GL.

In this case, the number of gate drive integrated circuits is equal to the number of gate lines.

As described above, a method in which each gate drive integrated circuit drives a gate line GL by supplying a scan signal to one gate line GL is referred to as a " single feeding method ".

The plurality of gate drive ICs (GIP 1, GIP 2,...) According to one embodiment may receive x clock signals and drive the gate lines, and thus may be driven by an x-phase single feeding scheme. 3, the plurality of gate drive integrated circuits (GIP1, GIP2, ...) are driven by a four-phase single feeding method.

In the four-phase single mode described above, the size and the number of the gate drive integrated circuits are different from the four-phase double feeding method in which the two gate drive integrated circuits on both sides simultaneously supply the scan signals to one gate line And it has a big advantage in implementing my narrow bezel. This advantage will be described later again with reference to Fig.

As shown in FIG. 3, when a plurality of gate drive integrated circuits are formed on the first side and the second side of the panel 110, the four clock signals CLK 1, CLK 2, CKL 3, GIP 3, GIP 5, GIP 7, ...) formed on the first side and gate drive integrated circuits (GIP 2, GIP 4, GIP 6, GIP 8, ).

CLK 1 and CLK 3 of the four clock signals CLK 1, CLK 2, CKL 3 and CLK 4 are connected to the gate drive ICs GIP 1, GIP 3, GIP 5, GIP 7, CLK 2 and CLK 4 of the four clock signals CLK 1, CLK 2, CKL 3 and CLK 4 are input to the gate drive integrated circuits GIP 2, GIP 4, GIP 6 , GIP 8, ...).

The four dummy clock signals D-CLK1, D-CLK2, D-CKL3 and D-CLK4 are connected to the gate drive ICs GIP1, GIP3, GIP5 and GIP7 ..., and gate drive integrated circuits (GIP2, GIP4, GIP6, GIP8, ...) formed on the second side.

D-CLK 2 and D-CLK 4 among the four dummy clock signals D-CLK 1, D-CLK 2, D-CKL 3 and D-CLK 4 are connected to the gate drive IC CLK1, D-CLK2, D-CKL3, and D-CLK4 among the four dummy clock signals D-CLK1, CLK 1 and D-CLK 3 may be input to the gate drive integrated circuits (GIP 2, GIP 4, GIP 6, GIP 8, ...) formed on the second side.

In the following, the clock signal input relationship will be described again from the point of view of the gate drive integrated circuit.

The gate drive ICs GIP1, GIP3, GIP5, GIP7, ... formed on the first side of the panel 110 are driven by using CLK1, D-CLK2, CLK3, D- And supplies a scan signal to the corresponding gate lines GL1, GL3, GL5, GL7, ....

For example, GIP1 supplies Vout (1) as a scan signal to the corresponding gate line (GL1) using CLK1 and GIP3 uses Vout (3) as a scan signal using CLK3 to the corresponding gate line And GIP 5 supplies Vout (5) as a scan signal to the corresponding gate line (GL5) using CLK5, and GIP7 supplies Vout (7) as a scan signal to the corresponding gate And supplies it to the line GL7.

The gate drive ICs (GIP2, GIP4, GIP6, GIP8, ...) formed on the second side of the panel 110 are D-CLK1, CLK2, D-CLK3, To supply the scan signals to the corresponding gate lines GL2, GL4, GL6, GL8, ....

For example, GIP2 supplies Vout (2) as a scan signal to the corresponding gate line GL2 using CLK2, and GIP4 uses VOUT (4) as a scan signal using CLK4 to the corresponding gate line And GIP 6 supplies Vout (6) as a scan signal to the corresponding gate line (GL6) using CLK6 and GIP8 supplies Vout (8) as a scan signal to the corresponding gate To the line GL8.

The dummy clock signals D-CLK 2 and D-CLK 4 input to the gate drive integrated circuits GIP 1, GIP 3, GIP 5, GIP 7, ... formed on the first side of the panel 110, Are clock signals (CLK 2, CLK 4) input to the gate drive integrated circuits (GIP 2, GIP 4, GIP 6, GIP 8, ...) formed on the second side of the panel 110.

That is, after four clock signals CLK 1 to CLK 4 are generated in the level shifter 200, CLK 2 and CLK 4 are applied to the gate drive ICs GIP 2 and GIP 4 formed on the second side of the panel 110 , GIP 6, GIP 8, ...) and also to the gate drive integrated circuits GIP 1, GIP 3, GIP 5, GIP 7, ... formed on the first side of the panel 110 .

The gate drive integrated circuit (GIP2, GIP4, GIP6, GIP8, ...) formed on the second side of the panel 110, together with the gate drive integrated circuit CLK 2 and CLK 4 input to the gate driver ICs GIP 1, GIP 3, GIP 5, GIP 7, GIP 7, ...) are the dummy clock signals.

The dummy clock signals D-CLK 1 and D-CLK 3 inputted to the gate drive integrated circuits GIP 2, GIP 4, GIP 6, GIP 8, (CLK 1, CLK 3) input to the gate drive integrated circuits (GIP 1, GIP 3, GIP 5, GIP 7, ...)

That is, after four clock signals CLK 1 to CLK 4 are generated in the level shifter 200, CLK 1 and CLK 3 are applied to the gate drive ICs GIP 1 and GIP 3 formed on the first side of the panel 110 , GIP 5, GIP 7, ...) and also to the gate drive integrated circuits GIP 2, GIP 4, GIP 6, GIP 8, ... formed on the second side of the panel 110 .

The gate drive integrated circuit (GIP 1, GIP 3, GIP 5, GIP 6, ...) formed on the first side of the panel 110 and the gate drive integrated circuit (GIP 2, GIP 4, GIP 6, GIP 6, GIP 6, GIP 8, ...) formed on the second side of the panel 110, GIP 8, ...).

The four-phase single feeding scheme according to an embodiment uses eight clock signals in the same manner as a general eight-phase single feeding scheme. However, the four-phase feeding scheme according to an embodiment is different from a general eight-phase single feeding scheme that generates eight clock signals CLK 1, CLK 2, ..., CLK 8, Only the four clock signals CLK 1 to CLK 4 are generated and the remaining four clock signals are generated when the four clock signals CLK 1 to CLK 4 actually generated by the level shifter 200 are supplied to the dummy clock signal D - CLK 1 to D-CLK 4).

Therefore, according to the embodiment, since the number of clock signals to be actually generated can be reduced, it is possible to reduce the number of logic blocks in the level shifter 200, which is a clock signal generating structure, It becomes simple.

The four dummy clock signals D-CLK 1 to D-CLK 4 in the four-phase single feeding scheme according to the embodiment are the general clock signals CLK 1 to CLK 4 that can be the scan signal output voltages The sensitivity to the RC delay (Delay) is very low as compared with the general clock signals (CLK1 to CLK4).

Therefore, when designing the signal wiring for transferring the dummy clock signals D-CLK 1 to D-CLK 4, it is not necessary to increase the line width in order to reduce the wiring resistance.

In other words, instead of using a common clock signal for the scan signal output, since the dummy clock signals (D-CLK 1 to D-CLK 4) with low sensitivity to RC delay are used, The signal wiring design region can be reduced as compared with a general 8-phase single feeding method which must be generated.

Due to the reduction in the area of the signal wiring design, the narrow bezel is very effective for the implementation.

The effect according to this embodiment will be even more effective when the narrow bezel is applied to the display of the mobile terminal, which is the most important element.

3, four clock signals CLK 1, CLK 2, CLK 3, CLK 3, CLK 3, CLK 3, CLK 3, CLK 3, CLK 3, CLK4 will be described with reference to Fig. 4, and the on-off timing relationship between the four clock signals CLK1, CLK2, CLK3, and CLK4 will be described.

4 is a diagram illustrating a clock signal according to an embodiment.

4, the level shifter 200 generates a level shifter 200 based on the clock information CLOCK input from the timing controller 140 and the high level voltage VGH and the low level voltage VGL supplied from the power supply unit 210 Thereby generating four clock signals CLK 1, CLK 2, CKL 3, and CLK 4.

The level shifter 200 outputs the generated x clock signals CLK 1 to CLK 4 to the gate driver 120 that drives the four phases of the clock signals CLK 1 to CLK 4 as well as four clock signals CLK 1 to CLK 4) are further reused to output the four dummy clock signals D-CLK1, D-CLK2, D-CLK3, and D-CLK4 to the gate driver 120.

Of the four clock signals CLK 1, CLK 2, CKL 3, and CLK 4 generated by the level shifter 200, CLK 1 and CLK 3 are turned on and off at the opposite timing, and CLK 2 and CLK 4 are also turned on and off Clock signals are the opposite of timing.

CLK 1 and CLK 2 are delayed clock signals. One of CLK 1 and CLK 2 is delayed by a predetermined time compared with the other, and when one of them is on, the other is in a state of being already on , And when one is turned off, the other one is already turned off. The same is true for CLK 2 and CLK 3, CLK 3 and CLK 4, and CLK 4 and CLK 1.

3, CLK 1 and CLK 3 of the four clock signals CLK 1, CLK 2, CKL 3 and CLK 4 are connected to the gate of the plurality of gate drive integrated circuits, Are input to the drive integrated circuits (GIP 1, GIP 3, ....). Of the four clock signals CLK 1, CLK 2, CKL 3, and CLK 4, CLK 2 and CLK 4 are connected to a gate drive integrated circuit (GIP 2) formed on the second side of the panel 110 among the plurality of gate drive integrated circuits , GIP 4, ....).

On the other hand, the clock signals input to the gate drive integrated circuits (GIP 1, GIP 3, ....) formed on the first side of the panel 110 are connected in such a manner that their on / off timings are opposite to each other on the basis of any one of the clock signals It should include a clock signal. That is, CLK 1 and CLK 3 are clock signals in this opposite relationship.

The clock signals input to the gate drive integrated circuits GIP 1, GIP 3, ... formed on the first side of the panel 110 are clocked by one of the clock signals, There must be a clock signal already on.

To this end, in one embodiment, as a clock signal in a delay relationship with CLK 1 and CLK 3 input to gate drive integrated circuits (GIP 1, GIP 3, ...) formed on the first side of the panel 110 Dummy clock signals (D-CLK 2, D-CLK 4) that reuse CLK 2 and CLK 4 are used.

CLK 1 and CLK 3 and two dummy clock signals D-CLK 2 and D-CLK 3 are provided to the gate drive integrated circuits GIP 1, GIP 3, ... formed on the first side of the panel 110, CLK 4 is input.

Similarly, the clock signals input to the gate drive integrated circuits (GIP2, GIP2, ....) formed on the second side of the panel 110 have the on / off timings in the opposite relationship with respect to any one of the clock signals It should include a clock signal. That is, CLK 2 and CLK 4 are clock signals in this opposite relationship.

The clock signals input to the gate drive integrated circuits (GIP2, GIP4, ....) formed on the second side of the panel 110 are clocked by one of the clock signals, There must be a clock signal already on.

To this end, in one embodiment, as a clock signal in a delay relationship with CLK 2 and CLK 2 input to the gate drive integrated circuits (GIP 2, GIP 2, ...) formed on the second side of the panel 110 Dummy clock signals (D-CLK 1, D-CLK 3) that reuse CLK 1 and CLK 3 are used.

CLK 2 and CLK 4 and two dummy clock signals D-CLK 1 and D-CLK 2 are provided to the gate drive integrated circuits GIP 2, GIP 4, ... formed on the second side of the panel 110, CLK 3 is input.

The plurality of gate drive integrated circuits (GIP 1, GIP 2,...) Illustrated in FIG. 3 operate in the same manner. Hereinafter, the circuit configuration of the gate drive integrated circuit (GIP) will be described in detail with reference to FIG. 5, and its operation will be described with reference to FIGS. 6A to 6I.

5 is a circuit diagram of a gate drive integrated circuit (GIP) formed on the panel 110 according to an embodiment.

Referring to FIG. 5, the gate drive IC GIP N of the N-th stage receives CLK 1 and supplies a corresponding output voltage Vout (N) to the N-th gate line GL (N) Is one of the gate drive integrated circuits (GIP 1, GIP 3, ...) formed.

5, since the gate drive integrated circuit GIP N of the N-th stage receives CLK 1 as a clock signal (first clock signal) for outputting a scan signal, the on-off timing is opposite to that of CLK 1 CLK3 which is already inputted at the timing when CLK1 is turned on is further input as the dummy clock signal (D-CLK4).

5, the gate drive IC GIP N of the N-th stage includes seven transistors T6, T3C, T3N, T3R, T7C, and T7D for driving in a four- And one capacitor Cout. In addition to receiving two clock signals CLK 1 and CLK 4 and one dummy clock signal D-CLK 4 as described above, The output values Vout (N-2), Vout (N-1), and Vout (N + 2) of the stage are further input.

Among the output values Vout (N-2), Vout (N + 2), and Vout (N-1) of the other three stages to which the gate drive IC GIP N of the N- 1) denotes an output voltage at the (N-2) th stage which is two horizontal periods (2H) ahead of the current N-th stage and Vout (N-2) (N + 1) -th stage, and Vout (N + 2) means an output voltage at the (N + 2) -th stage that is two horizontal periods (2H) shorter than the current N-th stage .

5, when CLK 1 is expressed as a first clock signal (main clock signal) in the gate drive IC GIP N of the N-th stage, CLK 2 is expressed as CLK (N + 1) in the sense that CLK 2 is input as the first clock signal (main clock signal) to the gate drive integrated circuit GIP N + 1 of the (N + CLK 3 is expressed as CLK (N + 2) in the sense that it is input as the first clock signal (main clock signal) to the gate drive integrated circuit (GIP N + 2) of the (N + May be expressed as CLK (N-1) in the sense that it is input as the first clock signal (main clock signal) to the gate drive integrated circuit GIP N-1 of the (N + 1) th stage.

The connection structure between the transistors in the gate drive integrated circuit (GIP N) of the N-th stage illustrated in FIG. 5 will be briefly described.

When the gate of the pull-up transistor T6 is connected to the Q node and the drain thereof is connected to the first clock signal supply terminal for supplying the first clock signal CLK1 for the scan signal output, the source outputs Vout (N) Respectively.

A capacitor Cout is connected between the gate and the source of the pull-up transistor T6, which is responsible for the voltage change of the Q node while charging and discharging are repeated.

The gate and the drain of the transistor T7D are connected to the scan signal output terminal at the same time and the source is connected to the first clock signal supply terminal.

The gate of the transistor T7C is connected to a second clock signal supply terminal for supplying a first clock signal CLK1 and a second clock signal CLK3 which are opposite in on / off timing, and a drain and a source are connected to a scan signal output terminal and a ground voltage VSS Respectively.

The gate and the drain of the transistor T1 are simultaneously connected to the (N-2) th stage output voltage supply terminal for supplying the output voltage Vout (N-2) at the (N-2) th stage, and the source is connected to the Q node.

The gate of the transistor T3N is connected to the (N + 2) -th stage output voltage supply terminal for supplying the output voltage Vout (N + 2) of the (N + 2) th stage, the drain is connected to the Q node, and the source is connected to the base- .

The gate of the transistor T3R is connected to the reset signal supply terminal for supplying the reset signal Reset, the drain is connected to the Q node, and the source is connected to the base low voltage supply terminal.

The gate of the transistor T3C is connected to a dummy clock signal supply terminal which supplies the same dummy clock signal D-CLK4 as CLK4 (CLK (N-1)), the drain is connected to the Q node, (N-1) th stage output voltage supply terminal for supplying the output voltage Vout (N-1) of the N-th stage.

The gate drive integrated circuit (GIP) illustrated by way of example in FIG. 5 is merely an example for convenience of explanation, and is not limited to this, and may include one or more of x clock signals, one or more y clock signals, The circuit configuration can be made in any circuit type as long as it can receive the output value of another stage and output an output voltage as a scan signal to the gate line.

Operation procedures for the gate drive integrated circuit (GIP N) of the N-th stage described with reference to FIG. 5 will be described with reference to FIGS. 6A to 6I.

6A to 6I are diagrams for explaining an operation procedure of a gate drive integrated circuit formed on a panel 110 according to an embodiment.

In each of Figs. 6A to 6I, the state of the gate drive integrated circuit (GIP N) in the Nth stage in Fig. 5 and the signal timing diagram (block display portion) are shown together for each operation procedure.

In the following description, CLK (N), CLK (N + 1), CLK (N + 2) and CLK N-1) are also described. Since the gate drive integrated circuit GIP N of the N-th stage receives CLK 1 as the first clock signal involved in the scan signal output, CLK 4, which is already on at the timing when CLK 1 is turned on, CLK (N-1) is a dummy clock signal of the gate drive integrated circuit GIP N of the N-th stage.

In the operating step of FIG. 6A, the transistor T3R is turned on by a reset signal (Reset) to maintain the voltage of the Q node at the low level voltage (VGL = VSS). At this time, the voltage Vout (N) at the scan signal output terminal is the low level voltage (VGL).

Next, in the operation step of FIG. 6B, the output voltage Vout (N-2) of the (N-2) th stage is changed to the high level voltage VGH, whereby the transistor T1 is turned on, The voltage of the node is changed to the high level voltage VGH.

At this time, CLK 3, that is, CLK (N + 2) is also changed to the high level voltage VGH. As a result, the transistor T7C is turned on, and the low level voltage VGL supplied from the base low voltage supply terminal VSS is supplied to the scan signal output terminal, so that Vout (N) is maintained at the low level voltage VGL do.

In the operation step of FIG. 6B, a constant potential difference (DELTA V = VGH-VGL) is generated across the capacitor Cout connected between the gate and the source of the transistor T6 to charge the capacitor Cout.

Next, in the operation step of FIG. 6C, CLK (N-1), that is, CLK 4 acting as a dummy clock signal in the gate drive integrated circuit of the Nth stage is changed to the high level voltage VGH, The output voltage Vout (N-1) at the first stage is changed to the high level voltage VGH, and the transistor T3C is turned on.

At this time, the transistor T1 is also turned on continuously, and the voltage of the Q node is maintained at the high level voltage VGH.

At this time, the transistor T7C is also turned on continuously, and thus Vout (N) is kept at the low level voltage VGL.

In the operation step of Fig. 6C, a constant potential difference (DELTA V = VGH-VGL) is continuously maintained at both ends of the capacitor Cout.

Next, in the operation step of FIG. 6D, the first clock signal CLK (N) CLK 1 directly involved in the scan signal output in the Nth stage is changed to the high level voltage VGH. As a result, the transistor T6 that has already satisfied the turn-on condition at the previous stage is turned on as a ratio.

As a result, the voltage Vout (N) at the scan signal output terminal is changed to the high level voltage VGH and the high level voltage VGH (N) is output as the scan signal to the Nth gate line GL (N).

As described above, in order to maintain a constant potential difference (DELTA V = VGH-VGL) of the capacitor Cout as the voltage Vout (N) of the scan signal output terminal changes to the high level voltage VGH, Is boosted by the level voltage (VGH).

CLK 1, which is CLK (N) and CLK 3 (CLK (N + 2)), which are opposite in on-off timing, are changed to the low level voltage VGL in the operation step of FIG. 6D, whereby the transistor T7C is turned off, The voltage Vout (N) of the scan signal output terminal can be changed to the high level voltage VGH.

In the operation step of FIG. 6D, the dummy clock signal CLK (N-1) maintains the high level voltage VGH and the output voltage Vout (N-1) at the (N-1) , The transistor T3C is kept turned on.

CLK (N-1) serving as the dummy clock signal D-CLK4 is changed to the low level voltage VGL in the operation step of FIG. 6E, and the output transfer of the (N-1) Level voltage VGL. Thus, the transistor T3C is turned off.

At this time, the voltage of the Q node and the boosted voltage are maintained and the voltage Vout (N) of the scan signal output terminal is also maintained at the high level voltage (VGH) because CLK 1 which is CLK (N) And Vout (N) of the high level voltage VGH is continuously output as a scan signal to the N-th gate line GL (N).

Next, in the operation step of FIG. 6F, the output voltage Vout (N + 2) of the (N + 2) -th stage is changed to the high level voltage VGH, and the transistor T3N is turned on.

Thus, the low level voltage VGL, which is the base low voltage VSS supplied from the induced voltage supply terminal, is supplied to the Q node so that the voltage of the Q node changes from the boosted voltage 2 * VGH to the low level voltage VGL Reset.

At this time, CLK 1, which is CLK (N), is changed to the low level voltage VGL, and transistor T6 is turned off.

At this time, CLK 3, which is CLK (N + 2), changes to the high level voltage VGH, turning on the transistor T7C, and the low level voltage VGL supplied from the base low voltage supply end is supplied to the scan signal output terminal. As a result, the voltage of the scan signal output terminal is reset to the low level voltage VGL.

In this operation step of FIG. 6F, the capacitor Cout is discharged.

Next, in the operation step of FIG. 6G, CLK (N-1) serving as the dummy clock signal D-CLK4 is changed to the high level voltage VGH, the transistor T3C is turned on, Vout (N-1) which is the voltage VGL is applied to the Q node. Thus, the Q node is maintained at the low level voltage VGL.

At this time, CLK 3, which is CLK (N + 2), is maintained at the high level voltage VGH, and the transistor T7C is continuously turned on. As a result, the low level voltage VGL supplied from the base- Is continuously supplied to the scan signal output terminal. That is, the voltage of the scan signal output terminal is maintained at the low level voltage VGL.

6H, the dummy clock signal CLK (N-1) maintains the high level voltage VGH and the output voltage Vout (N-1) at the (N-1) The low level voltage VGL is supplied to the Q node by the transistor T3C while maintaining the voltage VGL. Thus, the Q node maintains the low level voltage VGL.

At this time, CLK (N + 2) changes from the high level voltage VGH to the low level voltage VGL, and the transistor T7C is turned off.

Next, in the operation step of FIG. 6I, CLK (N + 2) is changed from the low level voltage VGL to the high level voltage VGH so that the transistor T7C is turned on and the voltage Vout Level voltage VGL.

FIG. 7 is a view for explaining the narrow bezel effect of the panel 110 according to one embodiment.

7 is a view for explaining the effect of reducing the size of the bezel by driving a plurality of gate drive integrated circuits included in the gate driver 120 in a single feeding manner, 7B shows a case where scan signals Vout (1) and Vout (2) are supplied to two pixels P1 and P2 in a double feeding manner, (1) and Vout (2) are supplied to the scan electrodes P1 and P2 in a single feeding manner.

Referring to FIG. 7A, two gate drive ICs GIP 1 and GIP 1 'formed on the panel 110 connected to the first gate line GL 1 formed on the panel 110 are connected to the first gate line GL 1, , The scan signal Vout (1) is simultaneously supplied from the both sides to the P1 pixel through the first gate line GL1. 7A, the two gate drive ICs GIP 2 and GIP 2 'formed on the panel 110 and connected to the second gate line GL 2 formed on the panel 110, The scan signal Vout (2) is simultaneously supplied from the both sides to the P2 pixel via the second gate line GL2.

7A, when a gate drive integrated circuit that is driven by a double feeding type is formed on the panel 110, the length La of one gate drive integrated circuit is smaller than the pixel length Lp of one pixel It should not be large (La ≤ Lp).

The reason for this structure is that gate drive ICs (GIP 1, GIP 1 ') for supplying the scan signal Vout (1) to the P1 pixel must be formed on both sides (first side and second side) (GIP 2, GIP 2 ') for supplying the scan signal Vout (2) to the pixels must also be formed on both sides (the first side and the second side).

7A, the width Wa of each gate drive integrated circuit (GIP 1, GIP 1 ', GIP 2, GIP 2') driven in the double feeding mode is determined by the gate drive IC 1, GIP 1 ', GIP 2, GIP 2').

7B, one gate drive integrated circuit (GIP 1) connected to the first gate line GL1 formed on the panel 110 and connected to the left side (first side) and formed on the panel 110 , The scan signal Vout (1) is supplied from the left side to the P1 pixel through the first gate line GL1 to be driven by the single feeding method. 7B, one gate drive IC GIP2 connected to the second gate line GL2 formed on the panel 110 and connected to the right side (second side) of the panel 110, , The scan signal Vout (2) is supplied from the right side to the P2 pixel through the second gate line GL2 because it is driven by the single feeding method.

7 (b), when the gate drive integrated circuit is formed on the panel 110, the length L of one gate drive integrated circuit is equal to or larger than the pixel length Lp and the pixel length Lp) (Lp? L? 2Lp).

The reason for this structure is that the gate drive integrated circuit GIP1 for supplying the scan signal Vout (1) to the P1 pixel may be formed only on the left side (first side), and the scan signal Vout (2) This is because the gate drive integrated circuit GIP 2 to be supplied may be formed only on the right side (second side).

7B, the width W of each gate drive integrated circuit (GIP 1, GIP 2) driven in the single feeding mode is determined by the length of each gate drive IC (GIP 1, GIP 2) L).

7B, the width W of each of the plurality of gate drive integrated circuits GIP 1 and GIP 2 is equal to the length L of each of the plurality of gate drive integrated circuits GIP 1 and GIP 2 ) May be narrower corresponding to the pixel length Lp.

7A showing the structure in which the double-feeding type gate drive integrated circuit is formed on the panel 110 and FIG. 7B showing the structure in which the single- 7A and 7B, the single-feeding type gate drive integrated circuit shown in FIG. 7B has a longer length in the vertical direction than the double-feeding type gate drive integrated circuit shown in FIG. 7A (L > La).

Thus, the single-feeding type gate drive integrated circuit shown in FIG. 7 (b) is formed longer in the vertical direction than the double-feeding type gate drive integrated circuit shown in FIG. 7 (a) There is a room for forming a shorter width (W <Wa).

Thus, as shown in Fig. 7B, by forming the gate driving ICs of the single feeding type on the panel 110, the gate driving ICs of the double feeding type shown in Fig. The size of the bezel of each of the first side and the second side can be reduced by? W (= Wa-W).

That is, as shown in FIG. 7 (b), by forming a single feeding type gate drive integrated circuit on the panel 110, it is possible to obtain an effect of further helping the implementation of the narrow bezel.

On the other hand, the plurality of gate drive integrated circuits can be formed on both sides (first side and second side) of the panel 110 as shown in Fig. 3, It may be formed only on one side of the two sides.

8 shows an alternative embodiment in which a plurality of gate drive integrated circuits are formed only on one side of the panel 110. [

8 is a view showing a panel 110 according to another embodiment.

Referring to FIG. 8, a plurality of gate drive integrated circuits (GIP 1, GIP 2, GIP 3, GIP 4, GIP 5, GIP 6, GIP 7, GIP 8, Is formed only on the first side of the inactive area which is the outer area of the active area 810 of the panel 110. [

8, a plurality of gate drive ICs GIP1, GIP2, GIP3, and GIP3 formed only on the first side of the panel 110 when the number of clock signals x is four and the number of dummy clock signals y is four, GIP 4, GIP 5, GIP 6, GIP 7, GIP 8, ...) sequentially receives CLK 1, CLK 2, CLK 3 and CLK 4 as a first clock signal related to the scan signal output.

Each of the plurality of gate drive integrated circuits (GIP1, GIP2, GIP3, GIP4, GIP5, GIP6, GIP7, GIP8, ...) includes CLK1, CLK2, CLK3 and CLK4 CLK 1, CLK 2, CLK 3, and CLK 4, which are not only sequentially input one by one as a first clock signal related to the scan signal output, but also have a second clock signal which is opposite in on-off timing to the input first clock signal Receive input.

Each of the plurality of gate drive ICs (GIP1, GIP2, GIP3, GIP4, GIP5, GIP6, GIP7, GIP8, ...) A clock signal that is already on among CLK 1, CLK 2, CLK 3, and CLK 4 is further input as a dummy clock signal.

For example, the gate drive integrated circuit GIP 1 of the first stage connected to the first gate line GL 1 receives CLK 1 as a first clock signal, and the on / off timing is opposite to CLK 1 as shown in FIG. 4 CLK &lt; / RTI &gt; 3 as a second clock signal. Also, GIP 1 receives CLK 4, which is already on when CLK 1 turns on, as a dummy clock signal.

The gate drive integrated circuit GIP N of the N-th stage connected to the N-th gate line GL N receives the CLK (N) as the first clock signal and receives the CLK (N) and the on- CLK (N + 2) whose timing is the opposite is further input as the second clock signal. Further, GIP N receives CLK (N-1), which is already turned on when CLK (N) turns on, as a dummy clock signal.

The circuit structure of each of the gate drive integrated circuits formed in the panel 110 according to another embodiment shown in Fig. 8 may be the same as that of Fig. 5, and the driving operation may be performed by the operation procedures described with reference to Figs. 6A to 6I Can be performed in the same manner.

As described above, according to the present invention, it is possible to provide a gate driver that has a simple circuit structure and enables efficient gate driving even when only a small number of clock signals are generated, and its panel and display device.

Further, according to the present invention, it is possible to provide a gate driver capable of further reducing the size of the bezel through efficient gate driving of the single feeding type, and its panel and display device.

In addition, according to the present invention, by using a dummy clock signal having a small sensitivity to RC delay, it is possible to efficiently perform gate driving even when only a smaller number of clock signals are generated than the required number of clock signals for gate driving, There is no need to increase the line width in order to reduce the resistance, thereby reducing the signal wiring design area in the panel, thereby making it possible to further make the narrow bezel, and an effect of providing the panel and the display device .

In addition, according to the present invention, a gate driver capable of simplifying a logic block according to a clock signal generation by enabling efficient gate driving even when generating only a fewer number of clock signals than a necessary number of clock signals for gate driving And a panel and a display device therefor.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Panel
120: gate driver
130: Data driver
140: Timing controller
200: Level shifter

Claims (13)

A panel formed by intersecting gate lines and data lines; And
And a gate driver sequentially supplying a scan signal to the gate lines based on the input x clock signals and the y dummy clock signals. The method according to claim 1,
And y is a natural number of 2 or more. The method according to claim 1,
Wherein the y dummy clock signals are all or part of the x clock signals. The method according to claim 1,
The gate driver includes:
And a plurality of gate drive integrated circuits formed directly on the panel to sequentially supply scan signals to the gate lines. 5. The method of claim 4,
The plurality of gate drive integrated circuits comprising:
Wherein the driving circuit is formed on the first side of the panel or on the first side and the second side and is driven in an x-phase single feeding mode. 6. The method of claim 5,
When the plurality of gate drive integrated circuits are formed on the first side and the second side of the panel,
The length of each of the plurality of gate drive integrated circuits is not less than the pixel length and not more than twice the pixel length,
Wherein a width of each of the plurality of gate drive integrated circuits is correspondingly narrower than a length of each of the plurality of gate drive integrated circuits is longer than the pixel length. 5. The method of claim 4,
When the plurality of gate drive integrated circuits are divided and formed on the first side and the second side of the panel,
Wherein the x clock signals are divided into a gate drive integrated circuit formed on the first side and a gate drive integrated circuit formed on the second side,
Wherein the y dummy clock signals are divided into a gate drive integrated circuit formed on the first side and a gate drive integrated circuit formed on the second side. 8. The method of claim 7,
The dummy clock signal input to the gate drive integrated circuit formed on the first side is the same as the clock signal input to the gate drive integrated circuit formed on the second side,
Wherein the dummy clock signal input to the gate drive integrated circuit formed on the second side is the same as the clock signal input to the gate drive integrated circuit formed on the first side. The method according to claim 1,
Wherein each of the plurality of gate drive integrated circuits includes:
One of the two clock signals of the x clock signals and the dummy clock signal of the y dummy clock signals,
One of the two clock signals is a first clock signal for outputting a scan signal and the other is a second clock signal having an on / off state opposite to that of the first clock signal.
Wherein the one dummy clock signal is a dummy clock signal that is already turned on when the first clock signal is turned on. 10. The method of claim 9,
Wherein each of the plurality of gate drive integrated circuits includes:
A pull-up transistor that is turned on by a voltage applied to a gate and outputs a high level voltage to a voltage output terminal in response to the application of the first clock signal, thereby supplying the scan signal to the gate line;
A transistor for turning on by one dummy clock signal applied to a gate and supplying a low level voltage to a Q node corresponding to a gate of the pull-up transistor;
And a transistor which is turned on by the second clock signal applied to the gate and applies a low level voltage to the voltage output terminal of the pull-up transistor. The method according to claim 1,
Generates the x clock signals based on the clock information input from the timing controller and the high level voltage and the low level voltage supplied from the power supply unit,
Further comprising a level shifter for outputting the x clock signals to the gate driver driving x phase, wherein the level shifter further outputs all or a part of the x clock signals to the gate driver as the y dummy clock signals, . Data lines formed in one direction;
Gate lines intersecting with the data lines; And
A gate for sequentially supplying a scan signal to the gate lines based on the input x clock signals and y dummy clock signals formed on the first side or the first side of the inactive region, A panel comprising drive integrated circuits. And a plurality of gate drive integrated circuits sequentially supplying scan signals to the gate lines based on the input x clock signals and the y dummy clock signals,
Each of the plurality of gate drive integrated circuits receives one or more dummy clock signals of y dummy clock signals,
Wherein at least one dummy clock signal input to each of the plurality of gate drive integrated circuits is part of the x clock signals or has the same on-off timing as some of the x clock signals.

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