KR102591850B1 - Display device, display panel, and gate driving circuit - Google Patents

Abstract

Embodiments of the present invention relate to a display device, a display panel, and a gate driving circuit, and more specifically, each corresponds to M clusters including N different subpixel lines, and includes a first main stage circuit and a second main stage circuit. In M gate driving units including a main stage circuit, cluster driving is performed using an intermediate stage circuit disposed between two adjacent gate driving units, thereby reducing the number of clock signals (number of phases of the clock signal). Through this, the number of clock wiring can be reduced and the bezel size can be made smaller.

Description

Display device, display panel, and gate driving circuit {DISPLAY DEVICE, DISPLAY PANEL, AND GATE DRIVING CIRCUIT}

Embodiments of the present invention relate to display devices, display panels, and gate driving circuits.

As the information society develops, various types of display devices for displaying images are being developed. The display device includes a display panel with a plurality of subpixels connected to a plurality of data lines and a plurality of gate lines, a data driving circuit for driving the plurality of data lines, and a gate driving circuit for driving the plurality of gate lines. can do.

The gate driving circuit of the display device uses clock signals having different phases to generate a gate signal and outputs it to gate lines. Accordingly, clock wires for transmitting clock signals to the gate driving circuit are disposed on the display panel.

When driving a display device becomes more complicated or necessary functions (e.g. compensation, etc.) are added, the number of clock signal phases required must increase. As a result, the number of clock wires arranged on the display panel also increases, causing a problem in that the bezel size increases.

Embodiments of the present invention can provide a display device, display panel, and gate driving circuit that can reduce the number of clock signals (number of phases of the clock signal), thereby reducing the number of clock wires and reducing the bezel size. there is.

In addition, embodiments of the present invention provide a display device and display panel that enable normal operation while reducing the number of clock signals (number of phases of the clock signal) when driving becomes complicated or necessary functions (e.g. compensation, etc.) are added. and a gate driving circuit.

Additionally, embodiments of the present invention can provide a display device, display panel, and gate driving circuit that perform cluster driving that can secure sufficient sensing time during display driving.

In one aspect, embodiments of the present invention include a display panel on which a plurality of data lines and a plurality of gate lines are arranged and including a plurality of subpixels, a data driving circuit that drives the plurality of data lines, and a plurality of gates. A display device including a gate driving circuit that drives a line, a data driving circuit, and a controller that controls the gate driving circuit can be provided.

A plurality of subpixels are grouped into M clusters, each of the M(M≥2) clusters includes N(N≥2) subpixel lines, and is placed on the N subpixel lines included in each of the M clusters. The subpixels can emit light simultaneously.

The gate driving circuit may include M gate driving units corresponding to the M clusters, and an intermediate stage circuit disposed between two adjacent gate driving units among the M gate driving units. Each of the M gate driving units may include a first main stage circuit and a second main stage circuit.

The M gate driving units include an (i-1)th gate driving unit that drives gate lines arranged in the (i-1)th cluster among the M clusters, and a (i-1)th gate driving unit that drives gate lines arranged in the ith cluster among the M clusters. It may include an i-th gate driving unit that drives and an (i+1)-th gate driving unit that drives gate lines arranged in the (i+1)-th cluster among the M clusters.

The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit outputs an intermediate carry signal to the ith gate driving unit and the (i+1)-th gate driving unit, and outputs an intermediate carry signal to the i-th gate driving unit. The intermediate carry signal can be output to the driving unit as a reset signal of the ith gate driving unit, and the intermediate carry signal can be output to the (i+1)th gate driving unit as a set signal of the (i+1)th gate driving unit. .

The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit may receive a carry signal from the i-th gate driving unit and the (i+1)-th gate driving unit. In this case, the carry signal input from the i-th gate driving unit may be a set signal of the mid-stage circuit, and the carry signal input from the (i+1)-th gate driving unit may be a reset signal of the mid-stage circuit.

Differently, the intermediate stage circuit disposed between the ith gate driving unit and the (i+1)th gate driving unit is from the intermediate stage circuit disposed between the (i-1)th gate driving unit and the ith gate driving unit. The intermediate carry signal can be input as a set signal, and the intermediate carry signal can be input as a reset signal from the intermediate stage circuit placed between the (i+1)th gate driving unit and the next (i+2)th gate driving unit. .

In another aspect, embodiments of the present invention are arranged in an active area, a plurality of subpixels connected to a plurality of data lines and a plurality of gate lines, a non-active area outside the active area, and a plurality of subpixels A display panel including a gate driving circuit connected to a gate line can be provided.

A plurality of subpixels are grouped into M clusters, each of the M(M≥2) clusters includes N(N≥2) subpixel lines, and is placed on the N subpixel lines included in each of the M clusters. The subpixels can emit light simultaneously.

The gate driving circuit corresponds to M clusters and is disposed between M gate driving units each including a first main stage circuit and a second main stage circuit, and two adjacent gate driving units among the M gate driving units. May include mid-stage circuitry.

The M gate driving units include an (i-1)th gate driving unit that drives gate lines arranged in the (i-1)th cluster among the M clusters, and a (i-1)th gate driving unit that drives gate lines arranged in the ith cluster among the M clusters. It may include an i-th gate driving unit that drives and an (i+1)-th gate driving unit that drives gate lines arranged in the (i+1)-th cluster among the M clusters.

The middle stage circuit disposed between the ith gate driving unit and the (i+1)th gate driving unit receives a carry signal from the ith gate driving unit and the (i+1)th gate driving unit, and drives the ith gate. An intermediate carry signal can be output to the unit and the (i+1)th gate driving unit.

The mid-stage circuit disposed between the ith gate driving unit and the (i+1)-th gate driving unit receives a carry signal from the ith gate driving unit as a set signal of the mid-stage circuit, and drives the (i+1)-th gate. A carry signal is input from the driving unit as a reset signal of the intermediate stage circuit, an intermediate carry signal is output to the i-th gate driving unit as a reset signal of the i-th gate driving unit, and an intermediate carry is output to the (i+1)-th gate driving unit. The signal can be output as a set signal of the (i+1)th gate driving unit. In this case, the display panel may further include (N+4) clock wires arranged in the non-active area.

In another aspect, embodiments of the present invention are arranged in an active area, a plurality of subpixels connected to a plurality of data lines and a plurality of gate lines, a non-active area outside the active area, and a plurality of subpixels A display panel including a gate driving circuit connected to a gate line can be provided.

A plurality of subpixels are grouped into M clusters, each of the M(M≥2) clusters includes N(N≥2) subpixel lines, and is placed on the N subpixel lines included in each of the M clusters. The subpixels can emit light simultaneously.

The gate driving circuit corresponds to M clusters and is disposed between M gate driving units each including a first main stage circuit and a second main stage circuit, and two adjacent gate driving units among the M gate driving units. May include mid-stage circuitry.

The M gate driving units include an (i-1)th gate driving unit that drives gate lines arranged in the (i-1)th cluster among the M clusters, and a (i-1)th gate driving unit that drives gate lines arranged in the ith cluster among the M clusters. It may include an i-th gate driving unit that drives and an (i+1)-th gate driving unit that drives gate lines arranged in the (i+1)-th cluster among the M clusters.

The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit outputs an intermediate carry signal to the ith gate driving unit and the (i+1)-th gate driving unit, and outputs an intermediate carry signal to the i-th gate driving unit. The intermediate carry signal can be output to the driving unit as a reset signal of the ith gate driving unit, and the intermediate carry signal can be output to the (i+1)th gate driving unit as a set signal of the (i+1)th gate driving unit. .

The intermediate stage circuit disposed between the ith gate driving unit and the (i+1)th gate driving unit receives an intermediate carry signal from the intermediate stage circuit disposed between the (i-1)th gate driving unit and the ith gate driving unit. can be input as a set signal, and an intermediate carry signal can be input as a reset signal from an intermediate stage circuit disposed between the (i+1)-th gate driving unit and the next (i+2)-th gate driving unit. In this case, this display panel may further include (N+5) clock wires arranged in the non-active area.

In another aspect, embodiments of the present invention are arranged in an active area, a plurality of subpixels connected to a plurality of data lines and a plurality of gate lines, a non-active area outside the active area, and a plurality of subpixels A display panel including a gate driving circuit connected to a gate line can be provided.

Multiple subpixels are grouped into M clusters, and each of the M clusters may include N subpixel lines. M may be a natural number of 2 or more, and N may be a natural number of 2 or more.

Subpixels arranged on N subpixel lines included in each of M clusters may emit light simultaneously.

Depending on the set and reset processing method of the intermediate stage circuit, the display panel may further include (N+4) clock wires that are placed in the non-active area and supply (N+4) clock signals to the gate driving circuit. , It is disposed in the non-active area and may further include (N+5) clock wires that supply (N+5) clock signals to the gate driving circuit.

The multiple gate lines may include multiple scan lines, multiple sense lines, and multiple light emission control lines.

Each of the plurality of subpixels includes a light-emitting device, a driving transistor that drives the light-emitting device, a scan transistor that controls the connection between the first node of the driving transistor and the corresponding data line in response to a scan signal, and a first node of the driving transistor. It may include a storage capacitor electrically connected between and the second node.

All or part of the plurality of subpixels include a sense transistor that controls the connection between the second node of the driving transistor and the corresponding reference line in response to a sense signal, and a light emission control transistor that controls light emission of the light emitting device in response to a light emission control signal. It may further include one or more of the following.

Gate nodes of sense transistors arranged in N subpixel lines may be electrically connected or sense signals may be applied simultaneously.

The gate nodes of the emission control transistors arranged in the N subpixel lines may be electrically connected or an emission control signal may be applied simultaneously.

In another aspect, embodiments of the present invention include M gate driving units each corresponding to M (M ≥ 2) clusters including different N (N ≥ 2) subpixel lines, and M gate driving units. A gate driving circuit including an intermediate stage circuit disposed between two adjacent gate driving units among the units may be provided.

Each of the M gate driving units may include a first main stage circuit and a second main stage circuit.

The M gate driving units include an (i-1)th gate driving unit that drives gate lines arranged in the (i-1)th cluster among the M clusters, and a (i-1)th gate driving unit that drives gate lines arranged in the ith cluster among the M clusters. It may include an i-th gate driving unit that drives and an (i+1)-th gate driving unit that drives gate lines arranged in the (i+1)-th cluster among the M clusters.

The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit outputs an intermediate carry signal to the ith gate driving unit and the (i+1)-th gate driving unit, and outputs an intermediate carry signal to the i-th gate driving unit. The intermediate carry signal can be output to the driving unit as a reset signal of the ith gate driving unit, and the intermediate carry signal can be output to the (i+1)th gate driving unit as a set signal of the (i+1)th gate driving unit. .

The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit may receive a carry signal from the i-th gate driving unit as a set signal of the intermediate stage circuit. Here, the carry signal input from the i-th gate driving unit may be a set signal of the mid-stage circuit, and the carry signal input from the (i+1)-th gate driving unit may be a reset signal of the mid-stage circuit.

Differently, the intermediate stage circuit disposed between the ith gate driving unit and the (i+1)th gate driving unit is from the intermediate stage circuit disposed between the (i-1)th gate driving unit and the ith gate driving unit. The intermediate carry signal can be input as a set signal, and the intermediate carry signal can be input as a reset signal from the intermediate stage circuit placed between the (i+1)th gate driving unit and the next (i+2)th gate driving unit. .

According to embodiments of the present invention, a display device, display panel, and gate driving circuit are provided that can reduce the number of clock signals (number of phases of the clock signal), thereby reducing the number of clock wires and reducing the bezel size. can do.

In addition, according to embodiments of the present invention, when driving becomes complicated or necessary functions (e.g. compensation, etc.) are added, a display device that enables normal driving while reducing the number of clock signals (number of phases of the clock signal); A display panel and gate driving circuit can be provided.

Additionally, according to embodiments of the present invention, it is possible to provide a display device, a display panel, and a gate driving circuit that perform cluster driving that can secure sufficient sensing time during display driving.

1 is a system configuration diagram of a display device according to embodiments of the present invention.
Figure 2 is an equivalent circuit of a subpixel of a display device according to embodiments of the present invention.
FIG. 3 is a diagram schematically showing a gate driving unit constituting a gate driving circuit of a display device according to embodiments of the present invention.
Figure 4 is a diagram showing basic driving periods of a display device according to embodiments of the present invention.
FIG. 5 is a diagram illustrating gate signals applied to a subpixel when driving a subpixel of a display device according to embodiments of the present invention.
Figure 6 is a timing diagram for sequential driving of a display device according to embodiments of the present invention.
Figure 7 is a diagram showing a clock wiring structure required for sequential driving of a display device according to embodiments of the present invention.
Figure 8 is a diagram showing clustering of subpixel lines for cluster driving of a display device according to embodiments of the present invention.
Figure 9 is a timing diagram for cluster driving of a display device according to embodiments of the present invention.
Figure 10 is a diagram showing gate signals applied to one cluster when driving a cluster of a display device according to embodiments of the present invention.
FIG. 11 is a diagram showing a clock wiring structure required to drive a cluster of a display device according to embodiments of the present invention.
FIG. 12 is a diagram illustrating a gate driving circuit having an intermediate stage to reduce the number of clock wires required for cluster driving of a display device according to embodiments of the present invention.
FIG. 13 is a diagram illustrating a structure in which the number of clock wires required to drive a cluster of a display device according to embodiments of the present invention is reduced.
FIG. 14 is a diagram showing the gate driving circuit with the intermediate stage of FIG. 12 in more detail.
FIG. 15 is a diagram showing the first main stage circuit of FIG. 14.
FIG. 16 is a diagram showing the second main stage circuit of FIG. 14.
FIG. 17 is a diagram showing the intermediate stage circuit of FIG. 14.
Figure 18 is a diagram briefly showing the supply structure of a sense signal and an emission control signal for driving a cluster of a display device according to embodiments of the present invention.
Figure 19 is a diagram briefly showing another supply structure of a sense signal and a light emission control signal for driving a cluster of a display device according to embodiments of the present invention.
FIG. 20 is a clock timing diagram of clock signals supplied to a gate driving circuit having an intermediate stage for cluster driving of a display device according to embodiments of the present invention.
Figure 21 is a diagram showing the number of clocks according to three driving methods (sequential driving method, cluster driving method, and cluster driving method with an intermediate stage).

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the description of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (e.g., level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g., process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

1 is a system configuration diagram of a display device 100 according to embodiments of the present invention.

Referring to FIG. 1, the display device 100 according to embodiments of the present invention has a plurality of data lines DL and a plurality of gate lines GL, and a plurality of data lines DL and a plurality of gate lines GL. It may include a display panel 110 in which a plurality of subpixels SP connected to the gate line GL are arranged, and a driving circuit for driving the display panel 110.

Functionally, the driving circuit includes a data driving circuit 120 for driving a plurality of data lines DL, a gate driving circuit 130 for driving a plurality of gate lines GL, and a data driving circuit 120. ) and a controller 140 that controls the gate driving circuit 130.

In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged to cross each other. For example, multiple data lines DL may be arranged in rows or columns, and multiple gate lines GL may be arranged in columns or rows. Below, for convenience of explanation, it is assumed that the plurality of data lines DL are arranged in rows and the plurality of gate lines GL are arranged in columns.

The controller 140 supplies various control signals (DCS, GCS) necessary for the driving operation of the data driving circuit 120 and the gate driving circuit 130, and operates the data driving circuit 120 and the gate driving circuit 130. Control.

This controller 140 starts scanning according to the timing implemented in each frame, converts the input image data input from the outside to fit the data signal format used in the data driving circuit 120, and converts the converted image data (DATA) ) is output, and data operation is controlled at an appropriate time according to the scan.

The above-described controller 140, along with input image data, various types of signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE) signal, a clock signal (CLK), etc. Timing signals are received from an external source (e.g., host system).

The controller 140 converts the input image data input from the outside to suit the data signal format used in the data driving circuit 120 and outputs the converted image data (DATA), and also operates the data driving circuit 120 and In order to control the gate driving circuit 130, timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal are input, and various control signals are generated to generate the data driving circuit 120. ) and output to the gate driving circuit 130.

For example, the controller 140 uses a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE) to control the gate driving circuit 130. : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable. Here, the gate start pulse (GSP) controls the operation start timing of one or more gate driver integrated circuits constituting the gate driving circuit 130. The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of a scan signal (gate pulse). The gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits.

In addition, the controller 140 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE) to control the data driving circuit 120. Outputs various data control signals (DCS: Data Control Signal) including Output Enable. Here, the source start pulse (SSP) controls the data sampling start timing of one or more source-driver integrated circuits constituting the data driving circuit 120. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data in each source-driver integrated circuit. The source output enable signal (SOE) controls the output timing of the data driving circuit 120.

This controller 140 may be a timing controller used in typical display technology, or may be a control device that can perform other control functions, including a timing controller.

The controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 receives image data DATA from the controller 140 and supplies a data voltage to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 is also called a source driving circuit.

The data driving circuit 120 may be implemented including at least one source-driver integrated circuit (S-DIC). Each source-driver integrated circuit (S-DIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc. there is. Each source-driver integrated circuit (S-DIC) may, in some cases, further include an analog to digital converter (ADC).

Each source-driver integrated circuit (S-DIC) is connected to a bonding pad of the display panel 110 using a tape automated bonding (TAB) method or a chip on glass (COG: chip on glass) method. It may be connected to or placed directly on the display panel 110, or in some cases, may be integrated and placed on the display panel 110. Additionally, each source-driver integrated circuit (S-DIC) may be implemented using a chip-on-film (COF) method mounted on a source-circuit film connected to the display panel 110.

The gate driving circuit 130 sequentially drives a plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the gate driving circuit 130 is also called a scan driving circuit.

The gate driving circuit 130 may include a shift register, a level shifter, etc.

The gate driving circuit 130 is connected to the bonding pad of the display panel 110 using a tape automated bonding (TAB) method or a chip on glass (COG) method, or is implemented as a GIP (Gate In Panel) type. It may be placed directly on the display panel 110, or, depending on the case, may be integrated and placed on the display panel 110. Additionally, the gate driving circuit 130 may be implemented using a chip-on-film (COF) method in which a plurality of gate driver integrated circuits (G-DICs) are implemented and mounted on a gate-circuit film connected to the display panel 110. .

The gate driving circuit 130 sequentially supplies scan signals of on voltage or off voltage to the plurality of gate lines GL under the control of the controller 140.

When a specific gate line is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data (DATA) received from the controller 140 into an analog data voltage to connect a plurality of data lines (DL). supplied by

The data driving circuit 120 may be located only on one side (e.g., upper or lower) of the display panel 110, and in some cases, both sides (e.g., upper or lower) of the display panel 110 depending on the driving method, panel design method, etc. For example, it may be located on both the upper and lower sides.

The gate driving circuit 130 may be located only on one side (e.g., left or right) of the display panel 110, and in some cases, both sides (e.g., left or right) of the display panel 110 depending on the driving method, panel design method, etc. For example, it can be located on both the left and right sides.

The plurality of gate lines (GL) disposed on the display panel 110 may include a plurality of scan lines (SCL), a plurality of sense lines (SCL), and a plurality of emission control lines (EML). The scan line (SCL), sense line (SCL), and emission control line (EML) are the gate nodes of different types of transistors (scan transistor, sense transistor, and emission control transistor) and transmit different types of gate signals (scan signal, These are wires that transmit sense signals and light emission control signals. Hereinafter, description will be made with reference to FIG. 2.

The display device 100 according to embodiments of the present invention may be a liquid crystal display device requiring a back light unit, an Organic Light Emitting Diode (OLED) display, a Quantum Dot display, or a Micro Light Emitting (Micro LED) display. It may be a self-luminous display such as a diode display.

When the display device 100 according to embodiments of the present invention is an OLED display, each subpixel (SP) may include an organic light emitting diode (OLED) that emits light as a light emitting device. When the display device 100 according to embodiments of the present invention is a quantum dot display, each subpixel (SP) may include a light emitting element made of quantum dots, which are semiconductor crystals that emit light on their own. When the display device 100 according to embodiments of the present invention is a micro LED display, each subpixel (SP) emits light on its own and may include a micro LED (Micro Light Emitting Diode) made of an inorganic material as a light emitting element. You can.

Figure 2 is an equivalent circuit of a subpixel (SP) of the display device 100 according to embodiments of the present invention.

Referring to FIG. 2, in the display device 100 according to embodiments of the present invention, each subpixel (SP) includes a light emitting element (ED) and a driving transistor ( DRT), a scan transistor (SCT) for transferring the data voltage (Vdata) to the driving transistor (DRT), a sense transistor (SENT) for initialization operation, an emission control transistor (EMT) for controlling emission, and a predetermined period of time. It may include a storage capacitor (Cst) for maintaining the voltage.

The light emitting element (ED) includes a first electrode (E1) and a second electrode (E2), and a light emitting layer (EL) located between the first electrode (E1) and the second electrode (E2). The first electrode E1 of the light emitting device ED may be an anode electrode or a cathode electrode, and the second electrode E2 may be a cathode electrode or an anode electrode. For example, the light emitting device (ED) may be an organic light emitting diode (OLED), a light emitting diode (LED), or a quantum dot light emitting device.

The second electrode E2 of the light emitting device ED may be a common electrode. In this case, the base voltage EVSS may be applied to the second electrode E2 of the light emitting device ED. Here, the base voltage (EVSS) may be, for example, a ground voltage or a voltage similar to the ground voltage.

The driving transistor DRT is a transistor for driving the light emitting device ED and includes a first node N1, a second node N2, and a third node N3.

The first node N1 of the driving transistor DRT is a node corresponding to the gate node and may be electrically connected to the source node or drain node of the scan transistor SCT. The second node N2 of the driving transistor DRT may be electrically connected to the first electrode E1 of the light emitting device ED and may be a source node or a drain node. The third node (N3) of the driving transistor (DRT) is a node to which the driving voltage (EVDD) is applied, and can be electrically connected to the driving voltage line (DVL) that supplies the driving voltage (EVDD), and is a drain node. Or it may be a source node. Below, for convenience of explanation, the second node N2 of the driving transistor DRT is a source node, and the third node N3 is a drain node.

The scan transistor (SCT) is the first node of the driving transistor (DRT) in response to the scan signal (SCAN) supplied from the corresponding scan line (SCL) among a plurality of scan lines (SCL), which are a type of gate line (GL). The connection between (N1) and the corresponding data line (DL) among the plurality of data lines (DL) can be controlled.

The drain node or source node of the scan transistor (SCT) may be electrically connected to the corresponding data line (DL). The source node or drain node of the scan transistor (SCT) may be electrically connected to the first node (N1) of the driving transistor (DRT). The gate node of the scan transistor (SCT) is electrically connected to a scan line (SCL), a type of gate line (GL), and can receive a scan signal (SCAN).

The scan transistor (SCT) is turned on by the scan signal (SCAN) of the turn-on level voltage, and the data voltage (Vdata) supplied from the corresponding data line (DL) is connected to the first node (N1) of the driving transistor (DRT). ) can be delivered.

The scan transistor (SCT) is turned on by the scan signal (SCAN) of the turn-on level voltage and turned off by the scan signal (SCAN) of the turn-off level voltage. Here, when the scan transistor (SCT) is n-type, the turn-on level voltage may be a high level voltage, and the turn-off level voltage may be a low level voltage. When the scan transistor (SCT) is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The sense transistor (SENT) responds to the sense signal (SENSE) supplied from the corresponding sense line (SENL) among the plurality of sense lines (SENL), which are a type of gate line (GL), and transmits the first signal to the light emitting device (ED). The connection between the second node N2 of the driving transistor DRT electrically connected to the electrode E1 and the corresponding reference line RVL among the plurality of reference lines RVL can be controlled.

The drain node or source node of the sense transistor (SENT) may be electrically connected to the reference line (RVL). The source node or drain node of the sense transistor (SENT) may be electrically connected to the second node (N2) of the driving transistor (DRT) and may be electrically connected to the first electrode (E1) of the light emitting device (ED). The gate node of the sense transistor (SENT) is electrically connected to the sense line (SENL), a type of gate line (GL), and can receive a sense signal (SENSE).

The sense transistor (SENT) is turned on to apply the reference voltage (Vref) supplied from the reference line (RVL) to the second node (N2) of the driving transistor (DRT).

The sense transistor (SENT) is turned on by the sense signal (SENSE) of the turn-on level voltage and turned off by the sense signal (SENSE) of the turn-off level voltage. Here, when the sense transistor (SENT) is n-type, the turn-on level voltage may be a high level voltage, and the turn-off level voltage may be a low level voltage. When the sense transistor (SENT) is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The emission control transistor (EMT) responds to the emission control signal (EM) supplied from the corresponding emission control line (EML) among the plurality of emission control lines (EML), which are a type of gate line (GL), and operates the driving transistor (DRT). It is possible to control the connection between the third node (N3) of and the corresponding driving line (DVL) among the plurality of driving lines (DVL). That is, as shown in FIG. 2, the emission control transistor (EMT) may be electrically connected between the third node (N3) of the driving transistor (DRT) and the driving line (DVL).

The drain node or source node of the emission control transistor (EMT) may be electrically connected to the driving line (DVL). The source node or drain node of the emission control transistor (EMT) may be electrically connected to the third node (N3) of the driving transistor (DRT). The gate node of the emission control transistor (EMT) is electrically connected to the emission control line (EML), a type of gate line (GL), and can receive the emission control signal (EM).

Alternatively, the emission control transistor (EMT) may control the connection between the second node (N2) of the driving transistor (DRT) and the first electrode (E1) of the light emitting device (ED). That is, unlike shown in FIG. 2, the emission control transistor (EMT) may be electrically connected between the second node (N2) of the driving transistor (DRT) and the light emitting element (ED).

The emission control transistor (EMT) is turned on by the emission control signal (EM) of the turn-on level voltage and turned off by the emission control signal (EM) of the turn-off level voltage. Here, when the emission control transistor (EMT) is n-type, the turn-on level voltage may be a high level voltage, and the turn-off level voltage may be a low level voltage. When the emission control transistor (EMT) is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT and generates a data voltage Vdata corresponding to the image signal voltage or a voltage corresponding thereto. It can be maintained for the frame time.

The storage capacitor Cst is not a parasitic capacitor (e.g. Cgs, Cgd), which is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DRT. It may be an external capacitor intentionally designed outside the transistor (DRT).

Each of the driving transistor (DRT), scan transistor (SCT), sense transistor (SENT), and emission control transistor (EMT) may be an n-type transistor or a p-type transistor. The driving transistor (DRT), scan transistor (SCT), sense transistor (SENT), and emission control transistor (EMT) may all be n-type transistors or p-type transistors. At least one of the driving transistor (DRT), scan transistor (SCT), sense transistor (SENT), and emission control transistor (EMT) is an n-type transistor (or p-type transistor), and the others are p-type transistors (or n-type transistors). You can.

Each subpixel structure illustrated in FIG. 2 is only an example for explanation and may further include one or more transistors or, in some cases, one or more capacitors. Alternatively, each of the multiple subpixels (SP) may have the same structure, or some of the multiple subpixels (SP) may have a different structure.

FIG. 3 is a diagram briefly illustrating a gate driving unit (GDU) constituting the gate driving circuit 130 of the display device 100 according to embodiments of the present invention.

Referring to FIG. 3 , the gate driving circuit 130 may include a plurality of gate driving units (GDU) to drive a plurality of gate lines GL.

Referring to FIG. 3, basically, each of the plurality of gate driving units (GDU) may include at least one logic (LOGIC) and at least one output buffer (OUT_BUF).

Each output buffer (OUT_BUF) includes a pull-up transistor (Tu) and a pull-down transistor (Td) whose turn-on operation alternates.

A clock signal (CLK) is applied to the drain node (or source node) of the pull-up transistor (Tu), and the source node (or drain node) of the pull-up transistor (Tu) is electrically connected to the output node (Nout). And the gate node of the pull-up transistor (Tu) is the Q node controlled by logic (LOGIC).

A base voltage (e.g., also called low-potential voltage, turn-off level voltage, ground voltage, or VSS voltage) is applied to the drain node (or source node) of the pull-down transistor (Td), and the pull-down transistor (Td) is applied to the drain node (or source node). )'s source node (or drain node) is electrically connected to the output node (Nout), and the gate node of the pull-down transistor (Td) is the QB node controlled by logic (LOGIC).

The Q node and QB node have opposite voltage states. For example, if the Q node is a high level voltage, the QB node is a low level voltage. If the Q node is a low level voltage, the QB node is a high level voltage.

Depending on the high level voltage (or low level voltage) of the Q node, when the pull-up transistor (Tu) is turned on, the pull-down transistor (Td) is connected to the low level voltage (or high level voltage) of the QB node. It is in a turn-off state according to . Depending on the low level voltage (or high level voltage) of the Q node, when the pull-up transistor (Tu) is turned off, the pull-down transistor (Td) is connected to the high level voltage (or low level voltage) of the QB node. Accordingly, it is in the turn-on state.

The output node (Nout) may be electrically connected to one of the scan line (SCL), sense line (SENL), and emission control line (EML).

When the pull-up transistor Tu is turned on, the clock signal CLK applied to the pull-up transistor Tu is output to the output node Nout. The clock signal CLK output to the output node Nout may be one of a scan signal SCL, a sense signal SENSE, and an emission control signal EM having a turn-on level voltage.

When the pull-down transistor Td is turned on, the base voltage VSS applied to the pull-down transistor Td is output to the output node Nout. The base voltage (VSS) output to the output node (Nout) may be one of a scan signal (SCL), a sense signal (SENSE), and an emission control signal (EM) having a turn-off level voltage.

Logic is a circuit for controlling the voltage of each Q node and QB node, and may include two or more transistors (switch elements). Logic receives a set signal (VST), sets the operation of the gate driving unit (GDU), and receives a reset signal (VRST) to reset the operation of the gate driving unit (GDU). (Reset) can be done. Logic (LOGIC) may receive a separate power input to control the voltage of each Q node and QB node.

FIG. 4 is a diagram showing basic driving periods of the display device 100 according to embodiments of the present invention, and FIG. 5 is a diagram showing the driving of the subpixel (SP) of the display device 100 according to embodiments of the present invention. This is a diagram showing the gate signals (SCAN, SENSE, EM) applied to the subpixel (SP).

Referring to FIG. 4, the basic driving periods of each subpixel (SP) of the display device 100 according to embodiments of the present invention include a sensing period (SENSING), a first holding period (HOLD1), and a data writing period ( DW), a second holding period (HOLD2), and an emission period (EMISSION).

Referring to Figures 4 and 5, the sensing period (SENSING) is a period for sensing the characteristic values (eg, threshold voltage, mobility) of the driving transistor (DRT). The sensing period (SENSING) may include an initialization period (INIT) and a sampling period (SAMP).

Referring to FIG. 5, during the initialization period (INIT) within the sensing period (SENSING), the scan transistor (SCT) is turned on by the scan signal (SCAN) of the turn-on level voltage, and the sense transistor (SENT) is turned on. -Turns on by the sense signal (SENSE) of the on level voltage.

Accordingly, the sensing driving data voltage (Vdata) is applied to the first node (N1) of the driving transistor (DRT), and the reference voltage (Vref) is applied to the second node (N2) of the driving transistor (DRT), The first node (N1) and the second node (N2) of the driving transistor (DRT) are initialized. During the initialization period (INIT), the emission control transistor (EMT) may be turned off by the emission control signal (EM) at a turn-off level voltage.

Referring to FIG. 5, during the sampling period (SAMP) within the sensing period (SENSING), the scan transistor (SCT) is turned on by the scan signal (SCAN) of the turn-on level voltage, and the sense transistor (SENT) is turned on. -Turns off by the sense signal (SENSE) of the off-level voltage. Also, during the initialization period (INIT), the emission control transistor (EMT) may be turned on by the emission control signal (EM) at the turn-on level voltage. Accordingly, the first node (N1) of the driving transistor (DRT) is in a state where the data voltage (Vdata) for sensing driving is applied, and the second node (N2) of the driving transistor (DRT) is in a floating state. The voltage of the second node N2 of the driving transistor DRT is boosted and becomes saturated after a certain period of time. The saturated voltage of the second node (N2) of the driving transistor (DRT) is the threshold voltage (Vth) of the driving transistor (DRT) in the sensing driving data voltage (Vdata) of the first node (N1) of the driving transistor (DRT). Corresponds to the voltage minus (Vdata-Vth).

Referring to FIG. 5, the first holding period (HOLD1) is a period after the sensing period (SENSING) but before the data writing period (DW). During the first holding period (HOLD1), the scan transistor (SCT), the sense transistor (SENT), and the emission control transistor (EMT) may be in a turned-off state. During the first holding period (HOLD1), the voltage of the first node (N1) and the second node (N2) of the driving transistor (DRT) may vary (increase).

Referring to FIG. 5, the data writing period (DW) is a period that determines the driving current flowing through the light emitting element (ED), and displays an image (image for the next frame) on the first node (N1) of the driving transistor (DRT). This is the period during which the data voltage (Vdata) for update is applied. At this time, due to the driving operation during the sensing period (SENSING), the driving current flowing through the light emitting device (ED) may be determined regardless of the threshold voltage of the driving transistor (DRT). Accordingly, luminance unevenness due to threshold voltage deviation between the driving transistors (DRT) does not occur. Therefore, the sensing period (SENSING) is also called an internal compensation period that compensates for the threshold voltage deviation between the driving transistors (DRT).

Referring to FIG. 5, during the data writing period (DW), the scan transistor (SCT) is turned on by the scan signal (SCAN) of the turn-on level voltage. Accordingly, the scan transistor (SCT) transfers the image display data voltage (VDTA) supplied to the data line (DL) to the first node (N1) of the driving transistor (DRT). Here, the first node N1 of the driving transistor DRT is electrically connected to one electrode of the storage capacitor Cst. Accordingly, during the data writing period (DW), a charge corresponding to the image display data voltage (VDTA) is charged in the storage capacitor (Cst).

Referring to FIG. 5, the second holding period (HOLD2) is a period after the data writing period (DW) and before the emission period (EMISSION) begins. During the second holding period (HOLD2), the scan transistor (SCT), sense transistor (SENT), and emission control transistor (EMT) may be in a turned-off state. During the second holding period (HOLD2), the voltage of the first node (N1) and the second node (N2) of the driving transistor (DRT) increases.

The increased voltage of the second node N2 of the driving transistor DRT (i.e., the voltage of the first electrode E1 of the light emitting device ED) is increased to a constant voltage (the voltage of the second electrode E2 of the light emitting device ED). When the voltage exceeds the voltage of (plus the threshold voltage of the light emitting device (ED)), the light emitting device (ED) begins to emit light.

Referring to FIG. 5, the emission period (EMISSION) is a period during which the light emitting element (ED) actually emits light. During the emission period (EMISSION), the emission control transistor (EMT) is turned on by the emission control signal (EM) at the turn-on level voltage so that the light emitting device (ED) can emit light. At this time, the luminance of the light emitting device (ED) is proportional to the driving current flowing through the light emitting device (ED). The emission period (EMISSION) may occupy most of one frame time.

Figure 6 is a timing diagram for sequential driving of the display device 100 according to embodiments of the present invention.

Referring to FIG. 6, a plurality of subpixels (SP) are arranged in a matrix form on the display panel 110. Accordingly, a plurality of subpixel lines (SPL1 to SPL8) may exist in the display panel 110.

Referring to FIG. 6, multiple subpixel lines (SPL1 to SPL8) may be driven individually and sequentially. This driving method is called sequential driving or individual driving. That is, the sequential driving method is a method of sequentially driving the subpixel lines (SPL1 to SPL8) in a line-by-line manner.

In the plurality of subpixel lines (SPL1 to SPL8), the sensing period (SENSING) proceeds sequentially, the first holding period (HOLD1) proceeds sequentially, the data writing period (DW) proceeds sequentially, and the second holding period (HOLD1) proceeds sequentially. The period (HOLD2) proceeds sequentially, and the emission period (EMISSION) proceeds sequentially. That is, the drive sets (sensing, holding, data writing, holding, and light emission) of each of the multiple subpixel lines (SPL1 to SPL8) proceed sequentially.

FIG. 7 is a diagram showing a clock wiring structure required for sequential driving of the display device 100 according to embodiments of the present invention.

Referring to FIG. 7, when the display device 100 according to embodiments of the present invention is driven in a sequential driving manner, many clock signals (SE_CLK1 to 6, Many different types of clock wires (SE_CW1 to 6, SC_CW1 to 6, EM_CW1 to 6, CR_CW1 to 6) are needed to supply SC_CLK1 to 6, EM_CLK1 to 6, and CR_CLK1 to 6) to the gate driving circuit 130. .

For example, the 6-phase sense clock signal (SE_CLK1~6) required for generating the sense signal (SENSE), the 6-phase scan clock signal (SC_CLK1~6) required for generating the scan signal (SCAN), and the emission control signal (EM) The 6-phase light emission control clock signal (EM_CLK1 to 6) required for the generation of the 6-phase carry clock signal (CR_CLK1 to 6) for controlling the set and reset between stages in the gate driving circuit 130. 6) etc. may be necessary. That is, in the case of the sequential driving method, 24-phase clock signals (SE_CLK1~6, SC_CLK1~6, EM_CLK1~6, CR_CLK1~6) are required. Even if the number of phases is reduced, clock signals with about 20 phases are needed.

Each gate driving unit (GDU) corresponding to each stage of gate driving in the gate driving circuit 130 must output a carry signal within the high level voltage section of the Q node, which is an operation section. Since the set signal and reset signal by the carry signal must not overlap each other, a temporal overlap occurs in the high level voltage section of the Q node between each gate driving unit (GDU). Accordingly, since gate driving units (GDUs) corresponding to adjacent stages cannot use clock signals of the same phase, more clock signals of different phases are inevitably needed.

In addition, compared to the external compensation method, which performs sensing and compensation regardless of display driving, when the threshold voltage of the driving transistor (DRT) is sensed and compensated during display driving according to the internal compensation method, complex driving timing is required. More and more clock signals are needed.

The display panel 110 includes an active area (A/A) in which an image is displayed and arranged in a plurality of subpixels (SP), and a non-active area (N/A) that is an outer area of the active area (A/A). Includes.

In the non-active area (N/A), a GIP type gate driving circuit 130 and clock wires (SE_CW1 to 6, SC_CW1 to 6, EM_CW1 to 6, and CR_CW1 to 6) are disposed.

As described above, according to the sequential driving method and internal compensation method, a significant number of clock wires (SE_CW1 to 6, SC_CW1 to 6, EM_CW1 to 6, CR_CW1 to 6) are placed in the non-active area (N/A). Therefore, the area where the clock wires (SE_CW1 to 6, SC_CW1 to 6, EM_CW1 to 6, CR_CW1 to 6) are formed in the non-active area (N/A) is bound to increase. Accordingly, the bezel of the display device 100 may become larger.

Meanwhile, during the sensing period (SENSING) of each subpixel (SP), in order to sense the characteristic value (e.g., threshold voltage, etc.) of the driving transistor (DRT) within each subpixel (SP), the driving transistor (DRT) within each subpixel (SP) It takes time for the voltage of the second node N2 of the transistor DRT to rise and become saturated. However, as with the internal compensation method, when a sensing period (SENSING) is allocated during the display driving period, the time necessary for normal sensing operation must be secured, but it is not easy to secure the sensing time due to the display driving time, etc. Accordingly, when the sensing time is insufficient, the characteristic value (e.g., threshold voltage) of the driving transistor (DRT) cannot be sensed accurately, and the deviation in characteristic value (e.g., threshold voltage) between the driving transistors (DRT) cannot be properly compensated. This phenomenon of insufficient sensing time may be more severe in high-resolution or large-sized display panels 110.

As described above, when compensating by sensing the characteristic value of the driving transistor (DRT) using an internal compensation method, when driving multiple subpixel lines (SPL1 to SPL8) individually and sequentially, the sensing period (SENSING) is set to the required time. It is difficult to secure it.

Therefore, according to the sequential driving method and the internal compensation method, the number of clock wires inevitably increases and it is difficult to secure sensing time, so a new driving method is needed to solve this problem.

Accordingly, embodiments of the present invention propose a cluster driving method. The cluster driving method is a driving method that groups multiple subpixel lines into one cluster and performs sensing and light emission operations simultaneously. Below, the cluster driving method is explained in more detail.

FIG. 8 is a diagram showing clustering of subpixel lines (SPL #1 to SPL #N) for cluster driving of a display device according to embodiments of the present invention.

Referring to FIG. 8, according to the cluster driving method, N (N≥2) subpixel lines (SPL #1 to SPL) are generated from all subpixel lines (SPL1, SPL2, ...) arranged on the display panel 110. #N) are grouped into one cluster (CLST: Cluster, also called block).

Here, N is the number of subpixel lines (SPL #1 to SPL #N) included in one cluster (CLST), and is a value indicating the cluster size.

Referring to FIG. 8, multiple subpixels (SP) are grouped into M clusters (CLST #1, CLST #2, ..., CLST #M). M may be a natural number of 2 or more.

Referring to FIG. 8, each of M clusters (CLST #1 to CLST #M) may include N subpixel lines (SPL #1, SPL #2, ..., SPL #N). N may be a natural number of 2 or more. Several subpixels (SP) are arranged in each of the N subpixel lines (SPL #1 to SPL #N).

If each of M clusters (CLST #1 to CLST #M) contains N subpixel lines (SPL #1, SPL #2, ..., SPL #N), cluster operation is called "N-cluster operation. "It is said.

For example, if each of M clusters (CLST #1 to CLST #M) includes 4 subpixel lines (SPL #1 to SPL #4), cluster driving is called “4-cluster driving.” For another example, if each of the M clusters (CLST #1 to CLST #M) includes 6 subpixel lines (SPL #1 to SPL #6), the cluster drive is called “6-cluster drive”. .

Below, for convenience of explanation, an example is given where each of M clusters (CLST #1 to CLST #M) includes 4 subpixel lines (SPL #1 to SPL #6, N=4). That is, take “4-cluster operation” as an example. Among M clusters (CLST #1 to CLST #M), the first cluster (CLST #1) and the second cluster (CLST #2) are taken as examples.

FIG. 9 is a timing diagram for cluster driving of the display device 100 according to embodiments of the present invention, and FIG. 10 is a timing diagram of one cluster ( This diagram shows the gate signals (SCAN, SENSE, EM) applied to the Cluster.

Referring to FIGS. 9 and 10, when driving a cluster (4-cluster driving), the display device 100 displays four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1). ) is operated according to the established procedures (SENSING, HOLD1, DW, HOLD2, EMISSIOND). And, after the driving of the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) begins, according to the designated timing, the four subpixel lines (SPL #1 to SPL #4) included in the second cluster (CLST #2) are Driving of the subpixel lines (SPL #1 to SPL #4) may begin.

As an example, driving of four scan lines (SCL) corresponding to four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1), and driving of the second cluster (CLST #2) To prevent the operation of the four scan lines (SCL) corresponding to the four subpixel lines (SPL #1 to SPL #4) included in from overlapping, the first cluster (CLST #1) and the second cluster (CLST #2) )'s driving timing can be controlled.

Referring to FIGS. 9 and 10, when driving a cluster, in the case of subpixels (SP) arranged in four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1), The sensing period (SENSING) and the emission period (EMISSION) proceed simultaneously, and the data writing period (DW) proceeds sequentially.

Referring to FIGS. 9 and 10, when driving a cluster, during the initialization period (INIT) within the sensing period (SENSING), the gate driving circuit 130 operates on four subpixel lines included in the first cluster (CLST #1). Scan signals (SCAN #1 ~ SCAN #4) of turn-on level voltage are simultaneously applied to four scan lines (SCL) corresponding to (SPL #1 ~ SPL #4), and the first cluster (CLST #1 ), the sense signal (SENSE) of the turn-on level voltage is simultaneously applied to the four sense lines (SENL) corresponding to the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST) The emission control signal (EM) of the turn-off level voltage is simultaneously applied to the four emission control lines (EML) corresponding to the four subpixel lines (SPL #1 to SPL #4) included in #1).

Referring to FIGS. 9 and 10, when driving a cluster, during a sampling period (SAMP) within a sensing period (SENSING), the gate driving circuit 130 operates on four subpixel lines included in the first cluster (CLST #1). Scan signals (SCAN #1 to SCAN #4) of turn-on level voltage are simultaneously and continuously applied to four scan lines (SCL) corresponding to (SPL #1 to SPL #4), and the first cluster (CLST A sense signal (SENSE) of the turn-off level voltage is simultaneously applied to the N sense lines (SENL) corresponding to the four subpixel lines (SPL #1 to SPL #4) included in #1), and the first cluster The emission control signal (EM) of the turn-on level voltage is simultaneously applied to the N emission control lines (EML) corresponding to the four subpixel lines (SPL #1 to SPL #4) included in (CLST #1). .

As described above, all four subpixel lines (SPL #1 to SPL #4) simultaneously receive a sense signal (SENSE) of a turn-on level voltage or a turn-off level voltage.

As an example of a supply structure of a sense signal (SENSE), each of the subpixels (SP) disposed on four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) is a sense transistor. (SENT) can be included one each. In this case, four sense lines (SENL) corresponding to four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) are disposed, and the gate driving circuit 130 has 4 A sense signal (SENSE) of a turn-on level voltage or a turn-off level voltage can be supplied through the sense lines (SENL). As an example of a method of supplying a sense signal (SENSE) to the first cluster (CLST #1), the gate driving circuit 130 may output four sense signals (SENSE). The four sense signals (SENSE) output from the gate driving circuit 130 may be applied to each of the four sense lines (SENL). As another example of a method of supplying the sense signal (SENSE) to the first cluster (CLST #1), the gate driving circuit 130 may output one sense signal (SENSE). In this case, one sense signal (SENSE) may be branched and supplied to four sense lines (SENL).

As another example of the supply structure of the sense signal (SENSE), the subpixels (SP) arranged on the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) are arranged in column units. One sense transistor (SENT) can be shared. In this case, one sense line (SENL) corresponding to four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) is disposed, and the gate driving circuit 130 has 1 A sense signal (SENSE) of a turn-on level voltage or a turn-off level voltage can be supplied through the sense lines (SENL). The sense signal (SENSE) of the turn-on level voltage or turn-off level voltage supplied to one sense line (SENL) is applied to one sense transistor (SENT) in column units, and is transmitted to four subpixel lines (SPL # It is shared by subpixels (SP) placed in the same column included in 1 to SPL #4).

As described above, all four subpixel lines (SPL #1 to SPL #4) simultaneously receive the emission control signal (EM) of the turn-on level voltage or the turn-off level voltage.

As an example of a supply structure of the emission control signal (EM), each of the subpixels (SP) arranged on the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) emits light. Each control transistor (EMT) may be included. In this case, four emission control lines (EML) corresponding to four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) are disposed, and the gate driving circuit 130 is An emission control signal (EM) of a turn-on level voltage or a turn-off level voltage can be supplied through four emission control lines (EML). As an example of a method of supplying the emission control signal (EM) to the first cluster (CLST #1), the gate driving circuit 130 may output four emission control signals (EM). The four emission control signals (EM) output from the gate driving circuit 130 may be applied to each of the four emission control lines (EML). As another example of a method of supplying the emission control signal (EM) to the first cluster (CLST #1), the gate driving circuit 130 may output one emission control signal (EM). One emission control signal (EM) can be branched and supplied to four emission control lines (EML).

As another example of the supply structure of the emission control signal (EM), the subpixels (SP) arranged on the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) are arranged in column units. One emission control transistor (EMT) can be shared. In this case, one emission control line (EML) corresponding to the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) is disposed, and the gate driving circuit 130 is An emission control signal (EM) of a turn-on level voltage or a turn-off level voltage can be supplied through one emission control line (EML). The emission control signal (EM) of the turn-on level voltage or turn-off level voltage supplied to one emission control line (EML) is applied to one sense transistor (SENT) in column units, and is transmitted to four subpixel lines ( It is shared by subpixels (SP) placed in the same column included in SPL #1 to SPL #4).

Referring to FIGS. 9 and 10, when driving the cluster, the subpixels (SP) included in the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) are used for sensing. When the periods (SENSING) start and complete simultaneously, the data voltage (Vdata) for image display is sequentially recorded. That is, when the cluster is driven, the data write period (DW) of each of the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) proceeds sequentially.

To this end, the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) have a first holding period (HOLD1) of different lengths, and then a data writing period ( DW).

During the first holding period (HOLD1), the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) receive scan signals (SCAN #1 to SCAN #) of the turn-off level voltage. 4), a sense signal (SENSE) of the turn-off level voltage and an emission control signal (EM) of the turn-off level voltage are supplied.

Referring to FIGS. 9 and 10, as the data write period (DW) of each of the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) progresses sequentially, the The four subpixel lines (SPL #1 to SPL #4) included in one cluster (CLST #1) have second holding periods (HOLD2) of different lengths. Afterwards, the emission period (EMISSION) of each of the four subpixel lines (SPL #1 to SPL #4) included in the first cluster (CLST #1) proceeds simultaneously.

FIG. 11 is a diagram showing a clock wiring structure required for cluster driving of the display device 110 according to embodiments of the present invention.

Referring to FIG. 11, in the case of the cluster driving method, N subpixel lines (SPL #1 to SPL #N) are grouped into one cluster (CLST) and driven simultaneously, so compared to the sequential driving method, some scan signals ( Phase reduction of clock signals for SCAN) may be possible. Except for the scan signal (SCAN) for data writing timing, the scan signal (SCAN) used for other timings is N numbers corresponding to N subpixel lines (SPL #1 ~ SPL #N) in one cluster (CLST). It can be output simultaneously to the scan line (SCL).

Referring to FIG. 11, for example, in the case of N-cluster driving, the 2-phase sense clock signals (SE_CLK1 to 2) required for generating the sense signal (SENSE) and the 2N-phase scan clock required for generating the scan signal (SCAN) signals (SC_CLK1 to 2N), one-phase emission control clock signal (EM_CLK1) required for generating the emission control signal (EM), and set and reset between stages in the gate driving circuit 130. A two-phase carry clock signal (CR_CLK1~2) for control may be required.

In the case of 4-cluster operation with N=4, the 2-phase sense clock signal (SE_CLK1~2) required for generating the sense signal (SENSE) and the 8-phase scan clock signal (SC_CLK1~2) required for generating the scan signal (SCAN) 8), 2 for controlling the one-phase emission control clock signal (EM_CLK1) required for generating the emission control signal (EM) and the set and reset between stages in the gate driving circuit 130 A carry clock signal (CR_CLK1~2) may be required. 13 phase clock signals (SE_CLK1~2, SC_CLK1~8, EM_CLK1, CR_CLK1~2) are required. That is, 13 clock signals (SE_CLK1~2, SC_CLK1~8, EM_CLK1, CR_CLK1~2) are required.

As such, in the case of the cluster driving method, even though the number of phases of the clock signal can be reduced compared to the case of the sequential driving method, if the transmission structure of the carry signal is the same as the sequential driving method, the clock signal by the carry signal Problems with increasing number of phases may still occur. Therefore, even in the case of the cluster driving method, there are significant limitations in reducing the area of the clock wiring area where the clock wiring (SE_CW1~2, SC_CW1~2N, EM_CW1, CR_CW1~2) is placed.

Accordingly, below, we will describe a method that can effectively reduce the area of the clock wiring area by further reducing the phase of clock signals.

FIG. 12 is a diagram showing a gate driving circuit 130 having an intermediate stage in order to reduce the number of clock wires required for cluster driving of the display device 100 according to embodiments of the present invention, and FIG. 13 is a diagram showing the gate driving circuit 130 of the present invention. This diagram shows a structure in which the number of clock wires required for cluster driving of the display device 100 according to embodiments is reduced.

The display device 100 according to embodiments of the present invention includes a display panel 110 including a plurality of subpixels (SP) and a plurality of data lines (DL) and a plurality of gate lines (GL). , a data driving circuit 120 that drives a plurality of data lines DL, a gate driving circuit 130 that drives a plurality of gate lines GL, the data driving circuit 120, and the gate driving circuit 130. It may include a controller 140 that controls .

For N-cluster operation, multiple subpixels (SP) are grouped into M clusters (CLST #1 ~ CLST #M, M≥2), and each of the M clusters (CLST #1 ~ CLST #M) is N It may include subpixel lines (SPL #1 to SPL #N, N≥2). One cluster among M clusters (CLST #1 to CLST #M) has a different driving timing from the other clusters.

When driving an N-cluster, subpixels (SP) arranged on N subpixel lines (SPL #1 ~ SPL #N) included in each of M clusters (CLST #1 ~ CLST #M) can emit light simultaneously. .

When driving an N-cluster, the subpixels (SP) placed on the N subpixel lines (SPL #1 ~ SPL #N) included in each of the M clusters (CLST #1 ~ CLST #M) will perform a sensing operation simultaneously. You can.

Referring to FIG. 12, the gate driving circuit 130 is implemented as a Gate In Panel (GIP) type and may be placed in the non-active area (N/A), which is an area outside the active area (A/A). The gate driving circuit 130 may be connected to a plurality of gate lines GL disposed in the active area A/A.

Referring to FIG. 12, under the subpixel structure as shown in FIG. 2, the gate driving circuit 130 has (N+4) clock wires (SE_CW1, SC_CW1 to N, EM_CW1, CR_CW1, INT_CR_CW1) arranged in the non-active area. ) Based on (N+4) clock signals (SE_CLK1, SC_CLK1~N, EM_CLK1, CR_CLK1, INT_CR_CLK1) input through ( EML) can be run.

Each of the M gate driving units (GDUs) included in the gate driving circuit 130 receives N scan clock signals (SC_CLK1~N) out of (N+4) clock signals (SE_CLK1, SC_CLK1~N, EM_CLK1, CR_CLK1, INT_CR_CLK1). N), based on 1 sense clock signal (SE_CLK1), 1 emission control clock signal (EM_CLK1), and 1 carry clock signal (CR_CLK1), N scan signals (SCAN), 1 sense signal (SENSE), 1 Two light emission control signals (EM) and one carry signal (CARRY) can be output.

Each intermediate stage circuit (INTER_STAGE) included in the gate driving circuit 130 uses the remaining one intermediate carry clock signal (INT_CR_CLK1) among (N+4) clock signals (SE_CLK1, SC_CLK1 to N, EM_CLK1, CR_CLK1, INT_CR_CLK1). Based on this, one intermediate carry signal (INT_CARRY) can be output.

Referring to FIG. 12, the gate driving circuit 130 includes M gate driving units (GDU; ..., GDU #(i-1), GDU #i, GDU #(i+1), ...) and Among the M gate driving units (GDUs), an intermediate stage circuit ( INTER_STAGE: Intermediate Stage Circuit) may be included.

Referring to FIG. 12, M gate driving units (GDUs) each correspond to M clusters (CLST #1 to CLST #M) each containing different N subpixel lines (SPL #1 to SPL #N). . Each of the M gate driving units (GDUs) may include a first main stage circuit (MAIN_STAGE1) and a second main stage circuit (MAIN_STAGE2).

The first main stage circuit (MAIN_STAGE1) receives a carry clock signal (CR_CLK1), scan clock signals (SC_CLK1 to 4), and a sense clock signal (SE_CLK1), and receives a carry signal (CARRY) and scan signals (SCAN<1: N>) and sense signal (SENSE<1:N>) are output.

The first main stage circuit (MAIN_STAGE1) may have a shift register structure.

The first main stage circuit (MAIN_STAGE1) can be set or reset using the intermediate carry signal (INT_CARRRY) output from the intermediate stage circuit (INTER_STAGE).

The second main stage circuit (MAIN_STAGE2) can receive the emission control clock signal (EM_CLK1) and output the emission control signal (EM<1:N>) with a high level voltage. The second main stage circuit (MAIN_STAGE2) receives the carry signal (CARRY) output from the first main stage circuit (MAIN_STAGE1) as an input signal (VINP) and generates a low-level voltage emission control signal (EM<1:N>). can be output.

The second main stage circuit (MAIN_STAGE2) may have an inverter structure. Like the first main stage circuit (MAIN_STAGE1), the second main stage circuit (MAIN_STAGE2) may be configured with a shift register structure using a set signal (VST) and a reset signal (VRST).

Each of the M gate driving units (GDUs) corresponds to M stages for gate driving.

Referring to FIG. 12, the M gate driving units (GDUs) are the (i-1)th gate driving unit (GDU #(i-1)) of the (i-1)th stage, and the ith gate driving of the ith stage. It may include a unit (GDU #i) and an (i+1)th gate driving unit (GDU #(i+1)) which is the (i+1)th stage.

The (i-1)th gate driving unit (GDU #(i-1)) is placed in the (i-1)th cluster (CLST #(i-1)) among M clusters (CLST #1 to CLST #M). The gate lines (GL) can be driven. The ith gate driving unit (GDU #i) can drive the gate lines (GL) arranged in the ith cluster (CLST #i) among the M clusters (CLST #1 to CLST #M). The (i+1)th gate driving unit (GDU #(i+1)) is placed in the (i+1)th cluster (CLST #(i+1)) among M clusters (CLST #1 to CLST #M). The gate lines (GL) can be driven.

Referring to FIG. 12, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is connected to the i-th gate. A carry signal (CARRY) can be input from the driving unit (GDU #i) and the (i+1)th gate driving unit (GDU #(i+1)).

Referring to FIG. 12, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is connected to the i-th gate. An intermediate carry signal (INT_CARRY) can be output to the driving unit (GDU #i) and the (i+1)th gate driving unit (GDU #(i+1)).

Referring to FIG. 12, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is connected to the i-th gate. The carry signal (CARRY) can be input from the driving unit (GDU #i) as the set signal (VST) of the intermediate stage circuit (INTER_STAGE).

Referring to FIG. 12, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is (i+ 1) The carry signal (CARRY) can be input from the gate driving unit (GDU #(i+1)) as the reset signal (VRST) of the intermediate stage circuit (INTER_STAGE).

Referring to FIG. 12, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is connected to the i-th gate. The intermediate carry signal (INT_CARRY) can be output to the driving unit (GDU #i) as a reset signal (VRST) of the ith gate driving unit (GDU #i).

Referring to FIG. 12, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is (i+ 1) The intermediate carry signal (INT_CARRY) is output as the set signal (VST) of the (i+1)th gate driving unit (GDU #(i+1)). You can.

Meanwhile, the gate driving method with the intermediate stage briefly described above will be examined in detail through the specific structure of the subpixel (SP).

As described above with reference to FIG. 2, each of the plurality of subpixels (SP) of the display device 100 according to embodiments of the present invention includes a light emitting element (ED), a light emitting element (ED), and a light emitting element (ED). A driving transistor (DRT) that drives, a scan transistor (SCT) that controls the connection between the first node (N1) of the driving transistor (DRT) and the corresponding data line (DL) in response to the scan signal (SCAN), and a driving transistor ( It includes a storage capacitor (Cst) electrically connected between the first node (N1) and the second node (N2) of the DRT).

As described above with reference to FIG. 2, all or part of the plurality of subpixels (SP) of the display device 100 according to embodiments of the present invention are operated by the driving transistor (DRT) in response to the sense signal (SENSE). A sense transistor (SENT) that controls the connection between the second node (N2) and the corresponding reference line, and an emission control transistor (EMT) that controls the emission of the light emitting element (ED) in response to the emission control signal (EM) are further added. It can be included.

For the structure of this subpixel (SP), a plurality of gate lines (GL) disposed on the display panel 110 include a plurality of scan lines (SCL), a plurality of sense lines (SENL), and a plurality of emission control lines (EML). ) may include.

Referring to FIG. 13, as an example, (N+4) clock wires (SE_CW1, SC_CW1 to N, EM_CW1, CR_CW1, INT_CR_CW1) are disposed in the non-active area (N/A) of the display panel 110. You can.

(N+4) clock wires (SE_CW1, SC_CW1~N, EM_CW1, CR_CW1, INT_CR_CW1) are connected to each of M gate driving units (GDUs), and N-phase (N) scan clock signals (SC_CLK1~N) ) are connected to each of the M gate drive units (GDUs), and 1 phase (1 ) one sense clock wire (SE_CW1) that transmits the sense clock signal (SE_CLK1) to each of the M gate driving units (GDUs), and is connected to each of the M gate driving units (GDUs), 1 phase (1) One light emission control clock wire (EM_CW1) that transmits the light emission control clock signal (EM_CLK1) to each of the M gate drive units (GDUs), is connected to each of the M gate drive units (GDUs), and has 1 phase (1 ) is connected to one carry clock wire (CR_CW1) that delivers the carry clock signal (CR_CLK1) to each of the M gate driving units (GDUs) and each intermediate stage circuit (INTER_STAGE), and is connected to the middle of one phase (one) It may include one intermediate carry clock wire (INT_CR_CW1) that delivers the carry clock signal (INT_CR_CLK1) to each intermediate stage circuit (INTER_STAGE).

As described above, when using the gate driving circuit 130 having an intermediate stage, compared to using the gate driving circuit 130 of FIG. 11, the number of clock wires (number of clock signals) increases from 2N+5 to N+. It can be reduced to 4.

For example, in the case of 4-cluster driving, if the gate driving circuit 130 without an intermediate stage is used as shown in FIG. 11, the number of clock wires (number of clock signals) is 13, but the gate driving circuit with an intermediate stage is 13. If (130) is used, the number of clock wires (number of clock signals) becomes 8.

Therefore, as shown in FIG. 13, if the gate driving circuit 130 is used for the intermediate stage, the number of clock wires is reduced, and the clock wire area area in the non-active area (N/A) can be further reduced. .

Under the above-described subpixel structure, driving timing including internal compensation when driving a cluster will be briefly described.

The N subpixel lines (SPL #1 ~ SPL #N) included in each of the M clusters (CLST #1 ~ CLST #M) are N scan lines (SCL), N sense lines (SENL), and N It can be connected to the emission control line (EML).

During one frame time, the driving time of each of the N subpixel lines (SPL #1 ~ SPL #N) included in each of the M clusters (CLST #1 ~ CLST #M) is the sensing period (SENSING), the first holding It may include a period (HOLD1), a data writing period (DW), a second holding period (HOLD2), and an emission period (EMISSION). The sensing period (SENSING) may include an initialization period (INIT) and a sampling period (SAMP) (see FIGS. 4, 5, 6, and 9).

During the initialization period (INIT) within the sensing period (SENSING), N scan signals (SCAN) with turn-on level voltage are simultaneously applied to N scan lines (SCL), and turn-on level voltages are applied to N scan lines (SENL). N sense signals (SENSE) having an on-level voltage may be applied simultaneously, and N emission control signals (EM) having a turn-off level voltage may be simultaneously applied to the N emission control lines (EML).

During the sampling period (SAMP) within the sensing period (SENSING), N scan signals (SCAN) with turn-on level voltage are simultaneously applied to N scan lines (SCL), and turn-on level voltages are applied to N scan lines (SENL). N sense signals (SENSE) having an off-level voltage may be applied simultaneously, and N emission control signals (EM) having a turn-on level voltage may be simultaneously applied to the N emission control lines (EML).

During the first holding period (HOLD1), N scan signals (SCAN) having a turn-off level voltage are applied to the N scan lines (SCL), and N scan signals (SCAN) having a turn-off level voltage are applied to the N sense lines (SENL). N sense signals (SENSE) may be applied, and N emission control signals (EM) having a turn-off level voltage may be applied to N emission control lines (EML).

During the data writing period (DW), N sense signals (SENSE) with turn-off level voltage are applied to N sense lines (SENL), and N sense signals (SENSE) with turn-off level voltage are applied to N emission control lines (EML). N emission control signals (EM) may be applied, and N scan signals (SCAN) having turn-on level voltages may be sequentially applied to N scan lines (SCL).

During the second holding period (HOLD2), N scan signals (SCAN) having a turn-off level voltage are applied to the N scan lines (SCL), and N scan signals (SCAN) having a turn-off level voltage are applied to the N sense lines (SENL). N sense signals (SENSE) may be applied, and N emission control signals (EM) having a turn-off level voltage may be applied to N emission control lines (EML).

During the emission period (EMISSION), N scan signals (SCAN) with turn-off level voltages are applied to N scan lines (SCL), and N scan signals (SCAN) with turn-off level voltages are applied to N sense lines (SENL). A sense signal (SENSE) is applied, N emission control signals (EM) with turn-on level voltage are applied to N emission control lines (EML), and N subpixel lines (SPL #1 to SPL #N) are applied. ) can emit light at the same time.

For reference, in this specification, the turn-on level voltage of various gate signals (SCAN, SENSE, EM, etc.) is a voltage that can turn on the corresponding transistor (scan transistor, sense transistor, light emission control transistor, etc.). If the transistor is n-type, it may be a high-level voltage, and if the transistor is p-type, it may be a low-level voltage. In this specification, the turn-off level voltage of various gate signals (SCAN, SENSE, EM, etc.) is a voltage that can turn off the corresponding transistor (scan transistor, sense transistor, light emission control transistor, etc.), and the corresponding transistor is n If the transistor is a p-type, it may be a low-level voltage, and if the transistor is a p-type, it may be a high-level voltage. These turn-on level voltages and turn-off level voltages may also be applied to gate signals applied to gate nodes of transistors in the gate driving circuit 130.

N subpixel lines (SPL #1 to SPL #N) included in each of M clusters (CLST #1 to CLST #M). During each sampling period (SAMP), N subpixel lines (SPL #1 to SPL The voltage of the second node N2 of the driving transistor DRT of each of the subpixels SP disposed in #N) may increase and then become saturated. When the second node N2 of the driving transistor DRT is a source node, the above-described voltage rise and saturation phenomenon is called source following.

The source following phenomenon during the sampling period (SAMP) is a phenomenon in which the voltage of the second node (N2) of the driving transistor (DRT) finds a voltage state including the threshold voltage (Vth) of the driving transistor (DRT). The saturated voltage of the second node (N2) of the driving transistor (DRT) may be a voltage value (Vdata-Vth) that is different from the voltage (Vdata) of the first node (N1) of the driving transistor by the threshold voltage (Vth). there is.

Accordingly, during the sampling period SAMP, the saturated voltage of the second node N2 of the driving transistor DRT may vary depending on the threshold voltage of the driving transistor DRT.

Below, the gate driving circuit 130 having an intermediate stage briefly described with reference to FIG. 12 will be described in more detail with reference to FIGS. 14 to 17.

FIG. 14 is a diagram showing the gate driving circuit 130 having the intermediate stage of FIG. 12 in more detail, FIG. 15 is a diagram showing the first main stage circuit (MAIN_STAGE1) of FIG. 14, and FIG. 16 is a diagram showing the first main stage circuit (MAIN_STAGE1) of FIG. 14. 2 This is a diagram showing the main stage circuit (MAIN_STAGE2), and FIG. 17 is a diagram showing the intermediate stage circuit (INTER_STAGE) of FIG. 14.

Referring to FIG. 14, under the subpixel structure as shown in FIG. 2, the gate driving circuit 130 has (N+4) clock wires (SE_CW1, SC_CW1 to N, EM_CW1, CR_CW1, INT_CR_CW1) arranged in the non-active area. ) Based on (N+4) clock signals (SE_CLK1, SC_CLK1~N, EM_CLK1, CR_CLK1, INT_CR_CLK1) input through ( EML) can be run.

Referring to FIG. 14, the gate driving circuit 130 includes M gate driving units (GDU; ..., GDU #(i-1), GDU #i, GDU #(i+1), ...) and Among the M gate driving units (GDUs), an intermediate stage circuit ( INTER_STAGE: Intermediate Stage Circuit) may be included.

Referring to FIG. 14, each of the M gate driving units (GDUs) includes N scan clock signals (SC_CLK1 to N) among (N+4) clock signals (SE_CLK1, SC_CLK1 to N, EM_CLK1, CR_CLK1, INT_CR_CLK1), Based on one sense clock signal (SE_CLK1), one emission control clock signal (EM_CLK1), and one carry clock signal (CR_CLK1), N scan signals (SCAN<1:N>), 1 (or 1 to 1) N) sense signals (SENSE<1:N>), 1 (or 1 to N) emission control signals (EM<1:N>), and 1 carry signal (CARRY) can be output. .

Referring to FIG. 14, M gate driving units (GDUs) each correspond to M clusters (CLST #1 to CLST #M) each including N different subpixel lines (SPL #1 to SPL #N). . Each of the M gate driving units (GDUs) may include a first main stage circuit (MAIN_STAGE1) and a second main stage circuit (MAIN_STAGE2).

M gate driving units (GDUs) each correspond to M stages for gate driving.

Referring to FIG. 14, the M gate driving units (GDUs) are the (i-1)th gate driving unit (GDU #(i-1)) of the (i-1)th stage, and the ith gate driving of the ith stage. It may include a unit (GDU #i) and an (i+1)th gate driving unit (GDU #(i+1)) which is the (i+1)th stage.

The (i-1)th gate driving unit (GDU #(i-1)) is placed in the (i-1)th cluster (CLST #(i-1)) among M clusters (CLST #1 to CLST #M). The gate lines (GL) can be driven. The ith gate driving unit (GDU #i) can drive the gate lines (GL) arranged in the ith cluster (CLST #i) among the M clusters (CLST #1 to CLST #M). The (i+1)th gate driving unit (GDU #(i+1)) is placed in the (i+1)th cluster (CLST #(i+1)) among M clusters (CLST #1 to CLST #M). The gate lines (GL) can be driven.

Referring to FIG. 14, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is connected to the i-th gate. A carry signal (CARRY) can be input from the driving unit (GDU #i) and the (i+1)th gate driving unit (GDU #(i+1)).

Referring to FIG. 14, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is connected to the i-th gate. An intermediate carry signal (INT_CARRY) can be output to the driving unit (GDU #i) and the (i+1)th gate driving unit (GDU #(i+1)).

Referring to FIG. 14, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is connected to the i-th gate. The carry signal (CARRY) can be input from the driving unit (GDU #i) as the set signal (VST) of the intermediate stage circuit (INTER_STAGE).

Referring to FIG. 14, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is (i+ 1) The carry signal (CARRY) can be input from the gate driving unit (GDU #(i+1)) as the reset signal (VRST) of the intermediate stage circuit (INTER_STAGE).

Referring to FIG. 14, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is connected to the i-th gate. The intermediate carry signal (INT_CARRY) can be output to the driving unit (GDU #i) as a reset signal (VRST) of the ith gate driving unit (GDU #i).

Referring to FIG. 14, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is (i+ 1) The intermediate carry signal (INT_CARRY) is output as the set signal (VST) of the (i+1)th gate driving unit (GDU #(i+1)). You can.

Referring to FIG. 14, the first main stage circuit (MAIN_STAGE1) of each of the M gate driving units (GDUs) includes a scan signal output unit 1420, a sense signal output unit 1410, and a carry signal output unit 1430. It can be included. The second main stage circuit (MAIN_STAGE2) of each of the M gate driving units (GDU) may include a light emission control signal output unit 1440. The intermediate stage circuit (INTER_STAGE) may include an intermediate carry signal output unit 1450.

Referring to FIG. 14, the scan signal output unit 1420 of the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i) responds to N scan clock signals (SC_CLK1 to N), N scan signals (SCAN<1:N>) can be output.

In the case of 4-cluster driving with N = 4, as shown in FIG. 15, the scan signal output unit 1420 of the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i) is 4. In response to the scan clock signals (SC_CLK1~4), four scan signals (SCAN<1:4>; SCAN #1, SCAN #2, SCAN #3, SCAN #4) can be output.

Referring to FIG. 14, the sense signal output unit 1410 of the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i) responds to one sense clock signal (SE_CLK1), 1 Output K sense signals (SENSE<1:N>; SENSE) (see FIG. 18), or K (1≤K≤N) sense signals (SENSE<1:N>; SENSE #1 ~ SENSE #N) It can be output (see FIG. 19).

In the case of 4-cluster driving with N = 4, as shown in FIG. 15, the sense signal output unit 1410 of the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i) is, In response to one sense clock signal (SE_CLK1), one sense signal (SENSE<1:4>; SENSE) is output (see FIG. 18), or K(1≤K≤4) sense signals (SENSE<1) are output. :4>; SENSE #1 ~ SENSE #4) can be output (see FIG. 19).

Referring to FIG. 14, the carry signal output unit 1430 of the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i) responds to one carry clock signal (CR_CLK1), i The second main stage circuit (MAIN_STAGE2) included in the (i-1)th gate driving unit (GDU #(i-1)) and the ith gate driving unit (GDU #i) ) and an intermediate stage circuit (INTER_STAGE) disposed between the ith gate driving unit (GDU #i) and the (i+1)th gate driving unit (GDU #(i+1)). INTER_STAGE) can output one carry signal (CARRY).

Referring to FIG. 14, the emission control signal output unit 1440 included in the second main stage circuit (MAIN_STAGE2) included in the ith gate driving unit (GDU #i) outputs one emission control clock signal (EM_CLK1). In response, one emission control signal (EM<1:N>; EM) or K(1≤K≤N) emission control signals (EM<1:N>) can be output.

In the case of 4-cluster driving with N = 4, as shown in FIG. 16, the light emission control signal output unit 1440 included in the second main stage circuit (MAIN_STAGE2) included in the ith gate driving unit (GDU #i) ) outputs one light emission control signal (EM<1:4>; EM) in response to one light emission control clock signal (EM_CLK1) (see FIG. 18), or emits K (1≤K≤4) lights. A control signal (EM <1:4>; EM #1 to EM #4) can be output (see FIG. 19).

Referring to FIG. 14, the intermediate carry included in the intermediate stage circuit (INTER_STAGE) located between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) The signal output unit 1450 responds to one intermediate carry clock signal (INT_CR_CLK1), the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i), and the (i+1)th One intermediate carry signal (INT_CARRY) can be output to the first main stage circuit (MAIN_STAGE1) included in the gate driving unit (GDU #(i+1)).

Referring to FIG. 14, one carry signal (CARRY) output from the carry signal (CARRY) output unit included in the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i) is i. It may be input as the input signal (VINP) of the second main stage circuit (MAIN_STAGE2) included in the second gate driving unit (GDU #i).

Referring to FIG. 14, one carry signal (CARRY) output from the carry signal (CARRY) output unit included in the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i) is i. It can be input as a set signal (VST) of the intermediate stage circuit (INTER_STAGE) disposed between the (i+1)th gate driving unit (GDU #i) and the (i+1)th gate driving unit (GDU #(i+1)).

Referring to FIG. 14, one carry signal (CARRY) output from the carry signal (CARRY) output unit included in the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i) is ( It can be input as a reset signal (VRST) of the intermediate stage circuit (INTER_STAGE) disposed between the (i-1)th gate driving unit (GDU #(i-1)) and the ith gate driving unit (GDU #i).

Referring to FIG. 14, the light emission control signal output unit 1440 included in the second main stage circuit (MAIN_STAGE2) is one signal output from the carry signal output unit 1430 included in the first main stage circuit (MAIN_STAGE1). One emission control signal (EM) in which the carry signal (CARRY) is inverted can be output.

Referring to FIG. 14, the intermediate carry included in the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) The intermediate carry signal (INT_CARRY) output from the signal output unit 1450 may be input as the reset signal (VRST) of the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i).

Referring to FIG. 14, the intermediate carry included in the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) The intermediate carry signal (INT_CARRY) output from the signal output unit 1450 is the set signal ( VST).

Referring to FIG. 15, the sense signal output unit 1410, the scan signal output unit 1420, and the carry signal output unit 1430 included in the first main stage circuit (MAIN_STAGE1) of the ith gate driving unit (GDU #i). ) Each may include at least one output buffer (OUT_BUF).

Referring to FIG. 15, the carry signal output unit 1430 is composed of a pull-up transistor (Tu_1) and a pull-down transistor (Td_1), and the pull-up transistor (Tu_1) and the pull-down transistor (Td_1) are connected. A carry signal (CARRY) can be output to the output node. The carry clock signal (CR_CLK1) is applied to the drain node (or source node) of the pull-up transistor (Tu_1), and the base power (VSS1) is applied to the drain node (or source node) of the pull-down transistor (Td_1). You can. A capacitor (Cu_1) may be connected between the gate node and the source node (or drain node) of the pull-up transistor (Tu_1).

The gate node of the pull-up transistor (Tu_1) corresponds to the Q node, and the gate node of the pull-down transistor (Td_1) corresponds to the QB node. When the Q node has a high level voltage, the pull-up transistor (Tu_1) is turned on and outputs the carry clock signal (CR_CLK1) as the carry signal (CARRY) of the high level voltage to the output node. When the QB node has a high level voltage, the pull-down transistor (Td_1) is turned on and outputs the base power supply (VSS1) as a carry signal (CARRY) of the low level voltage to the output node.

Referring to FIG. 15, the sense signal output unit 1410 is composed of a pull-up transistor (Tu_2) and a pull-down transistor (Td_2), and the pull-up transistor (Tu_2) and the pull-down transistor (Td_2) are connected. A sense signal (SENSE) can be output to the output node. The sense clock signal (SE_CLK1) is applied to the drain node (or source node) of the pull-up transistor (Tu_2), and the base power (VSS1) is applied to the drain node (or source node) of the pull-down transistor (Td_2). You can. A capacitor (Cu_2) may be connected between the gate node and the source node (or drain node) of the pull-up transistor (Tu_2).

The gate node of the pull-up transistor (Tu_2) corresponds to the Q node, and the gate node of the pull-down transistor (Td_1) corresponds to the QB node. When the Q node has a high level voltage, the pull-up transistor (Tu_2) is turned on and outputs the carry clock signal (CR_CLK1) as a sense signal (SENSE) of the turn-on level voltage to the output node. When the QB node has a high level voltage, the pull-down transistor (Td_2) is turned on and outputs the base power supply (VSS1) to the output node as a sense signal (SENSE) of the turn-off level voltage.

Referring to FIG. 15, in the case of N-4 4-cluster driving, the scan signal output unit 1420 uses 4 (N=4) pull-up transistors (Tu_3, Tu_4, Tu_5, Tu_6) and 4 (N It is composed of =4) pull-down transistors (Td_3, Td_4, Td_5, Td_6).

In the case of N-4 4-cluster driving, the first scan signal (SCAN) is transmitted from the scan signal output unit 1420 to the output node to which the first pull-up transistor (Tu_3) and the first pull-down transistor (Td_3) are connected. #1), output a second scan signal (SCAN #1) to the output node to which the second pull-up transistor (Tu_4) and the second pull-down transistor (Td_4) are connected, and output the second scan signal (SCAN #1) to the output node to which the second pull-up transistor (Tu_4) and the second pull-down transistor (Td_4) are connected. The third scan signal (SCAN #1) is output to the output node to which (Tu_5) and the third pull-down transistor (Td_5) are connected, and the fourth pull-up transistor (Tu_6) and the fourth pull-down transistor (Td_6) are output. The fourth scan signal (SCAN #1) can be output to the connected output node.

The first scan clock signal (SC_CLK1) is applied to the drain node (or source node) of the first pull-up transistor (Tu_3), and the second scan clock signal (SC_CLK1) is applied to the drain node (or source node) of the second pull-up transistor (Tu_4). The scan clock signal (SC_CLK2) is applied, the third scan clock signal (SC_CLK3) is applied to the drain node (or source node) of the third pull-up transistor (Tu_5), and the third scan clock signal (SC_CLK3) is applied to the drain node (or source node) of the fourth pull-up transistor (Tu_6). The fourth scan clock signal (SC_CLK4) is applied to the drain node (or source node). Capacitors (Cu_3, Cu_4, Cu_5, and Cu_6) may be connected between the gate node and the source node (or drain node) of the first to fourth pull-up transistors (Tu_3, Tu_4, Tu_5, and Tu_6).

The base power source VSS1 may be commonly applied to the drain nodes (or source nodes) of the first to fourth pull-down transistors Td_3, Td_4, Td_5, and Td_6.

The gate nodes (Q nodes) of the first to fourth pull-up transistors (Tu_3, Tu_4, Tu_5, and Tu_6) may all be electrically connected (Q node sharing structure). The gate nodes (QB nodes) of the first to fourth pull-down transistors (Td_3, Td_4, Td_5, and Td_6) may all be electrically connected (QB node sharing structure). In this case, only one logic (LOGIC) is needed to control the Q node and QB node.

Alternatively, the gate nodes (Q nodes) of the first to fourth pull-up transistors (Tu_3, Tu_4, Tu_5, and Tu_6) may all be electrically separated (Q node isolation structure). The gate nodes (QB nodes) of the first to fourth pull-down transistors (Td_3, Td_4, Td_5, and Td_6) can all be electrically separated (QB node isolation structure). In this case, 4 logics (LOGIC) are required.

When the Q node has a high level voltage, the first to fourth pull-up transistors (Tu_3, Tu_4, Tu_5, Tu_6) are turned on, and the first to fourth scan clock signals (SC_CLK1 to 4) are connected to the first to fourth pull-up transistors (Tu_3, Tu_4, Tu_5, Tu_6). It is output to the output node as the fourth scan signal (SCAN #1 to SCAN #4). Here, depending on the voltage levels of the first to fourth scan clock signals (SC_CLK1 to 4), the first to fourth scan signals (SCAN #1 to SCAN #4) may all be the same, and the first to fourth scan signals (SCAN #1 to SCAN #4) may be the same. Some of the signals (SCAN #1 to SCAN #4) may be different.

When the QB node has a high level voltage, the first to fourth pull-down transistors (Td_3, Td_4, Td_5, Td_6) are turned on, and the base power supply (VSS1) is sent to the first to fourth scan signals (SCAN #1). ~ SCAN #4) and output to the output node.

Referring to FIG. 15, the first main stage circuit (MAIN_STAGE1) of the ith gate driving unit (GDU #i) includes a sense signal output unit 1410, a scan signal output unit 1420, and a carry signal output unit 1430. , may further include logic (LOGIC).

Referring to FIG. 15, the logic (LOGIC) included in the first main stage circuit (MAIN_STAGE1) of the ith gate driving unit (GDU #i) is the (i-1)th gate driving unit (GDU #(i-1). )) and the ith gate driving unit (GDU #i) receive the intermediate carry signal (INT_CARRY) output from the intermediate stage circuit (INTER_STAGE) as a set signal (VST), and The intermediate carry signal (INT_CARRY) output from the intermediate stage circuit (INTER_STAGE) disposed between i) and (i+1)th gate driving unit (GDU #(i+1)) is input as a reset signal (VRST).

Referring to FIG. 15, the gate nodes (Q node) of the pull-up transistors (Tu_1 to Tu_6) are all electrically connected, and the gate nodes (QB node) of the pull-down transistors (Td_1 to Td_6) are electrically connected. All can be electrically connected (Q node sharing structure, QB node sharing structure).

In this way, in the case of having the Q node sharing structure and the QB node sharing structure, the logic (LOGIC) included in the first main stage circuit (MAIN_STAGE1) of the ith gate driving unit (GDU #i) is the input set signal (VST). ) or using the reset signal (VRST) and the input power sources (VDD, VSS2), the gate nodes of the pull-up transistors (Tu_1 to Tu_6) are all electrically connected to a shared Q node, and the pull-down The gate nodes of the transistors (Td_1 to Td_6) are all electrically connected to control the shared QB node.

The gate nodes (Q nodes) of the pull-up transistors (Tu_1 to Tu_6) can all be electrically separated, and the gate nodes (QB nodes) of the pull-down transistors (Td_1 to Td_6) can all be electrically separated. (Q node separation structure, QB node separation structure).

As such, in the case of having the Q node separation structure and the QB node separation structure, the first main stage circuit (MAIN_STAGE1) of the ith gate driving unit (GDU #i) output signals (CARRY, SENSE, SCAN #1, SCAN # 2, SCAN #3, SCAN #4) can include separate logic (LOGIC). That is, the first main stage circuit (MAIN_STAGE1) of the ith gate driving unit (GDU #i) is the gate node of the pull-up transistor (Tu_1) and the pull-down transistor (Td_1) for outputting the carry signal (CARRY). gate nodes (Q node, Logic (LOGIC) for controlling the QB node) and gate nodes (Q node, QB) of the pull-up transistor (Tu_3) and pull-down transistor (Td_3) for outputting the first scan signal (SCAN #1) gate nodes (Q node, QB node) of the logic (LOGIC) for controlling the node) and the pull-up transistor (Tu_4) and pull-down transistor (Td_4) for outputting the second scan signal (SCAN #2) ) and gate nodes (Q node, QB node) of the pull-up transistor (Tu_5) and pull-down transistor (Td_5) for outputting the third scan signal (SCAN #3). logic (LOGIC) for controlling, and the gate nodes (Q node, QB node) of the pull-up transistor (Tu_6) and pull-down transistor (Td_6) for outputting the fourth scan signal (SCAN #4). It may include logic (LOGIC) for control.

Referring to FIG. 15, when the high-level voltage set signal (VST) and the low-level voltage reset signal (VRST) are input, the logic (LOGIC) outputs the high-level voltage set signal (VST) to the Q node. , output low-level voltage power to the QB node. Accordingly, the Q node has a high level voltage, and the QB node has a low level voltage. Accordingly, all pull-up transistors (Tu_1 to Tu_6) included in the carry signal output unit 1430, sense signal output unit 1410, and scan signal output unit 1420 are turned on, and all pull-down transistors are turned on. (Td_1 to Td_6) are turned off.

Referring to FIG. 15, when the high-level voltage reset signal (VRST) and the low-level voltage set signal (VST) are input, the logic (LOGIC) outputs the high-level voltage power supply (VDD) to the QB node, The low-level voltage power supply (VSS2) is output to the Q node. Accordingly, the QB node has a high level voltage, and the Q node has a low level voltage. Accordingly, all pull-down transistors (Td_1 to Td_6) included in the carry signal output unit 1430, sense signal output unit 1410, and scan signal output unit 1420 are turned on, and all pull-up transistors are turned on. (Tu_1 to Tu_6) are turned off.

This logic (LOGIC_INT) may be composed of multiple transistors to operate as described above.

Referring to FIG. 16, the light emission control signal output unit 1440 of the second main stage circuit (MAIN_STAGE2) outputs one carry signal from the carry signal output unit 1430 included in the first main stage circuit (MAIN_STAGE1). (CARRY) is input as an input signal (VINP), and an emission control clock signal (EM_CLK1) and various power supplies (VD2, VDD2, VSS3, VSS4) are further input.

The light emission control signal output unit 1440 of the second main stage circuit (MAIN_STAGE2) receives the carry signal (CARRY) output from the carry signal output unit 1430 included in the first main stage circuit (MAIN_STAGE1) as an input signal (VINP). ), and can output one emission control signal (EM) using the input carry signal (CARRY).

Here, the emission control signal (EM) may be a signal whose voltage level is inverted from that of the carry signal (CARRY). That is, the emission control signal (EM) may be an inverted signal of the carry signal (CARRY).

The light emission control signal output unit 1440 of the second main stage circuit (MAIN_STAGE2) may receive the light emission control clock signal (EM_CLK1) and output the light emission control signal (EM) with a high level voltage. The second main stage circuit (MAIN_STAGE2) can receive the carry signal (CARRY) output from the first main stage circuit (MAIN_STAGE1) as an input signal (VINP) and output an emission control signal (EM) of a low level voltage. .

Referring to FIG. 17, the intermediate carry signal output unit 1450 of the intermediate stage circuit (INTER_STAGE) includes a pull-up transistor (Tu_i) and a pull-down transistor (Td_i), and the pull-up transistor (Tu_i) It may include logic (LOGIC_INT) that controls the Qi node corresponding to the gate node and the QBi node corresponding to the gate node of the pull-down transistor (Td_i).

The intermediate carry signal output unit 1450 may output the intermediate carry signal (INT_CARRY) to an output node to which the pull-up transistor (Tu_i) and the pull-down transistor (Td_i) are connected. The intermediate carry clock signal (INT_CR_CLK1) is applied to the drain node (or source node) of the pull-up transistor (Tu_i), and the base power (VSS1) is applied to the drain node (or source node) of the pull-down transistor (Td_i). It can be.

In the intermediate carry signal output unit 1450, the gate node of the pull-up transistor (Tu_i) corresponds to the Q node, and the gate node of the pull-down transistor (Td_i) corresponds to the QB node. When the Q node has a high level voltage, the pull-up transistor (Tu_i) is turned on and outputs the intermediate carry clock signal (INT_CR_CLK1) as the intermediate carry signal (INT_CARRY) of the high level voltage to the output node. When the QB node has a high level voltage, the pull-down transistor (Td_i) is turned on and outputs the base power supply (VSS1) as a carry signal (CARRY) of the low level voltage to the output node.

Referring to FIG. 17, the logic (LOGIC_INT) included in the intermediate carry signal output unit 1450 of the intermediate stage circuit (INTER_STAGE) includes various power supplies (VDD, VSS2), set signal (VST), and reset signal (VRST). By receiving input, you can set and reset operations, and control the Qi node and QBi node.

Included in the intermediate carry signal output unit 1450 of the intermediate stage circuit (INTER_STAGE) located between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) The set signal (VST) input to the logic (LOGIC_INT) is the carry signal (CARRY) output from the carry signal output unit 1430 of the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i). ) can be.

Included in the intermediate carry signal output unit 1450 of the intermediate stage circuit (INTER_STAGE) located between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) The reset signal VRST input to the logic (LOGIC_INT) is the carry signal output unit 1430 of the first main stage circuit (MAIN_STAGE1) included in the (i+1)th gate driving unit (GDU #(i+1)). It may be a carry signal (CARRY) output from ).

Referring to FIG. 17, when the high-level voltage set signal (VST) and the low-level voltage reset signal (VRST) are input, the logic (LOGIC_INT) outputs the high-level voltage set signal (VST) to the Qi node. , output low-level voltage power to the QBi node. Accordingly, the Q node has a high level voltage, and the QB node has a low level voltage. Accordingly, the pull-up transistor (Tui) is turned on, and the pull-down transistor (Tdi) is turned off.

Referring to FIG. 17, when the reset signal (VRST) of the high level voltage and the set signal (VST) of the low level voltage are input, the logic (LOGIC_INT) outputs the power supply (VDD) of the high level voltage to the QBi node, The low-level voltage power supply (VSS2) is output to the Qi node. Accordingly, the QBi node has a high level voltage, and the Qi node has a low level voltage. Accordingly, the pull-up transistor (Tui) is turned off and the pull-down transistor (Tdi) is turned on.

This logic (LOGIC_INT) may be composed of multiple transistors to operate as described above.

Figure 18 is a diagram briefly showing the supply structure of a sense signal (SENSE) and an emission control signal (EM) for cluster driving of the display device 100 according to embodiments of the present invention.

Referring to FIG. 18, one sense signal (SENSE) output from the sense signal output unit 1410 included in the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i) is i. It may be branched and applied to the N sense lines (SENL #1 to SENL #N) corresponding to the N subpixel lines (SPL #1 to SPL #N) included in the th cluster (CLST #i).

To this end, in the active area (A/A) or non-active area (N/A) of the display panel 110, at least one point ( CNT_SENL) may exist.

Accordingly, the sense transistor (SENT) disposed in the subpixels (SP) included in the N subpixel lines (SPL #1 to SPL #N) included in each of the M clusters (CLST #1 to CLST #M). Their gate nodes may be electrically connected or a sense signal (SENSE) may be applied simultaneously.

Referring to FIG. 18, one emission control signal (EM) output from the emission control signal output unit 1440 to the second main stage circuit (MAIN_STAGE2) included in the ith gate driving unit (GDU #i) is N. It can be branched and applied to N emission control lines (EML #1 to EML #N) corresponding to the subpixel lines (SPL #1 to SPL #N).

To this end, in the active area (A/A) or non-active area (N/A) of the display panel 110, one or more points where N emission control lines (EML #1 to EML #N) are electrically connected. (CNT_EML) may exist.

Accordingly, the emission control transistor (EMT) disposed in the subpixels (SP) included in the N subpixel lines (SPL #1 to SPL #N) included in each of the M clusters (CLST #1 to CLST #M). )'s gate nodes may be electrically connected or an emission control signal (EM) may be applied simultaneously.

The display panel 110, which has such a supply structure for the sense signal (SENSE) and the emission control signal (EM) and includes the GIP type gate driving circuit 130, is briefly described as follows.

The display panel 110 according to embodiments of the present invention is disposed in the active area (A/A) and includes a plurality of subpixels (SP) connected to a plurality of data lines (DL) and a plurality of gate lines (GL). and a gate driving circuit 130 disposed in the non-active area (N/A), which is an outer area of the active area (A/A), and connected to a plurality of gate lines (GL).

Multiple subpixels (SP) are grouped into M clusters (CLST #1 to CLST #M), and each of the M clusters (CLST #1 to CLST #M) contains N subpixel lines (SPL #1 to SPL # N) may be included. Here, M may be a natural number of 2 or more, and N may be a natural number of 2 or more.

Subpixels (SP) arranged on N subpixel lines (SPL #1 to SPL #N) included in each of M clusters (CLST #1 to CLST #M) may emit light simultaneously.

The plurality of gate lines (GL) may include a plurality of scan lines (SCL), a plurality of sense lines (SENL), and a plurality of emission control lines (EML).

Each of the plurality of subpixels (SP) includes a light emitting element (ED), a driving transistor (DRT) for driving the light emitting element (ED), and a first node ( A scan transistor (SCT) that controls the connection between N1) and the corresponding data line (DL), and a storage capacitor (Cst) electrically connected between the first node (N1) and the second node (N2) of the driving transistor (DRT) may include.

All or part of the plurality of subpixels (SP) include a sense transistor (SENT) that controls the connection between the second node (N2) of the driving transistor (DRT) and the corresponding reference line in response to the sense signal (SENSE), and a light emitting device. It may further include an emission control transistor (EMT) that controls light emission of the light emitting element (ED) in response to the control signal (EM).

Gate nodes of the sense transistors (SENT) arranged on N subpixel lines (SPL #1 to SPL #N) may be electrically connected or a sense signal (SENSE) may be applied simultaneously.

The gate nodes of the emission control transistors (EMT) arranged on N subpixel lines (SPL #1 to SPL #N) may be electrically connected or an emission control signal (EM) may be applied simultaneously.

The display panel 110 is placed in the non-active area (N/A) and has (N+4) clock wires (SE_CW1, SC_CW1 to N) that supply (N+4) clock signals to the gate driving circuit 130. , EM_CW1, CR_CW1, INT_CR_CW1) may be further included.

Meanwhile, the gate driving circuit 130 receives (N+4) clock signals input through (N+4) clock wires (SE_CW1, SC_CW1 to N, EM_CW1, CR_CW1, INT_CR_CW1) arranged in the non-active area. Based on this, multiple scan lines (SCL), multiple sense lines (SENL), and multiple emission control lines (EML) are driven.

Meanwhile, each of the M gate driving units (GDUs) included in the gate driving circuit 130 receives N scan clock signals ( Based on SC_CLK1~N), one sense clock signal (SE_CLK1), one emission control clock signal (EM_CLK1), and one carry clock signal (CR_CLK1), N scan signals (SCAN), 1 to N sense signals (SENSE), 1 to N emission control signals (EM), and 1 carry signal (CARRY) can be output.

Each intermediate stage circuit (INTER_STAGE) included in the gate driving circuit 130 uses the remaining one intermediate carry clock signal (INT_CR_CLK1) among (N+4) clock signals (SC_CLK1 to N, SE_CLK1, EM_CLK1, CR_CLK1, INT_CR_CLK1). Based on this, one intermediate carry signal (INT_CARRY) can be output.

FIG. 19 is a diagram briefly illustrating another supply structure of a sense signal (SENSE) and an emission control signal (EM) for cluster driving of the display device 100 according to embodiments of the present invention.

Referring to FIG. 19, each of the M gate driving units (GDUs) included in the gate driving circuit 130 receives N sense signals (SENSE #1 to SENSE #N) and N light emission control signals (EM #1 to EM #1). EM #N) can be output.

Referring to FIG. 19, N sense signals (SENSE #1 to SENSE) output from the sense signal output unit 1410 included in the first main stage circuit (MAIN_STAGE1) included in the ith gate driving unit (GDU #i). #N) is applied separately to the N subpixel lines (SPL #1 ~ SPL #N) included in the ith cluster (CLST #i) and the corresponding N sense lines (SENL #1 ~ SENL #N). It can be.

Referring to FIG. 19, N emission control signals (EM #1 to EM) output from the emission control signal output unit 1440 to the second main stage circuit (MAIN_STAGE2) included in the ith gate driving unit (GDU #i). #N) can be applied separately to N subpixel lines (SPL #1 to SPL #N) and corresponding N emission control lines (EML #1 to EML #N).

FIG. 20 shows clock signals (SE_CLK1, SC_CLK1, SC_CLK2, SC_CLK3) supplied to the gate driving circuit 130 having an intermediate stage for cluster driving of the display device 100 according to embodiments of the present invention. , SC_CLK4, EM_CLK1, CR_CLK1, INT_CR_CLK1).

Referring to FIG. 20, when driving a 4-cluster, eight clock signals (SE_CLK1, SC_CLK1, SC_CLK2, SC_CLK3, SC_CLK4, EM_CLK1, CR_CLK1, INT_CR_CLK1) are used to drive the gate.

Referring to Figure 20, eight clock signals (SE_CLK1, SC_CLK1, SC_CLK2, SC_CLK3, SC_CLK4, EM_CLK1, CR_CLK1, INT_CR_CLK1) for 4-cluster driving are internally compensated driving timing (SENSING - > HOLD1 -> DW -> HOLD2 -> EMISSION) the voltage level may change.

Referring to Figure 20, eight clock signals (SE_CLK1, SC_CLK1, SC_CLK2, SC_CLK3, SC_CLK4, EM_CLK1, CR_CLK1, INT_CR_CLK1) include four scan clock signals (SC_CLK1 to 4), one sense clock signal (SE_CLK1), It includes one emission control clock signal (EM_CLK1), one carry clock signal (CR_CLK1), and one intermediate carry clock signal (INT_CLK1).

In the first stage (Stage #1), the gate driving unit (GDU) corresponding to the first stage (Stage #1) inputs one intermediate carry clock signal (INT_CLK1) with a high level voltage as a set signal (VST). It starts when the gate driving unit (GDU) corresponding to the first stage (Stage #1) receives one intermediate carry clock signal (INT_CLK1) with a high level voltage as the reset signal (VRST) and is reset. (Rest) It is done.

In the second stage (Stage #2), the gate driving unit (GDU) corresponding to the second stage (Stage #2) inputs one intermediate carry clock signal (INT_CLK1) that resets the first stage (Stage #1). It can be started when the gate driving unit (GDU) corresponding to the second stage (Stage #2) receives one intermediate carry clock signal (INT_CLK1) with a high level voltage as a reset signal (VRST). It is reset (Rest).

The timing at which the intermediate carry clock signal INT_CLK1 changes from the low level voltage to the high level voltage may occur following the timing at which the carry clock signal CR_CLK1 changes from the high level voltage to the low level voltage. This is because the intermediate stage circuit (INTER_STAGE) receives the carry signal (CARRY) output from the carry signal output unit 1430 in the first main stage circuit (MAIN_STAGE1) as a set signal (VST).

When the first stage (Stage #1) starts, internal compensation driving periods (SENSING -> HOLD1 -> DW -> HOLD2 -> EMISSION) proceed.

During the sensing period (SENSING), the four scan clock signals (SC_CLK1 to 4) have high level voltages. During the sensing period (SENSING), one sense clock signal (SE_CLK1) has a high level voltage and changes to a low level voltage, and one emission control clock signal (EM_CLK1) has a low level voltage and changes to a high level voltage. can do.

After the sensing period (SENSING), during the data writing period (DW), the four scan clock signals (SC_CLK1 to 4) sequentially have high level voltage sections. During the data writing period (DW), one sense clock signal (SE_CLK1) and one emission control clock signal (EM_CLK1) have a low level voltage.

After the data writing period (DW), during the emission period (EMISSION), one emission control clock signal (EM_CLK1) has a high level voltage. Four scan clock signals (SC_CLK1 to 4) and one sense clock signal (SE_CLK1) have low level voltages.

Referring to FIG. 20, an intermediate stage circuit (INTER_STAGE) is additionally provided between gate driving units (GDUs) corresponding to each stage, so that a high section in which the Q node has a high level voltage in the first stage (Stage #1) (HIGH section) and the high section (HIGH section) in which the Q node has a high level voltage in the second stage (Stage #2) do not overlap with each other. Therefore, compared to normal cluster driving without an intermediate stage, many clock signals are not needed.

Figure 21 is a diagram showing the number of clocks according to three driving methods (sequential driving method, cluster driving method, and cluster driving method with an intermediate stage).

Referring to FIG. 21, when each subpixel (SP) has a 4T (Transistor) 1C (Capacitor) structure as shown in FIG. 2, a sequential driving method, a normal cluster driving method without an intermediate stage, and a cluster with an intermediate stage are used. For each driving method, the number of clock signals (number of phases) for generating the gate signals (SENSE, SCAN, EM), carry signal (CARRRY), and intermediate carry signal (INT_CARRY) are compared.

For example, in the case of sequential driving method (i.e., when the cluster size (N) is 1), 5 sense clock signals (SE_CLK1~5), 5 scan clock signals (SC_CLK1~5), and 5 light emission control clocks 20 clock signals may be required, including signals (EM_CLK1 to 5) and 5 carry clock signals (CR_CLK1 to 5). In some cases, 6 sense clock signals (SE_CLK1~6), 6 scan clock signals (SC_CLK1~6), 6 emission control clock signals (EM_CLK1~6), and 6 carry clock signals (CR_CLK1~6) Including, 24 clock signals may be required.

For example, in the case of the Normal 4-cluster driving method, which is a clockster driving method with a cluster size (N) of 4 and no intermediate stage, 2 sense clock signals (SE_CLK1~2) and 8 scan clock signals ( 13 (=2N+5=2*4+5) clock signals may be required, including SC_CLK1~8), one emission control clock signal (EM_CLK1), and two carry clock signals (CR_CLK1~2). .

For example, in the case of a 4-cluster driving method with an intermediate stage, 1 sense clock signal (SE_CLK1), 4 scan clock signals (SC_CLK1~4), 1 emission control clock signal (EM_CLK1), and 1 carry clock Eight (=N+4=4+4) clock signals may be required, including a signal (CR_CLK1) and one intermediate carry clock signal (INT_CR_CLK1).

Therefore, the number of clock signals (8) for gate driving in the 4-cluster driving method with an intermediate stage is much smaller than the number of clock signals (20 to 24) in the sequential driving method, and the number of clock signals (8) for gate driving in the 4-cluster driving method with an intermediate stage is much smaller than the number of clock signals (20 to 24) in the sequential driving method. It is less than the number of clock signals (13) in the cluster driving method.

For example, in the case of the Normal 6-cluster driving method, which is a clockster driving method with a cluster size (N) of 6 and no intermediate stage, 2 sense clock signals (SE_CLK1~2) and 12 scan clock signals ( 17 clock signals (=2N+5=2*6+5) may be required, including SC_CLK1~12), one emission control clock signal (EM_CLK1), and two carry clock signals (CR_CLK1~2). .

For example, in the case of a 6-cluster driving method with an intermediate stage, 1 sense clock signal (SE_CLK1), 6 scan clock signals (SC_CLK1~6), 1 emission control clock signal (EM_CLK1), and 1 carry clock Including a signal (CR_CLK1) and one intermediate carry clock signal (INT_CR_CLK1), 10 (=N+4=6+4) clock signals may be required.

Therefore, the number of clock signals for gate driving in the 6-cluster driving method with an intermediate stage (10) is much smaller than the number of clock signals (20 to 24) in the sequential driving method, and the number of clock signals for gate driving in the 6-cluster driving method with an intermediate stage is much smaller than the number of clock signals (20 to 24) in the sequential driving method. It is less than the number of clock signals (17) in the cluster driving method.

In conclusion, the cluster driving method with an intermediate stage according to embodiments of the present invention not only reduces the number of clock signals (number of clock phases) due to the cluster driving itself, but also operates without overlapping the high section of the Q node. By making this possible, the number of clock signals (number of clock phases) can be further reduced compared to the normal cluster driving method. Accordingly, the clock wiring area can be significantly reduced, thereby significantly reducing the bezel size.

The cluster driving method with an intermediate stage according to embodiments of the present invention may be more effective when there are multiple types of gate signals.

Additionally, in the case of a cluster driving method with an intermediate stage according to embodiments of the present invention, the gate driving circuit 130 can be greatly simplified by sharing the Q node.

In addition, according to embodiments of the present invention, a display device 100 and a display panel ( 110) and a gate driving circuit 130 may be provided.

In addition, according to embodiments of the present invention, when driving becomes complicated or necessary functions (e.g. compensation, etc.) are added, a display device that enables normal driving while reducing the number of clock signals (number of phases of the clock signal) ( 100), a display panel 110, and a gate driving circuit 130 may be provided.

In addition, according to embodiments of the present invention, a display device 100, a display panel 110, and a gate driving circuit 130 that perform cluster driving that can secure sufficient sensing time during display driving can be provided. .

Meanwhile, below, the set and reset of the intermediate stage circuit (INTER_STAGE) will be briefly described again.

The intermediate stage circuit (INTER_STAGE) disposed between the ith gate driving unit (GDU #i) and the (i+1)th gate driving unit (GDU #(i+1)) is the ith gate driving unit (GDU #i). ), the intermediate carry signal (INT_CARRY) is output as the reset signal (VRST) of the ith gate driving unit (GDU #i), and the intermediate carry is output to the (i+1)th gate driving unit (GDU #(i+1)). The signal (INT_CARRY) can be output as the set signal (VST) of the (i+1)th gate driving unit.

The set and reset of this intermediate stage circuit (INTER_STAGE) are performed by carry signals (CARRY) output from the corresponding gate driving unit as described above (first method), or in another method. As, it may be achieved by the intermediate carry signals (INT_CARRRY) of another intermediate stage circuit (INTER_STAGE) (second method).

According to the first method, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is A carry signal (CARRY) can be input from the driving unit (GDU #i) and the (i+1)th gate driving unit (GDU #(i+1)). In this case, the carry signal (CARRY) input from the ith gate driving unit (GDU #i) is the set signal (VST) of the intermediate stage circuit (INTER_STAGE), and the (i+1)th gate driving unit (GDU #(i) The carry signal (CARRY) input from +1)) may be the reset signal (VRST) of the intermediate stage circuit (INTER_STAGE). According to the first method, in the non-active area (N/A) of the display panel 110, (N+4) clock wires supply (N+4) clock signals to the gate driving circuit 130. can be placed.

According to the second method, the intermediate stage circuit (INTER_STAGE) disposed between the i-th gate driving unit (GDU #i) and the (i+1)-th gate driving unit (GDU #(i+1)) is (i- 1) The intermediate carry signal (INT_CARRY) is used as a set signal (VST) from the intermediate stage circuit (INTER_STAGE) disposed between the ith gate driving unit (GDU #(i-1)) and the ith gate driving unit (GDU #i). An intermediate stage circuit ( INTER_STAGE) can receive the intermediate carry signal (INT_CARRY) as a reset signal (VRST). According to the second method, in the non-active area (N/A) of the display panel 110, (N+5) clock wires supply (N+5) clock signals to the gate driving circuit 130. can be placed.

The above description is merely an illustrative explanation of the technical idea of the present invention, and various modifications and variations will be possible to those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but rather to explain it, and therefore the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display device
110: display panel
120: data driving circuit
130: Gate driving circuit
140: controller
1410: Sense signal output unit
1420: Scan signal output unit
1430: Carry signal output unit
1440: Light emission control signal output unit
1450: Intermediate carry signal output unit

Claims (25)

A display panel including a plurality of subpixels and a plurality of data lines and a plurality of gate lines;
a data driving circuit that drives the plurality of data lines;
a gate driving circuit that drives the plurality of gate lines; and
A controller that controls the data driving circuit and the gate driving circuit,
The plurality of subpixels are grouped into M clusters, each of the M (M ≥ 2) clusters includes N (N ≥ 2) subpixel lines, and the N sub-pixels included in each of the M clusters. Subpixels arranged in a pixel line emit light simultaneously,
The gate driving circuit includes M gate driving units respectively corresponding to the M clusters, and an intermediate stage circuit disposed between two adjacent gate driving units among the M gate driving units, and driving the M gates. Each unit includes a first main stage circuit and a second main stage circuit,
The M gate driving units include an (i-1)th gate driving unit that drives gate lines arranged in the (i-1)th cluster among the M clusters, and a (i-1)th gate driving unit arranged in the ith cluster among the M clusters. It includes an i-th gate driving unit that drives gate lines, and an (i+1)-th gate driving unit that drives gate lines arranged in an (i+1)-th cluster among the M clusters,
The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
An intermediate carry signal is output to the i-th gate driving unit and the (i+1)-th gate driving unit,
An intermediate carry signal is output to the ith gate driving unit as a reset signal of the ith gate driving unit, and an intermediate carry signal is output to the (i+1)th gate driving unit of the (i+1)th gate driving unit. A display device that outputs a set signal.
According to paragraph 1,
The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
A carry signal is received from the ith gate driving unit and the (i+1)th gate driving unit,
The carry signal input from the ith gate driving unit is the set signal of the intermediate stage circuit,
A carry signal input from the (i+1)th gate driving unit is a reset signal of the intermediate stage circuit.
According to paragraph 1,
The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
Receiving an intermediate carry signal as a set signal from an intermediate stage circuit disposed between the (i-1)th gate driving unit and the ith gate driving unit,
A display device that receives an intermediate carry signal as a reset signal from an intermediate stage circuit disposed between the (i+1)th gate driving unit and the next (i+2)th gate driving unit.
According to paragraph 1,
The plurality of gate lines include a plurality of scan lines, a plurality of sense lines, and a plurality of emission control lines,
Each of the plurality of subpixels is,
A light emitting device,
A driving transistor that drives the light emitting device,
a scan transistor that controls the connection between the first node of the driving transistor and the corresponding data line in response to a scan signal;
A storage capacitor electrically connected between a first node and a second node of the driving transistor,
All or part of the plurality of subpixels,
A display further comprising at least one of a sense transistor that controls the connection between the second node of the driving transistor and the corresponding reference line in response to a sense signal, and a light emission control transistor that controls light emission of the light emitting device in response to a light emission control signal. Device.
According to paragraph 4,
The gate driving circuit operates the plurality of scan lines, the plurality of sense lines, and the plurality of clock signals based on (N+4) clock signals input through (N+4) clock wires disposed in the non-active region. Driving the light emission control line,
Each of the M gate driving units,
Based on N scan clock signals, one sense clock signal, one light emission control clock signal, and one carry clock signal among the (N+4) clock signals, N scan signals, one sense signal, and one light emission Outputs a control signal and one carry signal,
A display device wherein each intermediate stage circuit outputs one intermediate carry signal based on the remaining intermediate carry clock signal among the (N+4) clock signals.
The method of claim 5, wherein gate nodes of sense transistors disposed in subpixels included in N subpixel lines included in each of the M clusters are electrically connected or the sense signals are applied simultaneously,
A display device in which gate nodes of emission control transistors disposed in subpixels included in N subpixel lines included in each of the M clusters are electrically connected or the emission control signal is applied simultaneously.
According to clause 5,
The (N+4) clock wires are,
N scan clock wires, 1 sense clock wire, 1 light emission control clock wire, and 1 carry clock wire connected to each of the M gate driving units,
A display device including one intermediate carry clock wire connected to each intermediate stage circuit.
According to clause 5,
The first main stage circuit included in the ith gate driving unit,
a scan signal output unit that outputs the N scan signals in response to the N scan clock signals;
A sense signal output unit that outputs the one sense signal or K (1≤K≤N) sense signals in response to the one sense clock signal,
In response to the one carry clock signal, the second main stage circuit included in the ith gate driving unit, and the intermediate disposed between the (i-1)th gate driving unit and the ith gate driving unit It includes a stage circuit and a carry signal output unit that outputs the one carry signal to the intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
The second main stage circuit included in the ith gate driving unit,
In response to the one light emission control clock signal, it includes a light emission control signal output unit that outputs the one light emission control signal or K (1≤K≤N) light emission control signals,
The intermediate stage circuit located between the i-th gate driving unit and the (i+1)-th gate driving unit,
In response to the one intermediate carry clock signal, the first main stage circuit included in the i-th gate driving unit and the first main stage circuit included in the (i+1)-th gate driving unit A display device including an intermediate carry signal output unit that outputs intermediate carry signals.
According to clause 8,
The one carry signal output from the carry signal output unit included in the first main stage circuit included in the ith gate driving unit is:
It is input as an input signal of the second main stage circuit included in the ith gate driving unit,
It is input as a set signal of the intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
A display device that is input as a reset signal of the intermediate stage circuit disposed between the (i-1)th gate driving unit and the ith gate driving unit.
According to clause 8,
The light emission control signal output unit included in the second main stage circuit,
A display device that outputs the one light emission control signal by inverting the one carry signal output from the carry signal output unit included in the first main stage circuit.
According to clause 8,
The intermediate carry signal output from the intermediate carry signal output unit included in the intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit is,
It is input as a reset signal of the first main stage circuit included in the ith gate driving unit,
A display device that is input as a set signal of the first main stage circuit included in the (i+1)th gate driving unit.
According to clause 8,
The one sense signal output from the sense signal output unit included in the first main stage circuit included in the ith gate driving unit is branched to the N sense lines corresponding to the N subpixel lines. approved,
The one emission control signal output from the emission control signal output unit to the second main stage circuit included in the ith gate driving unit branches to the N emission control lines corresponding to the N subpixel lines. A display device that is approved.
According to paragraph 4,
The gate driving circuit operates the plurality of scan lines, the plurality of sense lines, and the plurality of clock signals based on (N+4) clock signals input through (N+4) clock wires disposed in the non-active region. Driving the light emission control line,
Each of the M gate driving units,
Among the (N+4) clock signals, based on N scan clock signals, 1 sense clock signal, 1 emission control clock signal, and 1 carry clock signal, N scan signals, 1 to N sense signals, 1 Outputs to N light emission control signals and one carry signal,
A display device wherein each intermediate stage circuit outputs one intermediate carry signal based on the remaining intermediate carry clock signal among the (N+4) clock signals.
According to paragraph 4,
The N subpixel lines included in each of the M clusters are connected to N scan lines, N sense lines, and N light emission control lines,
During one frame time, the driving time of each of the N subpixel lines included in each of the M clusters is,
N scan signals having turn-on level voltages are simultaneously applied to the N scan lines, N sense signals having turn-on level voltages are simultaneously applied to the N sense lines, and the N light emission control lines an initialization period in which N light emission control signals having a turn-off level voltage are applied simultaneously,
N scan signals having turn-on level voltages are simultaneously applied to the N scan lines, N sense signals having turn-off level voltages are simultaneously applied to the N sense lines, and the N light emission control lines A sampling period in which N light emission control signals having a turn-on level voltage are applied simultaneously,
N scan signals having a turn-off level voltage are applied to the N scan lines, N sense signals having a turn-off level voltage are applied to the N sense lines, and a turn signal is applied to the N light emission control lines. - a first holding period in which N light emission control signals having an off-level voltage are applied,
N sense signals having a turn-off level voltage are applied to the N sense lines, N light emission control signals having a turn-off level voltage are applied to the N light emission control lines, and N light emission control signals having a turn-off level voltage are applied to the N light emission control lines. A data writing period in which N scan signals having a turn-on level voltage are sequentially applied,
N scan signals having a turn-off level voltage are applied to the N scan lines, N sense signals having a turn-off level voltage are applied to the N sense lines, and a turn signal is applied to the N light emission control lines. - a second holding period in which N light emission control signals having an off-level voltage are applied,
N scan signals having a turn-off level voltage are applied to the N scan lines, N sense signals having a turn-off level voltage are applied to the N sense lines, and a turn signal is applied to the N light emission control lines. - A display device including a light emission period in which N light emission control signals having an on-level voltage are applied and the N subpixel lines emit light simultaneously.
According to clause 14,
During the sampling period of each of the N subpixel lines included in each of the M clusters, the voltage of the second node of the driving transistor of each of the subpixels arranged in the N subpixel lines increases and then becomes saturated. Device.
According to clause 15,
A display device in which the saturated voltage of the second node of the driving transistor varies depending on the threshold voltage of the driving transistor.
A plurality of subpixels disposed in the active area and connected to a plurality of data lines and a plurality of gate lines; and
a gate driving circuit disposed in a non-active area outside the active area and connected to the plurality of gate lines;
The plurality of subpixels are grouped into M clusters, each of the M (M ≥ 2) clusters includes N (N ≥ 2) subpixel lines, and the N sub-pixels included in each of the M clusters. Subpixels arranged in a pixel line emit light simultaneously,
The gate driving circuit includes M gate driving units respectively corresponding to the M clusters, and an intermediate stage circuit disposed between two adjacent gate driving units among the M gate driving units, and driving the M gates. Each unit includes a first main stage circuit and a second main stage circuit,
The M gate driving units include an (i-1)th gate driving unit that drives gate lines arranged in the (i-1)th cluster among the M clusters, and a (i-1)th gate driving unit arranged in the ith cluster among the M clusters. It includes an i-th gate driving unit that drives gate lines, and an (i+1)-th gate driving unit that drives gate lines arranged in an (i+1)-th cluster among the M clusters,
The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
Receiving a carry signal from the ith gate driving unit and the (i+1)th gate driving unit,
A display panel that outputs an intermediate carry signal to the ith gate driving unit and the (i+1)th gate driving unit.
According to clause 17,
A display panel further comprising (N+4) clock wires disposed in the non-active area.
A plurality of subpixels disposed in the active area and connected to a plurality of data lines and a plurality of gate lines; and
a gate driving circuit disposed in a non-active area outside the active area and connected to the plurality of gate lines;
The plurality of subpixels are grouped into M clusters, each of the M (M ≥ 2) clusters includes N (N ≥ 2) subpixel lines, and the N sub-pixels included in each of the M clusters. Subpixels arranged in a pixel line emit light simultaneously,
The gate driving circuit includes M gate driving units respectively corresponding to the M clusters, and an intermediate stage circuit disposed between two adjacent gate driving units among the M gate driving units, and driving the M gates. Each unit includes a first main stage circuit and a second main stage circuit,
The M gate driving units include an (i-1)th gate driving unit that drives gate lines arranged in the (i-1)th cluster among the M clusters, and a (i-1)th gate driving unit arranged in the ith cluster among the M clusters. It includes an i-th gate driving unit that drives gate lines, and an (i+1)-th gate driving unit that drives gate lines arranged in an (i+1)-th cluster among the M clusters,
The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
An intermediate carry signal is output to the i-th gate driving unit and the (i+1)-th gate driving unit, and the intermediate carry signal is output to the i-th gate driving unit as a reset signal of the i-th gate driving unit, A display panel that outputs an intermediate carry signal to the (i+1)th gate driving unit as a set signal of the (i+1)th gate driving unit.
According to clause 19,
A display panel further comprising (N+5) clock wires disposed in the non-active area.
A plurality of subpixels disposed in the active area and connected to a plurality of data lines and a plurality of gate lines; and
a gate driving circuit disposed in a non-active area outside the active area and connected to the plurality of gate lines;
The plurality of subpixels are grouped into M clusters, each of the M clusters includes N subpixel lines, where M is a natural number of 2 or more, and N is a natural number of 2 or more,
Subpixels arranged on the N subpixel lines included in each of the M clusters emit light simultaneously,
It is disposed in the non-active area and further includes (N+4) clock wires that supply (N+4) clock signals to the gate driving circuit, or is disposed in the non-active area and (N+5) A display panel further comprising (N+5) clock wires that supply clock signals to the gate driving circuit.
According to clause 21,
The plurality of gate lines include a plurality of scan lines, a plurality of sense lines, and a plurality of emission control lines,
Each of the plurality of subpixels is,
A light emitting device,
A driving transistor that drives the light emitting device,
a scan transistor that controls the connection between the first node of the driving transistor and the corresponding data line in response to a scan signal;
A storage capacitor electrically connected between a first node and a second node of the driving transistor,
All or part of the plurality of subpixels,
It further includes at least one of a sense transistor that controls the connection between the second node of the driving transistor and the corresponding reference line in response to a sense signal, and a light emission control transistor that controls light emission of the light emitting device in response to a light emission control signal,
Gate nodes of the sense transistors arranged in the N subpixel lines are electrically connected or the sense signals are applied simultaneously,
A display panel in which gate nodes of the emission control transistors arranged in the N subpixel lines are electrically connected or the emission control signals are applied simultaneously.
In the gate driving circuit,
M gate driving units each corresponding to M (M ≥ 2) clusters each including N (N ≥ 2) different subpixel lines and each including a first main stage circuit and a second main stage circuit; and
An intermediate stage circuit disposed between two adjacent gate driving units among the M gate driving units,
The M gate driving units include an (i-1)th gate driving unit that drives gate lines arranged in the (i-1)th cluster among the M clusters, and a (i-1)th gate driving unit arranged in the ith cluster among the M clusters. It includes an i-th gate driving unit that drives gate lines, and an (i+1)-th gate driving unit that drives gate lines arranged in an (i+1)-th cluster among the M clusters,
The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
An intermediate carry signal is output to the i-th gate driving unit and the (i+1)-th gate driving unit, and the intermediate carry signal is output to the i-th gate driving unit as a reset signal of the i-th gate driving unit, A gate driving circuit that outputs an intermediate carry signal to the (i+1)th gate driving unit as a set signal of the (i+1)th gate driving unit.
According to clause 23,
The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
A carry signal is input from the ith gate driving unit as a set signal of the intermediate stage circuit,
The carry signal input from the ith gate driving unit is the set signal of the intermediate stage circuit,
A gate driving circuit wherein the carry signal input from the (i+1)th gate driving unit is a reset signal of the intermediate stage circuit.
According to clause 23,
The intermediate stage circuit disposed between the i-th gate driving unit and the (i+1)-th gate driving unit,
Receiving an intermediate carry signal as a set signal from an intermediate stage circuit disposed between the (i-1)th gate driving unit and the ith gate driving unit,
A gate driving circuit that receives an intermediate carry signal as a reset signal from an intermediate stage circuit disposed between the (i+1)th gate driving unit and the next (i+2)th gate driving unit.

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