KR102601635B1 - Display device, gate driving circuit, and driving method - Google Patents

Abstract

Embodiments of the present invention relate to a display device, a gate driving circuit, and a driving method, which provide a fake data insertion drive to insert a fake image between real images to prevent afterimages or improve video response speed, and to provide a fake data insertion drive after the fake data insertion drive. By increasing the turn-on level voltage of the scan signal and shortening the temporal length of the turn-on level voltage section of the scan signal after the fake data insertion drive, image quality can be improved even when implementing high resolution.

Description

Display device, gate driving circuit and driving method {DISPLAY DEVICE, GATE DRIVING CIRCUIT, AND DRIVING METHOD}

Embodiments of the present invention relate to a display device, a gate driving circuit, and a driving method.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, various types of display devices such as liquid crystal displays, organic light emitting displays, quantum dot displays, etc. are being developed. there is.

Such a display device can drive a display by charging a capacitor placed in each of a plurality of subpixels arranged on the display panel and utilizing this. However, in the case of a conventional display device, insufficient charging in each subpixel may occur, leading to a problem in which image quality deteriorates. In addition to these problems, in the case of conventional display devices, the image may not be differentiated and may be dragged, or a luminance deviation may occur due to a difference in the emission period for each line position, resulting in a decrease in image quality.

Embodiments of the present invention can provide a display device, gate driving circuit, and driving method that can improve image quality through an improved charging rate through overlap driving of subpixels.

Embodiments of the present invention include a display device that can improve video quality by preventing afterimages and improving video response speed by inserting fake data to display an video (fake video) different from the actual video intermittently; A gate driving circuit and driving method can be provided.

Embodiments of the present invention identify the cause of image quality deterioration that may occur when performing overlap driving and fake data insertion driving for high-resolution implementation at the same time as video display delay due to fake data insertion driving, and determine the cause of image display delay due to fake data insertion driving. It is possible to provide a display device, gate driving circuit, and driving method that can prevent or alleviate image display delay and improve image quality even when implementing high resolution.

Embodiments of the present invention include a plurality of subpixels connected to a plurality of data lines and a plurality of scan signal lines, and each of the plurality of subpixels has a light emitting element, a driving transistor for driving the light emitting element, and a scan signal line. A display panel including a scan transistor that controls the connection between the data line and the first node of the driving transistor according to the scan signal supplied through the display panel, and a capacitor connected between the first node and the second node of the driving transistor, and a plurality of data lines A display device including a data driving circuit for driving and a gate driving circuit for driving a plurality of scan signal lines can be provided.

In the display device according to embodiments of the present invention, a plurality of subpixels are arranged in a matrix form to form a plurality of subpixel rows, and the plurality of subpixel rows are (i+1)th to (i+6th)th May contain subpixel rows.

In the display device according to embodiments of the present invention, the plurality of scan signal lines are (i+1)th to (i+6)th subpixel rows, respectively, corresponding to (i+1)th to (i+6)th subpixel rows. It may include the second scan signal line.

In the display device according to embodiments of the present invention, the gate driving circuit is a (i+1)th scan signal line that sequentially has a turn-on level voltage section. The to (i+6)th scan signal can be applied.

In the display device according to embodiments of the present invention, a portion of the turn-on level voltage section of the (i+3)th scan signal and a portion of the turn-on level voltage section of the (i+4)th scan signal are There may be overlap.

In the display device according to embodiments of the present invention, the turn-on level voltage section of the (i+4)th scan signal and the turn-on level voltage section of the (i+5)th scan signal may not overlap.

In the display device according to embodiments of the present invention, the gate driving circuit has a turn-on level voltage section of the (i+4)th scan signal and a turn-on level voltage section of the (i+5)th scan signal. During the overlapping period, two or more scan signals having turn-on level voltage sections may be applied to two or more scan signal lines among a plurality of scan signal lines at the same timing.

In the display device according to embodiments of the present invention, the maximum voltage value in the turn-on level voltage section of the (i+5)th scan signal is the maximum voltage in the turn-on level voltage section of the (i+4)th scan signal. It may be higher than the value.

In the display device according to embodiments of the present invention, the temporal length of the turn-on level voltage section of the (i+5)th scan signal is the temporal length of the turn-on level voltage section of the (i+4)th scan signal. It may be shorter than the length.

In the display device according to embodiments of the present invention, the start point of the turn-on level voltage section of the (i+6)th scan signal is the same as the start time of the turn-on level voltage section of the (i+5)th scan signal. Correspondingly, the temporal length of the turn-on level voltage section of the (i+6)th scan signal may be longer than the temporal length of the turn-on level voltage section of the (i+5)th scan signal.

In the display device according to embodiments of the present invention, the maximum voltage value in the turn-on level voltage section of the (i+6)th scan signal is the maximum voltage in the turn-on level voltage section of the (i+5)th scan signal. It can correspond to a value.

In the display device according to embodiments of the present invention, the maximum voltage value in the turn-on level voltage section of the (i+5)th scan signal is the maximum voltage in the turn-on level voltage section of the (i+4)th scan signal. It may be a voltage value boosted by a preset boost voltage.

In the display device according to embodiments of the present invention, the turn-on level voltage section of the (i+5)th scan signal is a first voltage having a boost turn-on level voltage obtained by adding the reference turn-on level voltage and the boost voltage. It includes a turn-on level voltage section and a second turn-on level voltage section having a reference turn-on level voltage, where the reference turn-on level voltage is the turn-on level voltage section of the (i+4)th scan signal. It can correspond to the maximum voltage value of .

In the display device according to embodiments of the present invention, the turn-on level voltage section of the (i+6)th scan signal is a first voltage having a boost turn-on level voltage obtained by adding the reference turn-on level voltage and the boost voltage. It includes a turn-on level voltage section and a second turn-on level voltage section having a reference turn-on level voltage, where the reference turn-on level voltage is the turn-on level voltage section of the (i+4)th scan signal. It can correspond to the maximum voltage value of .

In the display device according to embodiments of the present invention, the start point of the turn-on level voltage section of the (i+6)th scan signal is the start time of the turn-on level voltage section of the (i+5)th scan signal. Corresponds to , the temporal length of the turn-on level voltage section of the (i+6)th scan signal may be longer than the temporal length of the first turn-on level voltage section of the (i+5)th scan signal.

In the display device according to embodiments of the present invention, the temporal length of the first turn-on level voltage section of the (i+6)th scan signal is the first turn-on level voltage of the (i+5)th scan signal. Corresponds to the temporal length of the section, and the temporal length of the second turn-on level voltage section of the (i+6)th scan signal is the temporal length of the second turn-on level voltage section of the (i+5)th scan signal. It can be longer.

In the display device according to embodiments of the present invention, the temporal length of the first turn-on level voltage section of the (i+6)th scan signal is the first turn-on level voltage of the (i+5)th scan signal. It is longer than the temporal length of the section, and the temporal length of the second turn-on level voltage section of the (i+6)th scan signal is the temporal length of the second turn-on level voltage section of the (i+5)th scan signal. can be responded to.

In the display device according to embodiments of the present invention, the data driving circuit, during the turn-on level voltage section of the (i+1)th to (i+6)th scan signals, the (i+1)th to (i)th scan signals. Image data voltages corresponding to the real image can be supplied to the subpixels included in the +6)th subpixel row.

In the display device according to embodiments of the present invention, the data driving circuit has a turn-on level voltage section of the (i+4)th scan signal and a turn-on level voltage section of the (i+5)th scan signal. During the overlapping period, a fake data voltage corresponding to a fake image unrelated to the real image may be supplied to subpixels included in two or more subpixel rows among a plurality of subpixel rows. Two or more subpixel rows to which a fake data voltage is supplied may correspond to two or more scan signal lines to which two or more scan signals having a turn-on level voltage section are applied at the same timing.

In the display device according to embodiments of the present invention, the data driving circuit is configured such that a real image is an image that can be perceived by the naked eye, a fake image is an image that is not perceptible by the human eye, and the fake data voltage is a black data voltage, a low gray data voltage, Or it may be a single color data voltage.

In the display device according to embodiments of the present invention, each of the plurality of subpixels further includes a sense transistor that controls the connection between the reference line and the second node of the driving transistor according to the sense signal supplied through the sense signal line; , the sense signal and the scan signal may have the same signal waveform, or the sense signal and the scan signal may have a turn-on level voltage section of the same length.

In the display device according to embodiments of the present invention, the turn-on level voltage section of the (i+4)th scan signal may be longer than 1 horizontal time.

Embodiments of the present invention include a plurality of subpixels connected to a plurality of data lines and a plurality of scan signal lines, and each of the plurality of subpixels has a light emitting element, a driving transistor for driving the light emitting element, and a scan signal line. A display panel including a scan transistor that controls the connection between the data line and the first node of the driving transistor according to the scan signal supplied through the display panel, and a capacitor connected between the first node and the second node of the driving transistor, and a plurality of data lines A display device including a data driving circuit for driving and a gate driving circuit for driving a plurality of scan signal lines can be provided.

In the display device according to embodiments of the present invention, a plurality of subpixels are arranged in a matrix form to form a plurality of subpixel rows, and in the display device according to embodiments of the present invention, the data driving circuit is configured to display one frame. An image data voltage for displaying an image is supplied to subpixels disposed in one subpixel row of a plurality of subpixel rows immediately before a first period of time, and during the first period, two or more subpixel rows of the plurality of subpixel rows are supplied. A fake data voltage for displaying a fake image different from the image can be supplied to the subpixels arranged in the subpixel row.

In the display device according to embodiments of the present invention, the gate driving circuit outputs a scan signal having a reference turn-on level voltage before the first period, and outputs a scan signal having a reference turn-on level voltage greater than the reference turn-on level voltage immediately after the first period. A scan signal with a high turn-on level voltage can be output.

Embodiments of the present invention include a gate voltage supply circuit that outputs a reference turn-on level voltage during a first driving period and a boost turn-on level voltage different from the reference turn-on level voltage during a second driving period; During the first driving period, first scan signals sequentially having turn-on level voltage sections based on the reference turn-on level voltage are output to the first scan signal lines, and during the second driving period, the boost turn-on level A gate driving circuit including a scan signal output circuit that outputs a second scan signal having a turn-on level voltage section by voltage to a second scan signal line can be provided.

In the gate driving circuit according to embodiments of the present invention, the turn-on level voltage sections of the first scan signals during the first driving period overlap each other, and the turn-on level of the first scan signals during the first driving period The voltage section and the turn-on level voltage section of the second scan signal during the second driving period may not overlap.

In the gate driving circuit according to embodiments of the present invention, the boost turn-on level voltage in the turn-on level voltage section of the second scan signal during the second driving period is the first scan signal during the first driving period. It may be higher than the reference turn-on level voltage in the turn-on level voltage section.

In the gate driving circuit according to embodiments of the present invention, the temporal length of the turn-on level voltage section of the second scan signal during the second driving period is the turn-on level of the first scan signals during the first driving period. It may be shorter than the temporal length of the voltage section.

In the gate driving circuit according to embodiments of the present invention, a real image is displayed on the display panel after the first driving period and after the second driving period, and between the first driving period and the second driving period, a real image is displayed on the display panel. A fake video that is different from the video may be displayed.

Embodiments of the present invention include a display panel including a plurality of subpixels connected to a plurality of data lines and a plurality of scan signal lines, a data driving circuit for driving the plurality of data lines, and a plurality of scan signal lines. A method of driving a display device including a gate driving circuit can be provided.

A method of driving a display device according to embodiments of the present invention includes sending first scan signals sequentially having turn-on level voltage sections based on a reference turn-on level voltage to first scan signal lines during a first driving period. A first stage of sequentially outputting and, during the second driving period, a second scan signal having a turn-on level voltage section due to a boost turn-on level voltage different from the reference turn-on level voltage to the second scan signal line. It may include a second step of outputting.

In the method of driving a display device according to embodiments of the present invention, the turn-on level voltage sections of the first scan signals during the first driving period overlap each other, and the turn-on level voltage sections of the first scan signals during the first driving period are The on-level voltage section and the turn-on level voltage section of the second scan signal during the second driving period may not overlap.

In the method of driving a display device according to embodiments of the present invention, the boost turn-on level voltage in the turn-on level voltage section of the second scan signal during the second driving period is the first driving period during the first driving period. It may be higher than the reference turn-on level voltage in the turn-on level voltage section of the scan signals.

In the method of driving a display device according to embodiments of the present invention, a real image is displayed on the display panel after the first driving period and after the second driving period, and between the first driving period and the second driving period, the display panel A fake video that is different from the real video may be displayed.

In the method of driving a display device according to embodiments of the present invention, the temporal length of the turn-on level voltage section of the second scan signal during the second driving period is the turn-on level voltage section of the first scan signal during the first driving period. It may be shorter than the temporal length of the on-level voltage section.

A method of driving a display device according to embodiments of the present invention includes scanning two or more scan signals having turn-on level voltage sections based on a reference turn-on level voltage at the same timing between the first step and the second step. A third step of simultaneously outputting signal lines may be further included.

According to embodiments of the present invention, a display device, gate driving circuit, and driving method that can improve image quality through improved charging rate through overlap driving of subpixels can be provided.

According to embodiments of the present invention, video quality can be improved by preventing afterimages and improving video response speed by inserting fake data to display an video (fake video) different from the actual video in between. A display device, gate driving circuit, and driving method can be provided.

According to embodiments of the present invention, the cause of the image quality deterioration that may occur when performing the overlap drive for high-resolution implementation and the fake data insertion drive at the same time is identified as the image display delay due to the fake data insertion drive, and the fake data insertion drive is identified. It is possible to provide a display device, gate driving circuit, and driving method that can improve image quality even when implementing high resolution by preventing or alleviating image display delay due to driving.

1 is a system configuration diagram of a display device according to embodiments of the present invention.
Figure 2 is a diagram showing an equivalent circuit of a subpixel disposed on a display panel of a display device according to embodiments of the present invention.
Figure 3 is an exemplary system implementation of a display device according to embodiments of the present invention.
Figure 4 is a diagram showing a fake data insertion drive of a display device according to embodiments of the present invention.
Figure 5 is a diagram showing a screen change according to a fake data insertion drive of a display device according to embodiments of the present invention.
Figures 6 and 7 are driving timing diagrams when a display device according to embodiments of the present invention performs fake data insertion driving and overlap driving.
Figures 8 and 9 are diagrams to explain the principle of fake data insertion operation performed by a display device according to embodiments of the present invention.
Figure 10 is a timing diagram of fake data insertion driving when a display device according to embodiments of the present invention is implemented with high resolution.
Figure 11 is a timing diagram for improved gate driving to prevent image display delay when a display device according to embodiments of the present invention is implemented with high resolution.
FIG. 12 is a diagram showing scan signal waveforms before and after fake data insertion according to improved gate driving to prevent image display delay when the display device according to embodiments of the present invention is implemented with high resolution.
Figure 13 is another timing diagram for improved gate driving to prevent image display delay when a display device according to embodiments of the present invention is implemented with high resolution.
FIG. 14 is another diagram showing scan signal waveforms before and after fake data insertion according to improved gate driving to prevent image display delay when the display device according to embodiments of the present invention is implemented with high resolution.
Figure 15 is a block diagram showing a gate driving circuit for providing improved gate driving to prevent image display delay when a display device according to embodiments of the present invention is implemented with high resolution.
Figure 16 is a flowchart of a method of driving a display device according to embodiments of the present invention.

The present invention provides a fake data insertion drive that inserts fake images between real images to prevent afterimages or improve video response speed, and to improve image quality even when implementing high resolution, the scan signal after the fake data insertion drive is provided. The turn-on level voltage can be increased and the temporal length of the turn-on level voltage section of the scan signal after the fake data insertion drive can be shortened.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the description of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (e.g., level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g., process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

Below, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a system configuration diagram of a display device 100 according to embodiments of the present invention.

Referring to FIG. 1, a display device 100 according to embodiments of the present invention may include a display panel 110 and a driving circuit for driving the display panel 110.

From a functional standpoint, the driving circuit may include a data driving circuit 120 and a gate driving circuit 130, and may further include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130. It can be included.

The display panel 110 includes multiple data lines (DL), multiple scan signal lines (SCL), multiple sense signal lines (SENL), multiple reference lines (RL), and multiple subpixels (SP). can do.

The display panel 110 may include an active area where an image is displayed and a non-active area where an image is not displayed. A plurality of subpixels (SP) for displaying an image may be disposed in the active area. In the non-active area, the driving circuits 120, 130, and 140 may be electrically connected or mounted, and a pad portion may be disposed.

The data driving circuit 120 is a circuit for driving a plurality of data lines DL and can supply data voltages to the plurality of data lines DL.

The gate driving circuit 130 drives multiple gate lines GL. For example, the plurality of gate lines (GL) may include a plurality of scan signal lines (SCL) and a plurality of sense signal lines (SENL). Accordingly, the gate driving circuit 130 can drive a plurality of scan signal lines (SCL) and a plurality of sense signal lines (SENL).

The controller 140 may supply various driving control signals (DCS, GCS) to the data driving circuit 120 and the gate driving circuit 130 in order to control the data driving circuit 120 and the gate driving circuit 130. .

The controller 140 starts scanning according to the timing implemented in each frame, and converts the input image data input from the outside to fit the data signal format used in the data driving circuit 120 to produce converted image data (DATA). Outputs and controls data operation at an appropriate time according to the scan.

The controller 140 provides various timing signals including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), a clock signal (CLK), etc., along with input image data. Receive data from external sources (e.g. host system).

The controller 140 converts the input image data input from the outside to suit the data signal format used in the data driving circuit 120 and outputs the converted image data, and also operates the data driving circuit 120 and the gate driving circuit. In order to control (130), timing signals such as vertical synchronization signal (VSYNC), horizontal synchronization signal (HSYNC), input data enable signal (DE), and clock signal (CLK) are input, and various control signals (DCS) are input. , GCS) is generated and output to the data driving circuit 120 and the gate driving circuit 130.

For example, the controller 140 uses a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE) to control the gate driving circuit 130. : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable.

Here, the gate start pulse (GSP) controls the operation start timing of one or more gate driver integrated circuits that constitute each gate driving circuit 130. The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of a scan signal (gate pulse). The gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits.

In addition, the controller 140 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE) to control the data driving circuit 120. Outputs various data control signals (DCS: Data Control Signal) including Output Enable.

Here, the source start pulse (SSP) controls the data sampling start timing of one or more source driver integrated circuits constituting the data driving circuit 120. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data in each source driver integrated circuit. The source output enable signal (SOE) controls the output timing of the data driving circuit 120.

The controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

The data driving circuit 120 receives image data DATA from the controller 140 and supplies a data voltage to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 is also called a source driving circuit.

This data driving circuit 120 may be implemented by including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc.

In some cases, each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC).

Each source driver integrated circuit (SDIC) is connected to the bonding pad of the display panel 110 using a tape automated bonding (TAB) method or a chip on glass (COG) method. , may be placed directly on the display panel 110, or in some cases, may be integrated and placed on the display panel 110. In addition, each source driver integrated circuit (SDIC) may be implemented in a chip on film (COF: Chip On Film) method. In this case, each source driver integrated circuit (SDIC) is a circuit film connected to the display panel 110 ( It is mounted on the circuit film (SF) and can be electrically connected to the display panel 110 through wires on the circuit film (SF).

The gate driving circuit 130 sequentially drives a plurality of scan signal lines (SCL) by sequentially supplying scan signals to the plurality of scan signal lines (SCL). The gate driving circuit 130 may output a scan signal with a turn-on level voltage or a scan signal with a turn-off level voltage according to the control of the controller 140.

The gate driving circuit 130 sequentially drives a plurality of sense signal lines (SENL) by sequentially supplying sense signals to the plurality of sense signal lines (SENL). The gate driving circuit 130 may output a sense signal having a turn-on level voltage or a sense signal having a turn-off level voltage according to the control of the controller 140.

A plurality of scan signal lines (SCL) and a plurality of sense signal lines (SENL) correspond to gate lines (GL). The scan signal and sense signal correspond to the gate signal applied to the gate node of the transistor.

The gate driving circuit 130 is connected to the bonding pad of the display panel 110 using a tape automated bonding (TAB) method or a chip on glass (COG) method, or is implemented as a GIP (Gate In Panel) type. It may be placed directly on the display panel 110, or in some cases, may be integrated and placed on the display panel 110. Additionally, the gate driving circuit 130 may be implemented in the form of an integrated circuit (IC) and mounted on a film connected to the display panel 110.

When a specific scan signal line (SCL) is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data (DATA) received from the controller 140 into an analog data voltage to generate a plurality of data. It is supplied through line (DL).

The data driving circuit 120 may be located only on one side (e.g., upper or lower) of the display panel 110, and in some cases, both sides (e.g., upper or lower) of the display panel 110 depending on the driving method, panel design method, etc. For example, it may be located both on the upper and lower sides.

The gate driving circuit 130 may be located only on one side (e.g., left or right) of the display panel 110, and in some cases, both sides (e.g., left or right) of the display panel 110 depending on the driving method, panel design method, etc. For example, it may be located on both the left and right sides.

The controller 140 may be a timing controller used in typical display technology, or a control device that further performs other control functions, including a timing controller, and may be a control device different from the timing controller. It may be a circuit within the control device. The controller 140 may be implemented with various circuits or electronic components, such as an Integrated Circuit (IC), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), or Processor.

The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through a printed circuit board, a flexible printed circuit, etc.

The controller 140 may transmit and receive signals with the data driving circuit 120 according to one or more predetermined interfaces. Here, for example, the interface may include a Low Voltage D Differential Signaling (LVDS) interface, an EPI interface, and a Serial Peripheral Interface (SPI).

The controller 140 may transmit and receive signals with the data driving circuit 120 and the gate driving circuit 130 according to one or more predetermined interfaces. Here, for example, the interface may include a Low Voltage D Differential Signaling (LVDS) interface, an EPI interface, and a Serial Peripheral Interface (SPI). The controller 140 may include a storage location such as one or more registers.

The display device 100 according to the present embodiments may be a self-luminous display such as an Organic Light Emitting Diode (OLED) display, a Quantum Dot display, or a Micro Light Emitting Diode (Micro LED) display.

When the display device 100 according to the present embodiments is an OLED display, each subpixel SP may include an organic light emitting diode (OLED) that emits light on its own as a light emitting device. When the display device 100 according to the present embodiments is a quantum dot display, each subpixel SP may include a light emitting element made of quantum dots, which are semiconductor crystals that emit light on their own. When the display device 100 according to the present embodiments is a micro LED display, each subpixel (SP) emits light on its own and may include a micro LED (Micro Light Emitting Diode) made of an inorganic material as a light emitting element. .

FIG. 2 is a diagram illustrating an equivalent circuit of a subpixel (SP) disposed on the display panel 110 of the display device 100 according to embodiments of the present invention.

Each of the plurality of subpixels (SP) may include, for example, a light emitting element (ED), a driving transistor (DT), a scan transistor (SCT), and a storage capacitor (Cst). This subpixel structure is called a 2T (Transistor) 1C (Capacitor) structure.

Referring to FIG. 2, each of the plurality of subpixels (SP) includes a light emitting element (ED), a driving transistor (DT), a scan transistor (SCT), and a storage capacitor (Cst), as well as a sense transistor (SENT). It can be included. This subpixel structure is called a 3T (Transistor) 1C (Capacitor) structure.

The light emitting device (ED) may include an anode electrode, a cathode electrode, and a light emitting layer located between the anode electrode and the cathode electrode. For example, the light emitting device (ED) may be an organic light emitting diode (OLED), a light emitting diode (LED), or a quantum dot light emitting device.

The driving transistor DT is a transistor for driving the light emitting device ED and may include a first node N1, a second node N2, and a third node N3.

The first node N1 of the driving transistor DT may be a gate node and may be electrically connected to the source node or drain node of the scan transistor SCT.

The second node (N2) of the driving transistor (DT) may be a source node or a drain node, is electrically connected to the source node or drain node of the sense transistor (SENT), and is also connected to the first electrode of the light emitting element (ED). Can be electrically connected.

The third node N3 of the driving transistor DT may be electrically connected to the driving voltage line DVL that supplies the driving voltage EVDD.

The scan transistor (SCT) is turned on or turned off according to the scan signal (SCAN) supplied from the scan signal line (SCL), and the first node (N1) of the data line (DL) and the driving transistor (DT) You can control the connection between them.

The scan transistor (SCT) is turned on by the scan signal (SCAN) having a turn-on level voltage, and transmits the data voltage (Vdata) supplied from the data line (DL) to the first node ( It can be passed on to N1).

The sense transistor (SENT) is turned on or off according to the sense signal (SENSE) supplied from the sense signal line (SENL), and is connected to the reference line (RL) and the second node (N2) of the driving transistor (DT). You can control the connection between them.

The sense transistor SENT is turned on by the sense signal SENSE having a turn-on level voltage, and the reference voltage Vref supplied from the reference line RL is connected to the second node ( It can be passed on to N2).

In addition, the sense transistor SENT is turned on by the sense signal SENSE having a turn-on level voltage, and transfers the voltage of the second node N2 of the driving transistor DT to the reference line RL. I can do it.

The function of the sense transistor (SENT) to transfer the voltage of the second node (N2) of the driving transistor (DT) to the reference line (RL) is based on the characteristic value (for example, threshold voltage or mobility) of the driving transistor (DT). It can be used when driving to sense. In this case, the voltage transmitted to the reference line RL may be a voltage for calculating the characteristic value of the driving transistor DT.

The function of the sense transistor (SENT) to transfer the voltage of the second node (N2) of the driving transistor (DT) to the reference line (RL) is to sense the characteristic value (for example, threshold voltage) of the light emitting device (ED). It can also be used when driving. In this case, the voltage transmitted to the reference line RL may be a voltage for calculating characteristic values of the light emitting device ED.

Each of the driving transistor (DT), scan transistor (SCT), and sense transistor (SENT) may be an n-type transistor or a p-type transistor. Below, for convenience of explanation, the driving transistor (DT), scan transistor (SCT), and sense transistor (SENT) are each n-type as an example.

The capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DT. The capacitor (Cst) is charged with a charge corresponding to the voltage difference between both ends and plays the role of maintaining the voltage difference between both ends for a set frame time. Accordingly, the corresponding subpixel (SP) may emit light during a set frame time.

The capacitor (Cst) is not a parasitic capacitor (e.g. Cgs, Cgd), which is an internal capacitor that exists between the gate node and the source node (or drain node) of the driving transistor (DT). It may be an external capacitor intentionally designed outside of .

Figure 3 is an exemplary system implementation of the display device 100 according to embodiments of the present invention.

Referring to FIG. 3 , the display panel 110 may include an active area (A/A) where an image is displayed and a non-active area (N/A) where an image is not displayed.

Referring to FIG. 3, when the data driving circuit 120 is implemented in a chip-on-film (COF) method, each source driver integrated circuit (SDIC) included in the data driving circuit 120 is a non-SDIC of the display panel 110. -Can be mounted on a film (SF) connected to the active area (N/A).

Referring to FIG. 3, the gate driving circuit 130 may be implemented as a GIP (Gate In Panel) type. In this case, the gate driving circuit 130 may be formed in the non-active area (N/A) of the display panel 110. Unlike FIG. 3, the gate driving circuit 130 may be implemented as a COF (Chip On Film) type.

The display device 100 includes at least one source printed circuit board (SPCB), control components, and various electrical components for circuit connection between one or more source driver integrated circuits (SDICs) and other devices. It may include a control printed circuit board (CPCB) for mounting devices.

A film (SF) on which a source driver integrated circuit (SDIC) is mounted may be connected to at least one source printed circuit board (SPCB). That is, one side of the film (SF) on which the source driver integrated circuit (SDIC) is mounted may be electrically connected to the display panel 110 and the other side may be electrically connected to the source printed circuit board (SPCB).

The control printed circuit board (CPCB) includes a controller 140 that controls the operations of the data driving circuit 120 and the gate driving circuit 130, a display panel 110, a data driving circuit 120, and a gate driving circuit. A power management integrated circuit (PMIC: Power Management IC, 410) that supplies various voltages or currents or controls various voltages or currents to be supplied may be mounted at (130).

At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be connected in a circuit through at least one connection member. Here, the connecting member may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like. At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated and implemented as one printed circuit board.

The display device 100 may further include a set board 330 electrically connected to a control printed circuit board (CPCB). This set board 330 may also be referred to as a power board. This set board 330 may include a main power management circuit 320 (M-PMC: Main Power Management Circuit) that manages the overall power of the display device 100.

The power management integrated circuit 310 is a circuit that manages power for the display module including the display panel 110 and its driving circuits 120, 130, and 140, and the main power management circuit 320 manages the display module. It is a circuit that manages overall power, and can be linked with the power management integrated circuit 310.

FIG. 4 is a diagram showing fake data insertion (FDI) operation of the display device 100 according to embodiments of the present invention, and FIG. 5 is a diagram showing the display device 100 according to embodiments of the present invention. This is a diagram showing the screen change according to the fake data insertion operation.

Referring to FIG. 4, the display device 100 according to embodiments of the present invention prevents afterimages to improve video quality and video response time (MPRT: Moving Picture Response Time) within one frame time. You can perform the function of inserting and displaying a fake image that is different from a real image. Before explaining the fake data insertion function, the structure and operation of the display panel 110 will be briefly described.

A plurality of subpixels SP disposed on the display panel 110 may be arranged in a matrix form. Accordingly, a plurality of sub-pixels SP disposed on the display panel 110 form a plurality of sub-pixel rows. These multiple subpixel rows can be scanned sequentially.

When each subpixel (SP) has a 3T1C structure, each of the multiple subpixel rows includes a scan signal line (SCL) for transmitting a scan signal (SCAN) and a sense signal line for transmitting a sense signal (SENSE). (SENL) may be deployed.

There may be a plurality of subpixel rows in the display panel 110, and one data line DL may be disposed in correspondence with each of the plurality of subpixel rows. In some cases, one data line DL may be arranged for each two or three or more subpixel columns.

Multiple subpixel rows arranged on the display panel 110 are driven sequentially. As in the subpixel driving operation described above, when the (n+1)th subpixel row among multiple subpixel rows is driven, a scan signal is sent to the subpixels (SP) arranged in the (n+1)th subpixel row. (SCAN) and sense signals (SENSE) are applied, and images are transmitted to the subpixels (SP) arranged in the (n+1)th subpixel row (R(n+1)) through multiple data lines (DL). A data voltage (Vdata) is supplied.

Subsequently, the (n+2)th subpixel row located below the (n+1)th subpixel row is driven. A scan signal (SCAN) and a sense signal (SENSE) are applied to the subpixels (SP) arranged in the (n+2)th subpixel row, and the (n+2)th sub-pixel row is applied through a plurality of data lines (DL). Image data voltage Vdata is supplied to the subpixels SP arranged in the pixel row R(n+2).

In this way, multiple subpixel rows are sequentially recorded with image data. Here, image data recording is a procedure performed in the image data recording step in the above-described subpixel driving operation.

In a plurality of subpixel rows, an image data recording step, a boosting step, and a light emitting step may be sequentially performed during one frame time according to the above-described subpixel driving operation.

Referring to Figure 4, each of the multiple subpixel rows does not last until the end of the "Real Image Period (RIP)" in which the "Real Image" is displayed according to the light emission stage of the subpixel driving operation within one frame time. No. Here, the real video period (RIP) may also be referred to as the “light emission period.”

In this specification, “real image” refers to an image that is actually visible to the user. In this specification, driving to display a real image is referred to as “Real Display Driving.”

In this specification, “Fake Image” is referred to as an image different from “real image”. In this specification, a “fake image” is an image that is not actually visible to the user. It is an image that is displayed between real images or together with a real image within a frame screen, and is displayed for a very short time and then disappears. It is an image that the user cannot recognize because it is lost. For example, a fake image according to embodiments of the present invention may be a black image, a low-gradation image, or a monochromatic image, and may be any image that cannot be perceived by the user. In this specification, driving to display a fake image is referred to as “Fake Display Driving.”

Referring to FIG. 4, in each of the plurality of subpixel rows, real display driving may be performed during a portion of one frame time (RIP), and fake display driving may be performed during the remaining time (FIP).

Referring to FIG. 4, during one frame time, one subpixel (SP) corresponds to a portion of one frame time through real display driving (image data recording step, boosting step, and light emitting step) and produces a real image ( It emits light during the real image period (RIP) during which the real image is displayed, and then, through fake display operation, the real image and other fake images ( Fake Image) is displayed or does not emit light.

The period during which a subpixel (SP) does not emit light or a fake image is displayed during one frame is called the “fake image period (FIP).” Here, the “fake image period (FIP)” may also be referred to as a non-emission period.

Fake display driving is a fake driving that is different from real display driving for displaying real images. It is driving for displaying fake images between real images. . This fake display operation can be performed by inserting a fake image between real images.

Therefore, fake display driving is also called “fake data insertion (FDI) driving.” Below, the fake display drive is described as “fake data insertion (FDI) drive.”

When driving a real display, an image data voltage (Vdata) corresponding to a real image is supplied to the subpixels (SP) to display a real image. Differently, when the fake data insertion operation is performed, the fake data voltage corresponding to the fake image that is completely unrelated to the real image is supplied to one or more subpixels (SP).

In other words, when driving a typical real display, the image data voltage (Vdata) supplied to subpixels (SP) may vary depending on the frame or image, but when driving fake data insertion, the image data voltage (Vdata) supplied to one or more subpixels (SP) The fake data voltage may be constant rather than variable depending on the frame or video.

Below, the data voltage corresponding to the real image is described as the image data voltage or real image data voltage, and the data voltage corresponding to the fake image is described as the fake data voltage or fake data voltage. For example, the fake data voltage may be a black data voltage, a low-gradation data voltage, or a single color data voltage.

Referring to FIG. 4, when driving a real display, a plurality of subpixel rows are scanned one by one and real image data is sequentially recorded (Real Image Data Write). Accordingly, a plurality of scan signal lines (SCL) corresponding to a plurality of subpixel rows are sequentially scanned one by one (Real Image Gate Scan).

Referring to FIG. 4, when a fake display is driven (fake data insertion drive), a plurality of subpixel rows are sequentially scanned k (k is a natural number of 2 or more) at a time, and fake data is recorded (Fake Image Data Write). That is, fake data is simultaneously recorded in k subpixel rows at any one time. Accordingly, a plurality of scan signal lines (SCL) corresponding to a plurality of subpixel rows are sequentially scanned k at a time (Fake Image Gate Scan).

In other words, at a certain point in time, during the fake data insertion drive, the fake data voltage may be simultaneously supplied to k subpixel rows. k, the number of subpixel rows in which image data insertion operation is simultaneously performed at a certain point in time, is a natural number of 2 or more. For example, the number (k) of subpixel rows in which the fake data insertion operation is performed at any one time may be 2, 4, or 8.

Referring to Figures 4 and 5, assuming that the fake image is a black image, at the first viewpoint (#1), the fake image is displayed in the area where the k subpixel rows located at the top of the screen are located, and the remaining area is displayed. A real image can be displayed. At the second viewpoint (#2), a fake image may be displayed in an area where k subpixel rows located in the middle of the screen are located, and a real image may be displayed in the remaining upper and lower areas. At a third viewpoint (#3), a fake image may be displayed in an area where k subpixel rows located at the bottom of the screen are located, and a real image may be displayed in the remaining area.

Figures 6 and 7 are driving timing diagrams when the display device 100 performs fake data insertion driving and overlap driving according to embodiments of the present invention.

Figure 6 shows a plurality of scan signals corresponding to a plurality of subpixel rows (..., R(n+1), R(n+2),..., R(n+10),...). It is a timing diagram showing the scan signal (SCAN) sequentially applied to the line (SCL), and Figure 7 shows a plurality of subpixel rows (..., R(n+1), R(n+2),... , R(n+10), ...), the third to fifth subpixel rows (R(n+3), R(n+4), R(n+5), R(n+6)) This is a timing diagram showing the scan signal (SCAN) and sense signal (SENSE) corresponding to .

Referring to FIG. 6, the display device 100 according to embodiments of the present invention has a plurality of subpixel rows (..., R(n+1), R(n+2),..., R (n+10), ...) In order to accurately express an image by securing sufficient charging time for each subpixel (SP), overlap driving can be performed.

Each scan signal (SCAN) of multiple subpixel rows (..., R(n+1), R(n+2), ..., R(n+10), ...) is turned on. It has level voltage sections (indicated as high level voltage sections in FIG. 6) sequentially.

According to overlap driving, each of the multiple subpixel rows (..., R(n+1), R(n+2),..., R(n+10),...) receives a scan signal (SCAN ) has a turn-on level voltage section of horizontal time (e.g. 2H) longer than 1 horizontal time (1H). In addition, each of the multiple subpixel rows (..., R(n+1), R(n+2),..., R(n+10),...) The turn-on level voltage section may partially overlap each other (e.g., 1H section).

For example, the back part of the turn-on level voltage section having a length of 2 horizontal times (2H) in the scan signal (SCAN) applied to the first subpixel row (R(n+1)) is the second sub-pixel row (R(n+1)). It may overlap with the front part of the turn-on level voltage section having a length of 2 horizontal times (2H) in the scan signal (SCAN) applied to the pixel row (R(n+2)).

Below, a driving method combining the above-described fake display driving (fake data insertion driving) and overlap driving will be described.

Referring to FIG. 6, the first subpixel row (R(n+1)), the second subpixel row (R(n+2)), the third subpixel row (R(n+3)), and the Real Image Data Write proceeds sequentially in 4 subpixel rows (R(n+4)).

Afterwards, a fake data insertion (FDI) drive is performed on the first to fourth subpixel rows (R(n+1) to R(n+4)) and the other k subpixel rows in the display panel 110. , Fake Image Data Write may be performed in k subpixel rows. Here, the k subpixel rows in which fake data recording is in progress are subpixel rows arranged before the first subpixel row (R(n+1)), and the real video period (RIP) of a certain period of time has already progressed. These may be subpixel rows.

Thereafter, the fifth subpixel row (R(n+5)), the sixth subpixel row (R(n+6)), the seventh subpixel row (R(n+7)), and the eighth subpixel row R ((n+8)) Real Image Data Write proceeds sequentially.

Afterwards, a fake data insertion (FDI) drive is performed on the fifth to eighth subpixel rows (R(n+5) to R(n+8)) and the other k subpixel rows in the display panel 110. , Fake Image Data Write may be performed in k subpixel rows. Here, the k subpixel rows in which fake data recording is in progress are subpixel rows arranged before the fifth subpixel row (R(n+5)), and a certain amount of real video period (RIP) has already progressed. These may be subpixel rows.

At the same time, the number (k) of subpixel rows in which the fake data insertion drive is performed may be the same or different. For example, the fake data insertion drive may be performed simultaneously in the first two subpixel rows, and then the fake data insertion drive may be performed simultaneously in units of four subpixel rows. As another example, the fake data insertion drive may be performed simultaneously in the first four subpixel rows, and then the fake data insertion drive may be performed simultaneously in units of eight subpixel rows.

By displaying real image data and fake image data in the same frame through the above-mentioned fake data insertion drive, the motion blur phenomenon in which the image is not differentiated and is dragged is prevented, thereby improving the image quality. It can improve picture quality.

When the above-described fake data insertion operation is performed, Real Image Data Write and Fake Image Data Write may be performed through the data line DL.

In addition, as described above, by simultaneously recording fake data in a plurality of subpixel rows, the luminance deviation due to the difference in real video period (RIP) depending on the position of the subpixel row can be compensated, and the video data recording time can secure.

Meanwhile, by adjusting the timing of the fake data insertion drive, the length of the real video period (RIP) can be adaptively adjusted according to the video.

The video data recording timing and fake data recording timing can be varied through gate driving control.

For example, when the fake data voltage (Vfake) is the black data voltage (Vblack), that is, when the fake image is a black image, the fake data insertion (FDI) drive is also called the black data insertion (BDI: Black Data Insertion) drive. can do.

The period during which k subpixel rows do not emit light due to the fake data insertion drive is called the fake image period (FIP). Since the fake video may be a black video, for example, the fake video period (FIP) may also be referred to as the black video period.

Meanwhile, multiple subpixel rows (..., R(n+1), R(n+2), R(n+3), R(n+4), R(n+5),... ) The gate driving for each is performed sequentially, but may overlap for a certain period of time.

Referring to Figure 7, multiple subpixel rows (..., R(n+1), R(n+2), R(n+3), R(n+4), R(n+5) , ...) Each scan signal (SCAN) and sense signal (SENSE) may be the same. That is, during overlap driving, multiple subpixel rows (... , R(n+1), R(n+2), R(n+3), R(n+4), R(n+5) , ...) the scan transistor (SCT) and sense transistor (SENT) included in each can be turned on and off at the same time. That is, during overlap driving, multiple subpixel rows (... , R(n+1), R(n+2), R(n+3), R(n+4), R(n+5) , ...) The scan signal (SCAN) and sense signal (SENSE) applied to each of the scan transistor (SCT) and sense transistor (SENT) included in each are the same gate signal with the turn-on level voltage section at the same timing. You can.

According to the examples of FIGS. 6 and 7, a plurality of subpixel rows (..., R(n+1), R(n+2), R(n+3), R(n+4), R( The length of the turn-on level voltage section of the gate signals (SCAN, SENSE) supplied to n+5), ...), respectively, may be, for example, 2H.

According to the examples of FIGS. 6 and 7, a plurality of subpixel rows (..., R(n+1), R(n+2), R(n+3), R(n+4), R( The turn-on level voltage sections of the two gate signals (SCAN, SENSE) supplied to n+5), ...) may overlap each other.

Multiple subpixel rows (... , R(n+1), R(n+2), R(n+3), R(n+4), R(n+5), ...) respectively. The length of the turn-on level voltage section of the gate signals (SCAN, SENSE) supplied to may be 2H.

Turn-on level of the scan signal (SCAN) and sense signal (SENSE) applied to the scan transistor (SCT) and sense transistor (SENT) of the subpixels (SP) arranged in the subpixel row R(n+1), respectively. The voltage section 2H is a scan signal (SCAN) and a sense signal ( It can overlap by 1H with the turn-on level voltage section (2H) of SENSE).

Turn-on level of the scan signal (SCAN) and sense signal (SENSE) applied to the scan transistor (SCT) and sense transistor (SENT) of the subpixels (SP) arranged in the subpixel row R(n+2), respectively. The voltage section 2H is a scan signal (SCAN) and a sense signal ( It can overlap by 1H with the turn-on level voltage section (2H) of SENSE).

Turn-on level of the scan signal (SCAN) and sense signal (SENSE) applied to the scan transistor (SCT) and sense transistor (SENT) of the subpixels (SP) arranged in the subpixel row R(n+3), respectively. The voltage section 2H is a scan signal (SCAN) and a sense signal ( It can overlap by 1H with the turn-on level voltage section (2H) of SENSE).

According to the example of FIGS. 6 and 7, the length of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each subpixel row is 2H, and the length of the two gate signals in the two adjacent subpixel rows is 2H. The turn-on level voltage sections of the signals (SCAN, SENSE) may overlap each other by 1H. As shown in Figures 6 and 7, when the length of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each subpixel row is 2H, it is called 2H overlap driving.

Overlap driving can be modified in various ways other than 2H overlap driving.

As another example of overlap driving, the length of the turn-on level voltage section of two gate signals (SCAN, SENSE) in each subpixel row is 3H, and the length of the turn-on level voltage section of two gate signals (SCAN, SENSE) in two adjacent subpixel rows is 3H. The turn-on level voltage section of SENSE may overlap by 2H.

As another example of overlap driving, the length of the turn-on level voltage section of two gate signals (SCAN, SENSE) in each subpixel row is 3H, and the length of the turn-on level voltage section of two gate signals (SCAN, SENSE) in two adjacent subpixel rows is 3H. , SENSE)'s turn-on level voltage section may overlap by 1H.

As another example of overlap driving, the length of the turn-on level voltage section of two gate signals (SCAN, SENSE) in each subpixel row is 4H, and the length of the turn-on level voltage section of two gate signals (SCAN, SENSE) in two adjacent subpixel rows is 4H. , SENSE)'s turn-on level voltage section may overlap by 3H.

As such, there may be various overlap drives, but for convenience of explanation, 2H overlap drive will be described below as an example.

When driving the 2H overlap described above, each subpixel row (... , R(n+1), R(n+2), R(n+3), R(n+4), R(n+5) , ...), the front part (1H length) of the turn-on level voltage section (2H length) of the two gate signals (SCAN, SENSE) is the data voltage (this is the pre-charge) to the corresponding subpixel. This is the gate signal part for pre-charge (PC: Pre-Charge) driving to which the data voltage (playing the role of data voltage) is applied. The latter part (length of 1H) of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each subpixel row is used for recording video data in which the real video data voltage (Vdata) is applied to the corresponding subpixel. This is the gate signal part to make this happen.

Through the above-described overlap driving, the charging rate in each subpixel can be improved, thereby improving image quality.

When performing the above-described fake data insertion drive and overlap drive together, the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+3) is It overlaps with the turn-on level voltage section of the two gate signals (SCAN, SENSE) at +4).

Here, the latter 1H period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+3) is the two gate signals in the next subpixel row R(n+4). This is a period that overlaps with the turn-on level voltage section of the signals (SCAN, SENSE), and is a period in which image data is recorded in the subpixel row R(n+3).

The first 1H period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+4) is a pre-charge driving period. And, the subpixel row R(n+3) and subpixel row R(n+4) are subpixel rows where image data is recorded before the fake data insertion drive is performed.

In addition, the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+5) is the two gate signals (SCAN, SENSE) in the subpixel row R(n+6). ) overlaps with the turn-on level voltage section.

Here, the latter 1H period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+5) is the two gate signals in the next subpixel row R(n+6). This is a period that overlaps with the turn-on level voltage section of the signals (SCAN, SENSE), and is a period in which image data is recorded in the subpixel row R(n+5). The first 1H period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+6) is a pre-charge driving period. And, the subpixel row R(n+5) and subpixel row R(n+6) are subpixel rows where image data is recorded before the fake data insertion drive is performed.

However, just before the fake data insertion drive is performed, the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+4) is It does not overlap with the turn-on level voltage section of the two gate signals (SCAN, SENSE) in 5).

The latter 1H period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+4) is a period in which image data is recorded in the subpixel row R(n+4).

During the latter 1H period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+4), pre-charge driving is performed in the next subpixel row R(n+5). I don't lose.

Based on the fake data insertion drive period, subpixel row R(n+4) is the subpixel row where image data is recorded immediately before the fake data insertion drive, and subpixel row R(n+5) is the fake data insertion drive. This is the subpixel row where image data is recorded immediately after .

The turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+4) and the two gate signals (SCAN, SENSE) in the next subpixel row R(n+5) The turn-on level voltage sections are separated from each other by the period during which the fake data insertion drive is performed.

In FIGS. 6 and 7, the Vg graph shows the voltage of the first node (N1) of the driving transistor (DT) of the subpixels included in the subpixel rows, and is the voltage state before entering the boosting step in the subpixel driving operation procedure. represents a change.

Referring to Figures 6 and 7, the Vs graph shows the voltage of the second node (N2) of the driving transistor (DT) of the subpixels included in the subpixel rows, before entering the boosting step in the subpixel driving operation procedure. Indicates a change in voltage state.

Referring to the Vg graphs of FIGS. 6 and 7, in the remaining period excluding the period during which fake data insertion is in progress, the Vg voltage of the first node (N1) of the driving transistor (DT) of the subpixels included in each subpixel row becomes the video data voltage (Vdata) according to the progress of video data recording.

However, during the period when fake data insertion is in progress, the Vg voltage of the first node (N1) of the driving transistor (DT) of the subpixels included in the subpixel rows where the fake data insertion drive is in progress is the fake data voltage (Vfake). You will have

Meanwhile, as described above, the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each of the subpixel rows R(n+1), R(n+2), and R(n+3) The latter period overlaps with the front period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the next subpixel row. However, the latter period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+4) is the two gate signals (SCAN, SENSE) in the next subpixel row R(n+5). It does not overlap with the first period of the turn-on level voltage section of (SCAN, SENSE).

Therefore, during the turn-on level voltage period of the two gate signals (SCAN, SENSE) in each of the subpixel rows R(n+1), R(n+2), and R(n+3), the subpixel row R The voltage Vs of the second node (N2) of the driving transistor (DT) of the subpixels included in each of (n+1), R(n+2), and R(n+3) is the reference voltage in the image data recording step. It has a voltage (Vref+△V) similar to (Vref). At this time, the potential difference Vgs between the first node N1 and the second node N2 of each driving transistor DT is Vdata-(Vref+ΔV).

The 1H period immediately before the fake data insertion drive period, that is, the latter period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the subpixel row R(n+4) (next subpixel row R(n+4) +5), the driving transistor (Dt) of the subpixels included in the subpixel row R(n+4) does not overlap with the first period of the turn-on level voltage section of the two gate signals (SCAN, SENSE) ) The Vs voltage of the second node (N2) may be a voltage (Vref+△(V/2)) lower than Vref+△V.

Accordingly, the potential difference Vgs (Vgs(4)) between the first node N1 and the second node N2 of each driving transistor DT is Vdata-(Vref+△(V/2)), which is the potential difference in the previous period. It can be increased from (Vdata-(Vref+△V)).

FIGS. 8 and 9 are diagrams to explain the principle of fake data insertion (FDI) operation performed by the display device 100 according to embodiments of the present invention. However, it is assumed that the fake data insertion operation is performed simultaneously in 8 subpixel rows. That is, assume the case of k=8.

During one frame time, each of the scan signals (SCAN(i+1) ~ SCAN(i+8), SCAN(j+1) ~ SCAN(j+8)) has a turn-on level voltage section and a turn-off level. It may have a voltage section.

The turn-on level voltage section of each scan signal (SCAN(i+1) ~ SCAN(i+8), SCAN(j+1) ~ SCAN(j+8)) turns on the scan transistor (SCT). It is a turn-on level voltage (VGH) that can be turned on, and each of the scan signals (SCAN(i+1) ~ SCAN(i+8), SCAN(j+1) ~ SCAN(j+8)) is turned off. The level voltage section is a turn-off level voltage (VGL) that can turn off the scan transistor (SCT). For example, if the scan transistor (SCT) is n-type, the turn-on level voltage (VGH) is higher than the turn-off level voltage (VGL), and if the scan transistor (SCT) is p-type, the turn-on level The voltage (VGH) may be lower than the turn-off level voltage (VGL). In this specification and drawings, the case where the scan transistor (SCT) is n-type is used as an example.

Referring to FIGS. 8 and 9, the gate driving circuit 130 generates a turn-on level voltage section using the (i+1)th to (i+4)th scan signal lines (SCL) according to the overlap driving method. The (i+1)th to (i+4)th scan signals (SCAN(i+1) to SCAN(i+4)) are sequentially output.

Referring to FIGS. 8 and 9, according to predetermined driving timing rules, the (i+4)th scan signal (SCAN(i+4)) having a turn-on level voltage section is output from the gate driving circuit 130. After this, the fake data insertion drive is performed.

Accordingly, the gate driving circuit 130 operates on the (i+5)th scan signal line (SCL) corresponding to point B next to the (i+4)th scan signal line (SCL) and the scan signal lines thereafter. Stop scanning signal output with (SCL).

During the fake data insertion driving period (Tf), the gate driving circuit 130 generates a turn-on level voltage section at the same timing with eight scan signal lines (SCL) arranged in eight subpixel rows corresponding to area A. Outputs 8 scan signals (SCAN(j+1) ~ SCAN(j+8)). Accordingly, the scan transistor (SCT) of the subpixels (SP) connected to the eight scan signal lines (SCL) is turned on, and the fake data voltage (Vfake) output from the data driving circuit 120 is in the A region. are supplied as subpixels (SP) to the eight subpixel rows corresponding to .

After the fake data insertion driving period (Tf) has elapsed, the gate driving circuit 130 resumes outputting the gate signal for driving the real display, and depending on the overlap driving method, (i+5)th to (i+8)th Outputs the (i+5)th to (i+8)th scan signals (SCAN(i+5) to SCAN(i+8)) sequentially having turn-on level voltage sections to the th scan signal line (SCL). do.

Referring to FIG. 8, the subpixel (SP) in area A and the subpixel (SP) in point B are connected to the same data line (DL). The data driving circuit 130 cannot simultaneously output the real image data voltage (Vdata) and the fake data voltage (Vfake) to one data line (DL).

Therefore, during the fake data insertion driving period (Tf), the gate driving circuit 130 scans with the (i+5)th scan signal line (SCL) corresponding to point B and the subsequent scan signal lines (SCL). This stops signal output.

In other words, during the fake data insertion driving period (Tf), the turn-on level voltage section of the (i+4)th scan signal (SCAN(i+4)) and the (i+5)th scan signal (SCAN(i) By spreading the turn-on level voltage section of +5)) so as not to overlap, the timing at which the fake data voltage (Vfake) is supplied to the subpixel (SP) in area A can be secured.

FIG. 10 is a timing diagram of fake data insertion (FDI) driving when the display device 100 according to embodiments of the present invention is implemented with high resolution.

When the display panel 110 is implemented with high resolution, more and more subpixels (SP) are arranged within a given size, and more and more data lines (DL) and gate lines (SCL and SENL) are arranged. When implementing the display panel 110 with high resolution, more and more subpixels (SP) must be driven within a set frame time, so the subpixels (SP) are connected to the storage capacitor (Cst) of each subpixel (SP). Charging time inevitably becomes insufficient.

Therefore, in order to implement high resolution, the display device 100 according to embodiments of the present invention has the length of the turn-on level voltage section of each of the scan signals (SCAN(i+1) to SCAN(i+8)). can be made longer than 1 horizontal time (1H).

For example, as shown in FIG. 10, the display device 100 according to embodiments of the present invention uses scan signals (SCAN(i+1) to SCAN(i+8)) to implement high resolution. The length of each turn-on level voltage section can be set to more than 4 horizontal times (4H).

Referring to FIG. 10, 1 horizontal time (1H) at the end of each turn-on level voltage section of the scan signals (SCAN(i+1) to SCAN(i+8)) is in the section for recording video data. It applies.

Referring to FIG. 10, in order to implement high resolution, if the temporal length of the turn-on level voltage section of each of the scan signals (SCAN(i+1) to SCAN(i+8)) is lengthened, the fake data insertion driving period The time interval (Tr) between the timing at which real video data was recorded just before (Tf) and the timing at which real video data was recorded immediately after the fake data insertion drive period (Tf) is bound to become longer.

The time interval (Tr) between the timing at which real video data was recorded immediately before the fake data insertion drive period (Tf) and the timing at which real video data was recorded immediately after the fake data insertion drive period (Tf) is the video by the fake data insertion drive. Corresponds to display delay. When implementing high resolution, video display delay due to fake data insertion drive is bound to increase, which can be a factor in degrading video quality.

Accordingly, embodiments of the present invention present an improved gate driving method that can improve image quality by reducing image display delay due to fake data insertion drive, despite high-resolution implementation. Below, we describe an improved gate driving method that can prevent image display delays when implementing high resolution.

FIG. 11 is a timing diagram for improved gate driving to prevent image display delay when the display device 100 according to embodiments of the present invention is implemented with high resolution, and FIG. 12 is a timing diagram of embodiments of the present invention. This is a diagram showing scan signal waveforms before and after fake data insertion (FDI) according to improved gate driving to prevent image display delay when the display device 100 according to is implemented with high resolution.

The display device 100 according to embodiments of the present invention includes a plurality of subpixels (SP) connected to a plurality of data lines (DL) and a plurality of scan signal lines (SCL), and a plurality of subpixels (SP) ) Each has a light emitting element (ED), a driving transistor (DT) for driving the light emitting element (ED), and a data line (DL) and a driving transistor according to the scan signal (SCAN) supplied through the scan signal line (SCL). A scan transistor (SCT) that controls the connection between the first node (N1) of (DT) and a storage capacitor (Cst) connected between the first node (N1) and the second node (N2) of the driving transistor (DT). It may include a display panel 110, a data driving circuit 120 for driving a plurality of data lines (DL), a gate driving circuit 130 for driving a plurality of scan signal lines (SCL), etc. You can.

Multiple subpixels (SP) may be arranged in a matrix form to form multiple subpixel rows.

Referring to FIG. 11, the plurality of subpixel rows may include (i+1)th to (i+6)th subpixel rows.

Referring to FIG. 11, the plurality of scan signal lines (SCL) are (i+1)th to (i+6)th scan signals corresponding to the (i+1)th to (i+6)th subpixel rows, respectively. (SCAN(i+1) ~ SCAN(i+6)) may include a line (SCL).

The gate driving circuit 130 generates a turn-on level voltage section using the (i+1)th to (i+6)th scan signal (SCAN(i+1) to SCAN(i+6)) line (SCL). The (i+1)th to (i+6)th scan signals (SCAN(i+1) to SCAN(i+6)) may be sequentially applied.

According to overlap driving, a portion of the turn-on level voltage section of the (i+3)th scan signal (SCAN(i+3)) and the turn of the (i+4)th scan signal (SCAN(i+4)) -Some parts of the on level voltage section may overlap.

According to the fake data insertion (FD) operation, the turn-on level voltage section of the (i+4)th scan signal (SCAN(i+4)) and the (i+5)th scan signal (SCAN(i+5)) The turn-on level voltage section does not overlap.

For fake data insertion driving, the gate driving circuit 130 uses the turn-on level voltage section of the (i+4)th scan signal (SCAN(i+4)) and the (i+5)th scan signal (SCAN(i+4)). During the period when the turn-on level voltage section of i+5)) does not overlap, that is, during the fake data insertion driving period (Tf), two of the plurality of scan signal lines (SCL) to receive the fake data voltage (Vfake) Two or more scan signals (SCAN) having turn-on level voltage sections can be applied at the same timing through two or more scan signal lines (SCL) connected to one or more subpixel rows.

Referring to FIGS. 11 and 12 , the display device 100 according to embodiments of the present invention can perform improved gate driving to reduce image display delay caused by fake data insertion driving.

The improved gate driving according to embodiments of the present invention is a turn-on level voltage section of scan signals (SCAN(i+5), SCAN(i+6), etc.) after the fake data insertion driving period (Tf). It is a drive that converts into an overdrive signal.

Accordingly, the gate driving circuit 130 is configured such that the turn-on level voltage section of the scan signals (SCAN(i+5), SCAN(i+6), etc.) after the fake data insertion driving period (Tf) is overdrive. The scan signals (SCAN(i+5), SCAN(i+6), etc.) after the fake data insertion driving period (Tf) can be controlled so that the signal waveform is formed.

According to the improved gate driving according to the embodiments of the present invention, as shown in FIGS. 11 and 12, the (i+5)th scan signal (SCAN(i+5) after the fake data insertion driving period (Tf) The maximum voltage value (VGH_BOOST) of the turn-on level voltage section of )) is the turn-on level voltage section of the (i+4)th scan signal (SCAN(i+4)) before the fake data insertion driving period (Tf). It may be higher than the maximum voltage value (VGH) of

According to the improved gate driving according to the embodiments of the present invention, even if the temporal length of the turn-on level voltage section of the scan signals is lengthened from 2 horizontal times (2H) to 4 horizontal times (4H) or more to implement high resolution , video display delay caused by fake data insertion drive can be reduced.

Referring to FIG. 11, the time interval (Tr) between the timing at which real video data was recorded immediately before the fake data insertion drive period (Tf) and the timing at which real video data was recorded immediately after the fake data insertion drive period (Tf) is the fake data. Corresponds to the video display delay value caused by insertion drive.

Referring to FIG. 11, when the gate driving circuit 130 according to embodiments of the present invention operates in an improved gate driving method, the image display delay value (Tf) due to the fake data insertion drive is significantly higher than that of FIG. 10. It gets shorter.

Referring to Figures 11 and 12, according to the improved gate driving according to the embodiments of the present invention, the (i+5)th scan signal (SCAN(i+5)) after the fake data insertion driving period (Tf) The temporal length (e.g., 2H) of the turn-on level voltage section of is the turn-on level voltage of the (i+4)th scan signal (SCAN(i+4)) before the fake data insertion driving period (Tf). It may be shorter than the temporal length of the section (e.g. 4H).

Referring to FIGS. 11 and 12, the temporal length (e.g., 2H) of the turn-on level voltage section of the (i+5)th scan signal (SCAN(i+5)) after the fake data insertion driving period (Tf) ) is the fake data insertion time interval (Tr) between the timing at which real video data was recorded immediately before the fake data insertion drive period (Tf) and the timing at which real video data was recorded immediately after the fake data insertion drive period (Tf). It may correspond to the time (Tr-Tf) minus the driving period (Tf).

The gate driving circuit 130 is operated immediately after the (i+4)th scan signal (SCAN(i+4)) that was output immediately before the fake data insertion driving period (Tf) after the fake data insertion driving period (Tf). Only the next (i+5)th scan signal (SCAN(i+5)) can be output in overdrive form.

Alternatively, the gate driving circuit 130 may generate the (i+4)th scan signal (SCAN(i+4)) output after the fake data insertion drive period (Tf) and immediately before the fake data insertion drive period (Tf). Not only the (i+5)th scan signal (SCAN(i+5)) immediately following , but also the (i+6)th scan signal (SCAN(i+6)) can be output in overdrive form.

Referring to Figures 11 and 12, the (i+6)th scan signal (SCAN(i+6)) is at the start of the turn-on level voltage section at the (i+5)th scan signal (SCAN(i+5). )) may correspond to the start of the turn-on level voltage section.

The image data recording timing for the subpixel row to which the (i+6)th scan signal (SCAN(i+6)) is applied is the subpixel row to which the (i+5)th scan signal (SCAN(i+5)) is applied. It lags behind the image data recording timing for the pixel row.

Accordingly, as shown in FIGS. 11 and 12, the temporal length (e.g., 3H) of the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is (i+ It may be longer than the temporal length (e.g., 2H) of the turn-on level voltage section of the 5)th scan signal (SCAN(i+5)).

11 and 12, the maximum voltage value (VGH_BOOST) in the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is the (i+5)th scan signal (SCAN(i+6)). It may correspond to the maximum voltage value (VGH_BOOST) of the turn-on level voltage section of (i+5)).

In Figure 12, the (i+4)th scan signal (SCAN(i+4)), the (i+5)th scan signal (SCAN(i+5)), and the (i+6)th scan signal (SCAN(i) +6)) For each, the part indicated by the dotted line is the signal waveform considering actual rising and falling phenomena.

Referring to Figures 11 and 12, the maximum voltage value (VGH_BOOST) in the turn-on level voltage section of the (i+5)th scan signal (SCAN(i+5)) is the (i+4)th scan signal (SCAN(i+5)). It may be a voltage value (VGH_BOOST) boosted by a preset boost voltage (Vboost) than the maximum voltage value (VGH) of the turn-on level voltage section (i+4)).

Referring to Figures 11 and 12, the turn-on level voltage section of the (i+5)th scan signal (SCAN(i+5)) is where the reference turn-on level voltage (VGH) and the boost voltage (Vboost) are It may include a first turn-on level voltage section (Ton1) with an added boost turn-on level voltage (VGH_BOOST) and a second turn-on level voltage section (Ton2) with a reference turn-on level voltage (VGH). You can.

In the turn-on level voltage section of the (i+5)th scan signal (SCAN(i+5)), the reference turn-on level voltage (VGH) of the second turn-on level voltage section (Ton2) is ( It may correspond to or be equal to the maximum voltage value (VGH) of the turn-on level voltage section of the i+4)th scan signal (SCAN(i+4)).

Among the turn-on level voltage sections of the (i+5)th scan signal (SCAN(i+5)), the first turn-on level voltage section (Ton1) may correspond to an overdriven voltage section.

Referring to Figures 11 and 12, the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is where the reference turn-on level voltage (VGH) and the boost voltage (Vboos) are It may include a first turn-on level voltage section (Ton1) with an added boost turn-on level voltage (VGH_BOOST) and a second turn-on level voltage section (Ton2) with a reference turn-on level voltage (VGH). You can.

Among the turn-on level voltage sections of the (i+6)th scan signal (SCAN(i+6)), the first turn-on level voltage section (Ton1) may correspond to an overdriven voltage section.

In the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)), the reference turn-on level voltage (VGH) of the second turn-on level voltage section (Ton2) is ( It may correspond to the maximum voltage value of the turn-on level voltage section of the i+4)th scan signal (SCAN(i+4)).

The start point of the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is the turn-on level voltage of the (i+5)th scan signal (SCAN(i+5)). It may correspond to the starting point of the section.

The temporal length (e.g. 3H) of the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is that of the (i+5)th scan signal (SCAN(i+5)). It may be longer than the temporal length of the turn-on level voltage section (e.g., 2H).

Referring to FIG. 12, the temporal length (Ton1) of the first turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is the (i+5)th scan signal (SCAN(i+6)). It may correspond to the temporal length (Ton1) of the first turn-on level voltage section of (i+5)).

For example, the temporal length (Ton1) of the first turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) and the (i+5)th scan signal (SCAN(i) The temporal length (Ton1) of the first turn-on level voltage section of +5)) may be 1 horizontal time (1H).

Referring to FIG. 12, the temporal length (Ton2) of the second turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is the (i+5)th scan signal (SCAN(i+6)). It may be longer than the temporal length (Ton2) of the second turn-on level voltage section of i+5)).

For example, the temporal length (Ton2) of the second turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is 2 horizontal times (2H), and (i+5) The temporal length (Ton2) of the second turn-on level voltage section of the th scan signal (SCAN(i+5)) may be 1 horizontal time (1H).

The data driving circuit 120 operates at (i+) during the turn-on level voltage section of the (i+1)th to (i+6)th scan signals (SCAN(i+1) to SCAN(i+6)). Image data voltages (Vdata) corresponding to the real image can be supplied to subpixels (SP) included in the 1)th to (i+6)th subpixel rows.

The data driving circuit 120 is configured to control the turn-on level voltage section of the (i+4)th scan signal (SCAN(i+4)) and the turn of the (i+5)th scan signal (SCAN(i+5)). -During the period when the on-level voltage section does not overlap, that is, during the fake data insertion driving period (Tf), the subpixels (SP) included in two or more subpixel rows among multiple subpixel rows are related to the real image. A fake data voltage (Vfake) corresponding to an absent fake image can be supplied.

Two or more subpixel rows to which the fake data voltage (Vfake) is supplied may correspond to two or more scan signal lines (SCL) to which two or more scan signals (SCAN) having a turn-on level voltage section are applied at the same timing. .

A real video may be an image that can be recognized by the naked eye, and a fake video may be an image that cannot be recognized by the naked eye. For example, the fake data voltage Vfake may be a black data voltage, a low-gradation data voltage, or a single color data voltage.

Each of the plurality of subpixels (SP) has a sense transistor ( SENT) may be further included.

The sense signal (SENSE) applied to the sense signal line (SENL) and the scan signal (SCAN) applied to the scan signal line (SCL) may have the same signal waveform.

After the fake data insertion driving period Tf, when the scan signal SCAN has an overdriven waveform, the sense signal SENSE may also have an overdriven waveform.

The sense signal SENSE applied to the sense signal line SENL and the scan signal SCAN applied to the scan signal line SCL may have a turn-on level voltage section of the same length.

After the fake data insertion driving period (Tf), the temporal length of the turn-on level voltage section of the sense signal (SENSE) is the shortened temporal length (Ton1+Ton2) of the turn-on level voltage section of the scan signal (SCAN). It can correspond to .

In order to implement high resolution, the (i+1)th to (i+4)th scan signals (SCAN(i+1) to SCAN() output from the gate driving circuit 130 before the fake data insertion driving period (Tf). The turn-on level voltage section of i+4)) may be longer than 1 horizontal time.

For example, for high-resolution implementation, before the fake data insertion driving period (Tf), the (i+1)th to (i+4)th scan signals (SCAN(i+1) output from the gate driving circuit 130 ) ~ SCAN(i+4)) turn-on level voltage section may be more than 4 horizontal times (4H).

FIG. 13 is another timing diagram for improved gate driving to prevent image display delay when the display device 100 according to embodiments of the present invention is implemented with high resolution, and FIG. 14 is an embodiment of the present invention. Another diagram showing scan signal (SCAN) waveforms before and after fake data insertion (FDI) according to improved gate driving to prevent image display delay when the display device 100 according to the above is implemented with high resolution.

The improved gate driving method to be described with reference to FIGS. 13 and 14 is basically the same as the gate driving method described with reference to FIGS. 11 and 12, and after the fake data insertion drive, the (i+5)th scan signal ( Only the (i+6)th scan signal (SCAN(i+6)) following SCAN(i+5)) is different. This difference will be mainly explained.

Referring to Figures 13 and 14, the (i+6)th scan signal (SCAN(i+6)) is at the start of the turn-on level voltage section at the (i+5)th scan signal (SCAN(i+5). )) may correspond to the start point of the turn-on level voltage section.

The image data recording timing (end of the hatched section) for the subpixel row to which the (i+6)th scan signal (SCAN(i+6)) is applied is the (i+5)th scan signal (SCAN(i+6)). i+5)) is behind the image data recording timing for the applied subpixel row (the end point of the section indicated by the hatch).

Accordingly, as shown in FIGS. 13 and 14, the temporal length (e.g., 3H) of the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is (i+ It may be longer than the temporal length (e.g., 2H) of the turn-on level voltage section of the 5)th scan signal (SCAN(i+5)).

13 and 14, the maximum voltage value (VGH_BOOST) in the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is the (i+5)th scan signal (SCAN(i+6)). It may correspond to the maximum voltage value (VGH_BOOST) of the turn-on level voltage section of (i+5)).

In Figure 14, the (i+4)th scan signal (SCAN(i+4)), the (i+5)th scan signal (SCAN(i+5)), and the (i+6)th scan signal (SCAN(i) +6)) For each, the part indicated by the dotted line is the signal waveform considering actual rising and falling phenomena.

Referring to Figures 13 and 14, the maximum voltage value (VGH_BOOST) in the turn-on level voltage section of the (i+5)th scan signal (SCAN(i+5)) is the (i+4)th scan signal (SCAN(i+5)). It may be a voltage value (VGH_BOOST) boosted by a preset boost voltage (Vboost) than the maximum voltage value (VGH) of the turn-on level voltage section (i+4)).

13 and 14, the turn-on level voltage section of the (i+5)th scan signal (SCAN(i+5)) is where the reference turn-on level voltage (VGH) and the boost voltage (Vboost) are It may include a first turn-on level voltage section (Ton1) with an added boost turn-on level voltage (VGH_BOOST) and a second turn-on level voltage section (Ton2) with a reference turn-on level voltage (VGH). You can.

Here, the reference turn-on level voltage (VGH) may correspond to or be equal to the maximum voltage value (VGH) of the turn-on level voltage section of the (i+4)th scan signal (SCAN(i+4)). .

Among the turn-on level voltage sections of the (i+5)th scan signal (SCAN(i+5)), the first turn-on level voltage section (Ton1) may correspond to an overdriven voltage section.

13 and 14, the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is where the reference turn-on level voltage (VGH) and the boost voltage (Vboos) are It may include a first turn-on level voltage section (Ton1) with an added boost turn-on level voltage (VGH_BOOST) and a second turn-on level voltage section (Ton2) with a reference turn-on level voltage (VGH). You can.

Among the turn-on level voltage sections of the (i+6)th scan signal (SCAN(i+6)), the first turn-on level voltage section (Ton1) may correspond to an overdriven voltage section.

In the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)), the reference turn-on level voltage (VGH) of the second turn-on level voltage section (Ton2) is ( It may correspond to the maximum voltage value of the turn-on level voltage section of the i+4)th scan signal (SCAN(i+4)).

The start point of the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is the turn-on level voltage of the (i+5)th scan signal (SCAN(i+5)). It may correspond to the starting point of the section.

The temporal length (e.g. 3H) of the turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is that of the (i+5)th scan signal (SCAN(i+5)). It may be longer than the temporal length of the turn-on level voltage section (e.g., 2H).

Referring to FIGS. 13 and 14, the temporal length (e.g., 2H) of the first turn-on level voltage section (Ton1) of the (i+6)th scan signal (SCAN(i+6)) is (i+ It may be longer than the temporal length (e.g., 1H) of the first turn-on level voltage section (Ton1) of the 5)th scan signal (SCAN(i+5)).

For example, the temporal length (Ton1) of the first turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is 2 horizontal times (2H), and (i+5) The temporal length (Ton1) of the first turn-on level voltage section of the th scan signal (SCAN(i+5)) may be 1 horizontal time (1H).

Referring to FIGS. 13 and 14, the temporal length (e.g., 1H) of the second turn-on level voltage section (Ton2) of the (i+6)th scan signal (SCAN(i+6)) is (i+ It may correspond to the temporal length (e.g., 1H) of the second turn-on level voltage section (Ton2) of the 5)th scan signal (SCAN(i+5)).

For example, the temporal length (Ton2) of the second turn-on level voltage section of the (i+6)th scan signal (SCAN(i+6)) is 1 horizontal time (1H), and (i+5) The temporal length (Ton2) of the second turn-on level voltage section of the th scan signal (SCAN(i+5)) may also be one horizontal time (1H).

Figure 15 is a block diagram showing a gate driving circuit 130 for providing improved gate driving to prevent image display delay when the display device 100 according to embodiments of the present invention is implemented with high resolution. .

Referring to FIG. 15, when the display device 100 according to embodiments of the present invention is implemented with high resolution, the gate driving circuit 130 to provide improved gate driving to prevent image display delay is, It may include a gate voltage supply circuit 1510 and a gate signal output circuit 1520.

The gate voltage supply circuit 1510 outputs a reference turn-on level voltage (VGH) and a boost turn-on level voltage (VGH_BOOST) as two turn-on level voltages, and outputs a turn-off level voltage (VGL). can do.

The gate signal output circuit 1520 generates a scan signal using two turn-on level voltages, the reference turn-on level voltage (VGH), the boost turn-on level voltage (VGH_BOOST), and the turn-off level voltage (VGL). (SCAN) can be generated and output to the corresponding scan signal line (SCL).

The gate voltage supply circuit 1510 outputs a reference turn-on level voltage (VGH) during the first driving period, and outputs a boost turn-on level voltage (VGH) different from the reference turn-on level voltage (VGH) during the second driving period. VGH_BOOST) can be output.

The gate signal output circuit 1520 outputs first scan signals (e.g., in FIGS. 11 and 13) sequentially having turn-on level voltage sections based on the reference turn-on level voltage (VGH) during the first driving period. SCAN(i+1) ~ SCAN(i+4)) are output to the first scan signal lines (SCL), and during the second driving period, the turn-on level voltage by the boost turn-on level voltage (VGH_BOOST) A second scan signal having a section (e.g., SCAN(i+5) and SCAN(i+6) in FIGS. 11 and 13) may be output to the second scan signal line SCL.

The first drive period mentioned above may be a drive period before the fake data insertion drive period (Tf). The second drive period may be a drive period after the fake data insertion drive period (Tf).

According to overlap driving, the turn-on level voltage sections of the first scan signals (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) during the first driving period may overlap each other. You can.

According to the fake data insertion drive, the turn-on level voltage section and the first scan signal (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) during the first driving period. The turn-on level voltage section of the second scan signal (e.g., SCAN(i+5) and SCAN(i+6) in FIGS. 11 and 13) during the two driving periods may not overlap.

The turn-on level voltage section of the first scan signals (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) during the first driving period and the second during the second driving period. The section in which the turn-on level voltage section of the scan signal (e.g., SCAN(i+5) and SCAN(i+6) in FIGS. 11 and 13) does not overlap corresponds to the fake data insertion driving period (Tf). You can.

Boost turn-on level voltage (VGH_BOOST) in the turn-on level voltage section of the second scan signal (e.g., SCAN(i+5) and SCAN(i+6) in FIGS. 11 and 13) during the second driving period. ) is the reference turn-on in the turn-on level voltage section of the first scan signals (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) during the first driving period. It may be higher than the level voltage (VGH).

Temporal length (e.g., 2H, 3H) of the turn-on level voltage section of the second scan signal (e.g., SCAN(i+5) and SCAN(i+6) in FIGS. 11 and 13) during the second driving period etc.) is the temporal length (e.g., turn-on level voltage section) of the first scan signals (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) during the first driving period. : 4H).

After the first driving period and the second driving period, a real image may be displayed on the display panel 110.

Between the first driving period and the second driving period, a fake image different from the real image may be displayed on the display panel 110.

Meanwhile, the gate signal output circuit 1520 uses two turn-on level voltages, the reference turn-on level voltage (VGH), the boost turn-on level voltage (VGH_BOOST), and the turn-off level voltage (VGL). A sense signal (SENSE) can be generated and output to the corresponding sense signal line (SENLL).

The sense signal (SENSE) may have the same signal waveform or the same voltage level change timing as the scan signal (SCAN). That is, the sense signal (SENSE) can be synchronized with the scan signal (SCAN).

Figure 16 is a flowchart of a method of driving the display device 100 according to embodiments of the present invention.

Referring to FIG. 16, the display device 100 according to embodiments of the present invention includes a display device including a plurality of subpixels (SP) connected to a plurality of data lines (DL) and a plurality of scan signal lines (SCL). It may include a panel 110, a data driving circuit 120 for driving a plurality of data lines (DL), and a gate driving circuit 130 for driving a plurality of scan signal lines (SCL).

Referring to FIG. 16, the method of driving the display device 100 according to embodiments of the present invention sequentially operates turn-on level voltage sections based on the reference turn-on level voltage (VGH) during the first driving period. A first real display driving step of sequentially outputting the first scan signals (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) to the first scan signal lines (SCL). (S1610) and, during the second driving period, a second scan signal (e.g., FIG. 11) having a turn-on level voltage section by the boost turn-on level voltage (VGH_BOOST) different from the reference turn-on level voltage (VGH) and a second real display driving step (S1630) of outputting SCAN(i+5) and SCAN(i+6) of FIG. 13 to the second scan signal line SCL.

The first drive period mentioned above may be a drive period before the fake data insertion drive period (Tf). The second drive period may be a drive period after the fake data insertion drive period (Tf).

According to overlap driving, the turn-on level voltage sections of the first scan signals (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) during the first driving period may overlap each other. You can.

According to the fake data insertion drive, the turn-on level voltage section and the first scan signal (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) during the first driving period. The turn-on level voltage section of the second scan signal (e.g., SCAN(i+5) and SCAN(i+6) in FIGS. 11 and 13) during the two driving periods may not overlap.

Boost turn-on level voltage (VGH_BOOST) in the turn-on level voltage section of the second scan signal (e.g., SCAN(i+5) and SCAN(i+6) in FIGS. 11 and 13) during the second driving period. ) is the reference turn-on in the turn-on level voltage section of the first scan signals (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) during the first driving period. It may be higher than the level voltage (VGH).

After the first driving period and the second driving period, a real image may be displayed on the display panel 110. Between the first driving period and the second driving period, a fake image different from the real image may be displayed on the display panel 110.

Temporal length (e.g., 2H, 3H) of the turn-on level voltage section of the second scan signal (e.g., SCAN(i+5) and SCAN(i+6) in FIGS. 11 and 13) during the second driving period etc.) is the temporal length (e.g., turn-on level voltage section) of the first scan signals (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) during the first driving period. : 4H).

Referring to FIG. 16, the method of driving the display device 100 according to embodiments of the present invention includes a reference turn-on between the first real display driving step (S1610) and the third real display driving step (S1630). Two or more scan signals (SCAN(J+1) to SCAN(j+8) in FIG. 9, when k=8) have turn-on level voltage sections by the level voltage (VGH) at the same timing. A fake display driving step (S1620) of simultaneously outputting the lines (SCL) may be further included.

The display device 100 according to embodiments of the present invention includes a plurality of subpixels (SP) connected to a plurality of data lines (DL) and a plurality of scan signal lines (SCL), and a plurality of subpixels (SP) ) Each includes a light emitting element (ED), a driving transistor (DT) for driving the light emitting element (ED), and a data line (DL) and driven according to the scan signal (SCAN) supplied through the scan signal line (SCL). A scan transistor (SCT) that controls the connection between the first node (N1) of the transistor (DT), and a capacitor (Cst) connected between the first node (N1) and the second node (N2) of the driving transistor (DT) It may include a display panel 110, a data driving circuit 120 for driving a plurality of data lines (DL), a gate driving circuit 130 for driving a plurality of scan signal lines (SCL), etc. You can.

Multiple subpixels (SP) may be arranged in a matrix form to form multiple subpixel rows.

The data driving circuit 120 is used to display an image using subpixels arranged in one subpixel row among a plurality of subpixel rows immediately before the first period (fake data insertion driving period (Tf)) within one frame time. Video data voltage (Vdata) can be supplied.

The data driving circuit 120 is configured to display a fake image different from the image using subpixels arranged in two or more subpixel rows among a plurality of subpixel rows during the first period (fake data insertion driving period (Tf)). A fake data voltage (Vfake) can be supplied.

The image displayed in the first period may be an image visible to the user, and the image displayed in the second period may be an image not visible to the user.

For example, the fake data voltage Vfake may be a black data voltage, a low-gradation data voltage, or a single color data voltage.

Before the first period, the gate driving circuit 130 uses a scan signal (e.g., SCAN(i+1) to SCAN(i+4) in FIGS. 11 and 13) having a reference turn-on level voltage (VGH). can be output.

Immediately after the first period, the gate driving circuit 130 receives a scan signal (e.g., SCAN(i+) in FIGS. 11 and 13 having a turn-on level voltage (VGH_BOOST) higher than the reference turn-on level voltage (VGH). 5), SCAN(i+6)) can be output.

According to embodiments of the present invention, a display device, gate driving circuit, and driving method that can improve image quality through improved charging rate through overlap driving of subpixels can be provided.

According to embodiments of the present invention, video quality can be improved by preventing afterimages and improving video response speed by inserting fake data to display an video (fake video) different from the actual video in between. A display device, gate driving circuit, and driving method can be provided.

According to embodiments of the present invention, the cause of the image quality deterioration that may occur when performing the overlap drive for high-resolution implementation and the fake data insertion drive at the same time is identified as the image display delay due to the fake data insertion drive, and the fake data insertion drive is identified. It is possible to provide a display device, gate driving circuit, and driving method that can improve image quality even when implementing high resolution by preventing or alleviating image display delay due to driving.

The above description is merely an illustrative explanation of the technical idea of the present invention, and various modifications and variations will be possible to those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but rather to explain it, and therefore the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display device
110: display panel
120: data driving circuit
130: Gate driving circuit
140: controller
1510: Gate voltage supply circuit
1520: Gate signal output circuit

Claims (20)

It includes a plurality of subpixels connected to a plurality of data lines and a plurality of scan signal lines, each of the plurality of subpixels having a light emitting element, a driving transistor for driving the light emitting element, and a scan signal supplied through the scan signal line. a display panel including a scan transistor that controls a connection between the data line and a first node of the driving transistor according to a signal, and a capacitor connected between a first node and a second node of the driving transistor;
a data driving circuit for driving the plurality of data lines; and
It includes a gate driving circuit for driving the plurality of scan signal lines,
The plurality of subpixels are arranged in a matrix form to form a plurality of subpixel rows, and the plurality of subpixel rows include (i+1)th to (i+6)th subpixel rows,
The plurality of scan signal lines include (i+1)th to (i+6)th scan signal lines respectively corresponding to the (i+1)th to (i+6)th subpixel rows,
The gate driving circuit generates (i+1)th to (i+6)th scan signals sequentially having turn-on level voltage sections through the (i+1)th to (i+6)th scan signal lines. Authorize,
A portion of the turn-on level voltage section of the (i+3)th scan signal and a portion of the turn-on level voltage section of the (i+4)th scan signal overlap,
The turn-on level voltage section of the (i+4)th scan signal and the turn-on level voltage section of the (i+5)th scan signal do not overlap,
The gate driving circuit performs the plurality of scan operations during a period in which the turn-on level voltage section of the (i+4)th scan signal and the turn-on level voltage section of the (i+5)th scan signal do not overlap. Applying two or more scan signals having turn-on level voltage sections at the same timing to two or more scan signal lines connected to two or more subpixel rows to be supplied with fake data voltages among the signal lines,
A display device wherein the maximum voltage value of the turn-on level voltage section of the (i+5)th scan signal is higher than the maximum voltage value of the turn-on level voltage section of the (i+4)th scan signal.
According to paragraph 1,
A display device in which the temporal length of the turn-on level voltage section of the (i+5)th scan signal is shorter than the temporal length of the turn-on level voltage section of the (i+4)th scan signal.
According to paragraph 2,
The start point of the turn-on level voltage section of the (i+6)th scan signal corresponds to the start time of the turn-on level voltage section of the (i+5)th scan signal,
A display device wherein the temporal length of the turn-on level voltage section of the (i+6)th scan signal is longer than the temporal length of the turn-on level voltage section of the (i+5)th scan signal.
According to paragraph 3,
A display device wherein the maximum voltage value of the turn-on level voltage section of the (i+6)th scan signal corresponds to the maximum voltage value of the turn-on level voltage section of the (i+5)th scan signal.
According to paragraph 1,
The maximum voltage value of the turn-on level voltage section of the (i+5)th scan signal is a voltage boosted by a preset boost voltage than the maximum voltage value of the turn-on level voltage section of the (i+4)th scan signal. It is a value,
The turn-on level voltage section of the (i+5)th scan signal is,
A first turn-on level voltage section having a boost turn-on level voltage obtained by adding the reference turn-on level voltage and the boost voltage;
Includes a second turn-on level voltage section having the reference turn-on level voltage,
The reference turn-on level voltage corresponds to the maximum voltage value of the turn-on level voltage section of the (i+4)th scan signal. According to clause 5,
The turn-on level voltage section of the (i+6)th scan signal is,
a first turn-on level voltage section having the boost turn-on level voltage obtained by adding the reference turn-on level voltage and the boost voltage;
Includes a second turn-on level voltage section having the reference turn-on level voltage,
The reference turn-on level voltage corresponds to the maximum voltage value of the turn-on level voltage section of the (i+4)th scan signal,
The start time of the turn-on level voltage section of the (i+6)th scan signal corresponds to the start time of the turn-on level voltage section of the (i+5)th scan signal,
A display device wherein the temporal length of the turn-on level voltage section of the (i+6)th scan signal is longer than the temporal length of the first turn-on level voltage section of the (i+5)th scan signal.
According to clause 6,
The temporal length of the first turn-on level voltage section of the (i+6)th scan signal corresponds to the temporal length of the first turn-on level voltage section of the (i+5)th scan signal,
A display device wherein the temporal length of the second turn-on level voltage section of the (i+6)th scan signal is longer than the temporal length of the second turn-on level voltage section of the (i+5)th scan signal.
According to clause 6,
The temporal length of the first turn-on level voltage section of the (i+6)th scan signal is longer than the temporal length of the first turn-on level voltage section of the (i+5)th scan signal,
The temporal length of the second turn-on level voltage section of the (i+6)th scan signal corresponds to the temporal length of the second turn-on level voltage section of the (i+5)th scan signal.
According to paragraph 1,
The data driving circuit is,
During the turn-on level voltage section of the (i+1)th to (i+6)th scan signal, the real subpixels included in the (i+1)th to (i+6)th subpixel rows Supply image data voltages corresponding to the image,
During a period in which the turn-on level voltage section of the (i+4)th scan signal and the turn-on level voltage section of the (i+5)th scan signal do not overlap, two or more sub-pixel rows of the plurality of subpixel rows Supplying a fake data voltage corresponding to a fake image unrelated to the real image to subpixels included in a pixel row,
The two or more subpixel rows to which the fake data voltage is supplied correspond to the two or more scan signal lines to which the two or more scan signals having a turn-on level voltage section are applied at the same timing.
According to clause 9,
The real image is an image that can be perceived by the naked eye, the fake image is an image that cannot be perceived by the human eye, and the fake data voltage is a black data voltage, a low-gray data voltage, or a monochromatic data voltage.
According to paragraph 1,
Each of the plurality of subpixels further includes a sense transistor that controls the connection between a reference line and a second node of the driving transistor according to a sense signal supplied through a sense signal line,
The display device wherein the sense signal and the scan signal have the same signal waveform, or the sense signal and the scan signal have a turn-on level voltage section of the same length.
According to paragraph 1,
A display device in which the turn-on level voltage section of the (i+4)th scan signal is longer than 1 horizontal time.
It includes a plurality of subpixels connected to a plurality of data lines and a plurality of scan signal lines, each of the plurality of subpixels having a light emitting element, a driving transistor for driving the light emitting element, and a scan signal supplied through the scan signal line. a display panel including a scan transistor that controls a connection between the data line and a first node of the driving transistor according to a signal, and a capacitor connected between a first node and a second node of the driving transistor;
a data driving circuit for driving the plurality of data lines; and
It includes a gate driving circuit for driving the plurality of scan signal lines,
The plurality of subpixels are arranged in a matrix form to form a plurality of subpixel rows,
The data driving circuit is,
Supplying an image data voltage for displaying an image using subpixels arranged in one subpixel row among the plurality of subpixel rows immediately before a first period within one frame time,
During the first period, supplying a fake data voltage for displaying a fake image different from the image to subpixels arranged in two or more subpixel rows among the plurality of subpixel rows,
The gate driving circuit is,
Before the first period, output first scan signals having a reference turn-on level voltage,
Immediately after the first period, output a second scan signal having a turn-on level voltage higher than the reference turn-on level voltage,
The turn-on level voltage sections of the first scan signals overlap each other,
A display device in which a turn-on level voltage section of the first scan signal immediately before the first period and a turn-on level voltage section of the second scan signal immediately after the first period do not overlap.
a gate voltage supply circuit that outputs a reference turn-on level voltage during a first driving period and outputs a boost turn-on level voltage different from the reference turn-on level voltage during a second driving period; and
During the first driving period, first scan signals sequentially having turn-on level voltage sections corresponding to the reference turn-on level voltage are output to first scan signal lines among a plurality of scan signal lines, and the second During the driving period, two or more second scan signals having a turn-on level voltage section due to the boost turn-on level voltage at the same timing are transmitted to two or more subpixel rows to be supplied with a fake data voltage among the plurality of scan signal lines. It includes a scan signal output circuit that outputs to two or more connected second scan signal lines,
Turn-on level voltage sections of the first scan signals during the first driving period overlap with each other,
The turn-on level voltage section of the first scan signals during the first driving period and the turn-on level voltage section of the two or more second scan signals during the second driving period do not overlap, and the second driving period The boost turn-on level voltage in the turn-on level voltage section of the two or more second scan signals during the period is the boost turn-on level voltage in the turn-on level voltage section of the first scan signals during the first driving period. Gate driving circuit higher than the reference turn-on level voltage.
According to clause 14,
The temporal length of the turn-on level voltage section of the second scan signal during the second driving period is shorter than the temporal length of the turn-on level voltage section of the first scan signals during the first driving period. driving circuit.
According to clause 14,
After the first driving period and the second driving period, a real image is displayed on the display panel,
A gate driving circuit wherein a fake image different from the real image is displayed on the display panel between the first driving period and the second driving period.
A display panel including a plurality of subpixels connected to a plurality of data lines and a plurality of scan signal lines, a data driving circuit for driving the plurality of data lines, and a gate driving circuit for driving the plurality of scan signal lines. In a method of driving a display device comprising:
A first step of sequentially outputting first scan signals having sequential turn-on level voltage sections based on a reference turn-on level voltage to first scan signal lines during a first driving period; and
During a second driving period, a second step of outputting a second scan signal having a turn-on level voltage section due to a boost turn-on level voltage different from the reference turn-on level voltage to a second scan signal line; ,
Turn-on level voltage sections of the first scan signals during the first driving period overlap with each other,
The turn-on level voltage section of the first scan signals during the first driving period and the turn-on level voltage section of the second scan signals during the second driving period do not overlap,
After the first driving period and after the second driving period, a real image is displayed on the display panel, and between the first driving period and the second driving period, a fake image different from the real image is displayed on the display panel. become,
The boost turn-on level voltage in the turn-on level voltage section of the second scan signal during the second driving period is the turn-on level voltage section of the first scan signals during the first driving period. A method of driving a display device higher than the reference turn-on level voltage of.
delete According to clause 17,
The temporal length of the turn-on level voltage section of the second scan signal during the second driving period is shorter than the temporal length of the turn-on level voltage section of the first scan signals during the first driving period. How to operate the device.
According to clause 17,
Between the first step and the second step,
A method of driving a display device further comprising a third step of simultaneously outputting scan signals having turn-on level voltage sections based on the reference turn-on level voltage at the same timing to two or more scan signal lines.

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