KR20230001881A - Display apparatus - Google Patents

Abstract

According to an embodiment of the present invention, a display apparatus comprises a display panel including a plurality of pixels including a light emitting element and a pixel circuit. The plurality of pixels include a plurality of sub-pixels emitting light of different colors, each of the plurality of subpixels is operated by being divided into first to third periods according to at least one of a first scan signal, a second scan signal, and an EM signal, the second scan signal is a gate-on voltage during the first period, the first scan signal and the second scan signal are the gate-on voltage during the second period, and the EM signal is the gate-on voltage during the third period. The light emitting element emits light, and the pixel circuit is operated by being divided into a plurality of bands with different highest target luminances, and the duty ratio of the EM signal can be driven differently so that the third period is variable in at least one of the plurality of bands. Accordingly, since a light emission period longer than the minimum period, during which color change is recognized, is ensured, color change can be minimized even if the duty ratio of the EM signal is varied, thereby increasing image quality.

Description

Display device {DISPLAY APPARATUS}

The present specification relates to a display device, and more particularly, to a display device in which image quality is improved by securing a sufficient charging time of pixels.

BACKGROUND OF THE INVENTION [0002] Video display devices, which implement various information on a screen, are a core technology of the information and communication era, and are developing toward thinner, lighter, portable, and high performance. Accordingly, light and thin display devices that can be manufactured are in the limelight. This display device is a self-luminous device and is advantageous in terms of power consumption due to low voltage driving, as well as high-speed response speed, high luminous efficiency, excellent viewing angle and contrast ratio, and is being studied as a next-generation display. This display device implements an image through a plurality of sub-pixels arranged in a matrix form. Each of the plurality of subpixels includes a pixel circuit such as a light emitting element and a plurality of transistors independently driving the light emitting element.

Specific examples of such a flat panel display include a liquid crystal display (LCD), a quantum dot display (QD), a field emission display (FED), and an organic light emitting display. devices (Organic Light Emitting Diode: OLED); and the like. Among them, the organic light emitting display device, which does not require a separate light source and is in the limelight as a means for miniaturizing the device and displaying vivid colors, has a fast response speed by using an organic light emitting diode (OLED) that emits light by itself. , contrast ratio, luminous efficiency, luminance and viewing angle are large.

Among such display devices, an organic light emitting diode display including an organic light emitting diode displays an image based on light generated from light emitting elements in pixels, and thus has various advantages, but image quality deterioration such as color coordinate change during driving This happens occasionally. This may be a factor deteriorating basic satisfaction with high image quality of a display device including organic light emitting diodes.

Accordingly, various driving techniques are being developed to solve image abnormalities, and driving conditions of pixel circuits that control light emission of pixels are important in order to improve image quality. For example, light emitting performance may be improved by controlling pixels to have a sufficient charging time.

The present specification relates to a display device including a pixel circuit in which image quality such as color change is improved by ensuring sufficient charging time for pixels to be charged in order to solve the above-mentioned problem.

A display device according to an embodiment of the present specification includes a display panel provided with a plurality of pixels including a light emitting element and a pixel circuit, wherein the plurality of pixels include a plurality of sub-pixels emitting light of different colors; The plurality of sub-pixels are driven in first to third periods according to at least one of the first scan signal, the second scan signal, and the EM signal, the second scan signal is a gate-on voltage during the first period, and the second scan signal is a gate-on voltage during the first period. During the period, the first scan signal and the second scan signal are gate-on voltages, and during the third period, the EM signal is gate-on voltage, the light emitting element emits light, and the pixel circuit is divided into a plurality of bands having different uppermost target luminances and driven. , the duty ratio of the EM signal may be driven differently so that the third period is variable in at least one of the plurality of bands.

In addition to the technical problems of the present specification mentioned above, other features and advantages of the present specification will be described below, or will be clearly understood by those skilled in the art from such description and description.

According to the embodiments of the present specification, by ensuring a light emission period longer than the minimum period in which color change is recognized, color change can be minimized even when the duty ratio of the EM signal is varied, thereby improving image quality.

In addition, since optical compensation is performed by adjusting the dimming level by varying the duty ratio of the EM signal in some bands, there is an effect of reducing process time (Tact Time).

Effects according to this specification are not limited by the contents exemplified above, and more various effects are included in this specification.

1 is a block diagram of a display device according to an exemplary embodiment of the present specification.
2 is a circuit diagram illustrating a pixel circuit of a display device according to an exemplary embodiment of the present specification.
3A to 5B are diagrams showing the operation of the pixel circuit shown in FIG. 2 in a display driving mode step by step.
6 is a diagram illustrating dimming levels for each band of pixels in a display device according to an exemplary embodiment of the present specification.
7A to 7C are diagrams illustrating light emission levels according to duty ratios of EM signals in a display device according to an exemplary embodiment of the present specification.
8 is a diagram illustrating a dimming level adjusting method for each band of a display device according to an exemplary embodiment of the present specification.
9A to 9C are diagrams illustrating driving timings of pixel circuits in a display device according to an exemplary embodiment of the present specification.
10 is a diagram of color coordinates in a fourth band of a display device according to an embodiment of the present specification.
11 is a diagram illustrating a dimming level adjusting method for each band of a display device according to another exemplary embodiment of the present specification.

Advantages and features of the present specification, and methods of achieving them will become clear with reference to examples described later in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the examples disclosed below and will be implemented in a variety of different forms, and only the examples in the present specification make the disclosure of the present specification complete, and common in the art to which the invention of the present specification belongs. It is provided to completely inform those who have knowledge of the scope of the invention, and the invention of this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining an example of this specification are illustrative and are not limited to those shown in this specification. Like reference numbers designate like elements throughout the specification. In addition, in describing the examples of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

When “includes,” “has,” “consists of,” etc. mentioned in this specification is used, other parts may be added unless “only” is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as “on,” “upper,” “lower,” “next to,” etc., “immediately” or “directly” Unless used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, “after,” “followed by,” “next,” “before,” etc. It can also include cases where it is not consecutive.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

The term “at least one” should be understood to include all conceivable combinations from one or more related items. For example, “at least one of the first, second, and third items” means not only the first, second, and third items, but also two of the first, second, and third items. It may mean a combination of all items that can be presented from one or more.

Each feature of the various examples of the present specification can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each example can be implemented independently of each other or can be implemented together in an association relationship. .

Hereinafter, an example of a display device according to an embodiment of the present specification will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, since the scales of the components shown in the accompanying drawings have different scales from actual ones for convenience of explanation, they are not limited to the scales shown in the drawings.

Hereinafter, various embodiments of the present specification will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a display device according to an exemplary embodiment of the present specification.

Referring to FIG. 1 , a display device according to an exemplary embodiment of the present specification includes a display panel 100, display drivers 110 and 140 for writing pixel data of an input image into pixels of the display panel 100, and a display driver. A controller 130 for controlling 110 and 140 and a power supply unit 150 generating power necessary for driving the display panel 100 are included.

The display panel 100 has a horizontal length in the X-axis direction, a vertical length in the Y-axis direction, and a thickness. The display panel 100 includes a pixel array AA that displays an input image on a screen. The pixel array AA is defined by a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, and the data lines DL and the gate lines GL. It includes pixels arranged in a matrix form.

Each of the pixels may be divided into red sub-pixels, green sub-pixels, and blue sub-pixels 101 to implement color of an image reproduced on the display panel 100 . Each of the pixels may further include a white sub-pixel. Each of the subpixels 101 includes a pixel circuit that drives the light emitting element EL. Also, the sub-pixels 101 may include color filters, but may be omitted. Hereinafter, a pixel may be interpreted as the same meaning as a sub-pixel.

The pixel array AA includes a plurality of pixel lines L1 to Ln. The pixel line includes pixels disposed on one line disposed along a row line direction (or X-axis direction). When the resolution of the pixel array AA is m*n, the pixel array AA includes n pixel lines L1 to L(N). Pixels disposed on one pixel line share gate lines and are connected to different data lines DL. The sub-pixels 101 disposed in the vertical direction along the column direction (or the Y-axis direction) share the same data line.

Touch sensors may be disposed on the screen of the display panel 100 . The touch sensors are on-cell type or add-on type, and are arranged on the screen of a display panel or in-cell type touch sensors embedded in a pixel array (AA). can be implemented as

The display device of the present specification may reproduce an input image by writing pixel data of the input image to the pixels of the display panel 100 in the display driving mode. In addition, the display device of the present specification may compensate for deterioration of the subpixels by sensing electrical characteristics of the subpixels through a sensing path connected to each of the subpixels in a sensing mode and adding or multiplying the sensing result to pixel data. For example, the controller 130 may compensate for deterioration data of a subpixel by modulating pixel data based on sensing data received from the data driver 110 in a sensing mode.

The display panel 100 may be implemented as a flexible display panel in which pixels are disposed on a flexible substrate such as a plastic substrate or a metal substrate. In the flexible display, the size and shape of the screen can be changed by winding, folding, or bending the flexible display panel. The flexible display may include a slideable display, a rollable display, a bendable display, a foldable display, and the like.

The data driver 110 converts the pixel data of the input image received as a digital signal from the controller 130 into a gamma compensation voltage using a digital-to-analog converter (hereinafter referred to as “DAC”) to obtain a data voltage. Outputs (Vdata). The data driver 110 may include a voltage divider circuit that outputs a gamma compensation voltage. The voltage divider circuit divides the gamma reference voltage from the power supply unit 150 to generate a gamma compensation voltage for each gray level, and provides the generated gamma compensation voltage to the DAC.

Data voltages output from the data driver 110 may be supplied to the data lines DL of the display panel 100 through a de-multiplexer (not shown). The demultiplexer divides and distributes the data voltage Vdata output through each channel of the data driver 110 to the plurality of data lines DL. Due to the demultiplexer, the number of channels of the data driver 110 may be reduced. The demultiplexer may be omitted.

The gate driver 140 may be implemented as a gate in panel (GIP) circuit formed directly on the bezel area (Bezel, BZ) of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 140 outputs gate signals to the gate lines GL under the control of the controller 130 . The gate driver 140 may sequentially supply the gate signals to the gate lines GL by shifting the gate signals using a shift register. The voltage of the gate signal swings between the gate off voltage and the gate on voltage. The gate signal may include a scan signal and an emission control signal (hereinafter, referred to as “EM signal”) for controlling emission time of pixels. The gate lines may be divided into scan lines to which scan signals are applied and EM lines (or emission control lines) to which EM signals are applied. A gate signal applied to the gate signals may be generated in the form of a pulse swinging between a gate-on voltage and a gate-off voltage.

The gate driver 140 may be disposed on each of the left and right bezels of the display panel 100 to supply gate signals to the gate lines GL in a double feeding method. In the double feeding method, the gate drivers 140 on both sides are synchronized so that gate signals can be simultaneously applied from both ends of one gate line. In another embodiment, the gate driver 140 may be disposed on one of the left and right bezels of the display panel 100 to supply gate signals to the gate lines GL in a single feeding method.

The gate driver 140 may include a first gate driver 141 and a second gate driver 142 . The first gate driver 141 outputs a scan signal and shifts the scan signal according to the shift clock. The second gate driver 142 outputs pulses of the EM signal and shifts the pulses of the EM signal according to the shift clock. In the case of a model without a bezel, at least some of the switch elements constituting the first and second gate drivers 121 and 122 may be distributedly disposed within the pixel array AA.

Two or more different scan signals may be applied to the pixel circuit at least one of a rising time, a falling time, and a pulse width. In this case, the first gate driver 141 may use two or more shift registers to output different scan signals to the pixel circuit through a plurality of gate lines. For example, the first gate driver 141 may include a first shift register that outputs a first scan signal and supplies it to a first gate line, and a second shift register that outputs a second scan signal and supplies it to a second gate line. can include

The display panel drivers 110 and 140 reproduce the input image on the screen of the display panel 100 by writing pixel data of the input image into the sub-pixels 101 . The display panel driver includes a data driver 110 and a gate driver 140 . The display panel drivers 110 and 140 may further include a demultiplexer 120 disposed between the data driver 110 and the data lines DL.

The data driver 110 converts the pixel data of the input image received as a digital signal from the controller 130 into a gamma compensation voltage using a digital-to-analog converter (hereinafter referred to as “DAC”) to obtain a data voltage. Outputs (Vdata). The data driver 110 may include a voltage divider circuit that outputs a gamma compensation voltage. The voltage divider circuit divides the gamma reference voltage from the power supply unit 150 to generate a gamma compensation voltage for each gray level, and provides the generated gamma compensation voltage to the DAC. Data voltages output from the data driver 110 may be supplied to the data lines DL of the display panel 100 through the demultiplexer 120 .

The demultiplexer 120 time-divides and distributes the data voltage Vdata output through each of the channels of the data driver 110 to the plurality of data lines DL. The number of channels of the data driver 110 may be reduced due to the demultiplexer 120 . The demultiplexer 120 may be omitted. In this case, the channels of the data driver 110 are directly connected to the data lines DL.

The controller 130 receives pixel data of an input image and a timing signal synchronized with the pixel data from the host system. The timing signal includes a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a clock CLK, and a data enable signal DE. One cycle of the vertical synchronization signal Vsync is one frame period. One period of the horizontal synchronization signal Hsync and the data enable signal DE is one horizontal period (1H). A pulse of the data enable signal DE is synchronized with 1-line data to be written in pixels of 1-pixel line. Since the frame period and the horizontal period can be known by counting the data enable signal DE, the vertical sync signal Vsync and the horizontal sync signal Hsync can be omitted.

The controller 130 transmits pixel data of the input image to the data driver 110 . The controller 130 includes a data timing control signal for controlling the operation timing of the data driver 110 based on the timing signals Vsync, Hsync, and DE received from the host system, and the operation timing of the mode switching unit 120 and the demultiplexer. A switch control signal for controlling and a gate timing control signal for controlling the operation timing of the gate driver 140 are generated. The gate timing control signal may include a start pulse and a shift clock.

The controller 130 multiplies the input frame frequency by i (i is a positive integer greater than 0) to control the operation timing of the display drivers 110 and 140 with the frame frequency of the input frame frequency x iHz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase-Alternating Line (PAL) method. The controller 130 may lower the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower a refresh rate of pixels in the low power consumption mode.

The voltage level of the gate timing control signal output from the controller 130 may be converted into a gate-off voltage and a gate-on voltage through a level shifter 160 (not shown) and supplied to the gate driver 140. . The level shifter 160 may convert a first low potential logic level of the gate timing control signal into a gate-on voltage and convert a second low potential logic level of the gate timing control signal into a gate-off voltage.

The host system may include a main circuit board of a television (TV) system, a personal computer (PC), a vehicle system, a navigation system, a mobile system, and a wearable system. In a mobile system or a wearable system, the controller 130, the data driver 110, and the power supply 150 may be integrated into one drive integrated circuit (Drive IC).

The power supply unit 150 may include a charge pump, a regulator, a buck converter, a boost converter, a programmable gamma IC (P-GMA IC), and the like. . The power supply unit 150 generates power necessary for driving the display driver and the display panel 100 by adjusting a DC input voltage from the host system. The power supply unit 150 may output DC voltages such as a gamma reference voltage, a first gate voltage, a second gate voltage, a high potential power supply voltage ELVDD, a low potential power supply voltage ELVSS, and a reference voltage Vref. The gamma reference voltage is supplied to the data driver 110 . The high potential power supply voltage ELVDD, the low potential power supply voltage ELVSS, and the reference voltage Vref are commonly supplied to the pixel circuits through power lines. The high potential power supply voltage ELVDD is set to a voltage higher than the low potential power supply voltage ELVSS and the reference voltage Vref. The power supply unit 150 may be implemented as a power management IC (PMIC).

The first and second gate voltages are supplied to the level shifter 160 and the gate driver 140 . The first gate voltage may be higher than the second gate voltage. In the following embodiments, the first gate voltage is described as a gate-off voltage (VGH) and the second gate voltage is described as a gate-on voltage (VGL), but it should be noted that the invention is not limited by these terms.

The display device 100 according to the exemplary embodiment of the present specification is an organic light emitting display device, and each of the subpixels 101 includes a light emitting element EL, a transistor TFT for driving the light emitting element EL, and the like. It is composed of a pixel circuit including circuit elements of The type and number of circuit elements constituting each of the sub-pixels 101 may be variously determined according to a provided function and a design method.

2 is a circuit diagram illustrating a pixel circuit of a display device according to an exemplary embodiment of the present specification. The pixel circuit of this specification is not limited to FIG. 2 .

Referring to FIG. 2 , a light emitting element EL, a plurality of transistors T1 to T5 and DT, and a capacitor Cst are included. The plurality of transistors T1 to T5 and DT include switch elements T1 and T5 and a driving element DT. The plurality of transistors T1 to T5 and DT may be implemented as NMOS transistors or PMOS transistors. However, it is not limited thereto, and may be implemented as a complementary metal-oxide-semiconductor (CMOS) transistor. Also, the plurality of transistors T1 to T5 and DT may be composed of low-temperature polycrystalline silicon transistors. However, it is not limited thereto, and at least one may be composed of an oxide thin film transistor.

In the display driving mode, the driving period of each of the subpixels 101 may be divided into an initialization period Ti, a sampling period Ts, and an emission period Tem.

The anode electrode of the light emitting element EL is connected to the fourth and fifth switch elements T4 and T5 through the fourth node n4. A cathode electrode of the light emitting element EL is connected to the low potential power supply voltage ELVSS. The driving element DT drives the light emitting element EL by controlling the amount of current flowing to the light emitting element EL according to the gate-source voltage Vgs. A current flowing through the light emitting element EL may be switched by the fourth switch element T4.

The capacitor Cst is connected between the first node n1 and the second node n2. The first node n1 is connected to the second electrode of the first switch element T1, the first electrode of the third switch element T3, and the first electrode of the capacitor Cst. The second node n2 is connected to the second electrode of the capacitor Cst, the gate electrode of the driving element DT, and the first electrode of the second switch element T2. The compensated data voltage Vdata equal to the threshold voltage Vth of the driving element DT is charged in the capacitor Cst.

The first switch element T1 supplies the data voltage Vdata to the first node n1 in response to the first scan signal SCAN1(N). The first switch element T1 includes a gate electrode connected to the first gate line GL1, a first electrode connected to the data line DL, and a second electrode connected to the first node n1.

The first scan signal SCAN1(N) is supplied to the pixels through the first gate line GL1. The first scan signal SCAN1(N) is generated as a gate-on voltage VGL pulse. A pulse of the first scan signal SCAN1(N) defines the sampling period Ts. The pulse width of the first scan signal SCAN1(N) may be set to approximately one horizontal period (1H). The first scan signal SCAN1(N) changes to the gate-on voltage VGL later than the second scan signal SCAN2(N), and the gate-off voltage VGH simultaneously with the second scan signal SCAN2(N). can change to The pulse width of the first scan signal SCAN1(N) is set smaller than that of the second scan signal SCAN2(N). During the initialization period Ti and the emission period Tem, the voltage of the first gate line GL1 maintains the gate-off voltage VGH.

The second switch element T2 connects the gate electrode of the driving element DT and the second electrode of the driving element DT in response to the second scan signal SCAN2(N) to make the driving element DT a diode ( diode) to operate. The second switch element T2 includes a gate electrode connected to the second gate line GL2, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The second switch element T2 may be formed of a low-temperature polycrystalline silicon transistor. However, it is not limited thereto, and may be composed of an oxide thin film transistor.

The second scan signal SCAN2(N) is supplied to the pixels through the second gate line GL2. The second scan signal SCAN2(N) may be generated as the gate-on voltage VGL. The second scan signal SCAN2(N) defines an initialization period Ti and a sampling period Ts. During the emission period Tem, the voltage of the second gate line GL2 maintains the gate-off voltage VGH.

The third switch element T3 supplies a predetermined reference voltage Vref to the first node n1 in response to the gate-on voltage VEL applied to the third gate line GL3. The reference voltage Vref is supplied to the pixels through the reference voltage line REFL in the display driving mode. The third switch element T3 includes a gate electrode connected to the third gate line GL3 to which the EM signal EM(N) is applied, a first electrode connected to the first node n1, and a reference voltage line REFL. It includes a second electrode connected to. In the initialization period Ti, the capacitor Cst is initialized by being discharged up to the reference voltage Vref.

A pulse of the EM signal EM(N) is generated with a gate off voltage VEH. The switch elements T3 and T4 controlled according to the voltage of the EM signal EM(N) form a current path between the first node n1 and the reference voltage line REFL during the sampling period Ts. is blocked, and a current path between the high potential power supply voltage ELVDD and the light emitting element EL is blocked.

The EM signal EM(N) is inverted to the gate-off voltage VGH when the first scan signal SCAN1(N) is inverted to the gate-on voltage VGL, and the first and second scan signals SCAN1, SCAN2) may be inverted to the gate-off voltage (VGH) and then inverted to the gate-on voltage (VGL). In order to accurately express the luminance of a lower gray level or lower gray level, the EM signal EM(N) has a gate-on voltage VGL and a gate-off voltage VGH at a predetermined duty ratio during the light emission period Tem. ) can be swing between.

The fourth switch element T4 switches the current path of the light emitting element EL in response to the EM signal EM(N). A gate electrode of the fourth switch element T4 is connected to the third gate line GL3 to which the EM signal EM(N) is applied. The first electrode of the fourth switch element T4 is connected to the third node n3, and the second electrode of the fourth switch element T4 is connected to the fourth node n4.

The fifth switch element T5 is turned on according to the gate-on voltage VGL of the second scan signal SCAN2(N) and applied to the fourth node n4 during the initialization period Ti and the sampling period Ts. Supply the reference voltage (Vref). During the initialization period Ti and the sampling period Ts, the anode voltage of the light emitting element EL is discharged to the reference voltage Vref. At this time, the light emitting element EL does not emit light because the voltage between the anode and the cathode is smaller than its threshold voltage. The fifth switch element T5 includes a gate electrode connected to the second gate line GL2, a first electrode connected to the reference voltage line REFL, and a second electrode connected to the fourth node n4.

The driving element DT includes a gate electrode connected to the second node n2, a first electrode connected to the power line PL to which the high potential power supply voltage ELVDD is applied, and a second electrode connected to the third node n3. includes

3A to 3B are diagrams showing the operation of the pixel circuit shown in FIG. 2 in a display driving mode step by step. 3A, 4A, and 5A are circuit diagrams showing the flow of current flowing through a pixel circuit step by step. 'X' in FIGS. 3A, 4A, and 5A represents a transistor in an off state. 3B, 4B, and 5B are waveform diagrams illustrating a method of driving a pixel circuit step by step.

Referring to FIGS. 3A and 3B , the voltages of the second and third gate lines GL2 and GL3 in the initialization period Ti are gate-on voltages VGL. Accordingly, the first scan signal SCAN(N) is applied as the gate-on voltage VGL.

The second to fifth switch elements T2 to T5 are turned on during the initialization period Ti to set the first node n1, second node n2, and fourth node n4 to the reference voltage Vref. discharge with

During the initialization period Tini, the driving element DT may be turned on. In the initialization period Ti, the capacitor Cst, the gate voltage of the driving element DT, and the anode voltage of the light emitting element EL are initialized to the reference voltage Vref.

Referring to FIGS. 4A and 4B , the voltages of the first and second gate lines GL1 and GL2 in the sampling period Ts are gate-on voltages VGL. Accordingly, the first scan signal SCAN1(N) and the second scan signal SCAN2(N) are applied as the gate-on voltage VGL.

The first, second, and fifth switch elements T1 , T2 , and T5 and the driving element DT are turned on during the sampling period Ts. At this time, the data voltage Vdata is applied to the first node n1, and the voltage of the second node n2 changes to ELVDD+Vth. Here, Vth is the threshold voltage of the driving element DT. As a result, the threshold voltage Vth of the driving element DT is sensed during the sampling period Ts and the second node n2 is charged. During the sampling period Ts, the capacitor Cst is charged with the data voltage Vdata obtained by compensating for the threshold voltage Vth of the driving element DT.

Referring to FIGS. 5A and 5B , the voltage of the third gate line GL3 in the light emitting period Tem is the gate-on voltage VEL. Accordingly, the EM signal EM(N) is applied as the gate-on voltage VEL.

The third and fourth switch elements T3 and T4 and the driving element DT are turned on during the light emitting period Tem. At this time, the voltage of the first node n1 changes to the reference voltage Vref, and the voltage of the second node n2 changes to Vref-Vdata+ELVDD+Vth.

During the light emitting period Tem, current flows through the driving element DT to the light emitting element EL so that the light emitting element EL may emit light. The current flowing through the light emitting element EL is controlled according to the gate-source voltage Vgs of the driving element DT. The gate-to-source voltage Vgs of the driving element DT is Vgs = Vref-Vdata + Vth during the light emission period Tem.

6 is a diagram illustrating dimming levels for each band of pixels in a display device according to an exemplary embodiment of the present specification.

Referring to FIG. 6 , the display panel 100 may include several bands (Band1, Band2, Band3, and Band4) to differently apply the target luminance Lv according to the operating environment. The bands Band1, Band2, Band3, and Band4 may be reference or driving modes for adjusting the dimming level. For example, the first band Band1 may be a setting for a situation requiring the highest maximum target luminance Lv according to ambient illumination in daytime sunlight or a driving mode corresponding thereto. The second band Band2 may be set under shade during the daytime or may be a driving mode corresponding thereto. The third band Band2 may be a setting for a cloudy day or a driving mode corresponding thereto. The fourth band Band4 may be set in a night environment or a driving mode corresponding thereto. In addition, bands may be further subdivided and classified according to various use environments and applications.

In each band (Band1, Band2, Band3, and Band4), the dimming level can be varied to adjust the luminance step in a specific gray level. In addition, the target luminance Lv may be set to have the same number of luminance steps in each band (Band1, Band2, Band3, and Band4). For example, a difference between the target luminance Lv of the first band Band1 and the target luminance Lv of the second band Band2 may have a difference of 256 steps.

A dimming level for controlling luminance may vary from 0% to 100%. Even in the same gradation, the dimming level is different according to the band, and accordingly, the expressed luminance may be different. For example, the maximum target luminance Lv of the first band Band1 may have a dimming level of 100%.

In this case, the dimming level may be adjusted by the data voltage applied to the pixel, or may be adjusted according to the duty ratio of the EM signal EM(N).

7A to 7C are diagrams illustrating light emission levels according to duty ratios of EM signals in a display device according to an exemplary embodiment of the present specification.

7A to 7C , a plurality of pixels including a light emitting element EL and a pixel circuit are provided on the display panel 100, and the plurality of pixels include a plurality of sub-pixels emitting different colors. do. The light emitting element EL may emit light after the pixel is charged for a predetermined time through the pixel circuit.

Referring to FIG. 7A , each sub-pixel may be first to third sub-pixels emitting light of different colors. For example, the first subpixel may emit red light, the second subpixel may emit green light, and the third subpixel may emit blue light.

The first to third sub-pixels may require different charging times. For example, a first subpixel emitting red light may have a shorter charging time than a second subpixel emitting green light, and a second subpixel may have a shorter charging time than a third subpixel emitting blue light. there is.

In other words, each sub-pixel reaches a saturated state after being charged for a certain period of time, and the charging times at which the saturated state is reached may be different from each other. Accordingly, each sub-pixel may have a different degree of light emission according to a charging time.

Referring to FIG. 7B , it is shown that a plurality of sub-pixels emitting light of different colors are all charged in a saturated state and emit light.

A charging time of each sub-pixel may be determined by a duty ratio of an EM signal. In other words, when the duty ratio of the EM signal is sufficiently long, the sub-pixel is charged in a saturated state and can emit light.

Referring to FIG. 7C , it is shown that only some sub-pixels emit light because the charging time of the pixels is not sufficiently secured.

Among the first to third subpixels, the first subpixel may be charged before the second subpixel and the third subpixel. Therefore, when a sufficient charging time is not ensured, only the first sub-pixel emitting red light emits light, so that the pixel may be expressed reddish by a color change. In this case, as the period in which only the first subpixel is charged while the second subpixel and the third subpixel do not start charging increases, the reddish level may increase.

In FIGS. 7A to 7C , the structure of a pixel is shown in a general strip shape, but is not limited thereto, and any pixel structure such as a pentile shape or an RGBW pixel shape further having subpixels emitting white light is not limited thereto. The same can be applied to

8 is a diagram illustrating a dimming level adjusting method for each band of a display device according to an exemplary embodiment of the present specification.

Referring to FIG. 8 , a dimming level may be adjusted according to a data voltage applied to a pixel in at least one of a plurality of bands Band1, Band2, Band3, and Band4.

Among the plurality of bands (Band1, Band2, Band3, and Band4), the maximum target luminance (Lv) of any one band may be the same as the minimum target luminance (Lv) of another band. For example, the minimum target luminance Lv of the first band Band1 may be the maximum target luminance Lv of the second band Band2.

Since the first to third bands Band1, Band2, and Band3 have a relatively high target luminance Lv, a luminance change for each gray level may be large. In this case, since the luminance corresponds to the data voltage, the dimming level may be adjusted by varying the data voltage.

In the fourth band Band4, since the target luminance Lv is relatively low and the luminance change amount for each gray level is small, pixels may not be normally driven when the dimming level is adjusted through the data voltage. Accordingly, the dimming level in the fourth band Band4 may be adjusted through the duty ratio of the EM signal EM(N).

In other words, in the first to third bands Band1, Band2, and Band3, the duty ratio of the EM signal EM(N) is fixed, and the dimming level can be adjusted by varying the data voltage. In addition, in the fourth band Band4, the data voltage is fixed, and the dimming level can be adjusted by varying the duty ratio of the EM signal EM(N).

However, as shown in FIGS. 7A to 7C , a phenomenon in which only some sub-pixels emit light may occur depending on the charging time of the pixels. In other words, in the fourth band Band4, when the duty ratio of the EM signal EM(N) is excessively reduced regardless of the target luminance Lv, only the first sub-pixel is charged to the level of the Reddish phenomenon. this may increase Accordingly, the EM signal EM(N) for adjusting the dimming level in the fourth band Band4 may be set to have a minimum duty ratio K.

At this time, the minimum duty ratio (K) of the EM signal (EM(N)) is set to have a value of at least 10% or more, preferably 25% or more to prevent the Reddish phenomenon from occurring. However, it is not limited thereto, and may be set to a lower minimum duty ratio (K) when applied together with other means.

9A to 9C are diagrams illustrating driving timings of pixel circuits in a display device according to an exemplary embodiment of the present specification.

In FIG. 9A, the duty ratio of the EM signal EM(N) is 100%, in FIG. 9B, the duty ratio of the EM signal EM(N) is 50%, and in FIG. 9C, the EM signal EM(N) The duty ratio may be 25%.

Referring to FIGS. 9A to 9C , the light emitting period Tem of the light emitting element EL is determined according to the duty ratio of the EM signal EM(N). Since the voltage of the third gate line GL3 is the gate-on voltage VEL during the emission period Tem, the EM signal EM(N) is applied as the gate-on voltage VEL during the emission period Tem.

In other words, the light emitting element EL emits light while the EM signal EM(N) is applied as the gate-on voltage VEL, and the light emitting period Tem depends on the duty cycle of the EM signal EM(N). can be determined according to

For example, when the EM signal EM(N) has a duty ratio of 25%, the light emission period Tem is 1/4 of that when the EM signal EM(N) has a duty ratio of 100%. It only glows for a period of time.

Since the luminance of the pixel may correspond to the light emission period Tem, the luminance when the EM signal EM(N) has a duty ratio of 25% is obtained when the EM signal EM(N) has a duty ratio of 100% It may be lower than when you have it. That is, the dimming level can be adjusted by varying the duty ratio of the EM signal EM(N).

10 is a diagram of color coordinates in a fourth band of a display device according to an embodiment of the present specification.

Referring to FIG. 10 , color coordinates may change when the duty ratio of the EM signal EM(N) is changed. When the duty ratio of the EM signal EM(N) is very small, the charging time of the pixels is not sufficiently secured, and only some sub-pixels emit light, which causes color coordinates to fluctuate and a Reddish phenomenon to occur.

At this time, by applying the minimum duty ratio (K) of the EM signal (EM(N)) in the fourth band (Band4), it is possible to secure an emission period (Tem) longer than the minimum period during which color change is recognized. Therefore, even if the duty ratio of the EM signal EM(N) is varied, the amount of change in the color coordinates is within 0.1, so the color change can be minimized and image quality can be improved.

In addition, by fixing the data voltage of the fourth band Band4 to the minimum target luminance Lv of the third band Band3 and varying the duty ratio of the EM signal EM(N), the first to third bands Since optical compensation is performed only for (Band1, Band2, Band3), it has the effect of reducing the process time (Tact Time).

11 is a diagram illustrating a dimming level adjusting method for each band of a display device according to another exemplary embodiment of the present specification.

Referring to FIG. 11, in the first to third bands (Band1, Band2, Band3) and the fourth band (Band4), the duty ratio of the EM signal (EM(N)) is different from each other, and the data voltage is varied to dim. Levels can be adjusted.

In the first to third bands Band1, Band2, and Band3, a relatively high target luminance Lv may be obtained. Accordingly, the dimming level may be adjusted by fixing the duty ratio of the EM signal EM(N) to 100% and varying the data voltage.

The fourth band Band1 may have a relatively low target luminance Lv. Accordingly, the dimming level may be adjusted by fixing the duty ratio of the EM signal EM(N) to the minimum duty ratio K and varying the data voltage so as to secure the minimum charging time of the pixel.

At this time, the minimum duty ratio (K) of the EM signal (EM(N)) is set to have a value of at least 10% or more, preferably 25% or more to prevent the Reddish phenomenon from occurring. However, it is not limited thereto, and may be set to a lower minimum duty ratio (K) when applied together with other means.

In addition, since the first to third bands (Band1, Band2, Band3) and the fourth band (Band1) are driven with different duty ratios of the EM signal (EM(N)), that is, the first to third bands (Band1, Since the duty ratio of the EM signal (EM(N)) in Band2 and Band3 is different from the duty ratio of the EM signal (EM(N)) in the fourth band (Band1), the third band (Band3) and the fourth band (Band3) Data voltages may be discontinuous between bands Band4.

In other words, the fourth band (Band1) having a duty ratio of the EM signal (EM(N)) lower than the duty ratio of the EM signal (EM(N)) in the first to third bands (Band1, Band2, and Band3). In , the dimming level may be adjusted by varying the data voltage to express luminance for each gray level. At this time, since a different duty ratio of the EM signal (EM(N)) is applied when the band interval is changed between the third band (Band3) and the fourth band (Band4), the data voltage is applied so that a rapid luminance change is not recognized. It can be. Accordingly, the data voltage may be discontinuously changed between the third band Band3 and the fourth band Band4 .

In this way, by securing a minimum time for charging each sub-pixel so that only one of the first to third sub-pixels emitting light of different colors is charged and the color change phenomenon does not occur, the amount of change in color coordinates is 0.1 Within this range, it is possible to improve image quality by minimizing color change.

In the display device according to the exemplary embodiments of the present specification, “dimming control” may be performed by at least one of the data driver 110 and the gate driver 140 under the control of the controller 130, and accordingly, pixels or sub-units may be performed. Dimming control can be realized by driving the pixel 101 and adjusting its luminance.

A display device according to an embodiment of the present specification may be described as follows.

A display device according to an embodiment of the present specification includes a display panel provided with a plurality of pixels including a light emitting element and a pixel circuit, wherein the plurality of pixels include a plurality of sub-pixels emitting light of different colors; The plurality of sub-pixels are driven in first to third periods according to at least one of the first scan signal, the second scan signal, and the EM signal, the second scan signal is a gate-on voltage during the first period, and the second scan signal is a gate-on voltage during the first period. During the period, the first scan signal and the second scan signal are gate-on voltages, and during the third period, the EM signal is gate-on voltage, the light emitting element emits light, and the pixel circuit is divided into a plurality of bands having different uppermost target luminances and driven. , the duty ratio of the EM signal may be driven differently so that the third period is variable in at least one of the plurality of bands.

In the display device according to the exemplary embodiment of the present specification, a duty ratio of an EM signal in at least one of a plurality of bands may vary from K to 100%.

In the display device according to the exemplary embodiment of the present specification, the plurality of bands include first to fourth bands, and in at least one of the first to fourth bands, a dimming level is set according to the duty ratio of the EM signal or the size of the data voltage. can be adjusted

In the display device according to the exemplary embodiment of the present specification, in the fourth band, the duty ratio of the EM signal may be variable and the data voltage may be constant.

In the display device according to the exemplary embodiment of the present specification, the duty ratio of the EM signal may be constant and the data voltage may be variable in the first to third bands.

In the display device according to the exemplary embodiment of the present specification, the duty ratios of the EM signals in the first to third bands are the same, and the duty ratios of the EM signals in the fourth band are smaller than the duty ratios of the EM signals in the first to third bands. can

In the display device according to the exemplary embodiment of the present specification, the data voltage may be discontinuously varied between the third band and the fourth band.

In the display device according to the exemplary embodiment of the present specification, the plurality of subpixels include first to third subpixels, and the first to third subpixels may have different charging times.

In the display device according to the exemplary embodiment of the present specification, a charging time of the first subpixel may be shorter than a charging time of the second subpixel or the third subpixel.

In the display device according to the exemplary embodiment of the present specification, a variation amount of color coordinates according to a dimming level in a plurality of bands may be within 0.1.

In the display device according to the exemplary embodiment of the present specification, the pixel circuit includes a driving element, first to fifth switch elements, and a capacitor, the capacitor is positioned between the first node and the second node, and the driving element is connected to the third node. Controls the application of the driving voltage, the first switch element controls the electrical connection between the first node and the data line according to the first scan signal, and the second switch element controls the electrical connection between the second node and the data line according to the second scan signal Controls the electrical connection between the third nodes, the third switch element supplies a reference voltage to the first node according to the EM signal, and the fourth switch element electrically connects the third node and the fourth node according to the EM signal , and the fifth switch device may supply a reference voltage to the fourth node according to the second scan signal.

In the display device according to the exemplary embodiment of the present specification, the driving element or the first to fifth switch elements may be a low-temperature polycrystalline silicon transistor, or at least one of the driving element or the first to fifth switch elements may be an oxide thin film transistor.

In the display device according to the exemplary embodiment of the present specification, the driving element or the first to fifth switch elements may include any one of an NMOS transistor, a PMOS transistor, and a CMOS transistor.

In the display device according to the exemplary embodiment of the present specification, the light emitting element may emit light when an EM signal is a gate-on voltage pulse.

A display device according to an exemplary embodiment of the present specification includes a display panel having a plurality of pixels including a light emitting element and a pixel circuit, wherein the pixel circuit includes a capacitor connected between a first node and a second node, and a second node. A driving element including a connected gate electrode, a first electrode connected to a power supply line to which a high potential power supply voltage is applied, and a second electrode connected to a third node, an anode electrode connected to a fourth node, and a cathode electrode to which a low potential voltage is applied A light emitting element including a first switch element including a gate electrode connected to a first gate line to which a first scan signal is applied, a first electrode connected to a data line, and a second electrode connected to a first node, a second scan signal A second switch element including a gate electrode connected to a second gate line to be applied, a first electrode connected to a second node, and a second electrode connected to a third node, and a gate connected to a third gate line to which a pulse of an EM signal is applied A third switch element including an electrode, a first electrode connected to a first node, and a second electrode connected to a reference voltage line to which a predetermined reference voltage is applied, a gate electrode connected to a third gate line, and a first connected to a third node. A fifth switch element including an electrode and a second electrode connected to a fourth node, and a gate electrode connected to a second gate line, a first electrode connected to a reference voltage line, and a second electrode connected to a fourth node. A switch element may be included, and an EM signal applied to the third gate line may have a variable duty ratio.

The features, structures, effects, etc. described in the above-described examples of this specification are included in at least one example of this specification, and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. illustrated in at least one example in this specification can be combined or modified with respect to other examples by those skilled in the art to which this specification belongs. Therefore, contents related to these combinations and variations should be construed as being included in the scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this specification belongs that various substitutions, modifications, and changes are possible without departing from the technical details of the present specification. It will be clear to those who have knowledge of Therefore, the scope of the present specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present specification.

100: display panel
110: data driving unit
120: demultiplexer
130: controller
140: gate driver
150: power supply

Claims (15)

A display panel provided with a plurality of pixels including a light emitting element and a pixel circuit;
The plurality of pixels include a plurality of sub-pixels emitting light of different colors,
The plurality of sub-pixels are divided into first to third periods and driven according to at least one of a first scan signal, a second scan signal, and an EM signal;
During the first period, the second scan signal is a gate-on voltage;
During the second period, the first scan signal and the second scan signal are gate-on voltages;
During the third period, the EM signal is a gate-on voltage and the light emitting element emits light;
The pixel circuit is driven by dividing into a plurality of bands having different highest target luminance;
Driving the duty ratio of the EM signal differently so that the third period varies in at least one of the plurality of bands.
display device.
According to claim 1,
The display device of claim 1 , wherein a duty ratio of the EM signal in at least one of the plurality of bands varies from K to 100%.
According to claim 1,
The plurality of bands include first to fourth bands,
In at least one of the first to fourth bands, a dimming level is adjusted according to a duty ratio of the EM signal or a size of a data voltage.
According to claim 3,
In the fourth band,
wherein the duty ratio of the EM signal is variable and the data voltage is constant.
According to claim 3,
In the first to third bands,
The display device of claim 1 , wherein the duty ratio of the EM signal is constant and the data voltage is variable.
According to claim 3,
Duty ratios of the EM signals in the first to third bands are the same,
and a duty ratio of the EM signal in the fourth band is smaller than a duty ratio of the EM signal in the first to third bands.
According to claim 6,
The data voltage is discontinuously varied between the third band and the fourth band.
According to claim 1,
The plurality of sub-pixels include first to third sub-pixels,
The first to third sub-pixels have different charging times, respectively.
According to claim 8,
A charging time of the first subpixel is shorter than a charging time of the second subpixel or the third subpixel.
According to claim 1,
The display device according to claim 1 , wherein a variation of color coordinates according to a dimming level in the plurality of bands is within 0.1.
According to claim 1,
The pixel circuit includes a driving element, first to fifth switch elements, and a capacitor;
The capacitor is located between the first node and the second node,
The driving element controls the application of a high potential driving voltage to a third node;
The first switch element controls the electrical connection between the first node and the data line according to the first scan signal,
The second switch element controls the electrical connection between the second node and the third node according to the second scan signal,
The third switch element supplies a reference voltage to the first node according to the EM signal,
The fourth switch element controls the electrical connection between the third node and the fourth node according to the EM signal,
The fifth switch element supplies the reference voltage to the fourth node according to the second scan signal.
According to claim 11,
The driving element or the first to fifth switch elements is a low-temperature polycrystalline silicon transistor, or at least one of the driving element or the first to fifth switch elements is an oxide thin film transistor.
According to claim 11,
The display device, wherein the driving element or the first to fifth switch elements are composed of any one of an NMOS transistor, a PMOS transistor, and a CMOS transistor.
According to claim 11,
The light emitting element emits light when the EM signal is a gate-on voltage pulse.
A display panel provided with a plurality of pixels including a light emitting element and a pixel circuit;
The pixel circuit,
a capacitor connected between the first node and the second node;
a driving element including a gate electrode connected to the second node, a first electrode connected to a power line to which a high-potential power supply voltage is applied, and a second electrode connected to a third node;
a light emitting element including an anode electrode connected to the fourth node and a cathode electrode to which a low potential voltage is applied;
a first switch element including a gate electrode connected to a first gate line to which a first scan signal is applied, a first electrode connected to a data line, and a second electrode connected to the first node;
a second switch element including a gate electrode connected to a second gate line to which a second scan signal is applied, a first electrode connected to the second node, and a second electrode connected to the third node;
a third switch element including a gate electrode connected to a third gate line to which a pulse of an EM signal is applied, a first electrode connected to the first node, and a second electrode connected to a reference voltage line to which a predetermined reference voltage is applied;
a fourth switch element including a gate electrode connected to the third gate line, a first electrode connected to the third node, and a second electrode connected to the fourth node; and
A fifth switch element including a gate electrode connected to the second gate line, a first electrode connected to the reference voltage line, and a second electrode connected to the fourth node;
The EM signal applied to the third gate line has a variable duty ratio.

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