KR102593910B1 - Display Device - Google Patents

Abstract

The present invention relates to a display device, comprising: a data driver that outputs a data voltage through a plurality of output buffers; A demultiplexer sequentially connecting input nodes to multiple data lines; and a switch array that sequentially connects the output buffers of the data driver to the input nodes of the demultiplexer and changes the connection relationship between the output buffers and the input nodes of the demultiplexer on a frame period basis.

Description

Display Device {Display Device}

The present invention relates to a display device in which a demultiplexer (DEMUX) is disposed between channels of a data driver and data lines of a pixel array.

Various flat panel displays such as Liquid Crystal Display (LCD), Electroluminescence Display, Field Emission Display (FED), and Plasma Display Panel (PDP) are being developed. there is.

Electroluminescent displays are roughly divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage. Organic light emitting displays have OLEDs (Organic Light Emitting Diodes, also known as OLEDs) formed in each pixel. Organic light emitting displays not only have a fast response speed and excellent luminous efficiency, brightness, and viewing angle, but also produce black gradations. Because it can be expressed in complete black, the contrast ratio and color reproduction rate are excellent.

The display device includes a display panel on which a pixel array is arranged on a screen, and a display panel driving circuit for writing pixel data of an input image to pixels of the display panel. The display panel driving circuit includes a data driver that supplies data signals to the data lines of the pixel array, and a gate signal (or scan signal) that is synchronized with the data signal to sequentially supply the gate lines (or scan lines) of the pixel array. It may include a gate driver (or scan driver) that operates.

The voltage of the data signal (hereinafter referred to as “data voltage”) is output from each of the channels of the data driver. In order to reduce the number of channels of the data driver, a demultiplexer (DEMUX) may be placed between the channels of the data driver and the data lines of the pixel array.

In a conventional display device, differences in luminance may be visible between pixels. In particular, in organic light emitting diode displays, luminance differences can be seen even with small current differences, so the above luminance unevenness problem may be more noticeable.

The present invention provides a display device that can prevent differences in luminance between pixels.

A display device of the present invention includes a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of subpixels connected to the data lines and the gate lines are arranged; a data driver that outputs a data voltage through a plurality of output buffers; a demultiplexer sequentially connecting input nodes to the plurality of data lines; and a switch array that sequentially connects the output buffers of the data driver to the input nodes of the demultiplexer and changes the connection relationship between the output buffers and the input nodes of the demultiplexer on a frame period basis.

A display device of the present invention includes a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of subpixels connected to the data lines and the gate lines are arranged; a first gamma compensation voltage generator that alternately outputs a gamma compensation voltage for data of a first color and a gamma compensation voltage for data of a second color; a second gamma compensation voltage generator that alternately outputs a gamma compensation voltage for data of the second color and a gamma compensation voltage for data of a third color; first and third digital-to-analog converters that convert the first color data and the second color data into a gamma compensation voltage from the first gamma compensation voltage generator; second and fourth digital-to-analog converters that convert the second color data and the third color data into a gamma compensation voltage from the second gamma compensation voltage generator; a first output buffer connected to an output node of the first digital-to-analog converter; a second output buffer connected to the output node of the second digital-to-analog converter; a third output buffer connected to the output node of the third digital-to-analog converter; a fourth output buffer connected to the output node of the fourth digital-to-analog converter; a demultiplexer sequentially connecting input nodes to the plurality of data lines; and a switch array that sequentially connects the output buffers to the input nodes of the demultiplexer and changes the connection relationship between the output buffers and the input nodes of the demultiplexer on a frame period basis.

The present invention alternates the connection relationship between the gamma compensation voltage generators, output buffers, and pixels on the time axis to reduce the luminance difference caused by the switching order of the demultiplexer, the deviation of the gamma compensation voltage compensator, the deviation between the output buffers, etc. offset with Therefore, the present invention can prevent luminance differences between pixels.

1 and 2 are block diagrams showing a display device according to an embodiment of the present invention.
Figure 3 is a diagram showing an example of pentile pixel arrangement.
Figure 4 is a diagram showing an example of real pixel arrangement.
FIG. 5 is a diagram showing switch elements of a demultiplexer connected between channels of a drive IC and data lines.
FIG. 6A is a circuit diagram showing an example of a pixel circuit.
FIG. 6B is a diagram showing a method of driving the pixel circuit shown in FIG. 6A.
Figure 7 is a circuit diagram showing the gamma compensation voltage generator in detail.
Figure 8 is a circuit diagram showing a switch array disposed between the output buffers of the drive IC and the demultiplexer array.
Figure 9 is a circuit diagram showing a switch array according to the first embodiment of the present invention.
Figure 10 is a circuit diagram showing a switch array according to a second embodiment of the present invention.
Figure 11 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the first embodiment of the present invention.
Figure 12 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the second embodiment of the present invention.
Figure 13 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the third embodiment of the present invention.
Figure 14 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the fourth embodiment of the present invention.
Figure 15 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the fifth embodiment of the present invention.
Figure 16 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the sixth embodiment of the present invention.
Figure 17 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the seventh embodiment of the present invention.
FIG. 18 is a diagram summarizing the structure and performance of the drive IC shown in FIGS. 11 to 17.
Figures 19a and 19b are diagrams showing a control method of a demultiplexer according to the first embodiment of the present invention.
20A to 21B are diagrams showing a control method of a demultiplexer according to a second embodiment of the present invention.
Figure 22 is a diagram showing an example of line options.
Figure 23 is a diagram showing an example of frame options.
FIGS. 24A and 24B are diagrams showing an example of alternating the connection relationship between the gamma compensation voltage generators, output buffers, and pixels on the time axis using the switch array shown in FIG. 9.
FIGS. 25A to 25H are diagrams showing an example of alternating the connection relationship between gamma compensation voltage generators, output buffers, and pixels on the time axis using the switch array shown in FIG. 10.
FIG. 26 is a diagram illustrating an example in which the connection relationship between green subpixels and gamma compensation voltage generators in the embodiments shown in FIGS. 24A to 25H is alternated between pixel lines and alternated on a frame period basis.
FIG. 27 is a diagram showing an example in which the connection relationship between subpixels and output buffers alternates between pixel lines and alternates on a frame period basis in the embodiments shown in FIGS. 24A to 25H.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the description of the embodiment, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The same reference numerals throughout the specification may be interpreted as identical components without different definitions of the components depending on the embodiment.

Each of the features of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

In the display device of the present invention, the pixel circuit and the gate driver may include multiple transistors. Transistors can be implemented with Oxide TFT (Thin Film Transistor) containing an oxide semiconductor, LTPS TFT containing Low Temperature Poly Silicon (LTPS), etc. Each of the transistors may be implemented as a p-channel TFT or n-channel TFT. In the embodiment, the description is centered on an example in which the transistors of the pixel circuit are implemented as p-channel TFTs, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal swings between Gate On Voltage and Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage (Gate High Voltage, VGH), and the gate-off voltage may be the gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

Hereinafter, embodiments will be described focusing on an organic light emitting display device as an example of the display device of the present invention, but the present invention is not limited thereto. For example, the present invention can be applied to any display device in which a demultiplexer is applied between the channels of the drive IC and the data lines.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 and 2, a display device according to an embodiment of the present invention includes a display panel 100 and a display driver for writing pixel data of an input image into pixels of the display panel 100.

The display panel 100 includes a pixel array that displays an input image on the screen AA. The pixel array includes multiple data lines (DL, DL1 to DL6), multiple gate lines (GL, GL1, GL2) that intersect the data lines (DL, DL1 to DL6), and data lines (DL, DL1). ~DL6) and pixels (P) arranged in a matrix form defined by gate lines (GL, GL1, GL2).

Each of the pixels P may include a red subpixel (R), a green subpixel (G), and a blue subpixel (B) to implement color. Each of the pixels P may further include a white subpixel. Each subpixel includes a pixel circuit.

Pixels P may be arranged as real color pixels and pentile pixels. Pentile pixels use the preset Pentile pixel rendering algorithm to drive two sub-pixels of different colors as one pixel (P) as shown in Figure 3, achieving higher resolution than real color pixels. Implement. The Pentile pixel rendering algorithm compensates for insufficient color expression in each pixel (P) with the color of light emitted from adjacent pixels. In the case of real color pixels, one pixel (P) is composed of R, G, and B subpixels as shown in FIG. 4.

The pixel array includes multiple pixel lines (L1 to Ln). A pixel line includes pixels arranged in 1 line in the pixel array of the display panel 100. When the resolution of the pixel array is m*n, the pixel array includes n pixel lines (L1 to Ln). Pixels placed on one pixel line share gate lines. Subpixels arranged in one pixel line are connected to different data lines (DL, DL1 to DL6). Subpixels arranged vertically along the data line direction share the same data line.

The display panel 100 has a VDD line 104 for supplying a pixel driving voltage (ELVDD) to the sub-pixels, and a Vini line 105 for supplying an initialization voltage (Vini) for initializing the pixel circuit to the sub-pixels. , a VSS electrode 106 for supplying a low-potential power supply voltage (VSS) to the pixels, etc. may be further included. The power lines 104 and 105 and the VSS electrode are connected to the power supply unit 136.

Touch sensors may be disposed on the pixel array of the display panel 100. Touch input can be sensed using separate touch sensors or sensed through pixels. Touch sensors can be implemented as on-cell type or add-on type touch sensors placed on the screen of the display panel or embedded in the pixel array. You can.

The display driver includes a data driver 110, a switch array 113, a demultiplexer array 111, a gamma compensation voltage generator 112, a gate driver 120, a timing controller 130, and a level shifter. , 134), power supply unit 136, etc. The display driver may further include a touch sensor driver for driving touch sensors. The display driver writes pixel data of the input image to the pixels P of the display panel 100 under the control of the timing controller 130. In mobile devices and wearable devices, the display driver may be integrated into the drive IC 300 shown in FIG. 2.

The power supply unit 136 uses a DC-DC converter to generate power required to drive the pixel array and display driver of the flexible display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power supply unit 136 adjusts the direct current input voltage from the host system 200 to a gamma reference voltage and a gate-on voltage (VGL). Direct current power such as gate-off voltage (VGH), pixel driving voltage (ELVDD), low-potential power supply voltage (ELVSS), and initialization voltage (Vini) can be generated. The gamma reference voltage is supplied to the gamma compensation voltage generator 112. Gate power (VGL, VGH) is supplied to the level shifter 134 and the gate driver 120. Pixel power, such as the pixel driving voltage (ELVDD), low-potential power supply voltage (ELVSS), and initialization voltage (Vin), is commonly supplied to the pixels (P).

The gate power can be set to VGH = 8V, VGL = -7V, and the pixel power can be set to ELVDD = 4.6V, ELVSS = -2 to -3V, and Vini = -3 to -4V, but are not limited to this. The data voltage (Vdata) may be set to Vdata = 3~6V, but is not limited to this.

The display driver may operate in a low-speed driving mode. The low-speed driving mode can be set to analyze the input image and reduce power consumption of the display device when the input image does not change by a preset number of frames. The low-speed drive mode can reduce power consumption by controlling the data writing cycle of pixels to be longer by lowering the refresh rate of pixels when a still image is input for more than a certain period of time. The low-speed drive mode is not limited to when a still image is input. For example, when the display device operates in standby mode or when a user command or input image is not input to the display driver for more than a predetermined period of time, the display driver may operate in a low-speed driving mode.

The data driver 110 converts the pixel data of the input image, which is digital data, into a gamma compensation voltage using a digital to analog converter (hereinafter referred to as “DAC”) and generates a pixel data voltage (Vdata) in each channel. ) is output. The channels of the data driver 110 output data voltages to the input nodes of the demultiplexer array 111 through an output buffer (Source AMP.) under the control of the timing controller 130. The output buffer is shown in Figures 8-17.

The gamma compensation voltage generator 112 distributes the gamma reference voltage from the power supply unit 136 through a voltage divider circuit to generate a gamma compensation voltage for each gray level and supplies it to the data driver 110.

The demultiplexer array 111 may be formed on the substrate of the display panel 100 together with the pixel array. The demultiplexer array 111 sequentially connects input nodes connected to the switch array 113 to a plurality of data lines DL, DL1 to DL6. The demultiplexer array 111 is disposed between the channels of the data driver 110 and the data lines DL, DL1 to DL6, and divides the data voltage Vdata output from the data driver 110 to the data lines. Distributed as (DL, DL1~DL6). The demultiplexer array 111 includes multiple demultiplexers DM1 and DM2 as shown in FIG. 5 . The demultiplexers DM1 and DM2 shown in FIG. 5 are examples of 1:2 demultiplexers, but the present invention is not limited thereto. For example, the demultiplexer can be implemented as a 1:N (N is a positive integer greater than or equal to 2) demultiplexer.

The switch array 113 sequentially connects output buffers from each of the data output channels of the data driver 110 to the input nodes of the demultiplexer array 111 and connects the output buffers and the input nodes of the demultiplexer in predetermined time units. Change the connection relationship.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit formed directly on the bezel area (Bezel, BZ) of the display panel 100 along with the TFT array of the pixel array. The gate driver 120 outputs a gate signal to the gate lines GL, GL1, and GL2 under the control of the timing controller 130. The gate driver 120 can sequentially supply the gate signals (GATE1 and GATE2) to the gate lines (GL, GL1, and GL2) by shifting the gate signals (GATE1, GATE2) using a shift register.

The gate signals (GATE1, GATE2) may include scan signals [SCAN(N-1), SCAN(N)] and EM signals (EM). The gate driver 120 may include a first gate driver 121 and a second gate driver 122. The first gate driver 121 outputs scan signals [SCAN(N-1), SCAN(N)] and sequentially shifts the scan signals (SCAN1, SCAN2) according to the shift clock. The second gate driver 122 outputs the EM signal EM and sequentially shifts the EM signal EM according to the shift clock. In the case of a model without a bezel, at least some of the switch elements constituting the first and second gate drivers 121 and 122 may be dispersedly disposed within the pixel array.

The timing controller 130 receives pixel data of the input image and a timing signal synchronized with the pixel data from the host system 200. The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE). One cycle of the vertical synchronization signal (Vsync) is one frame period. One cycle of the horizontal synchronization signal (Hsync) and the data enable signal (DE) is one horizontal period (1H). Pulses of the data enable signal DE are synchronized with 1-line data to be written to pixels of 1-pixel line. Since the frame period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) can be omitted.

The host system 200 may be the main circuit board of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, or a wearable device. In a mobile device or wearable device, the timing controller 130 and the display driver may be integrated into one drive IC.

The timing controller 130 can control the operation timing of the display driver with a frame frequency of Hz by multiplying the input frame frequency by i times the input frame frequency Хi (i is a positive integer greater than 0). The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method. The timing controller 130 may lower the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in a low-speed driving mode.

The timing controller 130 provides a data timing control signal for controlling the operation timing of the data driver 110 based on the timing signals (Vsync, Hsync, DE) received from the host system 200 and the operation of the demultiplexer array 111. A MUX signal for controlling timing and a gate timing control signal for controlling the operation timing of the gate driver 120 are generated. The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage (VGL) and a gate-off voltage (VGH) through the level shifter 134 and supplied to the gate driver 120. The level shifter 134 converts the low level voltage of the gate timing control signal to the gate on voltage (VGL), and converts the high level voltage of the gate timing control signal to the gate off voltage (VGH). Convert to

In a mobile device or wearable device, a display driver may be integrated into the drive IC 300. In a mobile device, the display panel 100 may be implemented as a plastic OLED panel. Plastic OLED panels include an array of pixels on an organic thin film glued onto a back plate. A touch sensor array may be formed on the pixel array. The back plate may be a PET (Polyethylene terephthalate) substrate. The back plate blocks moisture penetration to prevent the pixel array from being exposed to humidity and supports the organic thin film on which the pixel array is formed. The organic thin film may be a thin polyimide (PI) film substrate. A multi-layer buffer film may be formed on the organic thin film using an insulating material not shown. Wires connected to the pixel array and the touch sensor array may be formed on the organic thin film.

The memory 132 of the drive IC 300 stores compensation values, register setting data, etc. received from the external memory 210 when power is input. Compensation values can be applied to various algorithms that improve image quality. Register setting data defines the operation of the display driver. External memory 210 may include flash memory. The memory 132 of the drive IC 300 may include static RAM (SRAM).

Referring to FIG. 5, each of the demultiplexers DM1 and DM2 includes first and second switch elements S1 and S2. Each of the switch elements S1 and S2 may be implemented as a p-channel transistor, but is not limited thereto. The timing controller 130 generates MUX signals (MUX1 and MUX2) to control the switch on/off timing of the switch elements (S1 and S2).

The data channel nodes CH1 and CH2 of the data driver 110 include an output buffer AMP that outputs the data voltage Vdata from the DAC. The output buffer (AMP) is connected to the input nodes of the demultiplexers (61, 62).

The first switch element (S01) of the first demultiplexer (DM1) is connected between the first channel node (CH1) of the data driver 110 and the first data line (DL1) to turn on the gate of the first MUX signal (MUX1). It is turned on according to the voltage VGL and connects the first channel node CH1 to the first data line DL1. The second switch element (S02) of the first demultiplexer (DM2) is connected between the first channel node (CH1) and the second data line (DL2) of the data driver 110 to turn on the gate of the second MUX signal (MUX2). It is turned on according to the voltage VGL and connects the first channel node CH1 to the second data line DL2. The first and second subpixels SP1 and SP2 sequentially charge the data voltage Vdata distributed in time division through the first demultiplexer DM1.

The first switch element (S01) of the second demultiplexer (DM2) is turned on according to the gate-on voltage (VGL) of the first MUX signal (MUX1) to control the second channel node (CH2) of the data driver 110. 3 Connect to the data line (DL3). The second switch element (S02) of the second demultiplexer (DM2) is turned on according to the gate-on voltage (VGL) of the second MUX signal (MUX2) to control the second channel node (CH2) of the data driver 110. 4 Connect to the data line (DL4). The third and fourth subpixels SP3 and SP4 sequentially charge the data voltage Vdata distributed in time division through the second demultiplexer DM2.

FIG. 6A is a circuit diagram showing an example of a pixel circuit. The pixel circuit of the present invention is not limited to Figure 6A. FIG. 6B is a diagram showing a method of driving the pixel circuit shown in FIG. 6A.

Referring to FIGS. 6A and 6B, the pixel circuit uses a light-emitting device (OLED), a driving device (DT) that supplies current to the light-emitting device (OLED), and a plurality of switch devices (M1 to M6). It includes an internal compensation circuit that samples the threshold voltage (Vth) of (DT) and compensates the gate voltage of the driving element (DT) by the threshold voltage (Vth) of the driving element (DT). Each of the driving element (DT) and the switch elements (M1 to M6) may be implemented as a p-channel transistor.

The operation of the internal compensation circuit is to turn on the fifth and sixth switch elements (M5, M6) according to the gate-on voltage (VGL) of the N-1 scan signal [SCAN(N-1)] to operate the pixel circuit. The first and second switch elements (M1, M2) are turned on according to the initialization period (Tini) and the gate-on voltage (VGL) of the Nth scan signal [SCAN(N)] to turn on the driving element (DT). A sampling period (Tsam) in which the threshold voltage of is sampled and stored in the capacitor (Cst), a data writing period (Twr) in which the first to sixth switch elements (M1 to M6) remain in the off state, and the third and third It is divided into a light emission period (Tem) during which the 4 switch elements (M1, M2) are turned on and the light emitting element (OLED) emits light.

The emission period (Tem) is determined by the gate-on low voltage (VGL) of the EM signal [EM(N)] in order to accurately express the luminance of low gray levels with the duty ratio of the EM signal [EM(N)]. and the gate-off voltage (VGH), the third and fourth switch elements (M1, M2) may repeatedly turn on/off by swinging at a predetermined duty ratio.

The light emitting device (OLED) can be implemented as OLED. A light emitting device (OLED) includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light emitting device (OLED) is connected to the fourth node (n4) between the fourth and sixth switch devices (M4 and M6). The fourth node n4 is connected to the anode of the light emitting device OLED, the second electrode of the fourth switch device M4, and the second electrode of the sixth switch device M6. The cathode of the light emitting device (OLED) is connected to the VSS electrode 106 to which a low-potential power supply voltage (VSS) is applied. The light emitting device (OLED) emits light with a current (Ids) flowing according to the gate-source voltage (Vgs) of the driving device (DT). The current path of the light emitting device (OLED) is switched by the third and fourth switch devices (M3 and M4).

The storage capacitor Cst is connected between the VDD line 104 and the first node n1. The data voltage (Vdata) compensated by the threshold voltage (Vth) of the driving element (DT) is charged in the storage capacitor (Cst). Since the data voltage Vdata in each subpixel is compensated by the threshold voltage Vth of the driving element DT, the characteristic deviation of the driving element DT in the subpixels is compensated.

The first switch element M1 is turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)] and connects the second node n2 and the third node n3. The second node n2 is connected to the gate of the driving element DT, the first electrode of the storage capacitor Cst, and the first electrode of the first switch element M1. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switch element M1, and the first electrode of the fourth switch element M4. The gate of the first switch element M1 is connected to the first gate line 31 and receives the Nth scan signal [SCAN(N)]. The first electrode of the first switch element (M1) is connected to the second node (n2), and the second electrode of the first switch element (M1) is connected to the third node (n3).

The second switch element M2 is turned on in response to the gate-on voltage VGL of the Nth scan signal [SCAN(N)] and supplies the data voltage Vdata to the first node n1. The gate of the second switch element (M2) is connected to the first gate line 31 and receives the Nth scan signal [SCAN(N)]. The first electrode of the second switch element M2 is connected to the first node n1. The second electrode of the second switch element M2 is connected to the data line DL to which the data voltage Vdata is applied. The first node n1 is connected to the first electrode of the second switch element M2, the second electrode of the third switch element M2, and the first electrode of the driving element DT.

The third switch element M3 is turned on in response to the gate-on voltage VGL of the EM signal [EM(N)] and connects the VDD line 104 to the first node n1. The gate of the third switch element M3 is connected to the third gate line 33 and receives an EM signal [EM(N)]. The first electrode of the third switch element M3 is connected to the VDD line 104. The second electrode of the third switch element M3 is connected to the first node n1.

The fourth switch element M4 is turned on in response to the gate-on voltage VGL of the EM signal [EM(N)] to connect the third node n3 to the anode of the light emitting element OLED. The gate of the fourth switch element M4 is connected to the third gate line 33 and receives an EM signal [EM(N)]. The first electrode of the fourth switch element M4 is connected to the third node n3, and the second electrode is connected to the fourth node n4.

The EM signal [EM(N)] controls the on/off of the third and fourth switch elements M3 and M4 to switch the current path of the light emitting element OLED. Controls the lighting time.

The fifth switch element (M5) is turned on in response to the gate-on voltage (VGL) of the N-1 scan signal [SCAN(N-1)] and connects the second node (n2) to the Vini line 105. do. The gate of the fifth switch element M5 is connected to the second gate line 32 and receives the N-1 scan signal [SCAN(N-1)]. The first electrode of the fifth switch element M5 is connected to the second node n2, and the second electrode is connected to the Vini line 105.

The sixth switch element (M6) is turned on in response to the gate-on voltage (VGL) of the N-1 scan signal [SCAN(N-1)] and connects the Vini line 105 to the fourth node (n4). do. The gate of the sixth switch element M6 is connected to the second gate line 32 and receives the N-1 scan signal [SCAN(N-1)]. The first electrode of the sixth switch element M6 is connected to the Vini line 105, and the second electrode is connected to the fourth node n4.

The driving device (DT) drives the light emitting device (OLED) by adjusting the current (Ids) flowing through the light emitting device (OLED) according to the gate-source voltage (Vgs). The driving element DT includes a gate connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

During the initialization period (Tini), the N-1th scan signal [SCAN(N-1)] is generated as the gate-on voltage (VGL). The Nth scan signal [SCAN(N)] and the EM signal [EM(N)] maintain the gate-off voltage (VGH) during the initialization period (Tini). Accordingly, during the initialization period Tini, the fifth and sixth switch elements M5 and M6 are turned on and the second and fourth nodes n2 and n4 are initialized to Vini. A hold period (Th) may be set between the initialization period (Tini) and the sampling period (Tsam). In the hold period (Th), the gate signals [SCAN(N-1), SCAN(N), EM(N)] maintain the previous state.

During the sampling period (Tsam), the Nth scan signal [SCAN(N)] is generated as the gate-on voltage (VGL). The pulse of the Nth scan signal [SCAN(N)] is synchronized with the data voltage (Vdata) of the Nth pixel line. The N-1 scan signal [SCAN(N-1)] and the EM signal [EM(N)] maintain the gate-off voltage (VGH) during the sampling period (Tsam). Accordingly, the first and second switch elements M1 and M1 are turned on during the sampling period Tsam.

During the sampling period Tsam, the gate voltage DTG of the driving element DT is increased by the current flowing through the first and second switch elements M1 and M2. Since the driving element DT is turned off when the driving element DT is turned off, the gate node voltage DTG is Vdata - |Vth|. At this time, the voltage of the first node (n) is also Vdata - |Vth|. During the sampling period (Tsam), the gate-to-source voltage (Vgs) of the driving element (DT) is |Vgs| = Vdata -(Vdata-|Vth|) = |Vth|.

During the data writing period (Twr), the Nth scan signal [SCAN(N)] is inverted to the gate-off voltage (VGH). The N-1 scan signal [SCAN(N-1)] and the EM signal [EM(N)] maintain the gate-off voltage (VGH) during the sampling period (Tsam). Accordingly, all switch elements M1 to M6 remain in an off state during the data writing period Twr.

During the emission period (Tem), the EM signal [EM(N)] is turned on/off at a predetermined duty ratio and swings between the gate-on voltage (VGL) and the gate-off voltage (VGH). During the light emission period (Tem), the N-1th and Nth scan signals [SCAN(N-1) and SCAN(N) maintain the gate-off voltage (VGH). During the light emission period Tem, the third and fourth switch elements M3 and M4 repeatedly turn on/off according to the voltage of the EM signal EM. When the EM signal [EM(N)] is the gate-on voltage (VGL), the third and fourth switch elements (M3, M4) are turned on and current flows to the light emitting element (OLED). At this time, Vgs of the driving element (DT) is |Vgs| = VDD - (Vdata-|Vth|), and the current flowing through the light emitting device (OLED) is K(VDD-Vdata) ² . K is a proportionality constant determined by the charge mobility of the driving element (DT), parasitic capacitance, and channel capacity.

Figure 7 is a circuit diagram showing the gamma compensation voltage generator 112 in detail.

Referring to FIG. 7, the gamma compensation voltage generator 112 includes a voltage dividing circuit (RS1, R21 to R26, R31 to R38), a voltage selection unit (MUX11 to MUX13, MUX21 to MUX26), and buffers (BUF11 to BUF13, Includes BUF21~BUF26).

The first voltage dividing circuit RS1 receives the gamma reference voltage VREF from the power supply unit 136. The first voltage dividing circuit RS1 divides the gamma reference voltage VREF using an R string circuit including resistors connected in series.

The voltage selection unit is a multiplexer (MUX11) that selects the first gamma reference voltage (GMA1) from the voltages divided by the first divider circuit (RS1) according to the register setting (RGMA1), and the first divided voltage according to the register setting (RGMA8). A multiplexer (MUX13) selects the eighth gamma reference voltage (GMA8) from the voltages distributed by the circuit (RS1), and the eighth gamma reference voltage (GMA8) from the voltages divided by the first divider circuit (RS1) according to the register setting (RGMA9). 9 Contains a multiplexer (MUX12) that selects the gamma reference voltage (GMA9).

The first gamma reference voltage (GMA1) is the highest gamma compensation voltage. The ninth gamma reference voltage (GMA9) is the lowest gamma compensation voltage. The eighth gamma reference voltage (GM8) is a gamma tab voltage higher than the ninth gamma reference voltage (GMA9).

The second voltage division circuits (R21 to R26) are divided into 2-1st to 2-6th voltage division circuits (R21 to R26). Each of the 2-1st to 2-6th voltage dividing circuits (R21 to R26) divides the input voltage using an R string circuit including resistors connected in series. The voltage selection units (MUX21 to MUX26) include a 2-1 multiplexer (MUX21) connected between the 2-1 divider circuit (R21) and the 2-1 buffer (BUF21), the 2-2 divider circuit (R22), and the 2-1st divider circuit (R22). A 2-2 multiplexer (MUX22) connected between the 2-2 buffer (BUF22), a 2-3 multiplexer (MUX23) connected between the 2-3 voltage divider circuit (R23) and the 2-3 buffer (BUF23), A 2-4 multiplexer (MUX24) connected between the 4-4 voltage dividing circuit (R24) and the 2-4 buffer (BUF24), connected between the 2-5 voltage dividing circuit (R25) and the 2-5 buffer (BUF25) It includes a 2-5 multiplexer (MUX25), and a 2-6 multiplexer (MUX26) connected between the 2-6 voltage divider circuit (R26) and the 2-1 buffer (BUF26).

The 2-1 voltage dividing circuit (R21) receives the first gamma reference voltage (GMA1) and the eighth gamma reference voltage (GMA8), distributes the first gamma reference voltage (GMA1), and divides the first gamma reference voltage (GMA1) into different voltages through the nodes between the resistors. Outputs voltage. The 2-1 multiplexer MUX21 selects one of the voltages distributed by the 2-1 voltage divider circuit R21 as the second gamma reference voltage GMA2 according to the register setting RGMA2. The 2-1 buffer (BUF21) divides the second gamma reference voltage (GMA2) input from the 2-1 multiplexer (MUX21) between the 3-1 divider circuit (R31) and the 3-2 divider circuit (R32). Supply to nodes.

The 2-2 voltage dividing circuit (R22) receives the second gamma reference voltage (GMA2) and the eighth gamma reference voltage (GMA8), distributes the second gamma reference voltage (GMA2), and divides the second gamma reference voltage (GMA2) into different voltages through the nodes between the resistors. Outputs voltage. The 2-2 multiplexer MUX22 selects one of the voltages distributed by the 2-2 voltage divider circuit R22 as the third gamma reference voltage GMA3 according to the register setting RGMA3. The 2-2 buffer (BUF22) divides the third gamma reference voltage (GMA3) input from the 2-2 multiplexer (MUX22) between the 3-2 divider circuit (R32) and the 3-3 divider circuit (R33). Supply to nodes.

The 2-6th voltage dividing circuit (RS26) receives the sixth gamma reference voltage (GMA6) and the eighth gamma reference voltage (GMA8) and distributes the sixth gamma reference voltage (GMA6) to provide different Outputs voltage. The 2-6 multiplexer (MUX26) selects one of the voltages distributed by the 2-6 voltage divider circuit (RS26) as the seventh gamma reference voltage (GMA7) according to the register setting (RGMA7). The 2-6 buffer (BUF26) divides the 7th gamma reference voltage (GMA7) input from the 2-6 multiplexer (MUX26) between the 3-6 divider circuit (R36) and the 3-7 divider circuit (R37). Supply to nodes.

Each of the 3-1st to 3-8th voltage dividing circuits (RS31 to RS38) divides the input voltage using an R string circuit including resistors connected in series. The 3-1 voltage dividing circuit (R31) divides the first gamma reference voltage (GMA1) and the second gamma reference voltage (GMA2) to determine the ratio between the first gamma reference voltage (GMA1) and the second gamma reference voltage (GMA2). Outputs gamma compensation voltages for each group. The 3-2 voltage dividing circuit (R32) divides the second gamma reference voltage (GMA2) and the third gamma reference voltage (GMA3) to determine the ratio between the second gamma reference voltage (GMA2) and the third gamma reference voltage (GMA3). Outputs gamma compensation voltages for each group. The 3-6th voltage dividing circuit (R36) divides the sixth gamma reference voltage (GMA6) and the seventh gamma reference voltage (GMA7) to determine the ratio between the sixth gamma reference voltage (GMA6) and the seventh gamma reference voltage (GMA7). Outputs gamma compensation voltages for each group. The 3-7th voltage dividing circuit (RS37) divides the 7th gamma reference voltage (GMA7) and the 8th gamma reference voltage (GMA8) to determine the ratio between the 7th gamma reference voltage (GMA7) and the 8th gamma reference voltage (GMA8). Outputs gamma compensation voltages for each group. The 3-8th voltage dividing circuit (R38) divides the 8th gamma reference voltage (GMA8) and the 9th gamma reference voltage (GMA9) to determine the ratio between the 8th gamma reference voltage (GMA8) and the 9th gamma reference voltage (GMA9). Outputs gamma compensation voltages for each group.

The gamma compensation voltage generator 112 may be separated by color by taking into account the variation in luminous efficiency of each color of the light emitting device, that is, OLED, and the variation in panel load for each color. One gamma compensation voltage generator 112 can output the optimal gamma compensation voltage for each color by adjusting the voltage level of the gamma compensation voltage according to the register settings (RGMA1 to RGMA7). Register settings (RGMA1 to RGMA7) can be changed in synchronization with the pixel data input to the DAC.

Due to differences between the output buffers of the data driver 110, the offset of the voltage output through the output buffers may differ between the output buffers. Additionally, if the switch order of the demultiplexers DM1 and DM2 is repeated regularly, the amount of charging in the subpixels may vary between a subpixel in which the data voltage is charged first and a subpixel in which the data voltage is charged later. A luminance difference may be visible between subpixels at the same gray level due to the switch order of the demultiplexers (DM1, DM2), deviation of the gamma compensation voltage generator 112, offset deviation of the output buffer, etc. In order to solve this problem, the present invention provides a plurality of output buffers to the data driver ( Connect sequentially to the channels in 110) in a predetermined order.

Figure 8 is a circuit diagram showing a switch array disposed between output buffers and a demultiplexer array.

Referring to FIG. 8, the drive IC 71 includes a plurality of gamma compensation voltage generators 711 and 712, a plurality of DACs 721 to 724, and a plurality of output buffers A to D. The DACs 721 to 724 convert pixel data into a gamma compensation voltage from the gamma compensation voltage generators 711 and 712 and output a data voltage Vdata. The data voltage (Vdata) is output to the switch array 113 through output buffers (A to D).

The switch array 113 uses a plurality of switch elements (a to h) to change the connection relationship between the plurality of output buffers (A to D) and the demultiplexer array 111 on the time axis. The switch array 113 distributes the charge amount deviation between subpixels according to the switch order of the demultiplexer array 111, the deviation of the gamma compensation voltage generator 112, the offset of the output buffer, etc. on the time axis to make the luminance among the subpixels uniform. Let it be done.

The switch array 113 has first and second embodiments as shown in FIGS. 9 and 10. In the drive IC 300, the circuit configuration between the gamma compensation voltage generator, the DAC, and the output buffer includes the first to seventh embodiments (Case1 to Case7) as shown in FIGS. 10 to 17.

Figure 9 is a circuit diagram showing the switch array 113 according to the first embodiment of the present invention. Figure 10 is a circuit diagram showing a switch array according to a second embodiment of the present invention. 9 and 10, the data output channel of the drive IC 300 is a first channel node (CH1) including a first output buffer (A), and a second channel node (CH2) including a second output buffer (B). , a third channel node (CH3) including a third output buffer (C), and a fourth channel node (CH4) including a fourth output buffer (D).

Referring to FIG. 9, the switch array 113 includes first to eighth switch elements (a to h). The first to eighth switch elements (a to h) are connected to the output nodes of the output buffers (A to D) through the channel nodes (CH1 to CH4). The first switch element (a) is connected between the first channel node (CH1) and the input node (S1) of the first demultiplexer (DM1) and is turned on/off under the control of the timing controller 130. When the first switch element (a) is turned on, the first channel node (CH1) is connected to the input node (S1) of the first demultiplexer (DM1) and outputs a data voltage (Vdata) through the first output buffer (A) ) is supplied to the first demultiplexer (DM1).

The second switch element (b) is connected between the second channel node (CH2) and the input node (S1) of the first demultiplexer (DM1) and is turned on/off under the control of the timing controller 130. When the second switch element (b) is turned on, the second channel node (CH2) is connected to the input node (S1) of the first demultiplexer (DM1) and outputs a data voltage (Vdata) through the second output buffer (B) ) is supplied to the first demultiplexer (DM1).

The third switch element (c) is connected between the second channel node (CH2) and the input node (S2) of the second demultiplexer (DM2) and is turned on/off under the control of the timing controller 130. When the third switch element (c) is turned on, the second channel node (CH2) is connected to the input node (S2) of the second demultiplexer (DM2) and outputs a data voltage (Vdata) through the second output buffer (B) ) is supplied to the second demultiplexer (DM2).

The fourth switch element d is connected between the first channel node CH1 and the input node S2 of the second demultiplexer DM2 and is turned on/off under the control of the timing controller 130. When the fourth switch element (d) is turned on, the first channel node (CH1) is connected to the input node (S2) of the second demultiplexer (DM2) and outputs a data voltage (Vdata) through the first output buffer (A) ) is supplied to the second demultiplexer (DM2).

The first output buffer (A) may sequentially output the 1-1 and 2-2 data voltages (Vdata). The second output buffer B may sequentially output the 2-1 and 1-2 data voltages Vdata. The first demultiplexer (DM1) transmits the 1-1 and 1-2 data voltages (Vdata) sequentially input through the first and second switch elements (a, b) to the first and second data lines. Time share distribution. The second demultiplexer (DM2) transmits the 2-1 and 2-2 data voltages (Vdata) sequentially input through the third and fourth switch elements (c, d) to the third and fourth data lines. Time share distribution.

The fifth switch element (e) is connected between the third channel node (CH3) and the input node (S3) of the third demultiplexer (DM3) and is turned on/off under the control of the timing controller 130. The sixth switch element f is connected between the fourth channel node CH4 and the input node S3 of the third demultiplexer DM3 and is turned on/off under the control of the timing controller 130. The seventh switch element (g) is connected between the fourth channel node (CH4) and the input node (S4) of the fourth demultiplexer (DM4) and is turned on/off under the control of the timing controller 130. The eighth switch element (h) is connected between the third channel node (CH3) and the input node (S4) of the fourth demultiplexer (DM4) and is turned on/off under the control of the timing controller 130.

The third output buffer C may sequentially output the 3-1 and 4-2 data voltages Vdata. The fourth output buffer D may sequentially output the 4-1 and 3-2 data voltages Vdata. The third demultiplexer (DM3) applies the 3-1 and 3-2 data voltages (Vdata) sequentially input through the 5th and 6th switch elements (e, f) to the 4th and 6th data lines. Time share distribution. The fourth demultiplexer (DM4) applies the 4-1 and 4-2 data voltages (Vdata) sequentially input through the 7th and 8th switch elements (g, h) to the 7th and 8th data lines. Time share distribution.

The first demultiplexer DM1 time-divisionally distributes the data voltage from the switch array 113 to the first and second data lines. The second demultiplexer (DM2) time-divisionally distributes the data voltage from the switch array 113 to the third and fourth data lines. The third demultiplexer (DM3) time-divisionally distributes the data voltage from the switch array 113 to the sixth and seventh data lines. The fourth demultiplexer (DM4) time-divides the data voltage from the switch array 113 to the 7th and 8th data lines.

The switching order of the switch elements (a to h) is changed by the timing controller 130 on a horizontal period basis and on a frame period basis to temporally offset the luminance difference.

Referring to FIG. 10, the switch array 113 includes first to sixteenth switch elements (a to p). The first to sixteenth switch elements (a to p) are connected to the output nodes of the output buffers (A to D) through the channel nodes (CH1 to CH4).

The first switch element (a) is connected between the first channel node (CH1) and the input node (S1) of the first demultiplexer (DM1) and is turned on/off under the control of the timing controller 130. When the first switch element (a) is turned on, the first channel node (CH1) is connected to the input node (S1) of the first demultiplexer (DM1) and outputs a data voltage (Vdata) through the first output buffer (A) ) is supplied to the first demultiplexer (DM1).

The second switch element (b) is connected between the third channel node (CH3) and the input node (S1) of the first demultiplexer (DM1) and is turned on/off under the control of the timing controller 130. When the second switch element (b) is turned on, the third channel node (CH3) is connected to the input node (S1) of the first demultiplexer (DM1) and outputs a data voltage (Vdata) through the third output buffer (C) ) is supplied to the first demultiplexer (DM1).

The third switch element (c) is connected between the second channel node (CH2) and the input node (S1) of the first demultiplexer (DM1) and is turned on/off under the control of the timing controller 130. When the third switch element (c) is turned on, the second channel node (CH2) is connected to the input node (S1) of the first demultiplexer (DM1) and outputs a data voltage (Vdata) through the second output buffer (B) ) is supplied to the first demultiplexer (DM1).

The fourth switch element d is connected between the fourth channel node CH4 and the input node S1 of the first demultiplexer DM1 and is turned on/off under the control of the timing controller 130. When the fourth switch element (d) is turned on, the fourth channel node (CH4) is connected to the input node (S1) of the first demultiplexer (DM1) and outputs a data voltage (Vdata) through the first output buffer (A) ) is supplied to the second demultiplexer (DM2).

The fifth switch element (e) is connected between the second channel node (CH2) and the input node (S2) of the second demultiplexer (DM2) and is turned on/off under the control of the timing controller 130. The sixth switch element f is connected between the fourth channel node CH4 and the input node S2 of the second demultiplexer DM2 and is turned on/off under the control of the timing controller 130. The seventh switch element (g) is connected between the first channel node (CH1) and the input node (S2) of the second demultiplexer (DM2) and is turned on/off under the control of the timing controller 130. The eighth switch element (h) is connected between the third channel node (CH3) and the input node (S2) of the second demultiplexer (DM2) and is turned on/off under the control of the timing controller 130.

The ninth switch element (i) is connected between the third channel node (CH3) and the input node (S3) of the third demultiplexer (DM3) and is turned on/off under the control of the timing controller 130. The tenth switch element j is connected between the first channel node CH1 and the input node S3 of the third demultiplexer DM3 and is turned on/off under the control of the timing controller 130. The 11th switch element (k) is connected between the fourth channel node (CH4) and the input node (S3) of the third demultiplexer (DM3) and is turned on/off under the control of the timing controller 130. The twelfth switch element l is connected between the second channel node CH2 and the input node S3 of the third demultiplexer DM3 and is turned on/off under the control of the timing controller 130.

The 13th switch element (i) is connected between the fourth channel node (CH4) and the input node (S4) of the fourth demultiplexer (DM4) and is turned on/off under the control of the timing controller 130. The fourteenth switch element (n) is connected between the second channel node (CH2) and the input node (S4) of the fourth demultiplexer (DM4) and is turned on/off under the control of the timing controller (130). The 15th switch element (o) is connected between the third channel node (CH3) and the input node (S4) of the fourth demultiplexer (DM4) and is turned on/off under the control of the timing controller 130. The 16th switch element (p) is connected between the first channel node (CH1) and the input node (S4) of the fourth demultiplexer (DM4) and is turned on/off under the control of the timing controller 130.

The first output buffer (A) may sequentially output the data voltage (Vdata) in the order of the 1-1 data voltage, the 3-2 data voltage, the 2-3 data voltage, and the 4-4 data voltage. . The second output buffer (B) may sequentially output the data voltage (Vdata) in the order of the 2-1 data voltage, the 4-2 data voltage, the 1-3 data voltage, and the 3-4 data voltage. . The third output buffer C may sequentially output the data voltage Vdata in the following order: 3-1 data voltage, 1-2 data voltage, 4-3 data voltage, and 2-4 data voltage. . The fourth output buffer D may sequentially output the data voltage Vdata in the order of the 4-1 data voltage, the 2-2 data voltage, the 3-3 data voltage, and the 1-4 data voltage. .

The first demultiplexer DM1 time-divides the data voltage Vdata sequentially input through the first to fourth switch elements a to d to the first and second data lines. The second demultiplexer DM2 time-divides the data voltage Vdata sequentially input through the fifth to eighth switch elements e to h to the third and fourth data lines. The third demultiplexer DM3 time-divisionally distributes the data voltage Vdata sequentially input through the ninth to twelfth switch elements i to l to the fifth and sixth data lines. The fourth demultiplexer DM4 time-divisionally distributes the data voltage Vdata sequentially input through the 13th to 16th switch elements m to p to the 7th and 8th data lines.

Figure 11 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC 300 according to the first embodiment of the present invention.

Referring to FIG. 11, the drive IC 300 includes first to fourth gamma compensation voltage generators 711 to 714, first to fourth DACs 721 to 724, and first to fourth output buffers (A). Includes ~D).

In the case of a pixel array composed of pentile pixels, as shown in FIG. 3, a first pixel group including a pixel (P) including red and green subpixels (R, G), and a first pixel group including blue and green subpixels (B, It may be divided into a second pixel group including a pixel (P) including G). Within this pixel array, the number of green subpixels (G) is twice as large as the number of red and blue subpixels (R, B). Since the load of the channel connected to the green subpixels (G) is doubled, in order to equalize the load of the channels for each color, the gamma compensation voltage generators 711 to 714, DACs 721 to 724, and output buffers ( A~D) can be separated by color.

The first gamma compensation voltage generator 711 outputs a gamma compensation voltage for red data. The second gamma compensation voltage generator 712 outputs a gamma compensation voltage for green data to be written in the green subpixels of the first pixel group. The third gamma compensation voltage generator 713 outputs a gamma compensation voltage for blue data. The fourth gamma compensation voltage generator 714 outputs a gamma compensation voltage for green data to be written in the green subpixels of the second pixel group.

The first DAC 721 generates a data voltage Vdata by converting red data to be written in the red subpixel R into a gamma compensation voltage from the first gamma compensation voltage generator 711. The second DAC 722 converts green data to be written in the green subpixel (G) of the first pixel group into a gamma compensation voltage from the second gamma compensation voltage generator 712 and generates a data voltage (Vdata). . The third DAC 723 converts the blue data to be written in the blue subpixel B into the gamma compensation voltage from the third gamma compensation voltage generator 713 and generates the data voltage Vdata. The fourth DAC 724 converts green data to be written in the green subpixel (G) of the second pixel group into a gamma compensation voltage from the fourth gamma compensation voltage generator 714 and generates a data voltage (Vdata). .

The first output buffer (A) supplies the data voltage (Vdata) from the first DAC (721) to the input node of the switch array (113). The second output buffer B supplies the data voltage Vdata from the second DAC 722 to the input node of the switch array 113. The third output buffer C supplies the data voltage Vdata from the first DAC 721 to the input node of the switch array 113. The fourth output buffer D supplies the data voltage Vdata from the fourth DAC 724 to the input node of the switch array 113.

Figure 12 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the second embodiment of the present invention. In this embodiment, two DACs share one output buffer.

Referring to FIG. 12, the first gamma compensation voltage generator 711 outputs a gamma compensation voltage for red data. The second gamma compensation voltage generator 712 outputs a gamma compensation voltage for green data to be written in the green subpixels (G) of the first pixel group. The third gamma compensation voltage generator 713 outputs a gamma compensation voltage for blue data. The fourth gamma compensation voltage generator 714 outputs a gamma compensation voltage for green data to be written in the green subpixels (G) of the second pixel group.

The first DAC 721 generates a data voltage Vdata by converting red data to be written in the red subpixel R into a gamma compensation voltage from the first gamma compensation voltage generator 711. The second DAC 722 converts green data to be written in the green subpixel (G) of the first pixel group into a gamma compensation voltage from the second gamma compensation voltage generator 712 and generates a data voltage (Vdata). . The third DAC 723 converts the blue data to be written in the blue subpixel B into the gamma compensation voltage from the third gamma compensation voltage generator 713 and generates the data voltage Vdata. The fourth DAC 724 converts green data to be written in the green subpixel (G) of the second pixel group into a gamma compensation voltage from the fourth gamma compensation voltage generator 714 and generates a data voltage (Vdata). .

The first output buffer A supplies the data voltage Vdata sequentially input from the first and second DACs 721 and 722 to the input node of the switch array 113. One of the first and second DACs 721 and 722 outputs a delayed data voltage. The second output buffer B supplies the data voltage Vdata sequentially input from the third and fourth DACs 723 and 724 to the input node of the switch array 113. One of the third and fourth DACs 723 and 724 outputs a delayed data voltage.

Figure 13 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the third embodiment of the present invention. In this embodiment, two gamma compensation voltage generators share one DAC. The output voltage of one of the two gamma compensation voltage generators is delayed to be synchronized with the pixel data and input to the DAC.

Referring to FIG. 13, the drive IC 300 includes first to fourth gamma compensation voltage generators 711 to 714, first to fourth DACs 721 to 724, and first to fourth output buffers (A). Includes ~D).

The first gamma compensation voltage generator 711 outputs a gamma compensation voltage for red data. The second gamma compensation voltage generator 712 outputs a gamma compensation voltage for green data to be written in the green subpixels (G) of the first pixel group. The third gamma compensation voltage generator 713 outputs a gamma compensation voltage for blue data. The fourth gamma compensation voltage generator 714 outputs a gamma compensation voltage for green data to be written in the green subpixels (G) of the second pixel group.

The first and third DACs 721 and 723 sequentially receive red data to be written in the red subpixel (R) and green data to be written in the green subpixel (G) belonging to the first pixel group. The first and third DACs 721 and 723 convert red data into a gamma compensation voltage from the first gamma compensation voltage 711 and then convert green data into a gamma compensation voltage from the second gamma compensation voltage 712. Convert to The second and fourth DACs 722 and 724 sequentially receive blue data to be written in the blue subpixel (B) and green data to be written in the green subpixel (G) belonging to the second pixel group. The second and fourth DACs 722 and 724 convert the blue data into a gamma compensation voltage from the third gamma compensation voltage 713 and then convert the green data into a gamma compensation voltage from the fourth gamma compensation voltage 714. Convert to

The first multiplexer 715 includes first and second gamma compensation voltage generators ( Select the output of 711, 712). When red data is input to the first and third DACs 721 and 723, the first multiplexer 715 generates a gamma compensation voltage from the first gamma compensation voltage generator 711 to the first and third DACs (721, 723). 721, 723). Subsequently, the first multiplexer 715 converts the gamma compensation voltage from the second gamma compensation voltage generator 712 to the first and third DACs 721 and 723 when green data is input to the first and third DACs 721 and 723. It is supplied to fields (721, 723).

The second multiplexer 716 operates third and fourth gamma compensation voltage generators ( Select the output of 713, 714). When blue data is input to the second and fourth DACs 722 and 724, the second multiplexer 716 outputs the gamma compensation voltage from the third gamma compensation voltage generator 713 to the second and fourth DACs (722, 724). 722, 724). Subsequently, the second multiplexer 716 converts the gamma compensation voltage from the fourth gamma compensation voltage generator 714 to the second and fourth DACs 722 and 724 when green data is input to the second and fourth DACs 722 and 724. It is supplied to fields (722, 724).

Figure 14 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the fourth embodiment of the present invention. This embodiment shows a drive IC 300 in which gamma compensation voltage generators 711 to 713 are arranged one for each color, and two DACs share one output buffer.

Referring to FIG. 14, the drive IC 300 includes first to third gamma compensation voltage generators 711 to 713, first to fourth DACs 721 to 724, and first to fourth output buffers (A). Includes ~D).

The first gamma compensation voltage generator 711 outputs a gamma compensation voltage for red data. The second gamma compensation voltage generator 712 outputs a gamma compensation voltage for green data. The third gamma compensation voltage generator 713 outputs a gamma compensation voltage for blue data.

The first DAC 721 generates a data voltage Vdata by converting red data to be written in the red subpixel R into a gamma compensation voltage from the first gamma compensation voltage generator 711. The second and fourth DACs 722 and 724 convert green data to be written in the green subpixel G into a gamma compensation voltage from the second gamma compensation voltage generator 712 and generate a data voltage Vdata. . The third DAC 723 converts the blue data to be written in the blue subpixel B into the gamma compensation voltage from the third gamma compensation voltage generator 713 and generates the data voltage Vdata.

The first output buffer A supplies the data voltage Vdata sequentially input from the first and second DACs 721 and 722 to the input node of the switch array 113. One of the first and second DACs 721 and 722 outputs a delayed data voltage. The second output buffer B supplies the data voltage Vdata sequentially input from the third and fourth DACs 723 and 724 to the input node of the switch array 113. One of the third and fourth DACs 723 and 724 outputs a delayed data voltage.

Figure 15 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the fifth embodiment of the present invention. This embodiment shows a drive IC 300 in which one gamma compensation voltage generator 711 to 713 is arranged for each color, and two gamma compensation voltage generators share one DAC. The output voltage of one of the two gamma compensation voltage generators is delayed to be synchronized with the pixel data and input to the DAC.

Referring to FIG. 15, the drive IC 300 includes first to third gamma compensation voltage generators 711 to 713, first to fourth DACs 721 to 724, and first to fourth output buffers (A). Includes ~D).

The first gamma compensation voltage generator 711 outputs a gamma compensation voltage for red data. The second gamma compensation voltage generator 712 outputs a gamma compensation voltage for green data. The third gamma compensation voltage generator 713 outputs a gamma compensation voltage for blue data.

The first and third DACs 721 and 723 sequentially receive red data and green data. The first and third DACs 721 and 723 convert red data into a gamma compensation voltage from the first gamma compensation voltage 711 and then convert green data into a gamma compensation voltage from the second gamma compensation voltage 712. Convert to The second and fourth DACs 722 and 724 sequentially receive blue data and green data to be written in the blue subpixel B. The second and fourth DACs 722 and 724 convert the blue data into a gamma compensation voltage from the third gamma compensation voltage 713 and then convert the green data into a gamma compensation voltage from the second gamma compensation voltage 712. Convert to

The first multiplexer 715 includes first and second gamma compensation voltage generators ( Select the output of 711, 712). When red data is input to the first and third DACs 721 and 723, the first multiplexer 715 generates a gamma compensation voltage from the first gamma compensation voltage generator 711 to the first and third DACs (721, 723). 721, 723). Subsequently, the first multiplexer 715 converts the gamma compensation voltage from the second gamma compensation voltage generator 712 to the first and third DACs 721 and 723 when green data is input to the first and third DACs 721 and 723. It is supplied to fields (721, 723).

The second multiplexer 716 generates second and third gamma compensation voltage generators ( Select the output of 712, 713). When blue data is input to the second and fourth DACs 722 and 724, the second multiplexer 716 outputs the gamma compensation voltage from the third gamma compensation voltage generator 713 to the second and fourth DACs (722, 724). 722, 724). Subsequently, the second multiplexer 716 converts the gamma compensation voltage from the second gamma compensation voltage generator 712 to the second and fourth DACs 722 and 724 when green data is input to the second and fourth DACs 722 and 724. It is supplied to fields (722, 724).

Figure 16 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the sixth embodiment of the present invention. In this embodiment, one gamma compensation voltage generator outputs gamma compensation voltages for data of two colors. To this end, register setting data for optimizing the gamma compensation voltage for each color is changed to be synchronized with the pixel data input to the DAC.

Referring to FIG. 16, the drive IC 300 includes first and second gamma compensation voltage generators 711 and 712, first to fourth DACs 721 to 724, and first to fourth output buffers (A). Includes ~D).

The first gamma compensation voltage generator 711 sequentially outputs a gamma compensation voltage for red data and a gamma compensation voltage for green data to be written in the green subpixel (G) of the first pixel group. The second gamma compensation voltage generator 712 sequentially outputs a gamma compensation voltage for blue data and a gamma compensation voltage for green data to be written in the green subpixel (G) of the second pixel group.

The first DAC 721 converts red data into a gamma compensation voltage from the first gamma compensation voltage generator 711 and generates a data voltage Vdata. The second DAC 722 converts green data to be written in the green subpixel (G) of the first pixel group into a gamma compensation voltage from the first gamma compensation voltage generator 711 and generates a data voltage (Vdata). .

The third DAC 723 converts the blue data into the gamma compensation voltage from the second gamma compensation voltage generator 712 and generates the data voltage Vdata. The fourth DAC 724 converts green data to be written in the green subpixel (G) of the second pixel group into a gamma compensation voltage from the second gamma compensation voltage generator 712 and generates a data voltage (Vdata). .

The first output buffer A supplies the data voltage Vdata sequentially input from the first and second DACs 721 and 722 to the input node of the switch array 113. One of the first and second DACs 721 and 722 outputs a delayed data voltage. The second output buffer B supplies the data voltage Vdata sequentially input from the third and fourth DACs 723 and 724 to the input node of the switch array 113. One of the third and fourth DACs 723 and 724 outputs a delayed data voltage.

Figure 17 is a circuit diagram showing the gamma compensation voltage generator, DAC, and output buffer of the drive IC according to the seventh embodiment of the present invention. In this embodiment, one gamma compensation voltage generator outputs gamma compensation voltages for data of two colors. To this end, register setting data for optimizing the gamma compensation voltage for each color is changed to be synchronized with the pixel data input to the DAC.

Referring to FIG. 17, the drive IC 300 includes first and second gamma compensation voltage generators 711 and 712, first to fourth DACs 721 to 724, and first to fourth output buffers (A). Includes ~D).

The first gamma compensation voltage generator 711 alternately outputs a gamma compensation voltage for data of the first color (R) and a gamma compensation voltage for data of the second color (G). The second gamma compensation voltage generator 712 alternately outputs a gamma compensation voltage for data of the third color (B) and a gamma compensation voltage for data of the second color (G).

The first and third DACs 721 and 723 sequentially receive first color data and second color data. The first and third DACs 721 and 723 convert the first color data into the gamma compensation voltage from the first gamma compensation voltage 711 and then convert the second color data into the gamma compensation voltage from the first gamma compensation voltage 711. ) to a gamma compensation voltage. The second and fourth DACs 722 and 724 sequentially receive third color data and third color data. The second and fourth DACs 722 and 724 convert the third color data into the gamma compensation voltage from the second gamma compensation voltage 712, and then convert the second color data into the gamma compensation voltage from the second gamma compensation voltage 712. ) to a gamma compensation voltage.

The first output buffer (A) supplies the data voltage (Vdata) input from the first DAC (721) to the input node of the switch array (113). The second output buffer B supplies the data voltage Vdata input from the second DAC 722 to the input node of the switch array 113. The third output buffer C supplies the data voltage Vdata input from the third DAC 723 to the input node of the switch array 113. The fourth output buffer D supplies the data voltage Vdata input from the fourth DAC 724 to the input node of the switch array 113.

FIG. 18 is a diagram summarizing the structure and performance of the drive IC shown in FIGS. 11 to 17. In FIG. 18, “N” means that the horizontal resolution of the pixel array where the pentile pixel as shown in FIG. 3 is to be placed is N. The drive IC 300 connected to the 1:2 demultiplexer (DM1, DM2) outputs a data voltage (Vdata) through N data output channels when the horizontal resolution is N. The 1:2 demultiplexers (DM1 and DM2) time-divide and distribute data voltages input twice in succession during 1 horizontal period from N channels of the drive IC 300 to 2N data lines during 1 horizontal period. The chip size of the drive IC is determined depending on the number of gamma compensation voltage generators (GAMMA Set), DAC, output buffer (AMP), and design structure. The DAC input may be delayed when two gamma compensation voltage generators share one DAC. The input to the output buffer (AMP) may be delayed if two DACs share one output buffer. In the case of a pentile pixel structure, the number of green subpixels in the pixel array is twice as large as subpixels of other colors. For this reason, like the gamma compensation voltage generator for other colors, when the gamma compensation voltage for green data is output from one gamma compensation voltage generator, the load on the DAC acting on the gamma compensation voltage generator may be doubled.

FIGS. 19A to 23 are diagrams showing various embodiments of a control method of the demultiplexer (DM1). In FIGS. 19B, 20B, and 21B, R11 to R33 are data voltages to be written in the red subpixel (R), and G11 to G34 are data voltages to be written to the green subpixel (R). B12 to B34 are data voltages to be written to the blue subpixel (B).

Referring to FIGS. 19A and 19B, pulses of the first and second MUX signals (MUX1 and MUX2) may be generated in the same order every horizontal period. In each horizontal period, the first switch element (S01) is first turned on according to the gate-on voltage (VGL) of the first MUX signal (MUX1) in the 1/2 horizontal period to connect the input node (S1) to the first data line. Connect. Subsequently, the second switch element S02 is turned on according to the gate-on voltage VGL of the second MUX signal MUX2 in the 1/2 horizontal period to connect the input node S2 to the second data line. In this embodiment, since the pulse of the second MUX signal (MUX1) is generated after the pulse of the first MUX signal (MUX1) in every horizontal period, the second switch element (S02) turns after the first switch element (S01). The turn-on sequence (MUX 1/2) is repeated every horizontal period.

20A to 21B are diagrams showing a control method of a demultiplexer according to a second embodiment of the present invention. Figures 20a and 20b show a control method of the demultiplexer during the Nth frame period (Nth FR). Figures 21a and 21b show a control method of the demultiplexer during the N+1th frame period [(N+1)th FR]. This embodiment can reduce the variation in charging amounts of subpixels by changing the switch on/off order of the demultiplexer DM1 every N horizontal period and every N frame period.

Referring to FIGS. 20A and 20B, pulses of the first and second MUX signals (MUX1, MUX2) are generated in the order of MUX1 -> MUX2 (MUX 1/2) in odd-numbered horizontal periods. Subsequently, pulses of the first and second MUX signals (MUX1, MUX2) are generated in the order of MUX2 -> MUX1 (MUX 2/1) in the even-th horizontal period. The first switch element (S01) is first turned on in response to the first MUX signal (MUX1) in the 1/2 horizontal period of the odd-numbered horizontal period, and then the second switch element (S02) is turned on in the 1/2 horizontal period. 2 Turns on in response to the MUX signal (MUX2). Subsequently, after the second switch element (S02) is turned on in response to the second MUX signal (MUX2) in the 1/2 horizontal period of the even-th horizontal period, the first switch element (S01) is turned on in the 1/2 horizontal period. It is turned on in response to the first MUX signal (MUX1).

Referring to FIGS. 21A and 21B, pulses of the first and second MUX signals (MUX1, MUX2) are generated in the order of MUX2 -> MUX1 (MUX 2/1) in odd-numbered horizontal periods. Subsequently, pulses of the first and second MUX signals (MUX1, MUX2) are generated in the order of MUX1 -> MUX2 (MUX 1/2) in the even-th horizontal period. The second switch element (S02) is first turned on in response to the second MUX signal (MUX2) in the 1/2 horizontal period of the odd-numbered horizontal period, and then the first switch element (S01) is turned on in the 1/2 horizontal period. 1 Turns on in response to the MUX signal (MUX1). Subsequently, after the first switch element (S01) is turned on in response to the first MUX signal (MUX1) in the 1/2 horizontal period of the even-th horizontal period, the second switch element (S02) is turned on in the 1/2 horizontal period. It is turned on in response to the second MUX signal (MUX2).

Figures 22 and 23 are examples of line option and frame option codes indicating the switch on/off order of the demultiplexer (DM2). Figure 22 is a line option defined by register setting data. Figure 23 is a frame option defined by register setting data. The timing controller 130 can control the switch on/off order of the demultiplexer DM1 according to register setting data as shown in FIGS. 22 and 23. The timing controller 130 controls the switch on/off of the demultiplexer (DM) based on one of the line options and one of the frame options or sequentially applies the line options and frame options in a preset order. The switch on/off of the demultiplexer (DM) can be controlled.

In the case of a pentile pixel structure as shown in FIG. 3, the green sub-pixels can be driven using two gamma compensation voltage generators to reduce the load caused by the green sub-pixels. In this case, when there is a deviation between the gamma compensation voltage generators, the first gamma compensation voltage generator is connected to the green subpixels of the first pixel group, and the second gamma compensation voltage generator is connected to the green subpixels of the second pixel group. When the structure connected to is fixed, a luminance difference between the first pixel group and the second pixel group may be visible. The present invention uses the switch array 113 as shown in FIGS. 24A to 25H to alternate the connection relationship between the gamma compensation voltage generators of the drive IC 300 and the pixels to create an offset between the gamma compensation voltage generators. ) can reduce the luminance difference due to

The drive IC 300 shown in FIGS. 24A to 25H is an example of the drive IC shown in FIG. 17, but the drive IC is not limited to this and can be applied to all of the first to seventh embodiments.

FIGS. 24A and 24B are diagrams showing an example of alternating the connection relationship between gamma compensation voltage generators, output buffers, and pixels on the time axis using the switch array shown in FIG. 9. FIG. 24A shows the operation of the switch array 113 when the data voltage Vdata is applied to even-numbered subpixels of the first pixel line L1 in the 2 1/2 horizontal period of the N-th frame period. FIG. 24A shows the operation of the switch array 113 when the data voltage Vdata is applied to the even-th subpixels of the first pixel line L1 in the 2 1/2 horizontal period of the N+1 frame period. give.

24A and 24B, G1 is a green subpixel of the first pixel group, and G2 is a green subpixel of the second pixel group. 1 displayed in the subpixels is the first gamma compensation voltage generator (GAMMA1, 711), and 2 is the second gamma compensation voltage generator (GAMMA2, 711). A, B, C and D shown in subpixels represent the output buffers of the corresponding reference numerals.

24A and 24B, the connection relationships between gamma compensation voltage generators, output buffers, and pixels are changed in a preset order on the time axis. Accordingly, the switch array 113 changes the connection relationship between the gamma compensation voltage generators, output buffers, and pixels to temporally detail the luminance difference between pixels.

Referring to FIG. 24A, the first and second gamma compensation voltage compensators 711 and 712 output a gamma compensation voltage for green data in the 2 1/2 horizontal period of the N-th frame period. At this time, the first and third DACs 721 and 723 convert green data to be written in the green sub-pixel G1 of the first pixel group into a gamma compensation voltage from the first gamma compensation voltage generator 711, and Outputs data voltage (Vdata). The second and fourth DACs 722 and 724 convert green data to be written in the green sub-pixel G2 of the second pixel group into a gamma compensation voltage from the second gamma compensation voltage generator 712 to produce a data voltage ( Vdata) is output.

The first output buffer (A) supplies the data voltage (Vdata) from the first DAC (721) to the first and fourth switch elements (a, d) of the switch array 113. The second output buffer (B) supplies the data voltage (Vdata) from the second DAC (722) to the second and third switch elements (b, d) of the switch array 113. The third output buffer C supplies the data voltage Vdata from the third DAC 723 to the fifth and eighth switch elements e and h of the switch array 113. The fourth output buffer D supplies the data voltage Vdata from the fourth DAC 724 to the sixth and seventh switch elements f and g of the switch array 113.

In the 2 1/2 horizontal period of the N-th frame period, the first, third, fifth and seventh switch elements (a, c, e, g) of the switch array 113 are turned on, and the demultiplexer When the second switch elements S02 of the array 111 are turned on, the first gamma compensation voltage generator 711, the DAC 721 or 723, and a data voltage from the output buffer (A or C) is supplied. At this time, the data voltage from the second gamma compensation voltage generator 712, the DAC (722 or 724), and the output buffer (B or D) is supplied to the green subpixels (G2) of the second pixel group. If there is an offset difference between the gamma compensation voltage generators 711 and 712, a luminance difference between the first pixel group and the second pixel group may be visible at the same gray level.

Referring to FIG. 24B, the first and second gamma compensation voltage compensators 711 and 712 output a gamma compensation voltage for green data in the 2 1/2 horizontal period of the N+1 frame period. At this time, the first and third DACs 721 and 723 convert the green data to be written in the green sub-pixel G2 of the second pixel group into a gamma compensation voltage from the first gamma compensation voltage generator 711. Outputs data voltage (Vdata). The second and fourth DACs 722 and 724 convert green data to be written in the green sub-pixel G1 of the first pixel group into a gamma compensation voltage from the second gamma compensation voltage generator 712 to produce a data voltage ( Vdata) is output.

The first output buffer (A) supplies the data voltage (Vdata) from the first DAC (721) to the first and fourth switch elements (a, d) of the switch array 113. The second output buffer (B) supplies the data voltage (Vdata) from the second DAC (722) to the second and third switch elements (b, d) of the switch array 113. The third output buffer C supplies the data voltage Vdata from the third DAC 723 to the fifth and eighth switch elements e and h of the switch array 113. The fourth output buffer D supplies the data voltage Vdata from the fourth DAC 724 to the sixth and seventh switch elements f and g of the switch array 113.

In the 2 1/2 horizontal period of the N+1 frame period, the second, fourth, sixth and eighth switch elements (b, d, f, h) of the switch array 113 are turned on. , when the second switch elements S02 of the demultiplexer array 111 are turned on, the second gamma compensation voltage generator 712 and the DAC 722 or 724 are applied to the green subpixels G1 of the first pixel group. ), and the data voltage from the output buffer (B or D) is supplied. At this time, the data voltage from the first gamma compensation voltage generator 711, the DAC (721 or 723), and the output buffer (A or C) is supplied to the green subpixels (G2) of the second pixel group.

FIGS. 25A to 25H are diagrams showing an example of alternating the connection relationship between gamma compensation voltage generators, output buffers, and pixels on the time axis using the switch array shown in FIG. 10. The pixels shown in FIGS. 25A to 25H not only change their connection relationships with gamma compensation voltages on the time axis in a preset order by the switch array 113, but also change the pixels in the first to fourth output buffers (A, B, C and B) are sequentially connected to each other, and the connection relationship with the output buffers (A, B, C, B) on the time axis changes in a preset order. Therefore, in FIGS. 25A to 25H, the luminance difference due to the deviation between the gamma voltage compensation generators 711 and 712 and the output buffers A, B, C, and B is canceled on the time axis to reduce the luminance difference between pixels. Minimize.

FIG. 25A shows the operation of the switch array 113 when the data voltage Vdata is applied to odd-numbered subpixels of the first pixel line L1 in the 1/2 horizontal period of the N-th frame period. FIG. 25B shows the operation of the switch array 113 when the data voltage Vdata is applied to even-numbered subpixels of the first pixel line L1 in the 2 1/2 horizontal period of the N-th frame period. FIG. 25C shows the operation of the switch array 113 when the data voltage Vdata is applied to odd-numbered subpixels of the second pixel line L2 in the 3 1/2 horizontal period of the N-th frame period. FIG. 25D shows the operation of the switch array 113 when the data voltage Vdata is applied to the even-th subpixels of the second pixel line L1 in the 4 1/2 horizontal period of the N-th frame period.

FIG. 25e shows the operation of the switch array 113 when the data voltage Vdata is applied to odd-numbered subpixels of the first pixel line L1 in the first 1/2 horizontal period of the N+1 frame period. give. FIG. 25F shows the operation of the switch array 113 when the data voltage Vdata is applied to the even-th subpixels of the first pixel line L1 in the 2 1/2 horizontal period of the N+1 frame period. give. FIG. 25g shows the operation of the switch array 113 when the data voltage Vdata is applied to odd-numbered subpixels of the second pixel line L2 in the 3 1/2 horizontal period of the N+1 frame period. give. FIG. 25h shows the operation of the switch array 113 when the data voltage Vdata is applied to the even-th subpixels of the second pixel line L1 in the 4 1/2 horizontal period of the N+1 frame period. give.

25A to 25H, 1 indicated in the subpixels is the first gamma compensation voltage generator (GAMMA1, 711), and 2 is the second gamma compensation voltage generator (GAMMA2, 711). A, B, C and D shown in subpixels represent the output buffers of the corresponding reference numerals.

Referring to FIG. 25A, the first gamma compensation voltage compensator 711 outputs a gamma compensation voltage for red data in the first 1/2 horizontal period of the N-th frame period. The second gamma compensation voltage compensator 712 outputs a gamma compensation voltage for blue data in the first 1/2 horizontal period of the N-th frame period. At this time, the first and third DACs 721 and 723 convert red data to be written into the red subpixel R of the first pixel line L1 into a gamma compensation voltage from the first gamma compensation voltage generator 711. Convert it to output the data voltage (Vdata). The second and fourth DACs 722 and 724 convert the blue data to be written in the blue sub-pixel B of the first pixel line L1 into a gamma compensation voltage from the second gamma compensation voltage generator 712. Outputs data voltage (Vdata).

The first output buffer (A) transmits the data voltage (Vdata) from the first DAC (721) to the first, seventh, tenth, and sixteenth switch elements (a, g, k, supplied to p). The second output buffer (B) transmits the data voltage (Vdata) from the second DAC (722) to the third, fifth, twelfth, and fourteenth switch elements (c, e, l, supplied to n). The third output buffer (C) transmits the data voltage (Vdata) from the third DAC (723) to the second, eighth, ninth, and fifteenth switch elements (b, h, i, o). The fourth output buffer (D) transmits the data voltage (Vdata) from the fourth DAC (724) to the fourth, sixth, eleventh, and thirteenth switch elements (d, f, l, m).

In the 1 1/2 horizontal period of the N-th frame period, the first, fifth, ninth and thirteenth switch elements (a, e, i, m) of the switch array 113 are turned on, and the demultiplexer When the first switch elements S01 of the array 111 are turned on, the first gamma compensation voltage generator 711, the DAC 721, or 723), and the data voltage from the output buffer (A or C) is supplied. At the same time, the data voltage from the second gamma compensation voltage generator 712, the DAC (722 or 724), and the output buffer (B or D) is applied to the blue subpixels (B) of the first pixel line (L1). supplied.

Referring to FIG. 25B, the first and second gamma compensation voltage compensators 711 and 712 each output a gamma compensation voltage for green data in the second 1/2 horizontal period of the N-th frame period. At this time, the first and third DACs 721 and 723 send green data to be written to the green subpixels G1 of the first pixel group on the first pixel line L1 to the first gamma compensation voltage generator 711. ) is converted into a gamma compensation voltage to output the data voltage (Vdata). The second and fourth DACs 722 and 724 convert green data to be written to the green sub-pixel G2 of the second pixel group on the first pixel line L1 into gamma compensation from the second gamma compensation voltage generator 712. Converts it to a compensation voltage and outputs a data voltage (Vdata).

The first output buffer (A) transmits the data voltage (Vdata) from the first DAC (721) to the first, seventh, tenth, and sixteenth switch elements (a, g, k, supplied to p). The second output buffer (B) transmits the data voltage (Vdata) from the second DAC (722) to the third, fifth, twelfth, and fourteenth switch elements (c, e, l, supplied to n). The third output buffer (C) transmits the data voltage (Vdata) from the third DAC (723) to the second, eighth, ninth, and fifteenth switch elements (b, h, i, o). The fourth output buffer (D) transmits the data voltage (Vdata) from the fourth DAC (724) to the fourth, sixth, eleventh, and thirteenth switch elements (d, f, l, m).

In the 2 1/2 horizontal period of the N-th frame period, the second, sixth, tenth and fourteenth switch elements (b, f, j, n) of the switch array 113 are turned on, and the demultiplexer When the second switch elements S02 of the array 111 are turned on, the first gamma compensation voltage generator 711 is applied to the green subpixels G1 of the first pixel group on the first pixel line L1. , the data voltage from the DAC (721 or 723), and the output buffer (A or C) are supplied. At the same time, the second gamma compensation voltage generator 712, the DAC (722 or 724), and the output buffer (B or D) are applied to the green subpixels (G2) of the second pixel group in the first pixel line (L1). The data voltage from is supplied.

Referring to FIG. 25C, the first gamma compensation voltage compensator 711 outputs a gamma compensation voltage for red data in the third 1/2 horizontal period of the N-th frame period. The second gamma compensation voltage compensator 712 outputs a gamma compensation voltage for blue data in the third 1/2 horizontal period of the N-th frame period. At this time, the first and third DACs 721 and 723 convert red data to be written into the red subpixel R of the second pixel line L2 into a gamma compensation voltage from the first gamma compensation voltage generator 711. Convert it to output the data voltage (Vdata). The second and fourth DACs 722 and 724 convert the blue data to be written in the blue sub-pixel B of the second pixel line L2 into a gamma compensation voltage from the second gamma compensation voltage generator 712. Outputs data voltage (Vdata).

The first output buffer (A) transmits the data voltage (Vdata) from the first DAC (721) to the first, seventh, tenth, and sixteenth switch elements (a, g, k, supplied to p). The second output buffer (B) transmits the data voltage (Vdata) from the second DAC (722) to the third, fifth, twelfth, and fourteenth switch elements (c, e, l, supplied to n). The third output buffer (C) transmits the data voltage (Vdata) from the third DAC (723) to the second, eighth, ninth, and fifteenth switch elements (b, h, i, o). The fourth output buffer (D) transmits the data voltage (Vdata) from the fourth DAC (724) to the fourth, sixth, eleventh, and thirteenth switch elements (d, f, l, m).

In the 3 1/2 horizontal period of the N-th frame period, the 3rd, 7th, 11th and 15th switch elements (c, g, k, o) of the switch array 113 are turned on, and the demultiplexer When the first switch elements S01 of the array 111 are turned on, the second gamma compensation voltage generator 712, the DAC 722, or 724), and the data voltage from the output buffer (B or D) is supplied. At the same time, the data voltage from the first gamma compensation voltage generator 711, the DAC (721 or 723), and the output buffer (A or C) is applied to the red subpixels (R) of the second pixel line (L2). supplied.

Referring to FIG. 25D, the first and second gamma compensation voltage compensators 711 and 712 each output a gamma compensation voltage for green data in the fourth 1/2 horizontal period of the Nth frame period. At this time, the first and third DACs 721 and 723 send green data to be written to the green subpixels G2 of the second pixel group on the second pixel line L2 to the first gamma compensation voltage generator 711. ) is converted into a gamma compensation voltage to output the data voltage (Vdata). The second and fourth DACs 722 and 724 convert green data to be written to the green sub-pixel G1 of the first pixel group on the second pixel line L2 into a gamma compensation signal from the second gamma compensation voltage generator 712. Converts it to a compensation voltage and outputs a data voltage (Vdata).

The first output buffer (A) transmits the data voltage (Vdata) from the first DAC (721) to the first, seventh, tenth, and sixteenth switch elements (a, g, k, supplied to p). The second output buffer (B) transmits the data voltage (Vdata) from the second DAC (722) to the third, fifth, twelfth, and fourteenth switch elements (c, e, l, supplied to n). The third output buffer (C) transmits the data voltage (Vdata) from the third DAC (723) to the second, eighth, ninth, and fifteenth switch elements (b, h, i, o). The fourth output buffer (D) transmits the data voltage (Vdata) from the fourth DAC (724) to the fourth, sixth, eleventh, and thirteenth switch elements (d, f, l, m).

In the fourth 1/2 horizontal period of the N-th frame period, the fourth, eighth, twelfth and sixteenth switch elements (d, h, l, p) of the switch array 113 are turned on, and the demultiplexer When the second switch elements S02 of the array 111 are turned on, the second gamma compensation voltage generator 712 is applied to the green subpixels G1 of the first pixel group in the second pixel line L2. , the data voltage from the DAC (722 or 724), and the output buffer (B or D) are supplied. At the same time, the first gamma compensation voltage generator 711, the DAC (721 or 723), and the output buffer (A or C) are applied to the green subpixels (G2) of the second pixel group in the second pixel line (L2). The data voltage from is supplied.

Referring to FIG. 25E, the first gamma compensation voltage compensator 711 outputs a gamma compensation voltage for red data in the first 1/2 horizontal period of the N+1th frame period. The second gamma compensation voltage compensator 712 outputs a gamma compensation voltage for blue data in the first 1/2 horizontal period of the N+1th frame period. At this time, the first and third DACs 721 and 723 perform gamma compensation for red data to be written in the red subpixels R of the first pixel line L1 from the first gamma compensation voltage generator 711. Converts to voltage and outputs data voltage (Vdata). The second and fourth DACs 722 and 724 convert blue data to be written in the blue subpixels B of the first pixel line L1 into a gamma compensation voltage from the second gamma compensation voltage generator 712. to output the data voltage (Vdata).

The first output buffer (A) transmits the data voltage (Vdata) from the first DAC (721) to the first, seventh, tenth, and sixteenth switch elements (a, g, k, supplied to p). The second output buffer (B) transmits the data voltage (Vdata) from the second DAC (722) to the third, fifth, twelfth, and fourteenth switch elements (c, e, l, supplied to n). The third output buffer (C) transmits the data voltage (Vdata) from the third DAC (723) to the second, eighth, ninth, and fifteenth switch elements (b, h, i, o). The fourth output buffer (D) transmits the data voltage (Vdata) from the fourth DAC (724) to the fourth, sixth, eleventh, and thirteenth switch elements (d, f, l, m).

In the 1 1/2 horizontal period of the N+1 frame period, the second, sixth, tenth and fourteenth switch elements (b, f, j, n) of the switch array 113 are turned on. , When the first switch elements S01 of the demultiplexer array 111 are turned on, the first gamma compensation voltage generator 711 and the DAC ( 721 or 723), and a data voltage from the output buffer (A or C) is supplied. At the same time, the data voltage from the second gamma compensation voltage generator 712, the DAC (722 or 724), and the output buffer (B or D) is applied to the blue subpixels (B) of the first pixel line (L1). supplied.

Referring to FIG. 25F, the first and second gamma compensation voltage compensators 711 and 712 each output a gamma compensation voltage for green data in the 2 1/2 horizontal period of the N+1 frame period. At this time, the first and third DACs 721 and 723 send green data to be written to the green subpixels G2 of the second pixel group on the first pixel line L1 to the first gamma compensation voltage generator 711. ) is converted into a gamma compensation voltage to output the data voltage (Vdata). The second and fourth DACs 722 and 724 convert green data to be written to the green sub-pixel G1 of the first pixel group on the first pixel line L1 into gamma compensation from the second gamma compensation voltage generator 712. Converts it to a compensation voltage and outputs a data voltage (Vdata).

The first output buffer (A) transmits the data voltage (Vdata) from the first DAC (721) to the first, seventh, tenth, and sixteenth switch elements (a, g, k, supplied to p). The second output buffer (B) transmits the data voltage (Vdata) from the second DAC (722) to the third, fifth, twelfth, and fourteenth switch elements (c, e, l, supplied to n). The third output buffer (C) transmits the data voltage (Vdata) from the third DAC (723) to the second, eighth, ninth, and fifteenth switch elements (b, h, i, o). The fourth output buffer (D) transmits the data voltage (Vdata) from the fourth DAC (724) to the fourth, sixth, eleventh, and thirteenth switch elements (d, f, l, m).

In the 2 1/2 horizontal period of the N+1 frame period, the 3rd, 7th, 11th and 15th switch elements (c, g, k, o) of the switch array 113 are turned on. , When the second switch elements S02 of the demultiplexer array 111 are turned on, the second gamma compensation voltage generator ( 712), the DAC (722 or 724), and the data voltage from the output buffer (B or D) are supplied. At the same time, the first gamma compensation voltage generator 711, the DAC (721 or 723), and the output buffer (A or C) are applied to the green subpixels (G2) of the second pixel group in the first pixel line (L1). The data voltage from is supplied.

Referring to FIG. 25g, the first gamma compensation voltage compensator 711 outputs a gamma compensation voltage for red data in the third 1/2 horizontal period of the N+1th frame period. The second gamma compensation voltage compensator 712 outputs a gamma compensation voltage for blue data in the third 1/2 horizontal period of the N+1th frame period. At this time, the first and third DACs 721 and 723 perform gamma compensation for red data to be written in the red subpixels R of the second pixel line L2 from the first gamma compensation voltage generator 711. Converts to voltage and outputs data voltage (Vdata). The second and fourth DACs 722 and 724 convert blue data to be written in the blue subpixels B of the second pixel line L2 into a gamma compensation voltage from the second gamma compensation voltage generator 712. to output the data voltage (Vdata).

The first output buffer (A) transmits the data voltage (Vdata) from the first DAC (721) to the first, seventh, tenth, and sixteenth switch elements (a, g, k, supplied to p). The second output buffer (B) transmits the data voltage (Vdata) from the second DAC (722) to the third, fifth, twelfth, and fourteenth switch elements (c, e, l, supplied to n). The third output buffer (C) transmits the data voltage (Vdata) from the third DAC (723) to the second, eighth, ninth, and fifteenth switch elements (b, h, i, o). The fourth output buffer (D) transmits the data voltage (Vdata) from the fourth DAC (724) to the fourth, sixth, eleventh, and thirteenth switch elements (d, f, l, m).

In the 3 1/2 horizontal period of the N+1 frame period, the 4th, 8th, 12th and 16th switch elements (d, h, l, p) of the switch array 113 are turned on. , When the first switch elements S01 of the demultiplexer array 111 are turned on, the second gamma compensation voltage generator 712 and the DAC ( 722 or 724), and a data voltage from the output buffer (B or D) is supplied. At the same time, the data voltage from the first gamma compensation voltage generator 711, the DAC (721 or 723), and the output buffer (A or C) is applied to the red subpixels (R) of the second pixel line (L2). supplied.

Referring to FIG. 25H, the first and second gamma compensation voltage compensators 711 and 712 each output a gamma compensation voltage for green data in the fourth 1/2 horizontal period of the N+1th frame period. At this time, the first and third DACs 721 and 723 send green data to be written to the green subpixels G1 of the first pixel group on the second pixel line L2 to the first gamma compensation voltage generator 711. ) is converted into a gamma compensation voltage to output the data voltage (Vdata). The second and fourth DACs 722 and 724 convert green data to be written to the green sub-pixel G2 of the second pixel group on the second pixel line L2 into gamma compensation from the second gamma compensation voltage generator 712. Converts it to a compensation voltage and outputs a data voltage (Vdata).

The first output buffer (A) transmits the data voltage (Vdata) from the first DAC (721) to the first, seventh, tenth, and sixteenth switch elements (a, g, k, supplied to p). The second output buffer (B) transmits the data voltage (Vdata) from the second DAC (722) to the third, fifth, twelfth, and fourteenth switch elements (c, e, l, supplied to n). The third output buffer (C) transmits the data voltage (Vdata) from the third DAC (723) to the second, eighth, ninth, and fifteenth switch elements (b, h, i, o). The fourth output buffer (D) transmits the data voltage (Vdata) from the fourth DAC (724) to the fourth, sixth, eleventh, and thirteenth switch elements (d, f, l, m).

In the 4 1/2 horizontal period of the N+1 frame period, the first, fifth, ninth and thirteenth switch elements (a, e, i, m) of the switch array 113 are turned on. , When the second switch elements S02 of the demultiplexer array 111 are turned on, the first gamma compensation voltage generator ( 711), the DAC (721 or 723), and the data voltage from the output buffer (A or C) are supplied. At the same time, the second gamma compensation voltage generator 712, the DAC (722 or 724), and the output buffer (B or D) are applied to the green subpixels (G2) of the second pixel group in the second pixel line (L2). The data voltage from is supplied.

Switching on/off of the switch array 113 and the demultiplexer array 111 is defined by register setting data stored in the memory 132. The timing controller 130 controls the on/off timing of switch elements of the switch array 113 and the demultiplexer array 111 according to register setting data.

FIG. 26 is a diagram illustrating an example in which the connection relationship between green subpixels and gamma compensation voltage generators in the embodiments shown in FIGS. 24A to 25H is alternated between pixel lines and alternated on a frame period basis. In Figure 26, 1 is the first gamma compensation voltage generator (GAMMA1, 711), and 2 is the second gamma compensation voltage generator (GAMMA2, 711). EMB1 is the embodiment shown in FIGS. 24A and 24B. EMB2 is the embodiment shown in FIGS. 25A to 25H.

As can be seen in FIG. 26, since each of the green subpixels is alternately connected to the gamma compensation voltage generators 711 and 712 on the time axis, even if there is a deviation between the gamma compensation voltage generators 711 and 712, the luminance difference is temporal. is offset, so the luminance difference is not visible.

FIG. 27 is a diagram showing an example in which the connection relationship between subpixels and output buffers alternates between pixel lines and alternates on a frame period basis in the embodiments shown in FIGS. 24A to 25H. In Figure 27, A, B, C, and D indicate output buffers with corresponding reference numerals. EMB1 is the embodiment shown in FIGS. 24A and 24B. EMB2 is the embodiment shown in FIGS. 25A to 25H.

As can be seen in FIG. 27, since all subpixels are alternately connected between two or four of the output buffers (A, B, C, D) on the time axis, the output buffers (A, B, C) , D) Even if there is a deviation between the luminance differences, the luminance differences are canceled out in time, so the luminance differences are not visible.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

100: display panel 110: data driver
111 (DM1, DM2): Demultiplexer array
112, 711~714: Gamma compensation voltage generator
120: Gate driver 130: Timing controller
132: second memory 134: level shifter
136: power unit 200: host system
210: first memory 300: drive IC
721~724: DAC P: Pixel
A~D, AMP: Output buffer of drive IC
a~p: switch elements of switch array
S01, S02: Switch element of demultiplexer

Claims (12)

a pixel array including a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels connected to the data lines and the gate lines;
a data driver that outputs a data voltage through a plurality of output buffers;
a demultiplexer sequentially connecting input nodes to the plurality of data lines;
a switch array that sequentially connects the output buffers of the data driver to input nodes of the demultiplexer and changes the connection relationship between the output buffers and the input nodes of the demultiplexer on a frame period basis;
a first gamma compensation voltage generator that alternately outputs a gamma compensation voltage for data of a first color and a gamma compensation voltage for data of a second color;
a second gamma compensation voltage generator that alternately outputs a gamma compensation voltage for data of the second color and a gamma compensation voltage for data of a third color;
first and third digital-to-analog converters that convert the first color data and the second color data into a gamma compensation voltage from the first gamma compensation voltage generator; and
Second and fourth digital-to-analog converters that convert the second color data and the third color data into a gamma compensation voltage from the second gamma compensation voltage generator,
The output buffers include first to fourth output buffers respectively connected between the first to fourth digital-to-analog converters and the switch array,
The switch array is
a first switch element connected between the first output buffer and an input node of the first demultiplexer;
a second switch element connected between the second output buffer and the input node of the first demultiplexer;
a third switch element connected between the second output buffer and the input node of the second demultiplexer; and
a fourth switch element connected between the first output buffer and the input node of the second demultiplexer;
a fifth switch element connected between the third output buffer and the input node of the third demultiplexer;
a sixth switch element connected between the fourth output buffer and the input node of the third demultiplexer;
a seventh switch element connected between the fourth output buffer and the input node of the fourth demultiplexer; and
Further comprising an eighth switch element connected between the third output buffer and the input node of the fourth demultiplexer,
A display device in which on/off timing settings of the first to eighth switch elements are changed on a frame period basis. According to claim 1,
The demultiplexer is a display device that changes the connection relationship between the input nodes and data lines in units of the frame period. According to claim 2,
A display device further comprising a timing controller that changes switch on/off timing of the demultiplexer and the switch array in units of the frame period. delete delete delete According to claim 1,
The first output buffer supplies a data voltage from a first digital-to-analog converter to the first and fourth switch elements,
The second output buffer supplies a data voltage from a second digital-to-analog converter to the second and third switch elements,
The third output buffer supplies data voltage from a third digital-to-analog converter to the fifth and eighth switch elements,
The fourth output buffer supplies a data voltage from a fourth digital-to-analog converter to the sixth and seventh switch elements. According to claim 7,
The first demultiplexer time-divisionally distributes the data voltage from the switch array to first and second data lines,
The second demultiplexer time-divisionally distributes the data voltage from the switch array to third and fourth data lines,
The third demultiplexer time-divisionally distributes the data voltage from the switch array to sixth and seventh data lines,
The fourth demultiplexer time-divisionally distributes the data voltage from the switch array to the seventh and eighth data lines. According to claim 1,
The switch array is,
a first switch element connected between the first output buffer and the input node of the first demultiplexer;
a second switch element connected between a third output buffer and an input node of the first demultiplexer;
a third switch element connected between the second output buffer and the input node of the first demultiplexer;
a fourth switch element connected between the fourth output buffer and the input node of the first demultiplexer;
a fifth switch element connected between the second output buffer and the input node of the second demultiplexer;
a sixth switch element connected between the fourth output buffer and the input node of the second demultiplexer;
a seventh switch element connected between the first output buffer and the input node of the second demultiplexer;
an eighth switch element connected between the third output buffer and the input node of the second demultiplexer;
a ninth switch element connected between the third output buffer and the input node of the third demultiplexer;
a tenth switch element connected between the first output buffer and the input node of the third demultiplexer;
an eleventh switch element connected between the fourth output buffer and the input node of the third demultiplexer;
a twelfth switch element connected between the second output buffer and the input node of the third demultiplexer;
a thirteenth switch element connected between the fourth output buffer and the input node of the fourth demultiplexer;
a fourteenth switch element connected between the second output buffer and the input node of the fourth demultiplexer;
a fifteenth switch element connected between the third output buffer and the input node of the fourth demultiplexer; and
A sixteenth switch element connected between the first output buffer and the input node of the fourth demultiplexer,
A display device in which on/off timing settings of the first to sixteenth switch elements are changed on a frame period basis. According to clause 9,
The first output buffer supplies the data voltage from the first digital-to-analog converter to the first, seventh, tenth, and sixteenth switch elements,
The second output buffer supplies the data voltage from the second digital-to-analog converter to the third, fifth, twelfth, and fourteenth switch elements,
The third output buffer supplies the data voltage from the third digital-to-analog converter to the second, eighth, ninth, and fifteenth switch elements,
The fourth output buffer supplies the data voltage from the fourth digital-to-analog converter to the fourth, sixth, eleventh, and thirteenth switch elements. According to claim 10,
The first demultiplexer time-divisionally distributes the data voltage from the switch array to first and second data lines,
The second demultiplexer time-divisionally distributes the data voltage from the switch array to third and fourth data lines,
The third demultiplexer time-divisionally distributes the data voltage from the switch array to sixth and seventh data lines,
The fourth demultiplexer time-divisionally distributes the data voltage from the switch array to the seventh and eighth data lines. a pixel array including a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels connected to the data lines and the gate lines;
a first gamma compensation voltage generator that alternately outputs a gamma compensation voltage for data of a first color and a gamma compensation voltage for data of a second color;
a second gamma compensation voltage generator that alternately outputs a gamma compensation voltage for data of the second color and a gamma compensation voltage for data of a third color;
first and third digital-to-analog converters that convert the first color data and the second color data into a gamma compensation voltage from the first gamma compensation voltage generator;
second and fourth digital-to-analog converters that convert the second color data and the third color data into a gamma compensation voltage from the second gamma compensation voltage generator;
a first output buffer connected to an output node of the first digital-to-analog converter;
a second output buffer connected to the output node of the second digital-to-analog converter;
a third output buffer connected to the output node of the third digital-to-analog converter;
a fourth output buffer connected to the output node of the fourth digital-to-analog converter;
a demultiplexer sequentially connecting input nodes to the plurality of data lines; and
A switch array sequentially connects the output buffers to the input nodes of the demultiplexer and changes the connection relationship between the output buffers and the input nodes of the demultiplexer on a frame period basis,
The switch array is
a first switch element connected between the first output buffer and an input node of the first demultiplexer;
a second switch element connected between the second output buffer and the input node of the first demultiplexer;
a third switch element connected between the second output buffer and the input node of the second demultiplexer; and
a fourth switch element connected between the first output buffer and the input node of the second demultiplexer;
a fifth switch element connected between the third output buffer and the input node of the third demultiplexer;
a sixth switch element connected between the fourth output buffer and the input node of the third demultiplexer;
a seventh switch element connected between the fourth output buffer and the input node of the fourth demultiplexer; and
Further comprising an eighth switch element connected between the third output buffer and the input node of the fourth demultiplexer,
A display device in which on/off timing settings of the first to eighth switch elements are changed on a frame period basis.