KR20150135615A - Display device and method of driving the same - Google Patents

Abstract

The present invention relates to a display device and a method for driving the same and, more specifically, is to provide a display device which uses a lock signal that determines whether or not a data driver is being normally operated so as to supply a driving voltage to the data driver when the data driver is normally operated, and a method for manufacturing the display device. To this end, the display device according to the present invention comprises: a panel in which gate lines and data lines are formed; two or more data drivers which supply a data voltage to the data lines; a timing controller which transmits a lock signal to any one of the data drivers, sends image data to the data driver when the lock signal sequentially passing through the data drivers is received, and enables the data driver to generate the data voltage; a determination unit which outputs an enable signal when the lock signal sent to the timing controller is received; and a power driver which supplies a driving voltage for driving the data drivers to the data drivers when the enable signal is received from the determination unit.

Description

DISPLAY APPARATUS AND DRIVING METHOD THEREOF

The present invention relates to a display device and a driving method thereof, and more particularly, to a display device including a timing controller and a data driver performing communication in a point-to-point manner (EPI) and a driving method thereof.

Flat panel displays are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. 2. Description of the Related Art Flat panel displays include liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting display devices. Recently, electrophoretic display devices (EPDs) Is also widely used.

Among flat panel display devices (hereinafter, simply referred to as 'display devices'), liquid crystal display devices are devices for displaying images using optical anisotropy of liquid crystal, and have advantages of thinness, small size, low power consumption, It is widely used.

Among the display devices, the organic light emitting display uses self-luminous elements that emit light by itself, and thus has advantages such as a fast response speed, a high luminous efficiency, a high luminance, and a large viewing angle. .

Fig. 1 is a diagram showing a configuration of a conventional display device, and shows a display device including a timing controller 40 and a data driver 30 that perform communication in a point-to-point manner (EPI). 2 is a diagram showing an example in which a driving voltage is supplied from a power driver constituting a conventional display device to a data driver.

The display device includes a panel 10, a data driver 30, a gate driver 20, and a timing controller 40.

A point-to-point method is used as a method for the timing controller 40 and the data driver 30 to perform communication. The point-to-point method is also referred to as an embedded clock point-to-point interface (EPI) method. In the display device using the EPI scheme, the timing controller 40 and the data driver 30 perform one-to-one communication. The display device using the EPI scheme is described in detail in a patent document such as the disclosure number 10-2010-0068938.

When power is supplied to the display device using the EPI scheme, the timing controller 40 supplies a lock signal to the first data driver (SDIC # 1) 30. The lock signal is sequentially transmitted to the second to eighth data drivers (SDIC # 2 to SDIC # 8), and the eighth data driver transmits the lock signal to the timing controller. When the lock signal is normally received, the timing controller 40 supplies image data to the data drivers 30, and the data drivers 30 supply the data voltages corresponding to the image data to the panel 10, The panel 10 outputs an image.

For driving the data driver 30, a power driver 60 composed of a power integrated circuit (P-IC) supplies a driving voltage VDD to the data driver 30.

The power driver 60 is driven by an enable signal EN transmitted from the timing controller 40 and supplies the driving voltage VDD to the data driver 30. [

In this case, when power is supplied from the outside, the timing controller 40 transmits the enable signal EN to the power driver 60 regardless of whether the lock signal is normally received or not. For example, the power driver 60 supplies the driving voltage VDD to the data driver 30 when the enable signal EN is received.

As described above, in the conventional display device, since the drive voltage is supplied to the data driver 30 regardless of the lock signal, the lock signal is not received by the timing controller and the data driver 30 The driving voltage VDD can be supplied to the data driver 30 even when it is abnormally driven.

In this case, the driving voltage line through which the driving voltage VDD is transmitted can be removed. For example, even when the data driver 30 is not normally driven, since the driving voltage VDD is continuously supplied to the data driver 30, the driving voltage line or the data driver 30 30 and a connector to which the driving voltage line is connected. Also, since the data driver 30 is not normally operated, the data driver 30 can not normally perform the protection function, and thus the data driver 30 may be damaged.

Even when the data driver 30 is not normally connected to the panel 10 or the timing controller 40, the above-described phenomenon may occur.

If an abnormal mode occurs during driving of the display device and the LOCK signal is not normally transmitted to the next data driver 30, the data driver is not operated and an abnormal screen is output through the panel 10 . If an abnormal screen is output for 1 to 2 minutes or more, a connector or a tab connected to the data driver 30 or the driving voltage line may be removed by an overcurrent or the like.

As described above, in the conventional display device, since the drive voltage VDD is supplied to the data driver 30 even in the abnormal mode in which the lock signal is not normally received by the timing controller 40, A voltage line may be formed and a connector or a tab connecting the driving voltage line and the data driver may be removed and the data driver 30 may be damaged.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-mentioned problems, and it is an object of the present invention to provide a data driver that uses a lock signal to determine whether a data driver is normally driven, A display device, and a method of driving the display device.

According to an aspect of the present invention, there is provided a display device including: a panel having gate lines and data lines formed therein; At least two data drivers for supplying a data voltage to the data lines; And a timing controller for transmitting the lock signal to any one of the data drivers and transmitting the image data to the data driver when the lock signal sequentially passed through the data drivers is received, controller; A determination unit for outputting an enable signal when the lock signal transmitted to the timing controller is received; And a power driver for supplying a driving voltage for driving the data drivers to the data drivers when the enable signal is received from the determination unit.

According to another aspect of the present invention, there is provided a method of driving a display device, the method comprising: transmitting a lock signal to a data driver of at least two data drivers; Receiving the lock signal sequentially passed through the data drivers, the timing controller transmitting image data to the data drivers; Outputting the enable signal to the power driver when the lock signal transmitted to the timing controller is received; The power driver supplying a drive voltage to the data drivers; And converting the image data into a data voltage using the driving voltage and outputting the data voltage to the data lines formed on the panel and outputting the image to the panel .

According to the present invention, since the drive voltage is not supplied to the data driver when the data driver is not normally driven, damage to the line to which the drive voltage is supplied to the data driver or the data driver can be prevented. That is, according to the present invention, when the data driver using the EPI scheme is abnormally driven, the data driver can be protected.

Particularly, according to the present invention, by controlling the output of the enable signal input to the power driver by using the lock signal (LOCK) input to the timing controller and the determination unit, (Eg, FFC open, driver IC damage, etc.) occurs, a phenomenon in which parts connected to the data driver are fired (source tab power line burnt) can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an exemplary view showing a configuration of a conventional display device. Fig.
FIG. 2 is an exemplary view showing a state in which a driving voltage is supplied from a power driver constituting a conventional display device to a data driver; FIG.
3 is an exemplary view showing a configuration of a display device according to the present invention.
FIG. 4 is an exemplary diagram showing signals transmitted between a power driver and a data driver, which are applied to a display device according to the present invention. FIG.
5 is an exemplary view showing a configuration of a determination unit applied to a display device according to the present invention;
6 is an exemplary view showing a configuration of a power driver applied to a display device according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is an exemplary view showing a configuration of a display device according to the present invention.

3, the display device according to the present invention uses an embedded clock point-to-point interface (EPI) method. The panel 100 includes gate lines GL and data lines DL, At least two data drivers 300 for supplying a data voltage to the data lines DL and a lock signal LOCK to one of the data drivers 300, A timing controller 400 for transmitting the image data to the data driver 300 and generating the data voltage by the data driver 300 when the received lock signal is received, And a control unit 500 for outputting the enable signal EN when the enable signal EN is received from the control unit 500. The control unit 500 controls the data drivers 300 And a power driver 600 for supplying the data driver 300 with a driving voltage VDD for driving the data driver 300. 3, a display device provided with eight data drivers (SDIC # 1 to SDIC # 8) 300 and four gate drivers (GDIC # 1 to GDIC # 4) However, the present invention is not limited thereto. Accordingly, the number of the data drivers 300 and the number of the gate drivers 200 may be variously changed according to the shape and size of the panel.

First, the panel 100 performs a function of outputting an image.

The panel 100 may vary depending on the type of the display device. In particular, when the display device is a liquid crystal display device, the panel 100 may be a liquid crystal panel having a liquid crystal layer formed between two glass substrates.

In this case, the lower glass substrate of the panel 100 includes a plurality of data lines DL, a plurality of gate lines GL intersecting with the data lines, and intersections of the data lines and the gate lines A plurality of TFTs (Thin Film Transistors) formed on the pixels P formed on the pixel P, a plurality of pixel electrodes (not shown) formed on the pixels P for charging a data voltage, A common electrode for driving the liquid crystal filled in the liquid crystal layer together with the pixel electrode is formed. That is, in the panel 100, the pixels are arranged in a matrix form for each intersection region of the data lines and the gate lines. A black matrix BM and a color filter are formed on the upper glass substrate of the panel 100.

The display device according to the present invention can be applied to all kinds of display devices. Accordingly, the panel 100 may include an organic light emitting panel.

In this case, each pixel formed on the panel includes a plurality of thin film transistors (TFTs) connected to the organic light emitting diode, the data lines DL and the gate lines GL to control the organic light emitting diodes, Capacitors, and the like.

Next, the gate driver 200 supplies scan pulses to the gate lines by using gate control signals (GCS) transmitted from the timing controller 400.

Here, the scan pulse means a signal capable of turning on the switching thin film transistor connected to the gate lines. A signal capable of turning off the switching thin film transistor is referred to as a gate off signal. The scan pulse and the gate off signal are collectively referred to as a scan signal.

When the switching thin film transistor is of the N type, the scan pulse is a high level voltage and the gate off signal is a low level voltage. When the thin film transistor is of the P type, the scan pulse is a low level voltage and the gate off signal is a high level voltage.

The gate driver 200 may be formed independently of the panel 100 and connected to the panel 100 through a tape carrier package TCP or a flexible printed circuit board (FPCB) A gate-in-panel (GIP) method may be used.

Next, the timing controller 400 uses the timing signals input from an external system (not shown), that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, Generates a gate control signal (GCS) for controlling the operation timing of the gate driver (200) and a data control signal (DCS) for controlling the operation timing of the data driver (300) And generates image data to be processed.

To this end, the timing controller 400 includes a receiver for receiving input image data and timing signals from the external system, a control signal generator for generating various control signals, a rearrangement of the input image data, A data sorting unit for generating data and an output unit for outputting the control signals and the image data to the data driver 300 and the gate driver 200.

That is, the timing controller 400 rearranges input image data input from the external system according to the structure and characteristics of the panel 100, and transmits the rearranged image data to the data driver 300. Such a function can be executed in the data arrangement section.

The timing controller 400 generates a data control signal for controlling the data driver 300 using the timing signals transmitted from the external system, that is, the vertical synchronization signal, the horizontal synchronization signal, and the data enable signal DCS and a gate control signal GCS for controlling the gate driver 200 and transmits the control signals to the data driver 300 and the gate driver 200. This function can be executed in the control signal generation unit.

The data control signals DCS generated by the control signal generator include a source start pulse SSP, a source shift clock signal SSC and a source output enable signal SOE. The gate control signals GCS generated by the control signal generator include a gate start pulse GSP, a gate start signal VST, a gate shift clock GSC, a gate output enable signal GOE, a gate start signal VST ), A gate clock (GCLK), and the like.

Further, the control signal generator of the timing controller 400 may generate the input voltage VCC. The input voltage VCC is transmitted to the determining unit 500 and the determining unit 500 transmits the input voltage VCC to the power driver 600. [ That is, the input voltage VCC becomes the enable signal EN.

However, the input voltage VCC may be transmitted from the timing controller 400 to the determination unit 500 from a separate input voltage supply unit.

Since the timing controller 400 is connected to the data drivers SDIC # 1 to SDIC # 8 in the EPI scheme, the timing controller 400 controls the data drivers SDIC # 1 to SDIC # 8 To the first data driver (SDIC # 1) of the data drivers (SDIC # 1 to SDIC # 8) 300, a lock signal (LOCK) for initialization.

When the data drivers (SDIC # 1) are normally driven, the lock signal is retransmitted from the first data driver (SDIC # 1) to the timing controller (400) via the eighth data driver (SDIC # 8).

When the lock signal LOCK is received, the timing controller 400 transmits the image data to the data drivers 300. The data drivers convert the image data to a data voltage, To the panel through the data lines.

In this case, the lock signal LOCK is not only transferred from the eighth data driver (SDIC # 8) to the timing controller (400) but also from the eighth data driver (SDIC # 8) Lt; / RTI >

The determination unit 500 transmits the enable signal EN to the power driver 600 when the lock signal LOCK is received. The power driver 600 supplies the driving voltage VDD to the data drivers 300 when the enable signal EN is received.

Next, the data drivers (SDIC # 1 to SDIC # 8) 300 sequentially transmit the lock signal received from the timing controller, and the last data driver, for example, the eighth data driver (SDIC # 8 transmits the received lock signal (LOCK) to the timing controller 400 and the determination unit 500.

The data drivers are driven by the drive voltage received from the power driver 600 when the lock signal LOCK is transmitted to the determination unit 500. The data driver 300 converts image data received from the timing controller 400 into a data voltage when the lock signal LOCK is transmitted to the timing controller 400, And outputs the data to the data lines.

The data driver 300 converts the digital image data transmitted from the timing controller 400 into an analog data voltage and outputs the analog data voltage to one horizontal line for each horizontal period in which the scan pulse is supplied to the gate line, Of the data voltage to the data lines.

The data driver 300 may be connected to the panel 100 in the form of a chip-on-film (COF), directly mounted on the panel, or directly on the panel. The number of the data drivers 300 may be variously set according to the size of the panel, the resolution of the panel, and the like.

The data driver 300 converts the image data into the data voltage using gamma voltages supplied from a gamma voltage generator (not shown), and supplies the data voltage to the data lines. To this end, the data driver 300 includes a shift register unit, a latch unit, a digital-analog converter (DAC), and an output buffer.

The shift register unit outputs a sampling signal using data control signals (SSC, SSP, etc.) received from the timing controller (400).

The latch unit latches the digital image data (Data) sequentially received from the timing controller (400), and simultaneously outputs the digital image data (Data) to the digital-analog converter (DAC).

The digital-analog converter converts the image data transmitted from the latch unit into the data voltage at the same time and outputs the data voltage. That is, the digital-analog converter converts the image data into the data voltage using the gamma voltage supplied from the gamma voltage generator (not shown), and outputs the data voltage to the data lines.

The output buffer outputs the data voltage transmitted from the digital-analog converter to data lines (DL) of the panel according to a source output enable signal (SOE) transmitted from the timing controller (400).

The data driver 300 may be formed of an integrated circuit (IC) together with the timing controller 400. [

Next, when the lock signal transmitted from the data driver 300 is received, the determination unit 500 outputs the input voltage transmitted from the timing controller or the input voltage supply unit as the enable signal EN.

For example, when the lock signal is received, the determination unit 500 generates the enable signal EN using the input voltage VCC transmitted from the timing controller 400, And transmits the enable signal (EN) to the power driver (600). When the lock signal is received, the determination unit 500 determines whether or not the lock signal is received, using the input voltage VCC transmitted from a separate input voltage supply unit (not shown) mounted on the main board 700, And may transmit the enable signal EN to the power driver 600 after generating the enable signal EN.

The determination unit 500 may be formed in the timing controller 400 or may be formed in the power driver 600. The determination unit 500 may be formed independently of the timing controller 400 and the power driver 600 as shown in FIG.

Lastly, the power driver 600 performs a function of supplying the driving voltage VDD to the data drivers 300.

Particularly, the power driver 600 supplies the driving voltage VDD to the data drivers 300 only when the enable signal EN is received from the determination unit 500.

4 is a diagram illustrating signals transmitted between a determination unit and a power driver and a data driver applied to a display device according to the present invention.

As described above, when the lock signal LOCK is received from the data driver 300, the determination unit 500 generates the enable signal EN using the input voltage VCC And transmits the enable signal (EN) to the power driver (600).

In this case, the lock signal LOCK may be a voltage of, for example, 1.8V. The lock signal LOCK is transmitted from the timing controller 400 to the first data driver SDIC # 1, sequentially passes through the data drivers, and then the last data driver, for example, Is transmitted from the driver (SDIC # 8) to the timing controller (400) and the determination unit (500).

The input voltage VCC may be, for example, 3.3V. In this case, the enable signal EN may also be a voltage of 3.3V. That is, the input voltage VCC input to the determination unit 500 is converted into the enable signal through the determination unit 500 and output.

The input voltage VCC may be transmitted from the timing controller 400 or may be transmitted from a separate input voltage supply unit (not shown).

The power driver 600 generates the driving voltage VDD and supplies the driving voltage VDD to the data drivers 300 when the enable signal EN is received from the determining unit 500.

The data drivers 300 sequentially transmit the lock signal LOCK received from the timing controller 400 and the last data driver 300 transmits the lock signal to the timing controller 400 and the determination unit 400. [ (500).

5 is an exemplary view showing a configuration of a determination unit applied to a display device according to the present invention.

5, the determination unit 500 includes a first terminal to which an input voltage VCC is supplied, a second terminal to which the enable signal EN is output, a second terminal to which the enable signal EN is output, Lt; RTI ID = 0.0 > 510 < / RTI > The third terminal is the gate of the transistor 510.

In this case, the transistor 510 is turned on when the lock signal LOCK of 1.8 V is received by the gate, and supplies the input voltage VCC received from the first terminal to the second terminal.

When the second terminal is connected to the power driver 600, the enable signal EN is transmitted to the power driver 600 through the second terminal.

5, the determination unit 500 further includes a buffering unit 520 for receiving and stabilizing the enable signal outputted from the second terminal of the transistor 510 can do.

The buffering unit 520 may include an OP-Amp. 5, the buffering unit 520 includes a terminal to which a buffering unit input voltage VIN is supplied and a terminal to which the buffering unit input voltage VIN is supplied, .

The buffering unit input voltage VIN is a voltage for driving the buffering unit 520.

The buffering unit 520 performs a function of causing the enable signal EN output through the second terminal of the transistor 510 to be outputted to the power driver 600 stably without being distorted .

In other words, when the lock signal LOCK is received, the determination unit 500 outputs the input voltage VCC of about 3.3V as the enable signal EN. If the lock signal LOCK is not received, the determination unit 500 and the power driver 600 are in a floating state.

6 is an exemplary view showing a configuration of a power driver applied to a display device according to the present invention.

The power driver 600 supplies the driving voltage VDD to the data drivers 300 when the enable signal EN is received and when the enable signal EN is not received, (VDD) to the data drivers 300.

The power driver 600 includes a power supply unit 610 for receiving power from an external system and a power supply unit 610 for generating the driving voltage VDD by using the power supplied from the power supply unit 610. [ And a driving voltage supplier 630 for supplying the driving voltage VDD to the data drivers 300 when the enable signal EN is transmitted from the voltage generator 620 and the determining unit 500 do.

The power driver 600 may generate various voltages Vout necessary for the display device in addition to the driving voltage VDD. To this end, the power driver 600 may further include a voltage generator 640 for generating and outputting various voltages.

Hereinafter, a display device driving method according to the present invention will be described. The same or similar contents as those described above are omitted or briefly described.

The method for driving a display device according to the present invention is characterized in that the timing controller 400 transmits the lock signal LOCK to one of the data drivers 300 of at least two or more data drivers 300, The timing controller 400 transmits image data to the data drivers 300 when the lock signal LOCK sequentially passed through the timing controller 400 is received, And the power driver 600 outputs the drive voltage VDD to the data driver 600. The data driver 600 outputs the enable signal EN to the power driver 600 when the signal LOCK is received, (300), and the data driver (300) converts the image data to a data voltage using the driving voltage (VDD), and supplies the data voltage to the panel (100) And outputting to the data lines (DL), which consists of, includes the step of outputting an image on the panel 100.

First, in the step of transmitting the lock signal LOCK, the timing controller 400 determines whether the data drivers 300 are normally driven and synchronized with each other using the lock signal LOCK .

Next, in the step of transmitting the image data, when the lock signal LOCK transmitted to the data driver 300 is normally received, the timing controller 400 determines that the data drivers 300 are normally driven And supplies the video data to the data drivers 300.

Next, in the step of outputting the enable signal EN, the determination unit 500 outputs the enable signal EN to the power driver 600 when the lock signal 300 is received.

The step of outputting the enable signal EN may include the steps of determining whether the determination unit 500 receives the lock signal LOCK sequentially passed through the data driver 300, When the lock signal is received as a result of the determination, the determination unit 500 outputs the input voltage VCC transmitted from the timing controller 400 or the power supply unit (not shown) as the enable signal EN .

Next, in the step of supplying the driving voltage VDD, the power driver 600 supplies the driving voltage VDD to the data drivers 300 when the enabling signal EN is received.

The step of supplying the driving voltage to the data drivers may include a step in which the power driver 600 receives power from an external system and the power driver 600 applies the driving voltage VDD And supplying the drive voltage VDD to the data drivers 300 when the enable signal EN is received.

Finally, the data driver 300 converts the image data into the data voltage using the driving voltage VDD, and then outputs the data voltage to the panel. Here, the driving voltage VDD may be a voltage of 16V or more.

The present invention described above is briefly summarized as follows.

In the present invention, the determination unit 500 uses the OP-Amp 520 and transmits the enable signal EN synchronized with the lock signal to the power driver 600 using the OP-Amp .

Accordingly, when the lock signal is abnormal, the enable signal EN is not transmitted to the power driver 600, but is transmitted to the power driver 600 only when the lock signal is abnormal.

The power driver 600 supplies the driving voltage VDD to the data drivers 300 only when the enable signal EN is received.

Accordingly, since the driving voltage VDD is not supplied to the data driver in a non-ready state, the data driver 300 generates a source tab power line burnt ) Can be prevented.

That is, according to the present invention, when the data driver is driven in the abnormal mode, the data driver can be prevented from being damaged.

Also, when the lock signal is not generated, for example,

That is, when the data driver for which the LOCK signal is not generated is not normally connected to the panel or the timing controller, or when the data driver is abnormally driven, the driving voltage VDD is transmitted to the data driver Therefore, the data driver or the components connected to the data driver can be prevented from being damaged or burned.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: panel 200: gate driver
300: Data driver 400: Timing controller
500: Judgment section 600: Power driver

Claims (10)

A panel in which gate lines and data lines are formed;
At least two data drivers for supplying a data voltage to the data lines;
And a timing controller for transmitting the lock signal to any one of the data drivers and transmitting the image data to the data driver when the lock signal sequentially passed through the data drivers is received, controller;
A determination unit for outputting an enable signal when the lock signal transmitted to the timing controller is received; And
And a power driver for supplying a driving voltage for driving the data drivers to the data drivers when the enable signal is received from the determination unit. The method according to claim 1,
Wherein,
And when the lock signal is received, outputs the input voltage transmitted from the timing controller or the input voltage supply unit as the enable signal. The method according to claim 1,
Wherein,
Wherein the timing controller is formed in the timing controller, or formed in the power driver, or independently formed. The method according to claim 1,
Wherein,
And a transistor including a first terminal to which an input voltage is supplied, a second terminal to output the enable signal, and a third terminal to receive the lock signal,
And the third terminal is a gate of the transistor. 5. The method of claim 4,
Wherein the input voltage is transmitted from the timing controller or the input voltage supply unit. 5. The method of claim 4,
Wherein,
And a buffering unit for receiving and stabilizing the enable signal outputted from the second terminal of the transistor. The method according to claim 1,
The power driver includes:
A power supply unit that receives power from an external system;
A driving voltage generator for generating the driving voltage using the power supplied from the power supply; And
And a drive voltage supplier for supplying the drive voltage to the data drivers when the enable signal is transmitted from the determination unit. The timing controller transmitting a lock signal to a data driver of at least two or more data drivers;
Receiving the lock signal sequentially passed through the data drivers, the timing controller transmitting image data to the data drivers;
Outputting the enable signal to the power driver when the lock signal transmitted to the timing controller is received;
The power driver supplying a drive voltage to the data drivers; And
The data drivers converting the image data to a data voltage using the driving voltage, outputting the data voltage to the data lines formed on the panel, and outputting the image to the panel Device driving method. 9. The method of claim 8,
Wherein the step of outputting the enable signal comprises:
Determining whether the lock signal that the determination unit has sequentially passed through the data drivers is received;
And outputting, as the enable signal, the input voltage transmitted from the timing controller or the power supply unit when the lock signal is received as a result of the determination. 9. The method of claim 8,
Wherein supplying the driving voltage to the data drivers comprises:
The power driver receiving power from an external system;
The power driver generating the driving voltage using the power source; And
And when the enable signal is received, the power driver supplies the drive voltage to the data drivers.

Images