KR102211406B1 - Display device and method of driving the same - Google Patents

Abstract

The present invention relates to a display device and a driving method thereof. In particular, when the data driver is normally driven by using a lock signal for determining whether or not the data driver is normally driven, a driving voltage is applied to the data driver. It is an object of the present invention to provide a display device and a display device driving method capable of supplying the same. To this end, a display device according to the present invention includes a panel on which gate lines and data lines are formed; At least two or more data drivers supplying data voltages to the data lines; When a lock signal is transmitted to any one of the data drivers, and when the lock signal sequentially passing through the data drivers is received, image data is transmitted to the data driver, so that the data driver generates the data voltage controller; A determination unit configured to output an enable signal when the lock signal transmitted to the timing controller is received; And a power driver supplying a driving voltage for driving the data drivers to the data drivers when the enable signal is received from the determination unit.

Description

Display device and its driving method {DISPLAY DEVICE AND METHOD OF DRIVING THE SAME}

The present invention relates to a display device and a driving method thereof, and more particularly, to a display device and a driving method thereof, including a timing controller and a data driver performing communication in a point-to-point method (EPI).

Flat panel displays are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. Flat panel display devices include Liquid Crystal Display, Plasma Display Panel, Organic Light Emitting Display Device, and the like, and recently, an electrophoretic display device (EPD: ELECTROPHORETIC DISPLAY). Is also widely used.

Among flat panel display devices (hereinafter simply referred to as'display devices'), a liquid crystal display device is a device that displays an image using the optical anisotropy of a liquid crystal, and has advantages such as thinness, small size, low power consumption and high quality, It is widely used.

Among display devices, organic light-emitting display devices use self-luminous devices that emit light by themselves, and thus have advantages such as fast response speed, high luminous efficiency, high luminance, and large viewing angle. Is attracting attention.

1 is an exemplary diagram showing the configuration of a conventional display device, and shows a display device including a timing controller 40 and a data driver 30 performing communication in a point-to-point method (EPI). 2 is an exemplary view showing a state in which a driving voltage is supplied from a power driver constituting a conventional display device to a data driver.

The display device includes a panel 10, a data driver 30, a gate driver 20, and a timing controller 40.

As a method of communicating between the timing controller 40 and the data driver 30, a point-to-point method is used. The point-to-point method is also referred to as an EPI (Embedded Clock Point-Point Interface) (hereinafter, simply referred to as'EPI') method. In the display device using the EPI method, the timing controller 40 and the data driver 30 perform one-to-one communication. The display device using the EPI method is described in detail in patent documents such as Publication No. 10-2010-0068938.

When power is supplied to the display device using the EPI method, first, the timing controller 40 supplies a lock signal to the first data driver (SDIC#1) 30. The lock signal is sequentially transmitted to second to eighth data drivers (SDIC#2 to SDIC#8), and the eighth data driver transmits the lock signal to the timing controller. When the lock signal is normally received, the timing controller 40 supplies image data to the data drivers 30, and the data drivers 30 supply a data voltage corresponding to the image data to the panel 10. As supplied to, an image is output from the panel 10.

To drive the data driver 30, a power driver 60 including a power integrated circuit (P-IC) or the like supplies a driving voltage VDD to the data driver 30.

The power driver 60 is driven by an enable signal EN transmitted from the timing controller 40 to supply the driving voltage VDD to the data driver 30.

In this case, when power is supplied from the outside, the timing controller 40 transmits the enable signal EN to the power driver 60 regardless of whether the lock signal is normally received. For example, when the enable signal EN is received, the power driver 60 supplies the driving voltage VDD to the data driver 30.

As described above, in a conventional display device, since the driving voltage is supplied to the data driver 30 regardless of the lock signal, the lock signal is not received by the timing controller, so that the data driver 30 Even when abnormally driven, the driving voltage VDD may be supplied to the data driver 30.

In this case, the driving voltage line through which the driving voltage VDD is transmitted may be burned. For example, even when the data driver 30 is not normally driven, since the driving voltage VDD is continuously supplied to the data driver 30, the driving voltage line or the data driver ( 30) and a connector to which the driving voltage line is connected may be burned. In addition, since the data driver 30 is in a state in which the data driver 30 is not normally driven, the data driver 30 cannot normally perform a protection function, and thus the data driver 30 may be damaged.

Even when the data driver 30 is not normally connected to the panel 10 or the timing controller 40, the above-described phenomenon may occur.

In addition, when an abnormal mode occurs during driving of the display device and the LOCK signal is not normally transmitted to the next data driver 30, the data driver does not operate, and an abnormal screen is output through the panel 10. It could be. When an abnormal screen is output for 1 to 2 minutes or more, the connector or tab connected to the data driver 30 or the driving voltage line may be burned due to an overcurrent or the like.

As described above, in a conventional display device, since the driving voltage VDD is supplied to the data driver 30 even in an abnormal mode in which a lock signal is not normally received by the timing controller 40, the driving A voltage line may be burned, a connector or a tab connecting the driving voltage line and the data driver may be burned, and the data driver 30 may be damaged.

The present invention has been proposed in order to solve the above-described problem, and when the data driver is normally driven by using a lock signal for determining whether or not the data driver is normally driven, a driving voltage is supplied to the data driver. It is a technical problem to provide a display device and a display device driving method that can be supplied.

In order to achieve the above-described technical problem, a display device according to the present invention includes: a panel on which gate lines and data lines are formed; At least two or more data drivers supplying data voltages to the data lines; When a lock signal is transmitted to any one of the data drivers, and when the lock signal sequentially passing through the data drivers is received, image data is transmitted to the data driver, so that the data driver generates the data voltage controller; A determination unit configured to output an enable signal when the lock signal transmitted to the timing controller is received; And a power driver supplying a driving voltage for driving the data drivers to the data drivers when the enable signal is received from the determination unit.

In order to achieve the above-described technical problem, a method for driving a display device according to the present invention includes: transmitting, by a timing controller, a lock signal to any one of at least two data drivers; Transmitting, by the timing controller, image data to the data drivers when the lock signal sequentially passing through the data drivers is received; When the lock signal transmitted to the timing controller is received, outputting an enable signal to a power driver by a determination unit; Supplying, by the power driver, a driving voltage to the data drivers; And converting the image data into a data voltage by the data drivers using the driving voltage, and outputting the data voltage to data lines formed on the panel, and outputting an image to the panel. .

According to the present invention, when a data driver is not normally driven, since a driving voltage is not supplied to the data driver, damage to the data driver or a line to which the driving voltage is supplied to the data driver can be prevented. That is, according to the present invention, when the data driver using the EPI method is abnormally driven, the data driver can be protected.

In particular, according to the present invention, by controlling the output of the enable signal input to the power driver using the lock signal (LOCK) input to the timing controller and the determination unit, abnormality in the assembly process or handling process of the display device. When a mode (ex. FFC open, driver IC damage, etc.) occurs, a phenomenon in which components connected to the data driver are burned (source tab power line burnt) can be prevented.

1 is an exemplary view showing the configuration of a conventional display device.
2 is an exemplary diagram showing a state in which a driving voltage is supplied from a power driver constituting a conventional display device to a data driver.
3 is an exemplary view showing a configuration of a display device according to the present invention.
4 is an exemplary diagram illustrating signals transmitted between a determination unit applied to a display device according to the present invention, a power driver, and a data driver.
5 is an exemplary view showing a configuration of a determination unit applied to a display device according to the present invention.
6 is an exemplary view showing a configuration of a power driver applied to a display device according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is an exemplary view showing a configuration of a display device according to the present invention.

The display device according to the present invention uses an EPI (Embedded Clock Point-Point Interface) method, and as shown in FIG. 3, a panel 100 in which gate lines GL and data lines DL are formed. , At least two or more data drivers 300 supplying a data voltage to the data lines DL, a lock signal LOCK is transmitted to any one of the data drivers 300, and the data drivers are sequentially When the passed lock signal is received, the image data is transmitted to the data driver 300 and transmitted to the timing controller 400 and the timing controller 400 to allow the data driver 300 to generate the data voltage. When the lock signal is received, a determination unit 500 that outputs an enable signal EN, and when the enable signal EN is received from the determination unit 500, driving the data drivers 300 And a power driver 600 that supplies a driving voltage VDD for the data drivers 300 to the data drivers 300. In FIG. 3, a display device including eight data drivers (SDIC#1 to SDIC#8) 300 and four gate drivers (GDIC#1 to GDIC#4) 200 is an example of the present invention. Although shown as, the present invention is not limited thereto. Accordingly, the number of data drivers 300 and the number of gate drivers 200 may be variously changed according to the shape and size of the panel.

First, the panel 100 performs a function of outputting an image.

The panel 100 may vary depending on the type of the display device. In particular, when the display device is a liquid crystal display device, it may be a liquid crystal panel in which a liquid crystal layer is formed between two glass substrates.

In this case, on the lower glass substrate of the panel 100, a plurality of data lines DL, a plurality of gate lines GL crossing the data lines, and intersections of the data lines and the gate lines A plurality of thin film transistors (TFTs) formed in each pixel P, a plurality of pixel electrodes (not shown) formed in the pixel P to charge a data voltage, and the A common electrode for driving the liquid crystal filled in the liquid crystal layer is formed together with the pixel electrode. That is, in the panel 100, the pixels are arranged in a matrix form at each intersection of the data lines and the gate lines. A black matrix (BM) and a color filter are formed on the upper glass substrate of the panel 100.

The display device according to the present invention can be applied to all types of display devices. Accordingly, the panel 100 may be configured as an organic light emitting panel.

In this case, each pixel formed on the panel includes an organic light emitting diode, a plurality of thin film transistors connected to the data lines DL and the gate lines GL to control the organic light emitting diode, and a storage device. Capacitors may be included.

Next, the gate driver 200 supplies scan pulses to the gate lines using the gate control signals GCS transmitted from the timing controller 400.

Here, the scan pulse means a signal capable of turning on the switching thin film transistors connected to the gate lines. A signal capable of turning off the switching thin film transistor is referred to as a gate off signal. The scan pulse and the gate-off signal are collectively referred to as a scan signal.

When the switching thin film transistor is an N type, the scan pulse is a high-level voltage, and the gate-off signal is a low-level voltage. When the thin film transistor is a P type, the scan pulse is a low level voltage, and the gate-off signal is a high level voltage.

The gate driver 200 is formed independently of the panel 100 and may be connected to the panel 100 through a tape carrier package (TCP) or a flexible printed circuit board (FPCB), but the panel 100 ) Can also be configured in a Gate In Panel (GIP) method that is directly mounted inside.

Next, the timing controller 400 uses a timing signal input from an external system (not shown), that is, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a data enable signal (DE). Generates a gate control signal (GCS) for controlling the operation timing of the gate driver 200 and a data control signal (DCS) for controlling the operation timing of the data driver 300, and is transmitted to the data driver 300 Create image data to be used.

To this end, the timing controller 400 includes a receiving unit for receiving input image data and timing signals from the external system, a control signal generating unit for generating various control signals, and rearranging the input image data to rearrange the image. And a data alignment unit for generating data, and an output unit for outputting the control signals and the image data to the data driver 300 and the gate driver 200.

That is, the timing controller 400 rearranges the input image data input from the external system according to the structure and characteristics of the panel 100 and transmits the rearranged image data to the data driver 300. This function can be executed in the data alignment unit.

The timing controller 400 uses timing signals transmitted from the external system, that is, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and the like, and a data control signal for controlling the data driver 300 ( DCS) and a gate control signal GCS for controlling the gate driver 200 are generated, and the control signals are transmitted to the data drive 300 and the gate driver 200. This function can be executed by the control signal generator.

The data control signals DCS generated by the control signal generator include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and the like. Gate control signals GCS generated by the control signal generator include a gate start pulse (GSP), a gate start signal (VST), a gate shift clock (GSC), a gate output enable signal (GOE), and a gate start signal (VST). ), gate clock (GCLK), etc.

In addition, the control signal generator of the timing controller 400 may generate an input voltage VCC. The input voltage VCC is transmitted to the determination unit 500, and the determination unit 500 transmits the input voltage VCC to the power driver 600. That is, the input voltage VCC becomes the enable signal EN.

However, the input voltage VCC may be transmitted to the determination unit 500 from a separate input voltage supply unit other than the timing controller 400.

Since the timing controller 400 is connected to the data drivers (SDIC#1 to SDIC#8) in an EPI method, the timing controller 400 uses the data drivers (SDIC#1 to SDIC#8). The lock signal LOCK for initialization is transmitted to the first data driver (SDIC#1) among the data drivers (SDIC#1 to SDIC#8) 300.

When the data drivers (SDIC#1) are normally driven, the lock signal is retransmitted from the first data driver (SDIC#1) to the timing controller 400 through an eighth data driver (SDIC#8).

When the lock signal LOCK is received, the timing controller 400 transmits image data to the data drivers 300, and the data drivers convert the image data into a data voltage and then convert the data voltage. It is transmitted to the panel through the data lines.

In this case, the lock signal LOCK is not only transmitted from the eighth data driver (SDIC#8) to the timing controller 400, but also from the eighth data driver (SDIC#8), the determination unit 500 Also sent to.

When the lock signal LOCK is received, the determination unit 500 transmits the enable signal EN to the power driver 600. When the enable signal EN is received, the power driver 600 supplies the driving voltage VDD to the data drivers 300.

Next, the data drivers (SDIC#1 to SDIC#8) 300 sequentially transmit the lock signal received from the timing controller, and the last data driver, for example, the eighth data driver (SDIC#) 8) transmits the received lock signal LOCK to the timing controller 400 and the determination unit 500.

The data drivers are driven by the driving voltage received from the power driver 600 when the lock signal LOCK is transmitted to the determination unit 500. In addition, when the lock signal LOCK is transmitted to the timing controller 400, the data drivers 300 convert image data received from the timing controller 400 into a data voltage, and convert the data voltage. Output to the data lines.

To further explain, the data driver 300 converts the digital image data transmitted from the timing controller 400 to an analog data voltage, and converts one horizontal line into one horizontal period in which the scan pulse is supplied to the gate line. The data voltage of min is supplied to the data lines.

The data driver 300 may be connected to the panel 100 in the form of a chip-on-film (COF), and may be directly mounted on the panel or formed directly on the panel. The number of data drivers 300 may be variously set according to the size of the panel and the resolution of the panel.

The data driver 300 converts the image data into the data voltage by using gamma voltages supplied from a gamma voltage generator (not shown), and then supplies the data voltage to the data line. To this end, the data driver 300 includes a shift register unit, a latch unit, a digital to analog conversion unit (DAC), and an output buffer.

The shift register unit outputs a sampling signal using data control signals (SSC, SSP, etc.) received from the timing controller 400.

The latch unit performs a function of latching the digital image data sequentially received from the timing controller 400 and simultaneously outputting the digital image data to the digital-to-analog converter (DAC).

The digital-to-analog converter converts the image data transmitted from the latch unit to the data voltage at the same time, and outputs the same. That is, the digital-to-analog converter converts the image data into the data voltage by using a gamma voltage supplied from the gamma voltage generator (not shown), and then outputs the data voltage to the data lines.

The output buffer outputs the data voltage transmitted from the digital-to-analog converter to the data lines DL of the panel according to the source output enable signal SOE transmitted from the timing controller 400.

The data driver 300 may be formed as an integrated circuit (IC) together with the timing controller 400.

Next, when the lock signal transmitted from the data driver 300 is received, the determination unit 500 outputs the input voltage transmitted from the timing controller or the input voltage supply unit as the enable signal EN.

For example, when the lock signal is received, the determination unit 500 generates the enable signal EN using the input voltage VCC transmitted from the timing controller 400, The enable signal EN is transmitted to the power driver 600. In addition, the determination unit 500, when the lock signal is received, using the input voltage (VCC) transmitted from a separate input voltage supply unit (not shown) mounted on the main board 700, the After generating the enable signal EN, the enable signal EN may be transmitted to the power driver 600.

The determination unit 500 may be formed in the timing controller 400 or may be formed in the power driver 600. In addition, the determination unit 500 may be formed independently from the timing controller 400 and the power driver 600, as shown in FIG. 3.

Finally, the power driver 600 performs a function of supplying the driving voltage VDD to the data drivers 300.

In particular, the power driver 600 supplies the driving voltage VDD to the data drivers 300 only when the enable signal EN is received from the determination unit 500.

4 is an exemplary diagram illustrating signals transmitted between a determination unit applied to a display device according to the present invention, a power driver, and a data driver.

As described above, when the lock signal LOCK is received from the data driver 300, the determination unit 500 generates the enable signal EN using the input voltage VCC. After that, the enable signal EN is transmitted to the power driver 600.

In this case, the lock signal LOCK may be, for example, a voltage of 1.8V. The lock signal (LOCK) is transmitted from the timing controller 400 to the first data driver (SDIC#1), passes through the data drivers in sequence, and then the last data driver, for example, the eighth data It is transmitted from the driver (SDIC#8) to the timing controller 400 and the determination unit 500.

The input voltage VCC may be, for example, a voltage of 3.3V. In this case, the enable signal EN may also be a voltage of 3.3V. That is, the input voltage VCC input to the determination unit 500 is converted into the enable signal through the determination unit 500 and then output.

The input voltage VCC may be transmitted from the timing controller 400 or may be transmitted from a separate input voltage supply unit (not shown).

When the enable signal EN is received from the determination unit 500, the power driver 600 generates the driving voltage VDD and supplies it to the data drivers 300.

The data drivers 300 sequentially transmit the lock signal LOCK received from the timing controller 400, and the last data driver 300 transmits the lock signal to the timing controller 400 and the determination unit. It is supplied at 500.

5 is an exemplary view showing a configuration of a determination unit applied to a display device according to the present invention.

As shown in FIG. 5, the determination unit 500 includes a first terminal to which an input voltage VCC is supplied, a second terminal to which the enable signal EN is output, and the lock signal LOCK. And a transistor 510 including a third terminal through which is received. The third terminal is a gate of the transistor 510.

In this case, the transistor 510 is turned on when the 1.8V lock signal LOCK is received through the gate, and supplies the input voltage VCC received from the first terminal to the second terminal.

When the second terminal is connected to the power driver 600, the enable signal EN is transmitted to the power driver 600 through the second terminal.

However, the determination unit 500 further includes a buffering unit 520 that receives and stabilizes the enable signal output from the second terminal of the transistor 510 and outputs it as shown in FIG. 5. can do.

The buffering unit 520 may be configured as an OP-Amp. When the buffering unit 520 is composed of an OP-Amp, as shown in FIG. 5, the buffering unit 520 includes a terminal to which the buffering unit input voltage VIN is supplied and a terminal connected to the second terminal. Is formed.

The buffering unit input voltage VIN is a voltage for driving the buffering unit 520.

The buffering unit 520 performs a function of stably outputting the enable signal EN output through the second terminal of the transistor 510 to the power driver 600 without being distorted. .

To further explain, when the lock signal LOCK is received, the determination unit 500 outputs an input voltage VCC of approximately 3.3V as the enable signal EN. When the lock signal LOCK is not received, a floating state is established between the determination unit 500 and the power driver 600.

6 is an exemplary diagram showing a configuration of a power driver applied to a display device according to the present invention.

The power driver 600 supplies the driving voltage VDD to the data drivers 300 when the enable signal EN is received, and the driving voltage when the enable signal EN is not received. (VDD) is not supplied to the data drivers 300.

To this end, the power driver 600 is a power supply unit 610 that receives power from an external system, and a drive that generates the driving voltage VDD using power transmitted from the power supply unit 610 When the enable signal EN is transmitted from the voltage generation unit 620 and the determination unit 500, a driving voltage supply unit 630 that supplies the driving voltage VDD to the data drivers 300 is included. do.

In addition to the driving voltage VDD, the power driver 600 may generate various voltages Vout required by the display device. To this end, the power driver 600 may further include a voltage generator 640 that generates and outputs various voltages.

Hereinafter, a method of driving a display device according to the present invention will be described. In the following description, the same or similar content as described above will be omitted or briefly described.

In the method of driving a display device according to the present invention, the timing controller 400 transmits the lock signal LOCK to any one of at least two data drivers 300, the data driver 300 ), when the lock signal LOCK which has passed sequentially is received, transmitting image data to the data driver 300 by the timing controller 400, and the lock transmitted to the timing controller 400 When the signal LOCK is received, the determination unit 500 outputs the enable signal EN to the power driver 600, and the power driver 600 applies the driving voltage VDD to the data driver. Supplying to 300 and the data drivers 300 converting the image data into a data voltage using the driving voltage VDD, and then converting the data voltage to the panel 100. And outputting an image to the panel 100 by outputting the data lines DL.

First, in the step of transmitting the lock signal LOCK, the timing controller 400 uses the lock signal LOCK to determine whether the data drivers 300 are normally driven and are synchronized with each other. Check whether or not.

Next, in the step of transmitting the image data, when the lock signal LOCK transmitted to the data driver 300 is normally received, the timing controller 400 determines that the data drivers 300 are normally driven. Thus, image data is supplied to the data drivers 300.

Next, in the step of outputting the enable signal EN, when the lock signal 300 is received, the determination unit 500 outputs the enable signal EN to the power driver 600.

To this end, the outputting of the enable signal EN may include determining, by the determination unit 500, whether the lock signal LOCK sequentially passing through the data drivers 300 is received, When the lock signal is received as a result of the determination, the determination unit 500 outputs the input voltage VCC transmitted from the timing controller 400 or a power supply unit (not shown) as the enable signal EN. It includes the step of.

Next, in the step of supplying the driving voltage VDD, when the enable signal EN is received, the power driver 600 supplies the driving voltage VDD to the data drivers 300.

To this end, the step of supplying the driving voltage to the data drivers may include receiving power by the power driver 600 from an external system, and the power driver 600 using the power supply to the driving voltage VDD ) And when the enable signal EN is received, the power driver 600 supplying the driving voltage VDD to the data drivers 300.

Finally, the data drivers 300 convert the image data into the data voltage using the driving voltage VDD, and then output the data voltage to the panel. Here, as the driving voltage VDD, a voltage of 16V or higher may be used.

A brief summary of the present invention described above is as follows.

In the present invention, the determination unit 500 uses the OP-Amp 520, and transmits an enable signal EN synchronized with the lock signal to the power driver 600 using the OP-Amp. I can.

Accordingly, when the lock signal is abnormal, the enable signal EN is not transmitted to the power driver 600, but is transmitted to the power driver 600 only when it is normal.

The power driver 600 supplies the driving voltage VDD to the data drivers 300 only when the enable signal EN is received.

Therefore, since the driving voltage VDD is not supplied to the data driver while the data driver 300 is in a non-ready state, parts connected to the data driver burn (source tab power line burnt). ) Can be prevented.

That is, according to the present invention, when the data driver is driven in an abnormal mode, a phenomenon in which the data driver is damaged can be prevented.

In addition, when the lock signal is not generated, for example,

That is, when the data driver for which the LOCK signal is not generated is not normally connected to the panel or the timing controller, or when the data driver is abnormally driven, the driving voltage VDD is transmitted to the data driver. Therefore, damage or burning of the data driver or components connected to the data driver can be prevented.

Those skilled in the art to which the present invention pertains will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting. The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

100: panel 200: gate driver
300: data driver 400: timing controller
500: judgment unit 600: power driver

Claims (10)

A panel on which gate lines and data lines are formed;
At least two or more data drivers supplying data voltages to the data lines;
When a lock signal is transmitted to any one of the data drivers, and when the lock signal sequentially passing through the data drivers is received, image data is transmitted to the data driver, so that the data driver generates the data voltage controller;
A determination unit configured to output an enable signal when the lock signal transmitted to the timing controller is received; And
A power driver for supplying a driving voltage for driving the data drivers to the data drivers when the enable signal is received from the determination unit,
The determination unit,
A transistor including a first terminal to which an input voltage is supplied, a second terminal to which the enable signal is output, and a third terminal to which the lock signal is received; And
A buffering unit for receiving and stabilizing the enable signal output from the second terminal of the transistor and outputting it to the power driver,
The third terminal is the gate of the transistor,
The transistor is turned on when the lock signal is received through the third terminal, and supplies the input voltage received from the first terminal to the second terminal,
The input voltage is output as the enable signal through the second terminal,
The enable signal output through the second terminal is transmitted to the power driver through the buffering unit,
The buffering unit is composed of OP-Amp,
The buffering unit includes a terminal to which an input voltage of the buffering unit is supplied and a terminal connected to the second terminal,
The input voltage of the buffering unit is a voltage that drives the buffering unit. delete The method of claim 1,
The determination unit,
The display device, characterized in that formed on the timing controller, on the power driver, or independently formed on the power driver. delete delete delete The method of claim 1,
The power driver,
A power supply receiving power from an external system;
A driving voltage generator for generating the driving voltage using the power transmitted from the power supply; And
And a driving voltage supply unit supplying the driving voltage to the data drivers when the enable signal is transmitted from the determination unit. Transmitting, by the timing controller, a lock signal to any one of the at least two data drivers;
Transmitting, by the timing controller, image data to the data drivers when the lock signal sequentially passing through the data drivers is received;
When the lock signal transmitted to the timing controller is received, outputting an enable signal to a power driver by a determination unit;
Supplying, by the power driver, a driving voltage to the data drivers; And
The data drivers converting the image data into a data voltage using the driving voltage, and outputting the data voltage to data lines formed on a panel, and outputting an image to the panel,
The determination unit,
A transistor including a first terminal to which an input voltage is supplied, a second terminal to which the enable signal is output, and a third terminal to which the lock signal is received; And
A buffering unit for receiving and stabilizing the enable signal output from the second terminal of the transistor and outputting it to the power driver,
The third terminal is the gate of the transistor,
The transistor is turned on when the lock signal is received through the third terminal, and supplies the input voltage received from the first terminal to the second terminal,
The input voltage is output as the enable signal through the second terminal,
The enable signal output through the second terminal is transmitted to the power driver through the buffering unit,
The buffering unit is composed of OP-Amp,
The buffering unit includes a terminal to which an input voltage of the buffering unit is supplied and a terminal connected to the second terminal,
The input voltage of the buffering unit is a voltage driving the buffering unit. The method of claim 8,
The step of outputting the enable signal,
Determining, by the determination unit, whether the lock signal which has sequentially passed through the data drivers is received;
And when the lock signal is received as a result of the determination, the determination unit outputs the input voltage transmitted from the input voltage supply unit as the enable signal. The method of claim 8,
The step of supplying the driving voltage to the data drivers,
Receiving, by the power driver, power from an external system;
Generating the driving voltage by the power driver using the power source; And
And when the enable signal is received, the power driver supplying the driving voltage to the data drivers.

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