KR102626066B1 - Level shifter and display device using the same - Google Patents

Abstract

The present invention relates to a display device using an inverted signal and a driving method thereof, which includes a display panel driving circuit for writing data into pixels; a signal generator that generates a two-step signal to control the display panel driving circuit; a plurality of signal wires connecting the display panel driving circuit and the signal generator; and a signal inversion circuit that receives a two-step signal from the signal generator and inverts the two-step signal to supply three-step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage to the signal wires. do.

Description

Display device using an inverted signal and its driving method {LEVEL SHIFTER AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a display device using an inverted signal and a method of driving the same.

The driving circuit of a flat panel display (FPD) reproduces the input image on a pixel array by writing pixel data of the input image to pixels of the display panel. A flat panel display device includes a display panel driving circuit, such as a data driving circuit that supplies a pixel data signal to the data lines, and a gate driving circuit that supplies a gate signal (or a scan signal to the gate lines (or scan lines)). The flat panel display device includes a control circuit, such as a timing controller, that controls the data driving circuit and the gate driving circuit.

Various methods are being developed to reduce electro-magnetic interference (EMI) and noise on the signal wiring between the timing controller and the display panel driving circuit. The signal output from the timing controller may have its voltage level converted through a level shifter.

An example of a technology to improve electro-magnetic interference (EMI) on signal wiring is field cancellation technology that generates an anti-phase signal of a signal transmitted to a display panel driving circuit.

Field cancellation technology has the problem of adding wiring to transmit anti-phase signals. Additionally, field offset technology cannot be applied depending on the driving characteristics of the display device. For example, field cancellation technology applicable to liquid crystal displays cannot be applied to organic light emitting displays (OLED displays).

The present invention aims to solve the above-described needs and/or problems.

The present invention provides a display device using an inverted signal and a method of driving the same, which can eliminate EMI and noise on signal wires and minimize the increase in the number of wires.

The object of the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment of the present invention includes a display panel including a plurality of pixels adjacent to an area where a plurality of data lines and a plurality of gate lines intersect; a display panel driving circuit for writing data into the pixels; a signal generator that generates a two step signal to control the display panel driving circuit; a plurality of signal wires connecting the display panel driving circuit and the signal generator; and receiving a two-step signal from the signal generator, inverting the two-step signal, and supplying three step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage to the signal wires. It includes a signal inversion circuit that does.

The three step signals applied to the neighboring signal wires are out of phase with each other.

A display device according to another embodiment of the present invention includes a display panel including a plurality of pixels adjacent to an area where a plurality of data lines and a plurality of gate lines intersect; a display panel driving circuit for writing data into the pixels; a signal generator that generates a two-step input signal to control the display panel driving circuit; a plurality of signal wires connecting the display panel driving circuit and the signal generator; a signal inversion circuit that receives a two-step signal from the signal generator and inverts the two-step signal to convert it into a three-step signal including a positive polarity voltage, a reference level voltage, and a negative polarity voltage; and a restoration circuit that converts the three-step signals from the signal conversion circuit into two-step output signals and supplies them to the signal wires.

The two-step output signal is generated with a gate high voltage higher than the high voltage of the two-step input signal and a gate low voltage lower than the low voltage of the two-step input signal.

A method of driving a display device according to an embodiment of the present invention includes generating a two-step input signal to control a display panel driving circuit; receiving the two-step input signal and inverting the two-step input signal to generate three step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage; and controlling the display panel driving circuit by supplying the three step signals to a plurality of signal wires connected to the display panel driving circuit.

A method of driving a display device according to another embodiment of the present invention includes generating a two-step input signal to control a display panel driving circuit; receiving the two-step signal and inverting the two-step input signal to generate three-step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage; converting the three-step signals into two-step output signals and supplying them to the signal wires; and controlling the display panel driving circuit by supplying the two-step output signal to a plurality of signal wires connected to the display panel driving circuit.

The present invention inverts the output signal of a signal generator that generates a control signal for controlling a display panel driving circuit and supplies signals supplied to neighboring signal wires as signals out of phase with each other. Therefore, the present invention can eliminate EMI and noise on signal wires by implementing a field cancellation effect without adding separate signal wires.

The present invention can reduce the deterioration of transistors used in the display panel driving circuit by reducing and recovering the gate bias stress of the transistors of the display panel driving circuit using an inverted signal.

The present invention can convert a three-step signal output from a level shifter into a two-step signal using a restoration circuit and supply it to the display panel driving circuit. The recovery circuit can be selectively enabled according to preset option pin or register settings. The recovery circuit can be enabled/disabled under the control of the host system or timing controller. Accordingly, the present invention can adaptively enable the restoration circuit according to the driving mode and supply a two-step signal or a three-step signal as a control signal or clock signal to the display panel driving circuit.

The accompanying drawings, which are included as part of the detailed description to aid understanding of the present invention, provide embodiments of the present invention, and together with the detailed description, explain technical features of the present invention.
1 is a block diagram showing a display device according to an embodiment of the present invention.
Figure 2 is a circuit diagram showing switch elements of a demultiplexer array.
Figure 3 is a diagram showing an example of a pixel circuit in a liquid crystal display device.
FIG. 4 is a diagram showing an example of a pixel circuit in an organic light emitting display device.
FIG. 5 is a waveform diagram showing the operation of the demultiplexer and pixel circuit shown in FIG. 4.
Figure 6 is a diagram schematically showing the shift register of the gate driving circuit.
7 and 8 are diagrams showing wiring between a timing controller and a level shifter.
Figure 9 is a diagram showing the output signal of the signal generator and the level shifter.
10 and 11 are diagrams showing an example of a mix circuit connected between a signal generator and a level shifter.
Figure 12 is a diagram showing signal wires between the level shifter and the display panel driving circuit.
Figures 13 and 14 are diagrams showing the operation of the mix circuit.
Figure 15 is a circuit diagram showing in detail an example of a level shifter that receives a two-step signal and outputs a three-step signal.
Figure 16 is a circuit diagram showing in detail an example of a cascade type level shifter that receives first to third input signals.
Figure 17 is a circuit diagram showing an example of a mix circuit that receives first to third input signals and outputs a three step signal.
Figure 18 is a circuit diagram showing an example of a level shifter that receives first to third input signals and outputs a three step signal.
Figure 19 is a waveform diagram showing a three-step signal output from the mix circuit and level shifter.
FIG. 20 is a circuit diagram showing an example in which the mix circuit shown in FIG. 13 is connected to a signal generator and a level shifter.
FIG. 21 is a waveform diagram showing the input signal, the output signal of the mix circuit, and the output signal of the level shifter shown in FIG. 20.
Figure 22 is a circuit diagram showing an example of a cascade type mix circuit.
FIG. 23 is a circuit diagram showing an example in which the mix circuit shown in FIG. 22 is connected between a signal generator and a level shifter.
FIG. 24 is a waveform diagram showing the input signal, the output signal of the mix circuit, and the output signal of the level shifter shown in FIG. 23.
FIG. 25 is a circuit diagram showing an example in which the mix circuit shown in FIG. 17 and the level shifter shown in FIG. 18 are combined.
FIG. 26 is a waveform diagram showing the input signal, the output signal of the mix circuit, and the output signal of the level shifter shown in FIG. 25.
Figure 27 is a diagram showing a restoration circuit connected to the output nodes of the level shifter.
Figure 28 is a circuit diagram showing an example of a restoration circuit in detail.
FIG. 29 is a waveform diagram showing output signals of the level shifter and restoration circuit shown in FIG. 27.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. Only the embodiments are intended to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “provides,” “includes,” “has,” “consists of,” etc. mentioned in the present invention are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two components is described as 'on top', 'on top', 'on the bottom', 'next to ~', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component. Since the patent claims are written focusing on essential components, the ordinal numbers preceding the component names of the patent claims and the ordinal numbers preceding the component names of the embodiments may not match.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, the display panel driving circuit, pixel array, level shifter, etc. may include transistors. Transistors can be implemented as Oxide TFT (Thin Film Transistor) containing an oxide semiconductor, LTPS TFT containing Low Temperature Poly Silicon (LTPS), etc. Each of the transistors may be implemented as a transistor with a p-channel MOSFET (metal-oxide-semiconductor field effect transistor) or n-channel MOSFET structure.

A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal transitions between Gate On Voltage and Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while the transistor is turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage (Gate High Voltage, VGH), and the gate-off voltage may be the gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

The present invention can be applied to any flat panel display device, such as a liquid crystal display (LCD) or an organic light emitting display (OLED display). The display device of the present invention is controlled by receiving a signal generator that generates a control signal for controlling the display panel driving circuit, a plurality of signal wires connecting the display panel driver circuit and the signal generator, and a control signal from the signal generator. It includes a signal inversion circuit that inverts the signal and supplies a three-step signal including a positive polarity voltage, a reference level voltage, and a negative polarity voltage to the signal wires. The signal inversion circuit is described in embodiments as a mix circuit and/or a level shifter.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

Referring to FIG. 1, a display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The display panel 100 includes a pixel array (AA) that displays pixel data of an input image. Pixel data of the input image is displayed in pixels of the pixel array (AA). The pixel array (AA) includes a plurality of data lines (DL), a plurality of gate lines (GL) that intersect the data lines (DL), and a plurality of gate lines (GL) that intersect the data lines (DL) and the gate lines (GL). Contains a plurality of pixels arranged in the area. Pixels may be arranged in a matrix form. In addition to the matrix form, pixels can be arranged in various forms, such as sharing pixels emitting the same color, stripe form, or diamond form.

The display panel can be manufactured as a flexible display panel. The flexible display panel can be implemented as a transparent OLED panel using a plastic substrate. In a plastic OLED display panel, a pixel array is formed on an organic thin film adhered to a back plate.

The back plate of a plastic OLED display may be a PET (Polyethylene terephthalate) substrate. An organic thin film is formed on the back plate. A pixel array and a touch sensor array can be formed on an organic thin film. The back plate blocks moisture permeation toward the organic thin film to prevent the pixel array from being exposed to humidity. The organic thin film may be a thin polyimide (PI) film substrate. A multi-layer buffer film may be formed on the organic thin film using an insulating material not shown. Wires for supplying power or signals applied to the pixel array and the touch sensor array may be formed on the organic thin film.

When the resolution of the pixel array AA is n*m, the pixel array AA includes n pixel columns and m pixel lines L1 to Lm that intersect the pixel columns. A pixel column contains pixels arranged along the y-axis direction. A pixel line includes pixels arranged along the x-axis direction. 1 horizontal period (1H) is the time divided by 1 frame period by the number of m pixel lines (L1 to Lm). Pixel data is written to pixels of one pixel line in one horizontal period (1H).

Each pixel may be divided into red subpixel, green subpixel, and blue subpixel to implement color. Each of the pixels may further include a white subpixel. Each of the subpixels 101 includes a pixel circuit. The pixel circuit includes a pixel electrode, multiple thin film transistors (TFTs), and a capacitor. The pixel circuit is connected to the data line (DL) and gate line (GL).

Touch sensors may be disposed on the display panel 100 to implement a touch screen. Touch input can be sensed using separate touch sensors or sensed through pixels. Touch sensors can be implemented as on-cell type or add-on type touch sensors placed on the screen of the display panel or embedded in the pixel array. You can.

The display panel driving circuit includes a data driver 110, a gate driver 120, and a timing controller 130 for controlling the operation timing of the driving circuits 110 and 120. The display panel driving circuit writes data of the input image to the pixels of the display panel 100 under the control of the timing controller 130.

The data driver 110 converts the pixel data of the input image received as a digital signal from the timing controller 130 every frame into an analog gamma compensation voltage using a digital to analog converter (hereinafter referred to as “DAC”). Converts and outputs data signals (Vdata1~3). Data signals Vdata1 to 3 are supplied to the data lines DL. The data driver 110 may be integrated into the source drive IC 110a shown in FIGS. 7 and 8. The source drive IC 110a may be mounted on a chip on film (COF) and connected between the source PCB 152 and the display panel 100. Each of the source drive ICs 110a may have a built-in touch sensor driver for driving touch sensors.

The gate driver 120 may be formed in the bezel area BZ of the display panel 100 where images are not displayed. The gate driver 120 receives the gate timing control signal received from the level shifter 140 and generates a gate signal (or scan signal, GATE1 to 3) synchronized with the data signals (Vdata1 to 3) to generate gate lines (GL). ) is supplied to. The gate signals (GATE1 to 3) applied to the gate lines (GL) turn on the switch elements of the subpixels to select pixels in which the voltage of the data signals (Vdata1 to 3) is charged. The gate signals (GATE1 to 3) may be generated as pulse signals that swing between the gate high voltage (VGH) and the gate low voltage (VGL). The gate driver 120 shifts the gate signal using a shift register.

The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel drivers 110 and 120 with a frame frequency of input frame frequency x i (i is a positive integer greater than 0) Hz. . The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method.

The timing controller 130 receives pixel data of the input image and a timing signal synchronized therewith from the host system 200. Pixel data of the input image received by the timing controller 130 is a digital signal. The timing controller 130 transmits pixel data to the data driver 110. The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE). Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) can be omitted. The data enable signal (DE) has a period of 1 horizontal period (1H).

The display panel driving circuit may further include a demultiplexer array 112 disposed between the data driver 110 and the gate driver 120.

The demultiplexer array 112 sequentially connects one channel of the data driver 110 to a plurality of data lines DL and time-divides the data voltage output from one channel of the data driver 110 to the data lines DL. By distributing, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 includes a number of switch elements as shown in FIG. 2.

The timing controller 130 includes a data timing control signal for controlling the data driver 110 based on the timing signal received from the host system 200, a gate timing control signal for controlling the gate driver 120, and a demultiplexer array. A MUX control signal, etc. for controlling the switch elements of (112) may be generated. The gate timing control signal may include a start pulse (Gate Start Pulse (VST)), a shift clock (CLK), etc. The start pulse (VST) controls the start timing of the gate driver 120 every frame period. The shift clock CLK controls the shift timing of the gate signal output from the gate driver 120. The timing controller 130 may generate a control signal to control the level shifter 140.

The host system 200 may be any one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile system, and a wearable system. In mobile devices and wearable devices, the data driver 110, timing controller 130, level shifter 140, etc. may be integrated into one drive IC (not shown).

In a mobile system, the host system 200 may be implemented as an Application Processor (AP). The host system 200 may transmit pixel data of the input image to the drive IC through MIPI (Mobile Industry Processor Interface). The host system 200 may be connected to the drive IC through a flexible printed circuit (FPC) 310, for example.

The level shifter 140 converts the input signal received from the timing controller 130 or a mix circuit as shown in FIGS. 10 and 11 into a three-step voltage and outputs a three-step signal. can do. A three-step signal is a signal that includes a reference level, a high-level voltage higher than the reference level, and a low-level voltage lower than the reference level.

The three step signal may be one or more control signals among a data timing signal, gate timing signal, and MUX control signal. Accordingly, the three-step signal output from the level shifter 140 can be applied to at least one of the demultiplexer array 112, the gate driver 120, and the data driver 110 to control these circuits.

In another embodiment, the three-step signal output from the level shifter 140 is converted into a two-step signal and applied to at least one of the demultiplexer array 112, the gate driver 120, and the data driver 110 to control these circuits. can do.

The display device of the present invention further includes a power supply unit 400.

The power supply unit 400 uses a DC-DC converter to generate direct current (DC) voltage necessary to drive the pixel array of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, buck-boost converter, etc. The power unit 400 adjusts the direct current input voltage from the host system 200 to a gamma reference voltage (VGMA) and a gate high voltage (VGH, VEH). Direct current voltages such as gate low voltage (VGL, VEL), half VDD (HVDD), and common voltage of pixels can be generated. The gamma reference voltage (VGMA) is supplied to the data driver 110. The half VDD voltage is as low as 1/2 voltage compared to VDD and can be used as the output buffer driving voltage of the source drive IC. The gamma reference voltage (VGMA) is divided by gray level through a voltage dividing circuit and supplied to the DAC of the data driver 110.

FIG. 2 is a circuit diagram showing switch elements M1 and M2 of the demultiplexer array 112.

Referring to FIG. 2, the output buffer (AMP) included in one channel (CH1, CH2) in the data driver 110 may be connected to neighboring data lines DL1 to 4 through the demultiplexer array 112. . The data lines DL1 to 4 may be connected to the pixel electrodes 1011 to 1014 of the subpixels through the TFT.

Demultiplexer array 112 includes multiple demultiplexers 21 and 22. The demultiplexers 21 and 22 may be 1:N demultiplexers with one input node and N output nodes (N is two or more positive integers). The control nodes of the demultiplexers (21, 22) are connected to the gates of the switch elements (M1, M2) and control the switch elements (M1, M2) according to the MUX control signals (MUX1, MUX2). The MUX control signals MUX1 and MUX2 may be a three-step signal output from the level shifter 140 or a two-step signal output from a restoration circuit to be described later.

The demultiplexers 21 and 22 of the demultiplexer array 112 are illustrated as 1:2 demultiplexers in FIG. 2, but are not limited thereto. For example, each of the demultiplexers 21 and 22 is implemented as a 1:3 demultiplexer, so that one channel can be sequentially connected to three data lines in the data driver 110. The demultiplexer array 112 may be formed directly on the substrate of the display panel 100 or may be integrated into one drive IC together with the data driver 110.

The demultiplexer array 112 uses switch elements M1 and M2 to transmit the data signal Vdata1 output through the first channel CH1 of the data driver 110 to the first and second data lines DL1, The data signal Vdata1 output through the second channel CH2 of the data driver 110 is divided into the third and third channels using the first demultiplexer 21 for time division distribution to DL2 and the switch elements M1 and M2. It includes a second demultiplexer 22 that performs time division distribution to the fourth data lines DL3 and DL4.

Each of the switch elements M1 and M2 may be implemented as a transistor. The switch elements (M1, M2) are turned on according to the gate high voltage (VGH) of the MUX control signals (MUX1, MUX2) applied to the gate through the level shifter 140, and the data driver 110 ) channels to the data lines (DL1 to DL4).

The level shifter 140 may convert the MUX control signal received from the timing controller 130 into a three-step signal and output the first and second MUX signals (MUX1 and MUX2).

The first switch element M1 is turned on in response to the gate high voltage VGH of the first MUX signal MUX1. At this time, the output buffer (AMP) of the first channel (CH1) is connected to the first data line (DL1) through the first switch element (M1). At the same time, the output buffer AMP of the second channel CH2 is connected to the third data line DL3 through the first switch element M1.

The second switch element M2 is turned on in response to the gate high voltage VGH of the second MUX signal MUX2. At this time, the output buffer (AMP) of the first channel (CH1) is connected to the second data line (DL2) through the second switch element (M2). At the same time, the output buffer AMP of the second channel CH2 is connected to the fourth data line DL4 through the second switch element M2.

Figure 3 is a diagram showing an example of a pixel circuit in a liquid crystal display device.

Referring to FIG. 3, each of the subpixels includes a pixel electrode 1, a common electrode 2, a liquid crystal cell (Clc), a TFT connected to the pixel electrode 1, and a storage capacitor (Cst). The TFT is formed at the intersection of the data lines (DL1 to 3) and the gate line (GL1). The TFT supplies the voltage of the data signal (Vdata) from the data lines (DL1 to 3) to the pixel electrode (1) in response to the gate signal (GATE) from the gate line (GATE).

The first multiplexer 21 is connected between the first channels CH1 of the data driver 110 and the data lines DL1 and DL2. The second multiplexer 22 is connected between the second channel CH2 of the data driver 110 and the data lines DL3 and DL3.

As shown in the example of FIG. 4, subpixels of an organic light emitting display device use an organic light emitting diode (“OLED”) to generate light according to pixel data of an input image to display an image. Organic light emitting display devices do not require a backlight unit and can be implemented on flexible materials such as plastic substrates, thin glass substrates, and metal substrates. Therefore, the flexible display can be implemented as an organic light emitting display device.

Flexible displays can change the size and shape of the screen by wrapping, folding, or bending the display panel. Flexible displays can be implemented as rollable displays, bendable displays, foldable displays, slideable displays, etc. These flexible display devices can be applied not only to mobile devices such as smartphones and tablet PCs, but also to TVs, automobile displays, and wearable devices, and their application fields are expanding.

The pixels of an organic light emitting display device include an OLED, a driving element that drives the OLED by controlling the current flowing through the OLED according to the gate-source voltage (Vgs), and a storage capacitor that maintains the gate voltage of the driving element.

The driving element may be implemented as a transistor. In order to maintain uniform image quality across the screen of an organic light emitting display device, the driving element must have uniform electrical characteristics among all pixels. There may be differences in the electrical characteristics of driving elements between pixels due to process deviations and device characteristic deviations resulting from the display panel manufacturing process, and these differences may become larger as the driving time of the pixels elapses. To compensate for differences in electrical characteristics of driving elements between pixels, internal compensation technology and/or external compensation technology may be applied to the organic light emitting display device.

External compensation technology uses an external compensation circuit to sense the current or voltage of driving elements that change according to the electrical characteristics of the driving elements in real time. External compensation technology compensates in real time for the deviation (or change) in the electrical characteristics of the driving element in each pixel by modulating the pixel data (digital data) of the input image by the deviation (or change) in the electrical characteristics of the driving element sensed for each pixel.

Internal compensation technology uses an internal compensation circuit built into each pixel to sense the threshold voltage of the driving element for each sub-pixel and compensates the gate-source voltage (Vgs) of the driving element by the threshold voltage. The internal compensation circuit includes a storage capacitor (Cst) connected to the gate of the driving element (DT), and one or more switch elements (T1 to 5) connecting the storage capacitor (Cst), the driving element (DT), and the light emitting element (EL). Includes.

The multiplexers 21 and 22 can be applied to both organic light emitting display devices using internal compensation technology or external compensation technology. Figure 4 shows an example in which the multiplexer 21 is disposed in an organic light emitting display device to which internal compensation technology is applied, but the present invention is not limited thereto.

Referring to FIGS. 4 and 5 , the gate signal may include a scan signal and an emission control signal (hereinafter referred to as an “EM signal”) in an organic light emitting display device. In FIG. 4, GL11 to GL13 are gate lines connected to subpixels of a 1-pixel line. D1(N) and D2(N) are data signals (Vdata) applied to pixels of the Nth pixel line. D1(N+1) and D2(N+1) are data signals (Vdata) applied to pixels of the N+1th pixel line. X is a section in which there is no data signal (Vdata).

The power supply unit 400 may output direct current power such as a pixel driving voltage (VDD), a low potential voltage (VSS), and a reference voltage (Vref) applied to the pixels.

During one horizontal period (1H) during which data is written to the pixels of one pixel line, the pixels are divided into an initialization period (Tini), a data writing period (Twr), and a sustain period (Th) and driven as shown in FIG. It can be.

Pixels may emit light during an emission period (Tem). The emission period (Tem) corresponds to most of the 1 frame period excluding 1 horizontal period (1H) in the 1 frame period. A retention period (Th) may be added between the data writing period (Twr) and the light emission period (Tem).

In order to accurately express the luminance of low gray scale, the EM signal [EM(N)] is divided into gate-on voltage (VEL) and gate-off voltage at a predetermined duty ratio during the emission period (Tem). (VEH) can swing between.

The pulse of the second scan signal [SCAN2(N)] is inverted to the gate-on voltage (VGL) before the first scan signal [SCAN1(N)], and the pulse of the first scan signal [SCAN1(N)] is inverted at the same time as the pulse of the first scan signal [SCAN1(N)]. It is inverted to the off voltage (VGH). The pulse width of the first and second scan signals [SCAN1(N), SCAN2(N)] may be set to 1 horizontal period (1H) or less.

The pulse of the EM signal (EM) may be generated as a gate high voltage (VEH) to suppress light emission of the light emitting element (EL) during the data writing period (Twr) and sustain period (Th). The EM signal (EM) is inverted to the gate high voltage (VEH) when the first scan signal [SCAN1(N)] is inverted to the gate low voltage (VGL), and the first and second scan signals [SCAN1(N), [SCAN2(N)] may be inverted to the gate high voltage (VEH) and then to the gate low voltage (VEL).

During the initialization period (Tini), the second scan signal [SCAN2(N)] is inverted to the gate low voltage (VGL). At this time, major nodes of the pixel circuit may be initialized.

During the data writing period Twr, the first scan signal [SCAN1(N)] is inverted to the gate low voltage VGL. At this time, the data signal Vdata is applied to the first electrode of the capacitor Cst, and VDD-Vth is applied to the second electrode of the capacitor Cst. During the data writing period (Twr), when the gate-source voltage (Vgs) of the driving element (DT) reaches the threshold voltage (Vth) of the driving element (DT), the driving element (DT) turns off. ), the threshold voltage (Vth) of the driving element (DT) is sampled in the capacitor (Cst), and the data voltage (Vdata) compensated by the threshold voltage (Vth) is charged in the capacitor (Cst).

The light emitting element (EL) can be implemented as OLED. OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer of OLED may include, but is not limited to, a hole injection layer (HIL), hole transport layer (HTL), light emitting layer (EML), electron transport layer (ETL), and electron injection layer (EIL). The anode of the light emitting element EL is connected to the fourth and fifth switch elements T4 and T5 through the fourth node n4.

A low-potential power supply voltage (VSS) is applied to the cathode of the light emitting element (EL). The driving element DT drives the light emitting element EL by supplying current to the light emitting element EL according to the gate-source voltage Vgs. The light emitting element EL emits light with a current controlled by the driving element DT according to the voltage of the data signal Vdata. The current path of the light emitting element (EL) is switched by the fourth switch element (T4).

The capacitor Cst is connected between the first node n1 and the second node n2. The capacitor Cst is charged with the compensated voltage of the data signal Vdata equal to the threshold voltage Vth of the driving element DT. Since the voltage of the data signal Vdata in each subpixel is compensated by the threshold voltage Vth of the driving element DT, the threshold voltage deviation of the driving element DT in the subpixels can be compensated.

The first switch element (T1) is turned on in response to the gate low voltage (VGL) of the first scan signal [SCAN1(N)] to increase the voltage of the data signal (Vdata) to the first node (n1). ) is supplied to. The first switch element T1 includes a gate connected to the first gate line GL11 to which the first scan signal [SCAN1(N)] is applied, a first electrode connected to the data lines DL1 and DL2, and a first node ( It includes a second electrode connected to n1).

The second switch element T2 is turned on in response to the gate low voltage VGL of the second scan signal [SCAN2(N)] and connects the gate of the driving element DT and the second electrode. The second switch element T2 includes a gate connected to the second gate line GL12 to which the second scan signal [SCAN2(N)] is applied, a first electrode connected to the second node n2, and a third node n3. ) and a second electrode connected to the electrode.

The third switch element (T3) is turned on in response to the gate low voltage (VEL) of the EM signal [EM(N)] and is referenced to the first node (n1) during the initialization period (Tini) and the emission period (Tem). Supply voltage (Vref). Due to the third switch element T3, the first electrode voltage of the capacitor Cst is initialized to Vref during the initialization period Tini and the emission period Tem. The third switch element T3 is connected to the gate connected to the third gate line G13 to which the EM signal [EM(N)] is applied, the first electrode connected to the first node n1, and the Vref line to which Vref is applied. It includes a connected second electrode.

The fourth switch element (T4) is turned on in response to the gate low voltage (VEL) of the EM signal [EM(N)] to control the third node (n3) during the initialization period (Tini) and the emission period (Tem). 4 Connect to node (n4). The gate of the fourth switch element T4 is connected to the third gate line GL13. The first electrode of the fourth switch element T4 is connected to the third node n3, and the second electrode of the fourth switch element T4 is connected to the fourth node n4.

The fifth switch element (T5) is turned on in response to the gate low voltage (VGL) of the second scan signal [SCAN2(N)] and connects Vref to the fourth node during the initialization period (Tini) and the data writing period (Twr). It is supplied to (n4). The gate of the fifth switch element T5 is connected to the second gate line GL12. The first electrode of the fifth switch element T5 is connected to the Vref line, and the second electrode of the fifth switch element T5 is connected to the fourth node n4.

The driving element DT is operated as a diode by the second switch element T2 turned on during the data writing period Twr. The threshold voltage (Vth) of the driving element (DT) is sampled during the data writing period (Twr). The driving element DT drives the light emitting element EL by controlling the current flowing through the light emitting element EL according to the gate-source voltage Vgs during the light emission period Tem. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the VDD line to which VDD is applied, and a second electrode connected to the third node n3.

FIG. 6 is a diagram schematically showing the shift register of the gate driver 120. The shift register of the gate driver 120 includes dependently connected stages [SR(n-1) to (n+2)]. The shift register receives a start pulse (VST) or carry signal (CAR) and generates an output signal [OUT(n-1))~(n+2)] in accordance with the shift clock (CLK) timing. The carry signal (CAR) may be output from the previous stage.

Each of the stages [SR(n-1) to (n+2)] includes a control unit 60 that charges and discharges the Q node and QB node, and charges the gate line according to the Q node voltage to raise the waveform of the gate signal ( rising) and includes a buffer that discharges the gate line according to the QB node voltage. The buffer includes a pull-up transistor (Tu) and a pull-down transistor (Td). The output signals [OUT(n-1) to (n+2)] of the stages [SR(n-1) to (n+2)] are gate signals sequentially applied to the gate lines.

The gate timing control signals (VST, CLK) may be a three-step signal or a two-step pulse signal output from a level shifter.

In a large screen display device, the source PCBs 152 may be separated into two. FIGS. 7 and 8 are diagrams showing signal wires between the timing controller 130 and the level shifter 140 in a large screen display device.

7 and 8, the control board 150 is connected to the first and second source PCBs 152 through a flexible circuit board, for example, a flexible flat cable (FFC) 151 and connectors 151a and 151b. , 153).

The source drive ICs 110a are connected between the source PCBs 152 and 153 and the display panel 100.

The timing controller 130 and level shifter 140 may be mounted on the control board 150 as shown in FIG. 7. In this case, the input terminals of the level shifter 140 are connected to the timing controller 130 through wires formed on the control board 150. The output terminals of the level shifter 140 are connected to the gate driver through wires connecting the FFC 151, the source PCBs 152 and 153, the chip on film (COF) 110b, and the gate driver 120 on the display panel 100. It can be connected to (120).

The level shifter 140 may be mounted on each of the source PCBs 152 and 153 as shown in FIG. 8 . In this case, the level shifter 140 may include a first level shifter 141 mounted on the first source PCB 152 and a second level shifter 142 mounted on the second source PCB 153. . The input terminals of each of the level shifters 141 and 142 are connected to the timing controller 130 through wires connecting the control board 150, FFC 151, and source PCBs 152 and 153. The output terminals of the level shifters 141 and 142 may be connected to the gate driver 120 through wires connecting the source PCBs 152 and 153, the COF 110b, and the gate driver 120 on the display panel 100. there is.

The timing controller 130 may generate a control signal for controlling the display panel driving circuit using the signal generator 131 shown in FIGS. 9 to 11 .

FIG. 9 is a diagram showing output signals from the signal generator 131 and the level shifter 140.

Referring to FIG. 9, the signal generator 131 generates first and second signals IN1 and IN2 in the form of pulses. The signal generator 131 may sequentially output pulses of the first and second signals IN1 and IN2 using a shift register. The first and second input signals IN1 and IN2 may be output as two-step pulses with a TTL (transistor-transistor logic) voltage level between 0V and 3.3V.

The level shifter 140 receives a two-step signal from the signal generator 131 and outputs a three-step signal. The level shifter 140 inverts each of the first and second input signals IN1 and IN2 from the signal generator 131 to generate first and second output signals OUT1 that are in phase with each other. , OUT2) is output. The first and second output signals OUT1 and OUT2 are generated with a voltage greater than the voltage of the first and second input signals.

When the first output signal OUT1 is a positive voltage (+V), the second output signal OUT2 is a negative voltage (-V). Conversely, when the first output signal OUT1 is a negative voltage (-V), the second output signal OUT2 is a positive voltage (+V). Accordingly, when the first and second output signals OUT1 are applied to adjacent signal wires, a field cancellation effect occurs.

The output signals (OUT1, OUT2) are three-step signals whose polarity is inverted and include a reference level, a pulse of a positive voltage (+V) higher than the reference level, and a pulse of a negative voltage (-V) below the reference level. You can. The reference level may be the gate low voltage (VGL). The positive polarity voltage (+V) may be a voltage higher than the high voltage (3.3V) of the input signals IN1 and IN2, for example, the gate high voltage (VGH). The gate high voltage (VGH) may be a voltage of 20V or higher. The negative polarity voltage (-V) may be a negative voltage lower than the gate low voltage (VGL). The negative polarity voltage (-V) can be selected at a voltage lower than the gate low voltage (VGL). The negative polarity voltage (-V) may vary depending on the operating characteristics of the display panel driving circuit.

The first and second output signals OUT1 and OUT1 are transmitted to the display panel driving circuits 110, 112, and 120 through adjacent signal wires. Accordingly, since out-of-phase signals are transmitted to neighboring signal wires, a field cancellation effect occurs and EMI and noise can be minimized.

The display panel driving circuit includes transistors to which the output signals OUT1 and OUT2 of the level shifter 140 are applied to the gate. These transistors may deteriorate due to gate bias stress when a voltage of the same polarity is continuously applied to the gate voltage or when a direct current voltage is applied. For example, the threshold voltage of a transistor may shift due to gate bias stress.

The three-step signal transitions between positive and negative voltages. For this reason, in the case of a transistor to which a three-step signal is applied, gate bias stress accumulation can be reduced, and the stress can be recovered with voltages of opposite polarity. Accordingly, the deterioration of the transistors of the display panel driving circuit controlled by the output signals (OUT1, OUT1) of the level shifter can be reduced, thereby stabilizing operation and extending the lifespan.

10 and 11 are diagrams showing an example in which the mix circuit 10 is connected between the signal generator 131 and the level shifter 140. Figure 10 shows an example of a differential type mix circuit. Figure 11 shows an example of a cascade type mix circuit.

The mix circuit 10 may be connected between the signal generator 131 and the level shifter 140.

Referring to FIG. 10, the mix circuit 10 inverts the first and second input signals (IN1, IN2) from the signal generator 131 to generate first and second output signals (MOUT1, MOUT2) that are out of phase with each other. ) is output. Each of the output signals (MOUT1, MOUT2) is generated as a three-step signal with a three-step voltage.

The first and second output signals (MOUT1, MOUT2) include pulses generated as inversion signals of the pulses of the first and second input signals (IN1, IN2), a pulse of the positive polarity voltage (V1), and a negative polarity voltage ( Contains pulses of V2). The first and second input signals IN1 and IN2 may be output as two-step pulses between 0V and 3.3V. In this case, the positive voltage V1 of the first and second output signals MOUT1 and MOUT2 may be +3.3V, and the negative voltage V2 may be -3.3V. In the first and second output signals MOUT1 and MOUT2, a reference level section exists between the pulse of the positive voltage V1 and the pulse of the negative voltage V2. The reference level in the output signal of the mix circuit 10 may be 0V.

The level shifter 140 receives a three-step signal from the mix circuit 10 and outputs a three-step signal with an increased voltage. The level shifter 140 shifts the voltage of the input signals (MOUT1, MOUT2) from the mix circuit 10 to control the display panel driving circuits 110, 112, and 120 to control the first and second output signals OUT1 and OUT2. ) is output.

Each of the first and second output signals OUT1 and OUT2 is generated as a three-step signal with a three-step voltage. In the first and second output signals (OUT1, OUT2), the positive polarity voltage (+V) is higher than the high voltage (+3.3V) of the input signals (MOUT1, MOUT2), for example, the gate high voltage (VGH). It can be. The negative polarity voltage (-V) may be a voltage lower than the low voltage (-3V) of the input signals (MOUT1 and MOUT2), for example, the gate low voltage (VGL). The negative polarity voltage (-V) may be selected between voltages VGL and -VGH and may vary depending on the operating characteristics of the display panel driving circuit.

Referring to FIG. 11, the mix circuit 11 receives the first to third input signals IN1, IN2, and IN3 from the signal generator 131, and inverts the input signals IN1, IN2, and IN3 to mix them with each other. First to third output signals (MOUT1, MOUT2, MOUT3) that are in opposite phase are output. Each of the output signals (MOUT1, MOUT2, MOUT3) is generated as a three-step signal with a three-step voltage.

The output signals (MOUT1, MOUT2, MOUT3) of the mix circuit 11 include pulses of the positive polarity voltage (V1) and negative polarity voltage ( Contains pulses of V2). The input signals (IN1, IN2, IN3) can be output as two-step pulses between 0V and 3.3V. In this case, the positive polarity voltage (V1) of the output signals (MOUT1, MOUT2, MOUT3) may be a voltage of +3.3V, and the negative polarity voltage (V2) may be -3.3V. In the first and second output signals MOUT1 and MOUT2, a reference level section exists between the pulse of the positive voltage V1 and the pulse of the negative voltage V2.

The level shifter 140 receives a three-step signal from the mix circuit 11 and outputs a three-step signal with an increased voltage. The level shifter 140 shifts the voltage of the input signals (MOUT1, MOUT2, MOUT3) from the mix circuit 11 to output signals (OUT1, OUT2, OUT3) that control the display panel driving circuits (110, 112, 120). outputs. Each of the output signals (OUT1, OUT2, and OUT3) is generated as a three-step signal with a three-step voltage. In the output signals (OUT1, OUT2, OUT3), the positive polarity voltage (+V) may be a voltage higher than the high voltage (+3.3V) of the input signals (MOUT1, MOUT2), for example, the gate high voltage (VGH). . The negative polarity voltage (-V) may be a voltage lower than the low voltage (-3V) of the input signals (MOUT1 and MOUT2), for example, the gate low voltage (VGL). The negative polarity voltage (-V) may be selected between voltages VGL and -VGH and may vary depending on the operating characteristics of the display panel driving circuit.

Figure 12 is a diagram showing signal wires between the level shifter and the display panel driving circuit.

Referring to FIG. 12, the output signals OUT1 and OUT1 of the level shifter 140 are applied to at least one of the display panel driving circuits 110, 112, and 120 through the signal wires 31 to 36 to drive the display panel driving circuit. The furnaces 110, 112, and 120 can be controlled.

The three step signals applied to the neighboring signal wires 31 to 36 may be signals out of phase with each other. Accordingly, EMI and noise can be minimized due to the field cancellation effect on the signal wires 31 to 36. Additionally, the accumulation of gate bias stress in the transistors can be reduced, and the stress in the transistors can be recovered.

13 and 14 are diagrams showing the operation of the mix circuits 10 and 11.

Referring to FIG. 13, the mix circuits 10 and 11 include a constant current source (A) and first to fourth switch elements (M1 to M4). The switch elements (M1 to M4) may be implemented as transistors. A resistor R is connected between the first and second output nodes n131 and n132 of the mix circuits 10 and 11.

The first and second switch elements M1 and M2 output the non-inverted signal and the inverted signal of the first input signal IN1 through the first and second output nodes n131 and n132. The non-inverted signal of the first input signal IN1 is supplied to the first signal wire 31 through the first output node n131. The inverted signal of the first input signal IN1 is supplied to the second signal wire 32 through the second output node n132.

The first switch element (M1) is turned on in response to the high voltage (3.3V) of the first input signal (IN1) and connects the constant current source (A) and the first output node (n131). The first switch element M1 includes a gate through which the first input signal IN1 is input, a first electrode connected to the constant current source A, and a second electrode connected to the first output node n131. The second switch element M2 is turned on in response to the high voltage (3.3V) of the first input signal IN1 and connects the second output node n132 to the base voltage source GND. The second switch element M2 includes a gate through which the first input signal IN1 is input, a first electrode connected to the second output node n132, and a second electrode connected to the base voltage source GND.

The third and fourth switch elements M3 and M4 output the non-inverted signal and the inverted signal of the second input signal IN2 through the first and second output nodes n131 and n132. The non-inverted signal of the second input signal IN1 is supplied to the second signal wire 32 through the second output node n132. The inverted signal of the second input signal IN2 is supplied to the first signal wire 31 through the first output node n131.

The third switch element M3 is turned on in response to the high voltage (3.3V) of the second input signal IN3 and connects the constant current source A and the second output node n132. The third switch element M3 includes a gate through which the second input signal IN2 is input, a first electrode connected to the constant current source A, and a second electrode connected to the second output node n132. The fourth switch element M4 is turned on in response to the high voltage (3.3V) of the second input signal IN2 and connects the first output node n131 to the base voltage source GND. The fourth switch element M4 includes a gate through which the second input signal IN2 is input, a first electrode connected to the first output node n131, and a second electrode connected to the base voltage source GND.

When input signals (IN1, IN2) as in the example of Figure 13 are input to the mix circuits (10, 11), the current passes and output signals of the mix circuits (10, 11) t1, t2, and t3 on the time axis are as shown in Figure 14. . It is assumed that the input signals (IN1, IN2) at t1 are IN1 = High, IN2 = Low, and the input signals (IN1, IN2) at t2 are IN1 = Low, IN2 = Low. And, the input signals (IN1, IN2) at t3 are assumed to be IN1 = Low and IN2 = High.

Referring to FIG. 14, the first input signal IN1 at t1 is a high voltage (High). At t1, the first and second switch elements M1 and M2 are turned on and the non-inverted signal of the first input signal IN1 is output to the first output node n131. The voltage of the non-inverting signal is V = I*R when the current of the constant current source (A) is I and the resistance value of the resistor (R) is R. At the same time, the inverted signal of the first input signal IN1 is output to the second output node n132. The voltage of the inverted signal is V = -I*R.

At t2, the first and second input signals IN1 and IN2 are low voltages (Low). At this time, the first to fourth switch elements M1 to M4 are turned off, and the voltage of the first and second output nodes n131 and n132 is a low voltage (Low = 0V).

At t3, the second input signal IN2 is inverted to a high voltage (High). At t3, the third and fourth switch elements M3 and M4 are turned on, and the inverted signal of the second input signal IN2 is output to the first output node n131. The voltage of the inverted signal is V = -I*R. At the same time, the non-inverted signal of the first input signal IN1 is output to the second output node n132. The voltage of the non-inverting signal is V = I*R.

Figure 15 is a circuit diagram showing in detail an example of the level shifter 140 that receives a two-step signal and outputs a three-step signal.

Referring to FIG. 15, the level shifter 140 includes a first level shifter 151 that outputs a first three-step signal (OUT1) through a first output node, and a second three-step signal (OUT1) through a second output node. It includes a second level shifter 152 that outputs OUT2). The first output node may be connected to the first signal wire 31, and the second output node may be connected to the second signal wire 32.

The first level shifter 151 outputs a gate high voltage (VGH) in response to the first input signal (IN1) and outputs an inversion voltage (Vinv) in response to the second input signal (IN2). The second level shifter 152 outputs a gate high voltage (VGH) in response to the second input signal (IN2) and outputs an inversion voltage (Vinv) in response to the first input signal (IN1).

The inversion voltage (Vinv) may be the minimum gate low voltage (VGL) or a negative voltage between the gate low voltage (VGL) and the maximum negative voltage (-Max). The gate high voltage (VGH) and gate low voltage (VGL) may be VGH = 22V and VGL = -3V, but are not limited thereto. The maximum negative voltage (-Max) can be set as -Max = -(VGH-VGL) or -VGH, but is not limited to this.

The first and second input signals IN1 and IN2 of the level shifter 140 are anti-phase signals. Accordingly, when the first input signal IN1 is a high voltage, the second input signal IN2 is a low voltage. Conversely, when the first input signal IN1 is a low voltage, the second input signal IN2 is a high voltage.

Each of the first and second level shifters 151 and 152 includes first to third switch elements (M151, M152, and M153) and NOR gates (NOR1 and NOR2). The switch elements (M151, M152, and M153) may be implemented as transistors.

When the mix circuits 10 and 11 are disposed between the signal generator 131 and the level shifter 140, the input signal of the level shifter 140 is the three step signal (MOUT1) output from the mix circuits 10 and 11. , MOUT2).

The first switch element (M151) is turned on according to the input signal (IN1 or IN2) and outputs the gate high voltage (VGH), so that the high voltage (3.3V) of the input signal (IN1 or IN2) is converted to the gate high voltage (VGH). =22V). The first switch element M151 includes a gate to which an input signal (IN1 or IN2) is applied, a first electrode to which a gate high voltage (VGH) is applied, and a second electrode connected to an output node. In the case of the first level shifter 151, the first input signal IN1 is applied to the gate of the first switch element 151. In the case of the second level shifter 152, the second input signal IN2 is applied to the gate of the first switch element M151.

The second switch element (M152) is turned on according to the input signal (IN1 or IN2) and outputs an inversion voltage (Vinv). As described above, the inversion voltage (Vinv) is a negative voltage lower than the reference level, for example, the minimum gate low voltage (VGL), or a negative voltage between the gate low voltage (VGL) and the maximum negative voltage (-Max). It can be. The second switch element M152 includes a gate to which the input signal IN1 or IN2 is applied, a first electrode to which the inversion voltage Vinv is applied, and a second electrode connected to the output node. In the case of the first level shifter 151, the second input signal IN2 is applied to the gate of the second switch element 152. In the case of the second level shifter 152, the first input signal IN1 is applied to the gate of the second switch element 152.

NOR gates (NOR1, NOR2) output a low voltage when the logic values of the two input signals are the same, while outputting a high voltage when the logic values of the two input signals are the same. The third switch element (M153) is turned on when the output signal of the NOR gate (NOR1, NOR2) is a high voltage and supplies the gate low voltage (VGL) to the output node. The third switch element M153 includes a gate to which the output signals of the NOR gates NOR1 and NOR2 are applied, a first electrode connected to the output node, and a second electrode to which the gate low voltage VGL is applied.

When the demultiplexer 112 is a 1:3 demultiplexer or when the shift clock (CLK) input to the gate driver 120 is a three-phase clock, the signal generator 131 generates a signal whose phase is sequentially shifted. First to third input signals (IN1, IN2, IN3) can be output.

FIG. 16 is a circuit diagram showing in detail an example of a cascade type level shifter 140 that receives first to third input signals. Description of the connection relationship will be omitted for the same configuration as the embodiment shown in FIG. 16 to FIG. 15.

Referring to FIG. 16, the level shifter 140 is a first level shifter 161 that receives the first and second input signals IN1 and IN2 and outputs the first three step signal OU1 through the first output node. ), a second level shifter 162 that receives the second and third input signals (IN2, IN3) and outputs a second three step signal (OU1) through the second output node, and first and third input signals It includes a third level shifter 163 that receives inputs (IN1, IN3) and outputs a first three step signal (OU1) through a third output node.

The phases of the first to third input signals IN1, IN2, and IN3 of the level shifter 140 may be sequentially shifted.

The first level shifter 161 outputs a gate high voltage (VGH) in response to the first input signal (IN1) and outputs an inversion voltage (Vinv) in response to the second input signal (IN2). The second level shifter 162 outputs a gate high voltage (VGH) in response to the second input signal (IN2) and outputs an inversion voltage (Vinv) in response to the third input signal (IN3). The third level shifter 163 outputs a gate high voltage (VGH) in response to the third input signal (IN3) and outputs an inversion voltage (Vinv) in response to the first input signal (IN1).

Each of the first to third level shifters 161, 162, and 163 includes first to third switch elements M161, M162, and M163, and NOR gates NOR1, NOR2, and NOR3. The switch elements (M161, M162, and M163) may be implemented as transistors.

When the mix circuits 10 and 11 are disposed between the signal generator 131 and the level shifter 140, the input signals IN1, IN2 and IN3 of the level shifter 140 are transmitted from the mix circuits 10 and 11. It may be an output three step signal (MOUT1, MOUT2).

The first switch elements 161, 164, and 167 are turned on according to the input signals (IN1, IN2, IN3) and output the gate high voltage (VGH) to increase the high voltage (VGH) of the input signals (IN1, IN2, IN3). 3.3V) to the gate high voltage (VGH=22V). In the case of the first level shifter 151, the first input signal IN1 is applied to the gate of the first switch element 161. In the case of the second level shifter 162, the second input signal IN2 is applied to the gate of the first switch element 164. In the case of the third level shifter 163, the third input signal IN3 is applied to the gate of the first switch element 167.

The second switch element 162 is turned on according to the input signals (IN2, IN1, IN3) and outputs an inversion voltage (Vinv) in response to the input signals (IN1, IN2, IN3). do. In the case of the first level shifter 161, the second input signal IN2 is applied to the gate of the second switch element 162. In the case of the second level shifter 162, the third input signal IN3 is applied to the gate of the second switch element 165. In the case of the third level shifter 163, the first input signal IN1 is applied to the gate of the second switch element 168.

The NOR gate (NOR1, NOR2, NOR3) outputs a low voltage when the logic values of the two input signals are the same, while it outputs a high voltage when the logic values of the two input signals are the same. In the case of the first level shifter 161, the first and second input signals IN1 and IN2 are input to the first NOR gate (NOR1). In the case of the second level shifter 162, the second and third input signals IN2 and IN3 are input to the second NOR gate NOR2. In the case of the third level shifter 163, the first and third input signals IN1 and IN3 are input to the third NOR gate (NOR3).

The third switch elements (M163, M166, and M169) are turned on when the output signals of the NOR gates (NOR1, NOR2, and NOR3) are high voltage and supply the gate low voltage (VGL) to the output node. The third switch elements (M163, M166, M169) include a gate to which the output signal of the NOR gate (NOR1, NOR2, NOR3) is applied, a first electrode connected to the output node, and a second electrode to which the gate low voltage (VGL) is applied. Includes.

The mix circuits 10 and 11 and the level shifter 140 can receive two or more input signals and generate a three-step signal. The level shifter 140 can output a three-step signal that increases the voltage of the input signal from the signal generator 131 or the mix circuits 10 and 11. In addition, the level shifter 140 receives the output signal of the signal generator 131 and the output signal of the mix circuits 10 and 11, as in the example of FIG. 27, and outputs a three-step signal with the voltage of the input signal increased. It may be possible.

Figure 17 is a circuit diagram showing in detail an example of a mix circuit that receives first to third input signals and outputs a three step signal.

Referring to FIG. 17, the mix circuits 10 and 11 receive the first input signal IN1 or the third input signal IN3 and output a second three step signal MOUT2. do.

The first switch element (M1) is turned on in response to the high voltage (3.3V) of the second input signal (IN2) and connects the constant current source (A) and the first output node. The first switch element M1 includes a gate through which the second input signal IN2 is input, a first electrode connected to the constant current source A, and a second electrode connected to the first output node. The second switch element (M2) is turned on in response to the high voltage (3.3V) of the second input signal (IN2) and connects the second output node to the base voltage source (GND). The second switch element M2 includes a gate through which the second input signal IN2 is input, a first electrode connected to the second output node, and a second electrode connected to the ground voltage source GND.

The third switch element M3 is turned on in response to the high voltage (3.3V) of the first input signal IN1 and connects the constant current source A and the second output node. The third switch element M3 includes a gate through which the first input signal IN1 is input, a first electrode connected to the constant current source A, and a second electrode connected to the second output node. The fourth switch element M4 is turned on in response to the high voltage (3.3V) of the first input signal IN1 and connects the first output node to the base voltage source. The fourth switch element M4 includes a gate through which the first input signal IN1 is input, a first electrode connected to the first output node, and a second electrode connected to the base voltage source GND.

The fifth switch element M5 is turned on in response to the high voltage (3.3V) of the third input signal IN3 and connects the constant current source A and the first output node. The fifth switch element M5 includes a gate through which the third input signal IN2 is input, a first electrode connected to the constant current source A, and a second electrode connected to the first output node. The sixth switch element M6 is turned on in response to the high voltage (3.3V) of the third input signal IN3 and connects the second output node to the base voltage source GND. The sixth switch element M6 includes a gate through which the third input signal IN3 is input, a first electrode connected to the second output node, and a second electrode connected to the base voltage source GND.

Figure 18 is a circuit diagram showing an example of a level shifter that receives first to third input signals and outputs a three step signal.

Referring to FIG. 18, the level shifter 140 receives first to third input signals IN1, IN2, and IN3. The phases of the first to third input signals IN1, IN2, and IN3 may be sequentially shifted by the shift register of the signal generator 131. At least one of the first to third input signals IN1, IN2, and IN3 may be a three-step signal input from the mix circuits 10 and 11.

The level shifter 140 includes first to fourth switch elements (M181 to M184) and a NOR gate (NOR). Switch elements (M181 to M184) can be implemented as transistors.

The first switch element (M181) is turned on according to the first input signal (IN1) and outputs a gate high voltage (VGH), so that the high voltage (3.3V) of the input signal (IN1 or IN2) is converted to the gate high voltage (VGH). =22V). The first switch element M181 includes a gate to which the first input signal IN1 is applied, a first electrode to which the gate high voltage VGH is applied, and a second electrode connected to the output node.

The second switch element M182 is turned on according to the second input signal IN2 and outputs an inversion voltage Vinv. The inversion voltage Vinv may be a negative voltage lower than the reference level, for example, the minimum gate low voltage (VGL) or a negative voltage between the gate low voltage (VGL) and the maximum negative voltage (-Max). The second switch element M182 includes a gate to which the second input signal IN2 is applied, a first electrode to which the inversion voltage Vinv is applied, and a second electrode connected to the output node.

The third switch element (M183) is turned on according to the third input signal (IN3) and outputs an inversion voltage (Vinv). The third switch element M183 includes a gate to which the third input signal IN3 is applied, a first electrode to which the inversion voltage Vinv is applied, and a second electrode connected to the output node.

The NOR gate (NOR) outputs a low voltage when the logic values of the three input signals are the same, while it outputs a high voltage when the logic values of the three input signals are the same. The fourth switch element (M184) is turned on when the output signal of the NOR gate (NOR) is a high voltage and supplies the gate low voltage (VGL) to the output node. The third switch element M184 includes a gate to which the output signal of the NOR gate (NOR) is applied, a first electrode connected to the output node, and a second electrode to which the gate low voltage (VGL) is applied.

Figure 19 is a waveform diagram showing a three-step signal output from the mix circuits 10 and 11 and the level shifter 140.

Referring to FIG. 19, the three step signals output from the mix circuits 10 and 11 are generated at voltages of 3.3V, 0V, and -3.3V. In comparison, the three step signal output from the level shifter 140 is generated as a gate high voltage (VGH=22V), a gate low voltage (VGL=-3V), and an inversion voltage (Vinv). The voltage level of the inversion voltage Viniv may vary depending on the transistor characteristics. For example, in FIG. 19, the inversion voltage Vinv may be varied (or selected) at a voltage between step1 and -VGH.

FIG. 20 is a circuit diagram showing an example in which the mix circuit shown in FIG. 13 is connected to a signal generator and a level shifter. FIG. 21 is a waveform diagram showing the input signals (IN1, IN2), the output signals (MOUT1, MOUT2) of the mix circuit 10, and the output signals (OUT1, OUT2) of the level shifter 140 shown in FIG. 20. .

Referring to FIGS. 20 and 21 , the signal generator 131 may include a shift register to which a D flip-flop is dependently connected. The shift register can generate input signals (IN1, IN2) whose phases are sequentially shifted. The input signals (IN1, IN2) can transition between 3.3V and 0V.

The mix circuit 10 may be connected between the signal generator 131 and the level shifter 140. The mix circuit 10 outputs the non-inverted signal and the inverted signal of the first input signal IN1 and IN2 from the signal generator 131, and then outputs the non-inverted signal and the inverted signal of the second input signal IN2. output and three step signals (MOUT1, MOUT2) can be output. The output signals (MOUT1, MOUT2) of the mix circuit 10 are three step signals having a reference level (0V), a positive voltage of 3.3V, and a negative voltage of -3.3V.

The level shifter 140 shifts the voltage of the input signal from the signal generator 131 or the mix circuit 10 and outputs a three-step signal with a voltage greater than the voltage of the input signal. When the level shifter 140 receives an input signal from the mix circuit 10, the level shifter 140 converts the positive polarity voltage of 3.3V to the gate high voltage (VGH=22V) and sets the reference level of 0V to the gate low. It can be converted to voltage (VGL=-3V), and the negative polarity voltage of -3.3V can be converted to inversion voltage (Vinv).

Figure 22 is a circuit diagram showing an example of a cascade type mix circuit 11. FIG. 23 is a circuit diagram showing an example in which the mix circuit shown in FIG. 22 is connected between a signal generator and a level shifter. FIG. 24 shows the input signals (IN1, IN2, IN3) shown in FIG. 23, the output signals (MOUT1, MOUT2, MOUT3) of the mix circuit 11, and the output signals (OUT1, OUT2, OUT3) of the level shifter 140. This is a waveform diagram showing .

Referring to FIGS. 22 and 23, the signal generator 131 may generate input signals IN1, IN2, and IN3 whose phases are sequentially shifted using a shift register. The input signals (IN1, IN2, IN3) can transition between 3.3V and 0V.

The mix circuit 11 may be connected between the signal generator 131 and the level shifter 140. The mix circuit 11 can output three step signals (MOUT1, MOUT2, MOUT3) by alternately outputting non-inverted signals and inverted signals of the input signals (IN1, IN2, IN3) from the signal generator 131. . The output signals (MOUT1, MOUT2, MOUT3) of the mix circuit 11 are three step signals with a reference level (0V), a positive voltage of 3.3V, and a negative voltage of -3.3V.

The mix circuit 11 receives the first and second input signals (IN1, IN2) and alternately outputs non-inverted outputs and inverted outputs of the first and second input signals (IN1, IN2), respectively, to perform the first three step. A first mix circuit that outputs a signal (MOUT1), receives the second and third input signals (IN2, IN3) and alternately outputs non-inverted and inverted outputs of the second and third input signals (IN2, IN3), respectively. A second mix circuit that outputs a second three step signal (MOUT2), and a second mix circuit that receives the first and third input signals (IN1, IN3) and non-inverts the first and third input signals (IN1, IN3), respectively. It includes a third mix circuit that alternately outputs output and inverted output to output a third three-step signal (MOUT3).

A resistor (R) is connected between the first and second output nodes of the first mix circuit. The first output node of the first mix circuit is connected to the first input node of the level shifter 140 and supplies the first three step signal (MOUT1) to the level shifter 140. The first and second switch elements M11 and M12 supply the non-inverted signal of the first input signal IN1 to the first output node. The third and fourth switch elements M13 and M14 supply the inverted signal of the second input signal IN2 to the first output node.

A resistor (R) is connected between the first and second output nodes of the second mix circuit. The first output node of the second mix circuit is connected to the second input node of the level shifter 140 and supplies the second three-step signal MOUT2 to the level shifter 140. In the second mix circuit, the first and second switch elements M21 and M22 supply the non-inverted signal of the second input signal IN2 to the first output node. The third and fourth switch elements M23 and M24 supply the inverted signal of the third input signal IN3 to the first output node.

A resistor (R) is connected between the first and second output nodes of the third mix circuit. The first output node of the third mix circuit is connected to the third input node of the level shifter 140 and supplies the third three-step signal MOUT3 to the level shifter 140. In the third mix circuit, the first and second switch elements M31 and M32 supply the non-inverted signal of the third input signal IN3 to the first output node. The third and fourth switch elements M33 and M34 supply the inverted signal of the first input signal IN1 to the first output node.

The level shifter 140 shifts the voltage of the input signal from the signal generator 131 or the mix circuit 11 and outputs a three-step signal with a voltage greater than the voltage of the input signal. When the level shifter 140 receives an input signal from the mix circuit 11, the level shifter 140 converts the positive polarity voltage of 3.3V to the gate high voltage (VGH=22V) and sets the reference level of 0V to the gate low. It can be converted to a voltage (VGL=-3V), and the negative polarity voltage of -3.3V can be converted to an inversion voltage (Vinv) lower than the gate low voltage (VGL).

FIG. 25 is a circuit diagram showing an example in which the mix circuit shown in FIG. 17 and the level shifter shown in FIG. 18 are combined. FIG. 26 is a waveform diagram showing the input signal, the output signal of the mix circuit, and the output signal of the level shifter shown in FIG. 25.

Referring to FIGS. 25 and 26 , the signal generator 131 may generate input signals IN1, IN2, and IN3 whose phases are sequentially shifted using a shift register. The input signals (IN1, IN2, IN3) can transition between 3.3V and 0V.

The mix circuit 12 may be connected between the signal generator 131 and the level shifter 140. The mix circuit 12 can output three step signals (MOUT1, MOUT2, MOUT3) by alternately outputting non-inverted signals and inverted signals of the input signals (IN1, IN2, IN3) from the signal generator 131. . The output signals (MOUT1, MOUT2, MOUT3) of the mix circuit 12 are three step signals having a reference level (0V), a positive voltage of 3.3V, and a negative voltage of -3.3V.

The level shifter 140 receives the first and third input signals IN1 and IN3 from the signal generator 131 and shifts the voltage of the input signal using the three step signal MOUT2 from the mix circuit 12. This outputs a three-step signal with a voltage greater than that of the input signal. The NOR gate of the level shifter 140 receives the first and third input signals IN1 and IN3 and the three step signal MOUT2 from the mix circuit 12.

The level shifter 140 converts the positive polarity voltage of 3.3V in the three-step signal from the mix circuit 12 to the gate high voltage (VGH = 22V), and converts the reference level of 0V to the gate low voltage (VGL = -3V). and the negative polarity voltage of -3.3V can be converted to an inversion voltage (Vinv) lower than the gate low voltage (VGL).

When the demultiplexer 112 is a 1:K (K is a natural number of 4 or more) demultiplexer or when the shift clock (CLK) input to the gate driver 120 is a K phase clock, the signal generator 131 Can output first to Kth input signals whose phases are sequentially shifted. In this case, the mix circuit may be implemented as a circuit that combines two or more of the mix circuit shown in FIG. 13, the mix circuit shown in FIG. 17, the mix circuit shown in FIG. 22, and the mix circuit shown in FIG. 25. Additionally, the level shifter may be implemented as a combination of the level shifters described in the above-described embodiments.

It may be necessary to input a two-step pulse rather than a three-step pulse to the display panel driving circuit. In this case, the present invention can convert a three-step signal into a two-step signal using a restoration circuit and supply it to the display panel driving circuit. The restoration circuit may be connected between the mix circuit and the level shifter, or between the level shifter and the display panel driving circuit as shown in FIG. 27. The display panel driving circuit may include one or more of a data driver 110, a demultiplexer 112, and a gate driver 120.

The recovery circuit can be selectively enabled according to preset option pin or register settings. The recovery circuit can be enabled/disabled under the control of the host system or timing controller. Accordingly, the present invention can adaptively enable the restoration circuit according to the driving mode and supply a two-step signal or a three-step signal as a control signal or clock signal to the display panel driving circuit.

Figure 27 is a diagram showing a restoration circuit connected to the output nodes of the level shifter. Figure 28 is a circuit diagram showing an example of a restoration circuit in detail. FIG. 29 is a waveform diagram showing output signals of the level shifter and restoration circuit shown in FIG. 27.

27 to 29, the restoration circuit 290 may be connected to the output node of the level shifter 140.

The restoration circuit 290 receives the three-step signals (OUT1, OUT2) from the level shifter 140, converts them into two-step signals (OUTr1, OUTr2), and supplies them to the display panel driving circuit.

The three step signals (OUT1, OUT2) output from the level shifter 140 include a gate high voltage (VGH), a gate low voltage (VGL) lower than the gate high voltage (VGH), and a gate low voltage (VGL) as shown in FIG. 29. It is generated with a lower inversion voltage (Vinv). The two-step signal output from the restoration circuit 290 is generated as a gate high voltage (VGH) and a gate low voltage (VGL) as shown in FIG. 29.

The restoration circuit 290 includes a comparator 291 and a switch element (SW) as shown in FIG. 28. The switch element (SW) may be implemented as a transistor.

A reference voltage (Vref) is input to the inverting input node of the comparator 291. The three step signals OUT1 and OUT2 from the level shifter 140 are input to the non-inverting input node of the comparator 291. The reference voltage Vref is set to the voltage divided by the resistors R1 and R2 constituting the voltage dividing circuit. The voltage divider circuit includes resistors (R1, R2) connected in series between the high voltage (V) and the base voltage (GND), and an output node between the resistors (R1, R2). The reference voltage (Vref) can be set to the gate low voltage (VGL).

The switch element (SW) includes a first electrode connected to the output node of the voltage dividing circuit, a second electrode to which a three-step signal is applied from the level shifter 140, and a control electrode (or gate) connected to the output node of the comparator 261. Includes. The output node of the level shifter 140 is connected to the non-inverting input node of the comparator 291 and the second electrode of the switch.

The comparator 291 outputs a high voltage when the voltage of the three step signals OUT1 and OUT1 input from the level shifter 140 is greater than the reference voltage Vref. On the other hand, the comparator 291 outputs a low voltage when the voltage of the three step signals OUT1 and OUT1 input from the level shifter 140 is lower than the reference voltage Vref.

The switch element (SW) outputs the gate high voltage (VGH) of the three step signals (OUT1 and OUT2) in response to the high voltage of the comparator 291. The switch element (SW) outputs a reference voltage (Vref) in response to the low voltage of the comparator 291. Therefore, when the three step signals (OUT1, OUT1) input from the level shifter 140 are the gate high voltage (VGH), the switch element (SW) outputs the gate high voltage (VGH) as is, while the three step signal ( When OUT1, OUT1) is the gate low voltage (VGL) or the inversion voltage (Vinv), the reference voltage (Vref), that is, the gate low voltage (VGL), is output.

The output signal of the switch element (SW) is a two-step signal (OUTr1, OUTr2) generated by the gate high voltage (VGH) or the gate low voltage (VGL). The two-step signals OUTr1 and OUTr2 may be supplied to the display panel driving circuit through signal wires.

The two-step output signal output from the restoration circuit 29 has a gate high voltage (VGH=22V) higher than the high voltage (3.3V) of the two-step input signal output from the signal generator 131, and the two-step input signal It can be generated with a gate low voltage (VGL=-3V) that is lower than the low voltage (0V).

The above-described embodiments can be applied singly or combined.

A display device according to an embodiment of the present invention may be described by various embodiments as follows.

Example 1: A display device includes a display panel including a plurality of pixels adjacent to an area where a plurality of data lines and a plurality of gate lines intersect; a display panel driving circuit for writing data into the pixels; a signal generator that generates a two-step signal to control the display panel driving circuit; a plurality of signal wires connecting the display panel driving circuit and the signal generator; and a signal inversion circuit that receives a two-step signal from the signal generator and inverts the two-step signal to supply three-step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage to the signal wires. can do.

The three step signals applied to the neighboring signal wires may be out of phase with each other.

Embodiment 2: The display panel driving circuit includes a data driver that supplies pixel data of an input image as a data signal to the data lines; and a gate driver that supplies a gate signal synchronized with the data signal to the gate lines. The three step signals may be supplied to one or more of the data driver and the gate driver.

Embodiment 3: The display panel driving circuit may further include a demultiplexer connected between the data driver and the data lines to time-divide the data signal to the data lines. The three step signals may be supplied to the control node of the demultiplexer.

Example 4: The two-step signal output from the signal generator may include first and second input signals whose phases are sequentially shifted.

The signal inversion circuit inverts each of the first and second input signals and shifts the voltages of the first and second input signals to have voltages greater than the voltages of the first and second input signals and are out of phase with each other. It may include a level shifter that outputs first and second three step signals.

Example 5: The level shifter outputs a gate high voltage higher than the high voltage of the first input signal in response to the first input signal, and outputs a gate high voltage higher than the low voltage of the second input signal in response to the second input signal. a first level shifter outputting a low inversion voltage; and a second level shifter that outputs the gate high voltage in response to the second input signal and outputs the inverted voltage in response to the first input signal.

Example 6: The first level shifter includes a 1-1 switch element including a gate to which the first input signal is applied, a first electrode to which the gate high voltage is applied, and a second electrode connected to a first output node; A 1-2 switch element including a gate to which the second input signal is applied, a first electrode to which the inversion voltage is applied, and a second electrode connected to the first output node; a first NOR gate outputting a high voltage where the first and second input signals have the same logic value; And it may include 1-3 switch elements including a gate to which the output signal of the first NOR gate is applied, a first electrode connected to the first output node, and a second electrode to which the gate low voltage is applied.

The gate low voltage may be lower than the low voltage of the first and second input signals. The inversion voltage may be lower than the gate low voltage.

Example 7: The second level shifter includes a 2-1 switch element including a gate to which the second input signal is applied, a first electrode to which the gate high voltage is applied, and a second electrode connected to a second output node; a 2-2 switch element including a gate to which the first input signal is applied, a first electrode to which the inversion voltage is applied, and a second electrode connected to the second output node; a second NOR gate outputting a high voltage where the first and second input signals have the same logic value; And it may include a 2-3 switch element including a gate to which the output signal of the second NOR gate is applied, a first electrode connected to the second output node, and a second electrode to which the gate low voltage is applied.

Example 8: The two-step signal output from the signal generator may include first and second input signals whose phases are sequentially shifted.

The signal inversion circuit includes a mix circuit that outputs first and second three-step signals that have a high voltage, a reference level, and a low voltage for each of the first and second input signals and are out of phase with each other; and increasing the high voltage of the first and second three-step signals to a gate high voltage, converting the reference level of the first and second three-step signals to a gate low voltage, and converting the first and second three-step signals to a gate low voltage. It may include a level shifter that converts the low voltage into an inversion voltage lower than the gate low voltage and outputs first and second three step signals with increased voltage.

Example 9: The mix circuit includes a resistor connected between first and second output nodes; A first switch element including a gate through which the first input signal is input, a first electrode connected to a constant current source, and a second electrode connected to the first output node; a second switch element including a gate through which the first input signal is input, a first electrode connected to the second output node, and a second electrode connected to a base voltage source; a third switch element including a gate through which the second input signal is input, a first electrode connected to the constant current source, and a second electrode connected to the second output node; and a fourth switch element including a gate through which the second input signal is input, a first electrode connected to the first output node, and a second electrode connected to the base voltage source.

Embodiment 10: The signal generator may sequentially output first, second, and third input signals whose phases are shifted.

The signal inversion circuit includes a mix circuit that inverts each of the input signals and outputs first, second and third three step signals; and increasing the high voltage of the first, second and third three-step signals to the gate high voltage, converting the reference level of the first, second and third three-step signals to the gate low voltage, and converting the first, second and third three-step signals to a gate low voltage. It may include a level shifter that converts the low voltage of the second and third three step signals into an inversion voltage lower than the gate low voltage and outputs the first, second, and third three step signals with increased voltage.

Example 11: The signal generator may sequentially output first, second, and third input signals whose phases are shifted.

The signal inversion circuit includes a mix circuit that inverts each of the input signals and outputs first, second and third three step signals; and increasing the high voltage of the first, second and third three-step signals to the gate high voltage, converting the reference level of the first, second and third three-step signals to the gate low voltage, and converting the first, second and third three-step signals to a gate low voltage. It may include a level shifter that converts the low voltage of the second and third three step signals into an inversion voltage lower than the gate low voltage and outputs the first, second, and third three step signals with increased voltage.

The mix circuit includes a first mix circuit that receives the first and second input signals and alternately outputs a non-inverted output and an inverted output of each of the first and second input signals to output the first three step signal; a second mix circuit that receives the second and third input signals and outputs the second three-step signal by alternately outputting non-inverted outputs and inverted outputs of the second and third input signals, respectively; and a third mix circuit that receives the first and third input signals and alternately outputs a non-inverted output and an inverted output of each of the first and third input signals to output the third three-step signal. there is.

Example 12: The signal generator may sequentially output first, second, and third input signals whose phases are shifted.

The signal inversion circuit includes a mix circuit that inverts each of the input signals and outputs first, second and third three step signals; And receiving at least one input signal among the input signals and at least one three step signal among the three step signals, increasing the high voltage of the three step signals to the gate high voltage, and setting the reference level of the three step signals to the gate low voltage. and may include a level shifter that converts the low voltage of the three step signals into an inverted voltage lower than the gate low voltage and outputs a step signal with an increased voltage.

Example 13: A display device includes a display panel including a plurality of pixels adjacent to an area where a plurality of data lines and a plurality of gate lines intersect; a display panel driving circuit for writing data into the pixels; a signal generator that generates a two-step input signal to control the display panel driving circuit; a plurality of signal wires connecting the display panel driving circuit and the signal generator; a signal inversion circuit that receives a two-step signal from the signal generator and inverts the two-step signal to convert it into a three-step signal including a positive polarity voltage, a reference level voltage, and a negative polarity voltage; and a restoration circuit that converts the three-step signals from the signal conversion circuit into two-step output signals and supplies them to the signal wires.

The two-step output signal may be generated with a gate high voltage higher than the high voltage of the two-step input signal and a gate low voltage lower than the low voltage of the two-step input signal.

Embodiment 14: The display panel driving circuit includes a data driver that supplies pixel data of an input image as a data signal to the data lines; and a gate driver that supplies a gate signal synchronized with the data signal to the gate lines.

The two-step output signals may be supplied to one or more of the data driver and the gate driver.

Embodiment 15: The display panel driving circuit may further include a demultiplexer connected between the data driver and the data lines to time-divide the data signal to the data lines.

The two-step output signals may be supplied to the control node of the demultiplexer.

Example 16: The two-step input signal output from the signal generator may include first and second input signals whose phases are sequentially shifted.

The signal inversion circuit inverts each of the first and second input signals and shifts the voltages of the first and second input signals to have voltages greater than the voltages of the first and second input signals and are out of phase with each other. It may include a level shifter that outputs first and second three step signals.

Example 17: The two-step input signal output from the signal generator may include first and second input signals whose phases are sequentially shifted.

The signal inversion circuit includes a mix circuit that outputs first and second three-step signals that have a high voltage, a reference level, and a low voltage for each of the first and second input signals and are out of phase with each other; and increasing the high voltage of the first and second three-step signals to a gate high voltage, converting the reference level of the first and second three-step signals to a gate low voltage, and converting the first and second three-step signals to a gate low voltage. It may include a level shifter that converts the low voltage into an inversion voltage lower than the gate low voltage and outputs first and second three step signals with increased voltage.

Embodiment 18: The restoration circuit may convert the three-step signals input from the level shifter into the gate high voltage and the gate low voltage and output the two-step output signals.

Example 19: The restoration circuit includes a comparator that compares the three step signal and a reference voltage; And a switch element that is controlled according to the output voltage of the comparator to output the gate high voltage when the three step signal is greater than the reference voltage and to output the gate low voltage when the three step signal is less than the reference voltage. can do.

The reference voltage may be set to the gate low voltage.

A method of driving a display device according to an embodiment of the present invention can be described through various embodiments as follows.

Example 1: A method of driving a display device includes generating a two-step input signal to control a display panel driving circuit; receiving the two-step input signal and inverting the two-step input signal to generate three step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage; and controlling the display panel driving circuit by supplying the three step signals to a plurality of signal wires connected to the display panel driving circuit.

The three step signals applied to the neighboring signal wires may be out of phase with each other.

Example 2: A display autonomous driving method includes generating a two-step input signal to control a display panel driving circuit; receiving the two-step signal and inverting the two-step input signal to generate three-step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage; converting the three-step signals into two-step output signals and supplying them to the signal wires; and controlling the display panel driving circuit by supplying the two-step output signal to a plurality of signal wires connected to the display panel driving circuit. The two-step output signal may be generated with a gate high voltage higher than the high voltage of the two-step input signal and a gate low voltage lower than the low voltage of the two-step input signal.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

10, 11, 12: mix circuit 21, 22: multiplexer
100: display panel 110: data driver
112: Demultiplexer array 120: Gate driver
130: Timing controller 140: Level shifter
290: restoration circuit

Claims (21)

A display panel including a plurality of pixels adjacent to an area where a plurality of data lines and a plurality of gate lines intersect;
a display panel driving circuit for writing data into the pixels;
a signal generator that generates a two-step signal to control the display panel driving circuit;
a plurality of signal wires connecting the display panel driving circuit and the signal generator; and
a signal inversion circuit that receives a two-step signal from the signal generator, inverts the two-step signal, and supplies three-step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage to the signal wires; ,
The three step signals applied to the neighboring signal wires are out of phase with each other,
The two-step signal output from the signal generator is,
Comprising first and second input signals whose phases are sequentially shifted,
The signal inversion circuit is,
Each of the first and second input signals is inverted and the voltages of the first and second input signals are shifted to generate first and second three signals having voltages greater than the voltages of the first and second input signals and being in phase with each other. A display device including a level shifter that outputs step signals. According to claim 1,
The display panel driving circuit is,
a data driver that supplies pixel data of an input image as a data signal to the data lines; and
A gate driver that supplies a gate signal synchronized with the data signal to the gate lines,
The display device wherein the three step signals are supplied to one or more of the data driver and the gate driver. According to claim 2,
The display panel driving circuit is,
Further comprising a demultiplexer connected between the data driver and the data lines to time-divide the data signal to the data lines,
The three step signals are supplied to the control node of the demultiplexer. delete According to claim 1,
The level shifter is,
A first device that outputs a gate high voltage higher than the high voltage of the first input signal in response to the first input signal and outputs an inversion voltage lower than the low voltage of the second input signal in response to the second input signal. level shifter; and
A display device comprising a second level shifter that outputs the gate high voltage in response to the second input signal and outputs the inverted voltage in response to the first input signal. According to claim 5,
The first level shifter is,
A 1-1 switch element including a gate to which the first input signal is applied, a first electrode to which the gate high voltage is applied, and a second electrode connected to a first output node;
A 1-2 switch element including a gate to which the second input signal is applied, a first electrode to which the inversion voltage is applied, and a second electrode connected to the first output node;
a first NOR gate outputting a high voltage where the first and second input signals have the same logic value; and
Comprising 1-3 switch elements including a gate to which an output signal of the first NOR gate is applied, a first electrode connected to the first output node, and a second electrode to which a gate low voltage is applied,
The gate low voltage is a voltage lower than the low voltage of the first and second input signals,
A display device wherein the inversion voltage is lower than the gate low voltage. According to claim 6,
The second level shifter is,
A 2-1 switch element including a gate to which the second input signal is applied, a first electrode to which the gate high voltage is applied, and a second electrode connected to a second output node;
a 2-2 switch element including a gate to which the first input signal is applied, a first electrode to which the inversion voltage is applied, and a second electrode connected to the second output node;
a second NOR gate outputting a high voltage where the first and second input signals have the same logic value; and
A display device including 2-3 switch elements including a gate to which the output signal of the second NOR gate is applied, a first electrode connected to the second output node, and a second electrode to which the gate low voltage is applied. According to claim 1,
The signal inversion circuit is,
a mix circuit that outputs first and second three-step signals having a high voltage, a reference level, and a low voltage for each of the first and second input signals and being in phase with each other; and
Increase the high voltage of the first and second three-step signals to the gate high voltage, convert the reference level of the first and second three-step signals to the gate low voltage, and lower the first and second three-step signals to the low voltage. A display device including a level shifter that converts a voltage into an inversion voltage lower than the gate low voltage and outputs first and second three step signals with increased voltage. According to claim 8,
The mix circuit is
a resistor connected between the first and second output nodes;
A first switch element including a gate through which the first input signal is input, a first electrode connected to a constant current source, and a second electrode connected to the first output node;
a second switch element including a gate through which the first input signal is input, a first electrode connected to the second output node, and a second electrode connected to a base voltage source;
a third switch element including a gate through which the second input signal is input, a first electrode connected to the constant current source, and a second electrode connected to the second output node; and
A display device comprising a fourth switch element including a gate through which the second input signal is input, a first electrode connected to the first output node, and a second electrode connected to the base voltage source. According to claim 1,
The signal generator,
Output first, second and third input signals whose phases are sequentially shifted,
The signal inversion circuit is,
a mix circuit that inverts each of the input signals and outputs first, second and third three step signals; and
Increase the high voltage of the first, second and third three step signals to the gate high voltage, convert the reference level of the first, second and third three step signals to the gate low voltage, and convert the first, second and third three step signals to the gate low voltage. A display device comprising a level shifter that converts the low voltage of the second and third three step signals into an inversion voltage lower than the gate low voltage and outputs the first, second, and third three step signals with increased voltage. According to claim 1,
The signal generator,
Output first, second and third input signals whose phases are sequentially shifted,
The signal inversion circuit is,
a mix circuit that inverts each of the input signals and outputs first, second and third three step signals; and
Increase the high voltage of the first, second and third three step signals to the gate high voltage, convert the reference level of the first, second and third three step signals to the gate low voltage, and convert the first, second and third three step signals to the gate low voltage. A level shifter that converts the low voltage of the second and third three step signals into an inversion voltage lower than the gate low voltage and outputs first, second, and third three step signals with increased voltage,
The mix circuit is,
a first mix circuit that receives the first and second input signals and outputs the first three-step signal by alternately outputting non-inverted outputs and inverted outputs of the first and second input signals, respectively;
a second mix circuit that receives the second and third input signals and outputs the second three-step signal by alternately outputting non-inverted outputs and inverted outputs of the second and third input signals, respectively; and
A display device including a third mix circuit that receives the first and third input signals and alternately outputs non-inverted outputs and inverted outputs of the first and third input signals, respectively, to output the third three-step signal. . According to claim 1,
The signal generator,
Output first, second and third input signals whose phases are sequentially shifted,
The signal inversion circuit is,
a mix circuit that inverts each of the input signals and outputs first, second and third three step signals; and
Receive one or more input signals among the input signals and one or more three step signals among the three step signals, increase the high voltage of the three step signals to the gate high voltage, and set the reference level of the three step signals to the gate low voltage. A display device comprising a level shifter that converts the low voltage of the three step signals into an inverted voltage lower than the gate low voltage and outputs a step signal with an increased voltage. A display panel including a plurality of pixels adjacent to an area where a plurality of data lines and a plurality of gate lines intersect;
a display panel driving circuit for writing data into the pixels;
a signal generator that generates a two-step input signal to control the display panel driving circuit;
a plurality of signal wires connecting the display panel driving circuit and the signal generator;
a signal inversion circuit that receives a two-step signal from the signal generator and inverts the two-step signal to convert it into a three-step signal including a positive polarity voltage, a reference level voltage, and a negative polarity voltage; and
It includes a restoration circuit that converts the three-step signals from the signal inversion circuit into a two-step output signal and supplies the signal to the signal wires,
The display device wherein the two-step output signal is generated with a gate high voltage higher than the high voltage of the two-step input signal and a gate low voltage lower than the low voltage of the two-step input signal. According to claim 13,
The display panel driving circuit is,
a data driver that supplies pixel data of an input image as a data signal to the data lines; and
A gate driver that supplies a gate signal synchronized with the data signal to the gate lines,
The two-step output signals are supplied to one or more of the data driver and the gate driver. According to claim 13,
The display panel driving circuit is,
It further includes a demultiplexer connected between a data driver and the data lines to time-dividely distribute data signals to the data lines,
The two-step output signals are supplied to a control node of the demultiplexer. According to claim 13,
The two-step input signal output from the signal generator is,
Comprising first and second input signals whose phases are sequentially shifted,
The signal inversion circuit is,
Each of the first and second input signals is inverted and the voltages of the first and second input signals are shifted to generate first and second three signals having voltages greater than the voltages of the first and second input signals and being in phase with each other. A display device including a level shifter that outputs step signals. According to claim 13,
The two-step input signal output from the signal generator is,
Comprising first and second input signals whose phases are sequentially shifted,
The signal inversion circuit is,
a mix circuit that outputs first and second three-step signals having a high voltage, a reference level, and a low voltage for each of the first and second input signals and being in phase with each other; and
Increase the high voltage of the first and second three-step signals to the gate high voltage, convert the reference level of the first and second three-step signals to the gate low voltage, and lower the first and second three-step signals to the low voltage. A display device including a level shifter that converts a voltage into an inversion voltage lower than the gate low voltage and outputs first and second three step signals with increased voltage. The method of claim 16 or 17,
The restoration circuit is,
A display device that converts the three-step signals input from the level shifter into the gate high voltage and the gate low voltage and outputs the two-step output signals. According to claim 18,
The restoration circuit is,
a comparator that compares the three step signal and a reference voltage; and
A switch element that is controlled according to the output voltage of the comparator to output the gate high voltage when the three step signal is greater than the reference voltage and to output the gate low voltage when the three step signal is less than the reference voltage; ,
A display device wherein the reference voltage is set to the gate low voltage. Generating a two-step input signal to control a display panel driving circuit;
receiving the two-step input signal and inverting the two-step input signal to generate three step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage; and
Controlling the display panel driving circuit by supplying the three step signals to a plurality of signal wires connected to the display panel driving circuit,
The three step signals applied to the neighboring signal wires are out of phase with each other,
The two-step input signal is,
Comprising first and second input signals whose phases are sequentially shifted,
The three step signals are,
Each of the first and second input signals is inverted and the voltages of the first and second input signals are shifted to generate first and second three signals having voltages greater than the voltages of the first and second input signals and being in phase with each other. Method of driving a display device with step signals. Generating a two-step input signal to control a display panel driving circuit;
receiving the two-step input signal and inverting the two-step input signal to generate three step signals including a positive polarity voltage, a reference level voltage, and a negative polarity voltage;
converting the three-step signals into two-step output signals; and
Controlling the display panel driving circuit by supplying the two-step output signal to a plurality of signal wires connected to the display panel driving circuit,
A method of driving a display device in which the two-step output signal is generated with a gate high voltage higher than the high voltage of the two-step input signal and a gate low voltage lower than the low voltage of the two-step input signal.