KR102652558B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, which includes a short-circuit sensing unit disposed on at least one of a flexible circuit board, a source drive IC, and a level shifter. The short circuit sensing unit generates a flag signal in sensing mode. The short-circuit defect sensing unit includes a resistor to which a sample voltage is applied; and a comparator that compares a sensing voltage received from any one of the wiring of the flexible circuit board, the output terminal of the level shifter, and the output terminal of the source drive IC with a preset reference voltage.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device having a short circuit detection function.

Flat Panel Display (FPD) writes the pixel data of the input image to the pixels of the display panel and reproduces the input image on the pixel array.

A flat panel display device includes a display panel driving circuit that writes pixel data of an input image to pixels, and a timing controller that controls the display panel driving circuit. The display panel driving circuit includes a data driving circuit that supplies pixel data signals to the data lines, and a gate driving circuit that supplies a gate signal (or scan signal) to the gate lines (or scan lines). Includes. The data driving circuit can be implemented as an integrated circuit (IC).

Signals necessary for driving the display panel are supplied to the display panel driving circuit. Power wires may be short-circuited by conductive foreign substances or moisture on the signal transmission path. In this case, the display panel driving circuit and pixels cannot be driven normally. There is a known method for detecting defects in power wiring during a test process before product shipment.

There is no way to detect progressive defects in power wiring that occur after product shipment. After the product is shipped, power can be supplied to the display device without the step of inspecting the circuit for defects. Among the circuit components, a short-circuited part may be physically damaged when power is applied to the display device, and in severe cases, part of the circuit may be destroyed.

The present invention aims to solve the above-described needs and/or problems.

The present invention provides a display device that can detect short circuit defects in a display device driving circuit in advance and quickly and accurately determine the location of the short circuit defect.

The object of the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device of the present invention includes a display panel in which a plurality of data lines and a plurality of gate lines intersect and a pixel array is arranged; a gate driver disposed on the display panel to supply gate signals to the gate lines using a shift register; a level shifter that shifts the voltage level of an input signal and supplies it to the gate driver; a printed circuit board on which the level shifter is disposed; a source drive IC that supplies data signals to the data lines in a display mode; and a flexible circuit board on which the source drive IC is disposed and connected between the display panel and the printed circuit board.

At least one of the flexible circuit board, the source drive IC, and the level shifter includes a short circuit sensing unit that generates a flag signal in a sensing mode.

The short circuit detection unit includes a resistor to which a sample voltage is applied; and a comparator that compares a sensing voltage received from any one of the wiring of the flexible circuit board, the output terminal of the level shifter, and the output terminal of the source drive IC with a preset reference voltage.

The present invention can sense a short circuit fault in a display panel driving circuit using a short circuit fault sensing unit disposed on at least one of a source drive IC, a flexible circuit board on which the source drive IC is placed, and a level shifter.

The present invention can prevent damage to the display panel driving circuit by disabling the display panel driving circuit when a short circuit is sensed in the display panel driving circuit, thereby extending the life of the display device. The present invention can transmit a warning message to the outside when a short circuit defect is sensed in the display panel driving circuit.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

The accompanying drawings, which are included as part of the detailed description to aid understanding of the present invention, provide embodiments of the present invention, and together with the detailed description, explain technical features of the present invention.
1 is a block diagram showing a display device according to an embodiment of the present invention.
Figure 2 is a circuit diagram showing switch elements of a demultiplexer array.
Figure 3 is a diagram showing an example of a pixel circuit in a liquid crystal display device.
FIG. 4 is a diagram showing an example of a pixel circuit in an organic light emitting display device.
FIG. 5 is a waveform diagram showing the operation of the demultiplexer and pixel circuit shown in FIG. 4.
Figure 6 is a diagram schematically showing the shift register of the gate driving circuit.
7 and 8 are diagrams showing wiring between a timing controller and a level shifter.
Figure 9 is a flowchart schematically showing a defect sensing method according to an embodiment of the present invention.
Figure 10 is a diagram showing an example of a screen in which a panel signal is blocked after an alarm message displayed on the screen when a short circuit is detected in the display panel driving circuit.
FIG. 11 is a diagram showing an example of an alarm message being transmitted externally through a network when a short circuit is detected in the display panel driving circuit.
Figure 12 is a circuit diagram showing a short circuit detection unit according to the first embodiment of the present invention.
Figure 13 is an equivalent circuit diagram showing a short circuit between the COF and the short circuit amount detection unit when the COF's wires and pads are shorted.
Figures 14a and 14b are circuit diagrams showing a short circuit detection unit according to a second embodiment of the present invention.
Figures 15A to 15C are circuit diagrams showing a short circuit detection unit built into the source drive IC and the operation mode of the source drive IC.
Figures 16A to 16C are circuit diagrams showing a short circuit detection unit built into the level shifter and the operation mode of the level shifter.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. Only the embodiments are intended to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “provides,” “includes,” “has,” “consists of,” etc. mentioned in the present invention are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two components is described as 'on top', 'on top', 'on the bottom', 'next to ~', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component. Since the patent claims are written focusing on essential components, the ordinal numbers preceding the component names of the patent claims and the ordinal numbers preceding the component names of the embodiments may not match.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, the display panel driving circuit, pixel array, level shifter, etc. may include transistors. Transistors can be implemented as Oxide TFT (Thin Film Transistor) containing an oxide semiconductor, LTPS TFT containing Low Temperature Poly Silicon (LTPS), etc. Each of the transistors may be implemented as a transistor with a p-channel MOSFET (metal-oxide-semiconductor field effect transistor) or n-channel MOSFET structure.

A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from drain to source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal swings between Gate On Voltage and Gate Off Voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while the transistor is turned-off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage (Gate High Voltage, VGH), and the gate-off voltage may be the gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be the gate low voltage (VGL) and the gate-off voltage may be the gate high voltage (VGH).

The present invention can be applied to any flat panel display device, such as a liquid crystal display (LCD) or an organic light emitting display (OLED display).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

Referring to FIG. 1, a display device 1000 according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The screen of the display panel 100 includes a pixel array (AA) that displays pixel data of an input image. Pixel data of the input image is displayed in pixels of the pixel array (AA). The pixel array AA includes a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, and pixels arranged in a matrix form. In addition to the matrix form, pixels can be arranged in various forms, such as sharing pixels emitting the same color, stripe form, or diamond form.

When the resolution of the pixel array AA is n*m, the pixel array AA includes n pixel columns and m pixel lines L1 to Lm that intersect the pixel columns. A pixel column contains pixels arranged along the y-axis direction. A pixel line includes pixels arranged along the x-axis direction. 1 horizontal period (1H) is the time divided by 1 frame period by the number of m pixel lines (L1 to Lm). Pixel data is written to pixels of one pixel line in one horizontal period (1H).

Each pixel may be divided into red subpixel, green subpixel, and blue subpixel to implement color. Each of the pixels may further include a white subpixel. Each of the subpixels 101 includes a pixel circuit. The pixel circuit includes a pixel electrode, multiple thin film transistors (TFTs), and a capacitor. The pixel circuit is connected to the data line (DL) and gate line (GL).

Touch sensors may be placed on the screen of the display panel 100 to implement a touch screen. Touch input may be sensed using separate touch sensors or may be sensed through pixels. Touch sensors can be implemented as on-cell type or add-on type touch sensors placed on the screen of the display panel or embedded in the pixel array. You can.

The display panel driving circuit includes a data driver 110, a gate driver 120, and a timing controller 130 for controlling the operation timing of the driving circuits 110 and 120. The display panel driving circuit writes data of the input image to the pixels of the display panel 100 under the control of the timing controller 130 in the display mode. The display panel driving circuit can sense a short circuit defect in a sensing mode using a short circuit defect sensing unit (ERC).

The data driver 110 converts the pixel data of the input image received as a digital signal from the timing controller 130 every frame in the display mode to analog gamma using a digital to analog converter (hereinafter referred to as “DAC”). Converts it to a compensation voltage and outputs data signals (Vdata1~3). Data signals Vdata1 to 3 are supplied to the data lines DL.

The data driver 110 may be integrated into the source drive IC (SIC) shown in FIGS. 7 and 8. The source drive IC (SIC) may be mounted on a flexible circuit board, for example, a chip on film (COF). Each source drive IC (SIC) may have a built-in touch sensor driver for driving touch sensors.

The gate driver 120 may be formed in the bezel area BZ where an image is not displayed on the display panel 100 in the display mode. The gate driver 120 receives the gate timing control signal received from the level shifter 140, generates gate signals (GATE1 to 3)1 synchronized with the data signals (Vdata1 to 3), and supplies them to the gate lines (GL). do. The gate signals (GATE1 to 3) applied to the gate lines (GL) turn on the switch elements of the subpixels 101 and the voltages of the data signals (Vdata1 to 3) are charged to the pixel lines. Select . The gate signals (GATE1 to 3) may be generated as pulse signals that swing between the gate high voltage (VGH) and the gate low voltage (VGL). The gate driver 120 shifts the gate signal using a shift register.

The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel drivers 110 and 120 with a frame frequency of input frame frequency x i (i is a positive integer greater than 0) Hz. . The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method.

The timing controller 130 receives pixel data of an input image and a timing signal synchronized therewith from the host system 200 in a display mode. Pixel data of the input image received by the timing controller 130 is a digital signal. The timing controller 130 transmits pixel data to the data driver 110. The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE). Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) can be omitted. The data enable signal (DE) has a period of 1 horizontal period (1H).

The display panel driving circuit may further include a demultiplexer array 112 disposed between the data driver 110 and the gate driver 120.

The demultiplexer array 112 sequentially connects one channel of the data driver 110 to a plurality of data lines DL and time-divides the data voltage output from one channel of the data driver 110 to the data lines DL. By distributing, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 includes a number of switch elements as shown in FIG. 2.

The timing controller 130 provides a data timing control signal for controlling the data driver 110 and a gate timing control signal for controlling the gate driver 120 based on the timing signal received from the host system 200 in the display mode. , a MUX control signal for controlling the switch elements of the demultiplexer array 112, a control signal for sensing a short circuit defect, etc. may be generated.

The gate timing control signal may include a start pulse (Gate Start Pulse (VST)), a shift clock (GCLK), etc. The start pulse (VST) controls the start timing of the gate driver 120 every frame period. The shift clock GCLK controls the shift timing of the gate signal output from the gate driver 120. The timing controller 130 may generate a control signal to control the level shifter 140.

The host system 200 may be any one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile system, and a wearable system. In mobile devices and wearable devices, the data driver 110, timing controller 130, level shifter 140, etc. may be integrated into one drive IC (not shown).

In a mobile system, the host system 200 may be implemented as an Application Processor (AP). The host system 200 may transmit pixel data of the input image to the drive IC through MIPI (Mobile Industry Processor Interface). The host system 200 may be connected to the drive IC through a flexible printed circuit (FPC) 310, for example.

The level shifter 140 shifts the voltage of the input signal received from the timing controller 130 and outputs the shifted voltage. The input signal of the level shifter 140 may be a transistor-transistor logic (TTL) level signal of low level (0V) and high level (3.3V). The level shifter 140 may convert the high level of the input signal into a gate high voltage (VGH) and the low level of the input signal into a gate low voltage (VGL). The input signal of the level shifter 140 may include a gate timing control signal and a MUX control signal. The gate timing control signal whose voltage is shifted by the level shifter 140 is supplied to the gate driver 120. The MUX control signal whose voltage is shifted by the level shifter 140 is supplied to the demultiplexer 1120.

The display device 1000 of the present invention further includes a power supply unit 400.

The power supply unit 400 uses a DC-DC converter to generate direct current (DC) voltage necessary to drive the pixel array of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, buck-boost converter, etc. The power unit 400 adjusts the direct current input voltage from the host system 200 to a gamma reference voltage (VGMA) and a gate high voltage (VGH, VEH). Direct current voltages such as gate low voltage (VGL, VEL), half VDD (HVDD), and common voltage of pixels can be generated. The gamma reference voltage (VGMA) is supplied to the data driver 110. The half VDD voltage is as low as 1/2 voltage compared to VDD and can be used as the output buffer driving voltage of the source drive IC. The gamma reference voltage (VGMA) is divided by gray level through a voltage dividing circuit and supplied to the DAC of the data driver 110. Power generated from the power supply unit 400 may be supplied to the display panel 100 through the COF as shown in FIG. 9 .

FIG. 2 is a circuit diagram showing switch elements M1 and M2 of the demultiplexer array 112.

Referring to FIG. 2, the output buffer (AMP) included in one channel (CH1, CH2) in the data driver 110 may be connected to neighboring data lines DL1 to 4 through the demultiplexer array 112. . The data lines DL1 to 4 may be connected to the pixel electrodes 1011 to 1014 of the subpixels through a thin film transistor (TFT).

The demultiplexer array 112 includes a plurality of demultiplexers. The demultiplexers 21 and 22 may be 1:N demultiplexers with one input node and N output nodes (N is two or more positive integers). The MUX control signals (MUX1, MUX2) are input to the control nodes of the demultiplexers (21, 22) and applied to the gates of the switch elements (M1, M2). The MUX control signals (MUX1, MUX2) control the on/off timing of the switch elements (M1, M2).

The demultiplexers 21 and 22 are illustrated as 1:2 demultiplexers in FIG. 2, but are not limited thereto. For example, each of the demultiplexers 21 and 22 is implemented as a 1:3 demultiplexer, so that one channel can be sequentially connected to three data lines in the data driver 110. The demultiplexer array 112 may be formed directly on the substrate of the display panel 100 or may be integrated into one drive IC together with the data driver 110.

The demultiplexer array 112 uses switch elements M1 and M2 to transmit the data signal Vdata1 output through the first channel CH1 of the data driver 110 to the first and second data lines DL1, The data signal Vdata1 output through the second channel CH2 of the data driver 110 is divided into the third and third channels using the first demultiplexer 21 for time division distribution to DL2 and the switch elements M1 and M2. It includes a second demultiplexer 22 that performs time division distribution on the fourth data lines DL3 and DL4.

Each of the switch elements M1 and M2 may be implemented as a transistor. The switch elements (M1, M2) are turned on according to the gate high voltage (VGH) of the MUX control signals (MUX1, MUX2) applied to the gate through the level shifter 140, and the data driver 110 ) channels to the data lines (DL1 to DL4).

The first switch element M1 is turned on in response to the gate high voltage VGH of the first MUX signal MUX1. At this time, the output buffer (AMP) of the first channel (CH1) is connected to the first data line (DL1) through the first switch element (M1). At the same time, the output buffer AMP of the second channel CH2 is connected to the third data line DL3 through the first switch element M1.

The second switch element M2 is turned on in response to the gate high voltage VGH of the second MUX signal MUX2. At this time, the output buffer (AMP) of the first channel (CH1) is connected to the second data line (DL2) through the second switch element (M2). At the same time, the output buffer AMP of the second channel CH2 is connected to the fourth data line DL4 through the second switch element M2.

Figure 3 is a diagram showing an example of a pixel circuit in a liquid crystal display device.

Referring to FIG. 3, each of the subpixels includes a pixel electrode 1, a common electrode 2, a liquid crystal cell (Clc), a TFT connected to the pixel electrode 31, and a storage capacitor (Cst). The TFT is formed at the intersection of the data lines (DL1 to 3) and the gate line (GL1). The TFT supplies the voltage of the data signal (Vdata) from the data lines (DL1 to 3) to the pixel electrode 31 in response to the gate signal (GATE) from the gate line (GATE).

A data signal, that is, a data voltage of pixel data, is applied to the pixel electrode 1. A common voltage (Vcom), which is the reference potential of the pixels, is applied to the common electrode 2.

As shown in the example of FIG. 4, subpixels of an organic light emitting display device use an organic light emitting diode (“OLED”) to generate light according to pixel data of an input image to display an image. Organic light emitting display devices do not require a backlight unit and can be implemented on flexible materials such as plastic substrates, thin glass substrates, and metal substrates. Therefore, the flexible display can be implemented as an organic light emitting display device.

Flexible displays can change the size and shape of the screen by wrapping, folding, or bending the display panel. Flexible displays can be implemented as rollable displays, bendable displays, foldable displays, slideable displays, etc. The application fields of these flexible displays are expanding.

Flexible displays can be implemented as OLED panels using flexible substrates such as plastic panels. A pixel array may be formed on an organic thin film adhered to a back plate of a plastic panel. The back plate may be a PET (Polyethylene terephthalate) substrate. An organic thin film is formed on the back plate. A pixel array and a touch sensor array can be formed on an organic thin film. The back plate blocks moisture permeation toward the organic thin film to prevent the pixel array from being exposed to humidity. The organic thin film may be a thin polyimide (PI) film substrate. A multi-layer buffer film may be formed on the organic thin film using an insulating material not shown. Wires for supplying power or signals applied to the pixel array and the touch sensor array may be formed on the organic thin film.

The pixels of an organic light emitting display device may include an OLED, a driving element that drives the OLED by controlling the current flowing through the OLED according to the gate-source voltage (Vgs), and a storage capacitor that maintains the gate voltage of the driving element. .

The driving element may be implemented as a transistor. In order to maintain uniform image quality across the screen of an organic light emitting display device, the driving element must have uniform electrical characteristics among all pixels. There may be differences in the electrical characteristics of driving elements between pixels due to process deviations and device characteristic deviations resulting from the display panel manufacturing process, and these differences may become larger as the driving time of the pixels elapses. To compensate for differences in electrical characteristics of driving elements between pixels, internal compensation technology and/or external compensation technology may be applied to the organic light emitting display device.

External compensation technology uses an external compensation circuit to sense the current or voltage of driving elements that change according to the electrical characteristics of the driving elements in real time. External compensation technology compensates in real time for the deviation (or change) in the electrical characteristics of the driving element in each pixel by modulating the pixel data (digital data) of the input image by the deviation (or change) in the electrical characteristics of the driving element sensed for each pixel.

Internal compensation technology uses an internal compensation circuit built into each pixel to sense the threshold voltage of the driving element for each sub-pixel and compensates the gate-source voltage (Vgs) of the driving element by the threshold voltage. The internal compensation circuit includes a storage capacitor (Cst) connected to the gate of the driving element (DT), and one or more switch elements (T1 to 5) connecting the storage capacitor (Cst), the driving element (DT), and the light emitting element (EL). Includes.

The multiplexers 21 and 22 can be applied to both organic light emitting display devices using internal compensation technology or external compensation technology. Figure 4 shows an example in which the multiplexer 21 is disposed in an organic light emitting display device to which internal compensation technology is applied, but the present invention is not limited thereto.

Referring to FIGS. 4 and 5 , the gate signal may include a scan signal and an emission control signal (hereinafter referred to as an “EM signal”) in an organic light emitting display device. In FIG. 4, GL11 to GL13 are gate lines connected to subpixels of a 1-pixel line. In Figure 5, D1(N) and D2(N) are data signals (Vdata) applied to pixels of the Nth pixel line. D1(N+1) and D2(N+1) are data signals (Vdata) applied to pixels of the N+1th pixel line. X is a section in which there is no data signal (Vdata).

The power supply unit 400 may output pixel power such as a pixel driving voltage (ELVDD), a low potential voltage (ELVSS), and a reference voltage (Vref) applied to pixels in an organic light emitting display device.

1 The horizontal period (1H) may include an initialization period (Tini), a data writing period (Twr), and a maintenance period (Th).

Pixels may emit light during an emission period (Tem). The emission period (Tem) corresponds to most of the 1 frame period excluding 1 horizontal period (1H) in the 1 frame period. A retention period (Th) may be added between the data writing period (Twr) and the light emission period (Tem).

In order to accurately express the luminance of low gray scale, the EM signal [EM(N)] is divided into gate-on voltage (VEL) and gate-off voltage at a predetermined duty ratio during the emission period (Tem). (VEH) can swing between.

The pulse of the second scan signal [SCAN2(N)] is inverted to the gate-on voltage (VGL) before the first scan signal [SCAN1(N)], and the pulse of the first scan signal [SCAN1(N)] is inverted at the same time as the pulse of the first scan signal [SCAN1(N)]. It is inverted to the off voltage (VGH). The pulse width of the first and second scan signals [SCAN1(N), SCAN2(N)] may be set to 1 horizontal period (1H) or less.

The pulse of the EM signal (EM) may be generated as a gate high voltage (VEH) to suppress light emission of the light emitting element (EL) during the data writing period (Twr) and sustain period (Th). The EM signal (EM) is inverted to the gate high voltage (VEH) when the first scan signal [SCAN1(N)] is inverted to the gate low voltage (VGL), and the first and second scan signals [SCAN1(N), [SCAN2(N)] may be inverted to the gate high voltage (VEH) and then to the gate low voltage (VEL).

During the initialization period (Tini), the second scan signal [SCAN2(N)] is inverted to the gate low voltage (VGL). At this time, major nodes of the pixel circuit may be initialized.

During the data writing period Twr, the first scan signal [SCAN1(N)] is inverted to the gate low voltage VGL. At this time, the data signal Vdata is applied to the first electrode of the capacitor Cst, and ELVDD-Vth is applied to the second electrode of the capacitor Cst. During the data writing period (Twr), when the gate-source voltage (Vgs) of the driving element (DT) reaches the threshold voltage (Vth) of the driving element (DT), the driving element (DT) turns off. ), the threshold voltage (Vth) of the driving element (DT) is sampled in the capacitor (Cst), and the data voltage (Vdata) compensated by the threshold voltage (Vth) is charged in the capacitor (Cst).

The light emitting element (EL) can be implemented as OLED. OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer of OLED may include, but is not limited to, a hole injection layer (HIL), hole transport layer (HTL), light emitting layer (EML), electron transport layer (ETL), and electron injection layer (EIL). The anode of the light emitting element EL is connected to the fourth and fifth switch elements T4 and T5 through the fourth node n4.

A low-potential power supply voltage (VSS) is applied to the cathode of the light emitting element (EL). The driving element DT drives the light emitting element EL by supplying current to the light emitting element EL according to the gate-source voltage Vgs. The light emitting element EL emits light with a current controlled by the driving element DT according to the voltage of the data signal Vdata. The current path of the light emitting element (EL) is switched by the fourth switch element (T4).

The capacitor Cst is connected between the first node n1 and the second node n2. The capacitor Cst is charged with the compensated voltage of the data signal Vdata equal to the threshold voltage Vth of the driving element DT. Since the voltage of the data signal Vdata in each subpixel is compensated by the threshold voltage Vth of the driving element DT, the threshold voltage deviation of the driving element DT in the subpixels can be compensated.

The first switch element (T1) is turned on in response to the gate low voltage (VGL) of the first scan signal [SCAN1(N)] to increase the voltage of the data signal (Vdata) to the first node (n1). ) is supplied to. The first switch element T1 includes a gate connected to the first gate line GL11 to which the first scan signal [SCAN1(N)] is applied, a first electrode connected to the data lines DL1 and DL2, and a first node ( It includes a second electrode connected to n1).

The second switch element T2 is turned on in response to the gate low voltage VGL of the second scan signal [SCAN2(N)] and connects the gate of the driving element DT and the second electrode. The second switch element T2 includes a gate connected to the second gate line GL12 to which the second scan signal [SCAN2(N)] is applied, a first electrode connected to the second node n2, and a third node n3. ) and a second electrode connected to the electrode.

The third switch element (T3) is turned on in response to the gate low voltage (VEL) of the EM signal [EM(N)] and is referenced to the first node (n1) during the initialization period (Tini) and the emission period (Tem). Supply voltage (Vref). Due to the third switch element T3, the first electrode voltage of the capacitor Cst is initialized to Vref during the initialization period Tini and the emission period Tem. The third switch element T3 is connected to the gate connected to the third gate line G13 to which the EM signal [EM(N)] is applied, the first electrode connected to the first node n1, and the Vref line to which Vref is applied. It includes a connected second electrode.

The fourth switch element (T4) is turned on in response to the gate low voltage (VEL) of the EM signal [EM(N)] to control the third node (n3) during the initialization period (Tini) and the emission period (Tem). 4 Connect to node (n4). The gate of the fourth switch element T4 is connected to the third gate line GL13. The first electrode of the fourth switch element T4 is connected to the third node n3, and the second electrode of the fourth switch element T4 is connected to the fourth node n4.

The fifth switch element (T5) is turned on in response to the gate low voltage (VGL) of the second scan signal [SCAN2(N)] and connects Vref to the fourth node during the initialization period (Tini) and the data writing period (Twr). It is supplied to (n4). The gate of the fifth switch element T5 is connected to the second gate line GL12. The first electrode of the fifth switch element T5 is connected to the Vref line, and the second electrode of the fifth switch element T5 is connected to the fourth node n4.

The driving element DT is operated as a diode by the second switch element T2 turned on during the data writing period Twr. The threshold voltage (Vth) of the driving element (DT) is sampled during the data writing period (Twr). The driving element DT drives the light emitting element EL by controlling the current flowing through the light emitting element EL according to the gate-source voltage Vgs during the light emission period Tem. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the ELVDD line to which ELVDD is applied, and a second electrode connected to the third node n3.

The gate driver 120 may include a shift register. The timing controller 130 may control the gate driver 120 by generating gate timing control signals (VST, GCLK) as shown in FIG. 6. Gate timing control signals (VST, GCLK) may be input to the shift register of the gate driver 120.

FIG. 6 is a diagram schematically showing the shift register of the gate driver 120. The shift register of the gate driver 120 includes dependently connected stages [SR(n-1) to (n+2)]. The shift register receives a start pulse (VST) or carry signal (CAR) and generates an output signal [OUT(n-1)) to (n+2)] in accordance with the shift clock (GCLK) timing. The carry signal (CAR) may be output from the previous stage.

Each of the stages [SR(n-1) to (n+2)] includes a control unit 60 that charges and discharges the Q node and QB node, and charges the gate line according to the Q node voltage to raise the waveform of the gate signal ( rising) and includes a buffer that discharges the gate line according to the QB node voltage. The buffer includes a pull-up transistor (Tup) and a pull-down transistor (Tdn). The output signals [OUT(n-1) to (n+2)] of the stages [SR(n-1) to (n+2)] are gate signals sequentially applied to the gate lines.

In a large screen display device, the control board may be connected to two or more source printed circuit boards (PCBs) as shown in FIGS. 7 and 8.

7 and 8, the control board 150 is connected to the first and second source PCBs through a flexible circuit board, for example, a flexible flat cable (FFC) 151 and connectors 151a and 151b. You can.

The COF on which the source drive IC (SIC) is mounted is connected between the source PCB and the display panel 100. The input pads of the COF are connected to the output terminals of the source PCB. The output pads of the COF are connected to the input pads of the display panel. The output pads of the COF may be adhered to the input pads of the display panel 100 through an anisotropic conductive film (ACF).

The timing controller 130 and level shifter 140 may be mounted on the control board 150 as shown in FIG. 7. Input terminals of the level shifter 140 are connected to the timing controller 130 through wires formed on the control board 150. The output terminals of the level shifter 140 may be connected to the gate driver 120 through the FFC 151, the source PCB, the COF, and the LOG (Line On Glass) wires on the display panel 100.

The level shifter 140 may be mounted on each of the source PCBs as shown in FIG. 8. In this case, the level shifter 140 may include a first level shifter 141 mounted on a first source PCB and a second level shifter 142 mounted on a second source PCB. The input terminals of each of the level shifters 141 and 142 may be connected to the timing controller 130 through wires connecting the control board 150, the FFC 151, and the source PCB. The output terminals of the level shifters 141 and 142 may be connected to the gate driver 120 through the source PCB, COF, and LOG wires on the display panel 100.

As shown in FIG. 9, the COF disposed on the leftmost and/or rightmost side of the display panel 100 close to the gate driver 120 is connected to the power wires to which the power or pixel power of the gate driver 120 is applied and the clock. Wires may be formed.

In the display panel driving circuit, particularly in the bonding portion between the COF and the display panel 100, a short circuit may occur between power wires due to conductive foreign substances or moisture. If a short circuit occurs in the COF or bonding part, a short circuit occurs in the source drive IC or level shifter. When power is input to the display device 1000 with such a short circuit defect (Power ON) and the display panel driving circuit is driven to generate a panel signal, the panel signal is applied to the short circuit. Panel signals include signals necessary to drive pixels, such as data signals, gate signals, and pixel driving power. If a panel signal is generated from a display device with a short circuit, not only may the short circuit be damaged, but in extreme cases, the source drive IC and level shifter may be physically destroyed.

The display device of the present invention includes a short circuit detection unit. The present invention uses a short circuit detection unit to monitor in real time whether a display panel driving circuit is short-circuited, and when a short circuit in the display panel driving circuit is detected, it disables the display panel driving circuit to block panel signal generation. When the display panel driving circuit is short-circuited, the display device displays an alarm message on the screen.

Figure 9 is a flowchart schematically showing a defect sensing method according to an embodiment of the present invention. Figure 10 is a diagram showing an example of a screen in which a panel signal is blocked after an alarm message displayed on the screen when a short circuit is detected in the display panel driving circuit. FIG. 11 is a diagram showing an example in which an alarm message is transmitted externally through a network when a short circuit is detected in the display panel driving circuit.

Referring to Figures 9 and 10, the display device 1000 self-diagnoses the display panel driving circuit and monitors a short circuit in the display panel driving circuit (S00, S01). When power to the display device 1000 is input, the display device 1000 drives a short-circuit detection unit to determine whether the display panel driving circuit, especially the source drive IC, COF, level shifter (LS), etc. is short-circuited.

When the display panel driving circuit is short-circuited, the display device 1000 displays a preset alarm message on the screen as shown in FIG. 10 and then disables the display panel driving circuit to block the panel signal (S02).

When the panel signal is blocked, the screen appears black. The display device 1000 can transmit an alarm message (AM) to the outside through a wired/wireless network connected to the communication module of the host system 2000 (SO2). The alarm message may be transmitted to the process control system 2000 connected to the process line in the module assembly process of the display device. After product shipment of the display device, an alarm message may be transmitted to a service center (Warranty and repair service center, 3000) through a wired/wireless network.

When a short circuit in the display panel driving circuit is not detected when the power of the display device 1000 is input, the display panel driving circuit operates normally, generates a panel signal, and displays the input video signal on the screen (S03, S04). .

Figure 12 is a circuit diagram showing a short circuit detection unit according to the first embodiment of the present invention.

Referring to FIG. 12, the display panel driving circuit includes a COF connected between the display panel 100 and the PCB.

The pixel array AA and the gate driver 120 may be disposed on the display panel 100 . A level shifter (LS) may be placed on the PCB. The short circuit detection unit (ERC) may be placed on the PCB, but is not limited to this. For example, the short circuit detection unit (ERC) may be built into the level shifter (LS) and/or the source drive IC (SIC) as shown in FIGS. 14A to 16C.

A source drive IC (SIC) may be placed on the COF. The COF includes clock wires 30, dummy wires 33, data input wires 34, data output wires 35, input pads 31 connected to the connector of the PCB, and a display panel 100. It includes output pads 32 connected to . The input pads 31 are connected to one end of each of the clock wires 30, one end of each of the dummy wires 33, and one end of each of the data input wires 34, and are connected to the output pad of the PCB through a connector. It is connected 1:1 to the field. The output pads 32 are connected to the other end of each of the clock wires 30, the other end of each of the dummy wires 33, and one end of each of the data output wires 35, and are connected to the display panel 100 through the ACF. ) is joined to the pads.

Clock wires 30 connect clock output terminals of the level shifter LS to clock input terminals of the gate driver 120. A LOG (line on glass) clock wiring (CL) connecting the COF and the gate driver 120 is formed on the display panel substrate.

Pads connected to the other ends of each of the data input wires 34 are connected to input terminals of the source drive IC (SIC). Pads connected to the other ends of each of the data output wires 34 are connected to output terminals of the source drive IC (SIC). Data input wires 34 connect the data output terminals of the timing controller 130 and the input terminals of the source drive IC (SIC).

It can be used to check alignment between the dummy wires 30, the COF connected to the dummy wires 30, and the display panel 100 in a bonding process. The dummy wires 30 may be used for purposes other than alignment.

The level shifter (LS) includes buffers connected to output terminals in each of the channels of the level shifter (LS). The buffer of the level shifter (LS) uses the first and second transistors (M11 and M12) to output a signal swinging between the gate high voltage (VGH) and the gate low voltage (VGL) through the output terminal in the display mode. do. The first transistor M11 is turned on under the control of the timing controller 130 and supplies the gate high voltage VGH to the output terminal. The second transistor M12 is turned on under the control of the timing controller 130 and connects the output terminal to the VGL node to discharge the output terminal to the gate low voltage VGH.

The level shifter LS further includes a third transistor M13 that is turned on in ground mode.

The third transistor M13 is synchronized to the short-circuit detection unit ERC by the timing controller 130. The third transistor M13 is turned on when the short circuit detection unit (ERC) is driven under the control of the timing controller 130 and connects the output terminal of the level shifter LS to the ground (GND).

The start pulse and shift clock output from the level shifter LS are supplied to the data driver 120 through the clock wires 30.

The source drive IC (SIC) includes output buffers (AMP) and a fourth transistor (M31) connected to each of the output terminals of the source drive IC (SIC) to output a data signal (Vdata).

The fourth transistor (M31) is synchronized with the short circuit detection unit (ERC) by the timing controller (M31). The fourth transistor M31 is turned on when the short circuit detection unit (ERC) is driven under the control of the timing controller 130 and connects the output terminal of the source drive IC (SIC) to the ground (GND).

The short circuit detection unit (ERC) includes a current limiting resistor (R1) to which a sample voltage (Vsam) is applied, and a comparator (COMP) connected to the current limiting resistor (R1). The short circuit detection unit (ERC) may generate a flag signal (Vflag) indicating a short circuit failure of at least one of the COF, the source drive IC (SIC), and the level shifter in the sensing mode.

The current limiting resistor (R1) is connected between the sample voltage input node and the input pad 32 of the COF to limit the current flowing into the COF to increase short-circuit sensing sensitivity. The current limiting resistor (R1) can be connected to the output pad of the PCB and the input pad 32 of the COF through a connector. Without the current limiting resistor (R1), the input voltage of the comparator (COMP) has a small voltage level difference regardless of whether there is a short circuit, so short circuit sensing sensitivity is lowered. The resistance value of the current limiting resistor (R1) and the voltage level of the reference voltage (Vr) of the comparator (COMP) can be appropriately selected according to the desired short circuit sensing sensitivity and short circuit judgment level.

When the power of the display device 100 is input (Power ON), the power supply unit 400 supplies a sample voltage (Vsam) to the short circuit detection unit (ERC). The sample voltage (Vsam) may be 3.3V, but is not limited thereto.

The comparator (COMP) is connected to the first input terminal (-) to which the reference voltage (Vr) is applied, the node between the current limiting resistor (R1) and the input pad of the COF, and receives the sensed voltage (Vsen). 2 It includes an input terminal (+) and an output terminal that outputs a flag signal (Vflag).

The first input terminal (-) of the comparator (COMP1) to which the sensing voltage (Vsen) is applied and the current limiting resistor (R1) may be connected to the input pad 31 of the COF.

When power is input to the display device 1000 (Power ON), the short circuit detection unit (ERC) and the transistors M13 and M31 are driven under the control of the timing controller 130. When the transistors M13 and M31 are turned on, the COF wires are connected to the ground (GND).

If the conductive foreign material 40 is present in the bonding portion between the COF and the display panel 100, the sensing voltage Vsen is lowered. When the COF's wires and pads are short-circuited, the sensing voltage (Vsen) at the node between the current limiting resistor (R1) and the resistance (R2) due to the conductive foreign matter is determined according to the voltage distribution law, as shown in FIG. 13. . Compared to the case where there is no conductive foreign matter, if the COF is short-circuited due to the conductive foreign matter, the sample sensing voltage (Vsen) is lowered.

The comparator (COMP) compares the reference voltage (Vr) and the sensing voltage (Vsen) and outputs a high level flag signal (Vflag) when the sensing voltage (Vsen) is greater than the reference voltage (Vr). The comparator (COMP) compares the reference voltage (Vr) and the sensing voltage (Vsen) and outputs a low level flag signal (Vflag) when the sensing voltage (Vsen) becomes lower than the reference voltage (Vr). Accordingly, when the COF wires and pads are shorted, the voltage of the flag signal Vflag is at a low level.

The short circuit judgment level may vary depending on the reference voltage (Vref) of the comparator (COMP). For example, when Vsam = Vr = 3.3V, R1 = 10KΩ, R2 < 10KΩ, a short circuit is detected when Vsen < 3.3V. When Vsam = 3.3V, Vr = 1.6 V, R1 = 10KΩ, R2 < 10KΩ, a short circuit is detected when Vsen < 1.6V.

When a low-level flag signal (Vflag) is input to the timing controller 130, preset warning message data can be transmitted to the source drive IC (SIC) and a warning message can be displayed on the screen. Warning message data can be stored in the internal memory of the source drive IC (SIC). In this case, the source drive IC (SIC) may display the warning message on the screen by outputting the data voltage of the warning message data in response to the flag signal (Vflag). When a low-level flag signal (Vflag) is received, the host system 200 may transmit a preset warning message (AM) to the outside through a communication module and a network.

Figures 14a and 14b are circuit diagrams showing a short circuit detection unit according to a second embodiment of the present invention. In Figures 14a and 14b, the current limiting resistor is omitted.

Referring to FIGS. 14A and 14B , at least one of the source drive IC (SIC) and the level shifter (LS) may include a short circuit sensing unit.

Each of the channels of the source drive IC (SIC) may include a comparison unit (COMP) of the short circuit detection unit (ERC) and a current limiting resistor (R1). The first input terminal (+) of the comparator (COMP) to which the sensing voltage (Vsen) is applied from each channel of the source drive IC (SIC), and the current limiting resistor (RC) are connected to the output terminal of the source drive IC (SIC). connected. The output terminal is connected to the output pad 32 of the COF.

In sensing mode, each channel of the source drive IC (SIC) can detect a short circuit defect through the output terminal. The sensing mode can be divided into a first stage and a second stage. In the first and second steps, the channels of the source drive IC (SIC) and the level shifter (LS) are sequentially sensed for short circuit defects in a preset order, but it should be noted that the order is not limited to this.

In the first step, the source drive IC (SIC) outputs the sample voltage (Vsam) through the output terminal of the odd-numbered channel (CODD) as shown in FIG. 14A and detects the sensing voltage (Vsen) with the comparator (COMP). At this time, the output terminal of the even-th channel (CEVEN) is connected to the ground (GND) through the transistor (M31). The sample voltage (Vsam) output from the odd-numbered channel (CODD) is applied to the odd-numbered wires 35 on the COF. In the first step, the short circuit amount of the odd channel (CODD) of the source drive IC (SIC) may be detected by the comparator (COMP).

In the first step, the level shifter LS outputs the sample voltage Vsam through the output terminal of the odd-numbered channel LODD, as shown in FIG. 14b, and detects the sensing voltage Vsen with the comparator COMP. At this time, the output terminal of the odd-numbered channel (LEVEN) is connected to the ground (GND) through the transistor (M13). The sample voltage (Vsam) output from the odd-numbered channel (LODD) is applied to the odd-numbered wires 30 on the COF. At this time, the short circuit amount of the odd channel (LODD) of the level shifter (LS) can be detected by the comparator (COMP).

In the second step, the source drive IC (SIC) outputs the sample voltage (Vsam) through the output terminal of the even-th channel (CEVEN) as shown in FIG. 14b, and detects the sensing voltage (Vsen) with the comparator (COMP). At this time, the output terminal of the even-th channel (CEVEN) is connected to the ground (GND) through the transistor (M31). The sample voltage (Vsam) output from the even number channel (CEVEN) is applied to the even number interconnections 35 on the COF. In the second step, the amount of short circuit in the even channel (CEVEN) of the source drive IC (SIC) may be detected by the comparator (COMP).

In the second step, the level shifter LS outputs the sample voltage Vsam through the output terminal of the even-th channel LEVEN, as shown in FIG. 14b, and detects the sensing voltage Vsen with the comparator COMP. At this time, the output terminal of the odd-numbered channel (LODD) is connected to the ground (GND) through the transistor (M13). The sample voltage (Vsam) output from the even-numbered channel (LODD) is applied to the even-numbered wirings 30 on the COF. At this time, the short-circuit amount of the even-th channel (LEVEN) of the level shifter (LS) can be detected by the comparator (COMP).

As shown in FIGS. 14A and 14B, the level shifter LS can generate the sample voltage Vsam using the buffers M11 and M12 without adding separate circuit elements. For example, the gate voltage of the first transistor M11 can be adjusted to output a sample voltage with an output voltage determined according to the gate-source voltage. In this case, the current limiting resistor R1 may be replaced with the channel resistance of the first transistor M11. In another embodiment, separate current limiting resistors and switch elements may be added as shown in FIGS. 16A to 16C.

Figures 15A to 15C are circuit diagrams showing a short circuit detection unit built into a source drive IC (SIC) and the operation mode of this source drive IC.

Referring to FIGS. 15A to 15C, each channel of the source drive IC (SIC) may operate in sensing mode, ground mode, and display mode under the control of the timing controller 130.

The sensing mode outputs a sample voltage (Vsam) through the channel of the source drive IC (SIC) and receives a sensing voltage (Vsen) to sense short circuit defects. Ground mode connects the corresponding channel to the ground (GND) in conjunction with the sensing mode of another channel of the source drive IC (SIC), or connects the corresponding channel to the sensing mode of the short circuit detection unit (ERC) or other display panel driving circuit. Connect to ground (GND).

In the display mode, pixel data of the input image is written into pixels and the image is displayed on the pixel array (AA). The channel of the source drive IC (SIC) outputs the data voltage (Vdata) output from the DAC in display mode. In sensing mode, a short circuit defect in the display panel driving circuit is sensed. In sensing mode, the channel of the source drive IC (SIC) outputs a sample voltage (Vsam) and compares the sensing voltage (Vsen) with the reference value (Vr) to detect short circuit defects. In ground mode, the channel of the source drive IC (SIC) is connected to ground (GND).

Each channel of the source drive IC (SIC) includes a DAC, output buffer (AMP), current limiting resistor (R1), comparator (COMP), switch elements (SW1 to SW6), transistor (M31), etc. Switch elements (SW1 to SW6) can be implemented as transistors.

The DAC converts pixel data into a gamma compensation voltage and outputs a data voltage (Vdata). The output buffer (AMP) transfers the data voltage (Vdata) to the output terminal (OUT1) without loss.

The current limiting resistor (R1) is connected between the output buffer (AMP) and the output terminal (OUT1) of the source drive IC. The comparator (COMP) is connected between the current limiting resistor (R1) and the flag signal output terminal (OUT2). The first input terminal (-) of the comparator (COMP) is connected to the node between the first current limiting resistor (R1) and the output terminal (OUT1) and receives the sensing voltage (Vsen) from the output terminal (OUT1).

The switch elements (SW1 to SW6) switch the data signal path, sample voltage path, and sensing voltage path.

The first and second switch elements SW1 and SW2 are turned on in the display mode. The first and second switch elements SW1 and SW2 may remain in an off state in sensing mode and ground mode. The first switch element (SW1) is connected between the DAC and the output buffer (AMP) and connects the output terminal of the DAC to the output buffer (AMP) in display mode. The second switch element (SW2) is connected between the output buffer (AMP) and the output terminal (OUT1). The first and second switch elements (SW1, SW2) connect a data signal path through which the data voltage (Vdata) output from the DAC is transmitted in the display mode under the control of the timing controller 130, and in the sensing mode and ground mode. Block the data signal path.

The transistor M31 is turned on in ground mode under the control of the timing controller 130 and connects the output terminal (OUT1) of the corresponding channel to the ground (GND). Transistor (M31) remains off in sensing mode and display mode.

The third to sixth switch elements (SW3 to SW6) are turned on in sensing mode. The third to sixth switch elements (SW3 to SW6) may remain off in the display mode and ground mode. The third switch element (SW3) is connected between the sample voltage source and the input terminal (+) of the output buffer (AMP) and is turned on in sensing mode to connect the sample voltage source to the input terminal (+) of the output buffer (AMP). . The power supply unit 400 may output a sample voltage (Vsam). The timing controller 130 transmits the sensing voltage data to the source drive IC (SIC) in sensing mode, and the DAC converts the sensing voltage data into a gamma reference voltage from the power supply unit 400 and outputs a sample voltage (Vsam). there is. The sample voltage source may be the power supply unit 400 or a DAC.

The fourth switch element (SW4) is connected between the output buffer (AMP) and the current limiting resistor (R1) and is turned on in the sensing mode to connect the output terminal of the output buffer (AMP) and the current limiting resistor (R1). The fifth switch element (SW5) is connected between the node between the current limiting resistor (R1) and the output terminal (OUT1) and the input terminal (-) of the comparator (COMP) and is turned on in sensing mode to output the output terminal (OUT1). ) to the input terminal (-) of the comparator (COMP). The sixth switch element (SW6) is connected between the output terminal of the comparator (COMP) and the flag signal output terminal (OUT2) and is turned on in sensing mode to connect the output terminal of the comparator (COMP) and the flag signal output terminal (OUT2). Connect.

FIGS. 16A to 16C are circuit diagrams showing a short circuit sensing unit built into the level shifter (LS) and the operation mode of the level shifter (LS).

Referring to FIGS. 16A to 16C, each channel of the level shifter LS may operate in a sensing mode, a ground mode, and a display mode under the control of the timing controller 130.

The sensing mode outputs the sample voltage (Vsam) through the channel of the level shifter (LS) and receives the sensing voltage (Vsen) to sense short circuit defects. Ground mode connects the corresponding channel to ground (GND) in conjunction with the sensing mode of another channel of the level shifter (LS), or connects the corresponding channel to the sensing mode of the short-circuit detection unit (ERC) or other display panel driving circuit. Connect to ground (GND).

In the display mode, pixel data of the input image is written into pixels and the image is displayed on the pixel array (AA). The channel of the level shifter (LS) shifts the voltage level of the input signal in the display mode and swings between the gate high voltage (VGH) and the gate low voltage (VGL) using the first and second transistors (M11 and M12). outputs a signal. In sensing mode, a short circuit defect in the display panel driving circuit is sensed. In sensing mode, the channel of the level shifter (LS) outputs a sample voltage (Vsam) and detects a short circuit by comparing the sensing voltage (Vsen) with the reference value (Vr). In ground mode, the channel of the level shifter (LS) is connected to ground (GND).

Each of the channels of the level shifter (LS) includes transistors (M11 to M13), a current limiting resistor (R1), a comparator (COMP), and switch elements (SW11 and SW12). The switch elements (SW11 and SW12) may be implemented as transistors.

The current limiting resistor (R1) is connected between the output terminal (OUT11) of the level shifter (LS) and the sample voltage source. The sample voltage source may be the power supply unit 400. The comparator (COMP) is connected between the current limiting resistor (R1) and the flag signal output terminal (OUT12). The first input terminal (-) of the comparator (COMP) is connected to the node between the first current limiting resistor (R1) and the output terminal (OUT11) and receives the sensing voltage (Vsen) from the output terminal (OUT11).

The first switch element (SW11) is connected between the buffer output node between the first transistor (M11) and the second transistor and the output terminal (OUT11) of the level shifter (LS). The first switch element (SW11) is turned on in the display mode under the control of the timing controller 130 to connect the buffer output node to the output terminal (OUT11). The first switch element (SW11) remains off in sensing mode and ground mode.

The second switch element (SW12) is connected between the current limiting resistor (R1) and the output terminal (OUT11) of the level shifter. The second switch element (SW12) is turned on in the sensing mode under the control of the timing controller 130 and connects the current limiting resistor (R1) to the output terminal (OUT11). The second switch element (SW12) remains off in the display mode and ground mode.

The third transistor (M13) is turned on in ground mode under the control of the timing controller 130 and connects the output terminal (OUT11) of the corresponding channel to the ground (GND). The third transistor (M31) remains off in sensing mode and display mode.

The above-described embodiments can be applied singly or combined.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

10: comparator 21, 22: demultiplexer
100: display panel 110, SIC: data driver (source drive IC)
120: Gate driver 130: Timing controller
140, LS: level shifter 200: host system
400: Power supply R1: Current limiting resistor
ERC: Short circuit detection unit

Claims (14)

a display panel in which a plurality of data lines and a plurality of gate lines intersect and a pixel array is arranged;
a gate driver disposed on the display panel to supply gate signals to the gate lines using a shift register;
a level shifter that shifts the voltage level of an input signal and supplies it to the gate driver;
a printed circuit board on which the level shifter is disposed;
a source drive IC that supplies data signals to the data lines in a display mode; and
Comprising a flexible circuit board on which the source drive IC is disposed and connected between the display panel and the printed circuit board,
At least one of the flexible circuit board, the source drive IC, and the level shifter includes a short circuit sensing unit that generates a flag signal in a sensing mode,
The short circuit fault sensing unit,
a resistance to which the sample voltage is applied; and
A comparator that compares a sensing voltage received from any one of the wiring of the flexible circuit board, the output terminal of the level shifter, and the output terminal of the source drive IC with a preset reference voltage,
The display device wherein the comparator outputs a flag signal indicating short circuit of one or more of the wiring of the flexible circuit board, the output terminal of the level shifter, and the output terminal of the source drive IC in a sensing mode. According to claim 1,
The flexible circuit board is,
a plurality of clock wires connecting output terminals of the level shifter to clock input terminals of the gate driver;
a plurality of dummy wires;
data input wires connected to data input terminals of the source drive IC;
a plurality of data output wires connected to data output terminals of the source drive IC;
a plurality of input pads connected to the printed circuit board; and
A display device including a plurality of output pads bonded to the display panel. According to claim 2,
the resistor and the comparator are disposed on the printed circuit board,
A first input terminal of the comparator to which the sensing voltage is applied and the resistor are connected to the input pad,
A display device in which the reference voltage is applied to a second input terminal of the comparator. According to claim 3,
A display device in which at least one of the wiring of the flexible circuit board, the output terminal of the level shifter, and the output terminal of the source drive IC is shorted when the flag signal is at a specific level. According to claim 3,
a timing controller that transmits pixel data of the input image to the source drive IC in the display mode and controls operation timing of the source drive IC and the gate driver; and
A display device comprising a communication module and a host system that transmits pixel data of the input image and a timing signal to the timing controller. According to claim 5,
A display device in which a warning message is displayed on the pixel array when the flag signal is at a specific level. According to claim 5,
A display device in which a warning message is transmitted externally through the communication module when the flag signal is at a specific level. According to claim 3,
In the sensing mode, the level shifter and the source drive IC operate in ground mode, so that the output terminal of the level shifter and the output terminal of the source drive IC are connected to ground. According to claim 2,
Each of the channels of the source drive IC includes the resistor and the comparator,
Each of the channels of the source drive IC further includes a transistor connecting an output terminal to ground in ground mode,
A first input terminal of the comparator to which the sensing voltage is applied and the resistor are connected to an output terminal of the source drive IC in the sensing mode,
The reference voltage is applied to the second input terminal of the comparator,
The output terminal of the comparator is connected to the flag signal output terminal of the source drive IC,
The comparator is a display device that outputs a flag signal indicating short-circuiting of each channel of the source drive IC. According to clause 9,
The sensing mode includes a first step and a second step,
In the first step, the sample voltage is applied to the resistor and the sensing voltage is applied to the comparator in each of the odd-numbered channels of the source drive IC,
In the first step, each of the even channels of the source drive IC operates in the ground mode so that the output terminal of the source drive IC is connected to the ground,
In the second step, the sample voltage is applied to the resistor and the sensing voltage is applied to the comparator in each of the even channels of the source drive IC,
In the second step, each of the odd-numbered channels of the source drive IC operates in the ground mode, and the output terminal of the source drive IC is connected to the ground. According to clause 9,
Each of the channels of the source drive IC is,
a digital-to-analog converter that outputs a data signal in the display mode;
A first switch element connected between the output terminal of the digital-analog converter and the output buffer of the source drive IC and turned on in the display mode to connect the output terminal of the digital-analog converter to the output buffer;
a second switch element connected between the output buffer and an output terminal of the source drive IC and turned on in the display mode to connect the output buffer to an output terminal of the source drive IC;
a third switch element connected between a sample voltage source generating the sample voltage and an input terminal of the output buffer and turned on in the sensing mode to connect the sample voltage source to an input terminal of the output buffer;
a fourth switch element connected between the output terminal of the output buffer and the resistor and turned on in the sensing mode to connect the output terminal of the output buffer and the resistor;
It is connected between the node between the resistor and the output terminal of the source drive IC, and the first input terminal of the comparator, and is turned on in the sensing mode to connect the output terminal of the source drive IC to the first input terminal of the comparator. A fifth switch element connecting; and
A display device comprising a sixth switch element connected between the output terminal of the comparator and the flag signal output terminal and turned on in the sensing mode to connect the output terminal of the comparator to the flag signal output terminal. According to claim 2,
Each of the channels of the level shifter includes the resistor and the comparator,
Each of the channels of the level shifter further includes a transistor connecting an output terminal to ground in ground mode,
The first input terminal of the comparator and the resistor are connected to the output terminal of the level shifter in the sensing mode,
The reference voltage is applied to the second input terminal of the comparator,
The output terminal of the comparator is connected to the flag signal output terminal of the level shifter,
A display device wherein the comparator outputs a flag signal indicating short-circuiting of each channel of the level shifter. According to claim 12,
The sensing mode includes a first step and a second step,
In the first step, the sample voltage is applied to the resistor and the sensing voltage is applied to the comparator in each of the odd-numbered channels of the level shifter,
In the first step, each of the even-th channels of the level shifter operates in the ground mode so that the output terminal of the level shifter is connected to the ground,
In the second step, the sample voltage is applied to the resistor and the sensing voltage is applied to the comparator in each of the even channels of the level shifter,
In the second step, each of the odd-numbered channels of the level shifter operates in the ground mode, and the output terminal of the level shifter is connected to the ground. According to claim 12,
Each of the channels of the level shifter is,
a buffer that outputs a signal swinging between the high voltage and the low voltage to the output terminal of the level shifter in the display mode using a first transistor for switching a high voltage and a second transistor for switching a low voltage;
A first buffer connected between a buffer output node between the first transistor and the second transistor and an output terminal of the level shifter, turned on in the display mode, and connected to the buffer output node to the output terminal of the level shifter. switch element; and
A display device further comprising a second switch element connected between the resistor and the output terminal of the level shifter and turned on in the sensing mode to connect the resistor to the output terminal of the level shifter.