KR102322710B1 - Display device and sensing method for sensing bonding resistance thereof - Google Patents

Abstract

The present invention relates to a display device capable of checking whether bonding is defective by sensing the bonding resistance of a driving circuit unit using a driving IC having a sensing unit, and a bonding resistance sensing method thereof, and the bonding resistance sensing method according to an embodiment includes a bonding resistance A step of supplying an input voltage to a sensing path, and generating a voltage reflecting the bonding resistance of the plurality of bonding pads at a sensing node between the bonding resistance sensing path and the reference resistance through the input voltage passing through the bonding resistance sensing path, and driving; The steps of the ADC built-in IC receiving the voltage reflecting the bonding resistance from the sensing node, converting it into sensing data and outputting it, and judging whether or not bonding of the driving circuit unit is defective by using the sensing data.

Description

Display device and bonding resistance sensing method thereof

The present invention relates to a display device capable of sensing a bonding resistance of a driving circuit unit using a driving circuit having a sensing unit, and a bonding resistance sensing method thereof.

Recently, as a display device that displays an image using digital data, a liquid crystal display (LCD) using liquid crystal, an organic light emitting diode (OLED) display using an organic light emitting diode, and an electrophoretic particle are used. An electrophoretic display (EPD), etc. is a representative example.

A display device includes a panel for displaying an image, a driving circuit for driving the panel, and a timing controller for controlling the driving circuit. The driving circuit is provided in the form of a COF (Chip On Film) in which an IC (Integrated Circuit) is individually mounted on a circuit film.

Through the bonding process, one pad part of each COF is bonded and connected to the pad part of the panel through an ACF (Anisotropic Conductive Film), and the other pad part is bonded and connected to the pad part of the PCB (Printed Circuit Board) through the ACF. After the bonding process, the bonding resistance of each COF is measured through the inspection process to check whether the COF is defective in bonding.

To this end, bonding pads used for measuring bonding resistance are provided on the panel, PCB, and each COF, and test pads connected to the bonding pads are provided on the PCB for measuring bonding resistance. In the conventional method of measuring bonding resistance, a resistance measuring device is connected to a test pad to measure the bonding resistance of the bonding pad, and whether bonding is defective is determined according to the measurement result.

However, since the conventional bonding resistance measurement method individually measures the bonding resistance of each COF using a resistance meter, the inspection time of the bonding resistance increases, resulting in an increase in process tact time and measurement error. There is this.

In addition, the conventional bonding resistance measurement method cannot be applied unless the display device is decapsulated after product shipment, and it is difficult to check the progressive connection defect of the driving circuit caused by the progressive increase in bonding resistance. .

The present invention provides a display device capable of checking whether bonding is defective by sensing the bonding resistance of a driving circuit unit using a driving IC having a sensing unit, and a bonding resistance sensing method thereof.

A display device according to an exemplary embodiment includes a driving IC mounted on a circuit film, a driving circuit unit bonded between a panel and a PCB, a first bonding unit bonding and connecting the PCB and the circuit film, and a panel and the circuit A plurality of bonding pads positioned in the second bonding unit for bonding and connecting the film includes a bonding resistance sensing path provided by being connected in series. In the first sensing mode, the driving IC senses a signal reflecting the characteristics of each sub-pixel through the panel and outputs the first sensing data through the ADC. In the second sensing mode, the driving IC senses a signal reflecting the bonding resistance of the plurality of bonding pads through the bonding resistance sensing path and outputs second sensing data through the ADC.

The timing controller controls the driving IC to operate in the first and second sensing modes, and determines whether bonding of the driving circuit unit is defective using the second sensing data, and outputs the determination.

The driving circuit unit further includes a reference resistor connected in series between the bonding resistance sensing path and the ground, and a switch connecting the sensing node between the bonding resistance sensing path and the reference resistance and the input terminal of the ADC in the second sensing mode.

A bonding resistance sensing path according to an embodiment is connected in series with a supply line of an input voltage, a first bonding pad bonded between the PCB and the circuit film, and the first bonding pad in series, and bonding between the panel and the circuit film a second bonding pad connected in series with the second bonding pad and disposed in parallel with the second bonding pad, a third bonding pad bonded between the panel and the circuit film, and the third bonding pad connected in series with the first bonding pad a fourth bonding pad disposed in parallel with the pad and bonded between the PCB and the circuit film, and a fifth bonding pad connected in series with the fourth bonding pad and disposed in parallel with the fourth bonding pad, bonded between the PCB and the circuit film Includes pad. Each of the first to fifth bonding pads includes a pair of pads bonded and connected by an anisotropic conductive film facing the circuit film and the PCB or panel.

The first and second bonding pads are connected in series through a first connection line provided on the circuit film. The second and third bonding pads are connected in series through a second connection line provided on the panel. The third and fourth bonding pads are connected in series to the circuit film through a third connection line provided in parallel with the first connection line. The fourth and fifth bonding pads are connected in series through a fourth connection line provided on the PCB. The bonding resistance sensing path is provided on the circuit film and further includes a fifth connection line connecting the fifth bonding pad and the input terminal of the driving IC.

The driving circuit unit further includes a plurality of power lines for supplying a driving voltage from the PCB to the panel through the circuit film, and the fourth and fifth bonding pads are spaced apart from each other with the plurality of power lines interposed therebetween. The fifth bonding pad may be disposed on one side of the circuit film adjacent to the plurality of power wirings or disposed on a central portion of the circuit film. The bonding resistance sensing path may be disposed on one side of the driving circuit unit or disposed on both sides of the driving circuit unit, respectively.

A bonding resistance sensing method of a display device according to an embodiment includes supplying an input voltage to the above-described bonding resistance sensing path, and the input voltage passes through the bonding resistance sensing path at a sensing node between the bonding resistance sensing path and a reference resistance. A step of generating a voltage reflecting the bonding resistance of a plurality of bonding pads, the ADC built-in driving IC receiving a voltage reflecting the bonding resistance from a sensing node, converting it into sensing data and outputting it, and driving using the sensing data and determining whether bonding of the circuit unit is defective.

In one embodiment of the present invention, the bonding resistance of the driving circuit unit is sensed using an ADC built into the driving IC, and the bonding failure risk of the driving circuit unit can be easily checked using the sensing result, thereby reducing the risk of a bonding failure system. .

An exemplary embodiment of the present invention can reduce the inspection time for inspecting the bonding resistance after the bonding process of the driving circuit unit, thereby reducing the process tact time and reducing the measurement error.

In an embodiment of the present invention, even after shipment of the product, progressive bonding failure can be detected by sensing the bonding resistance of the driving circuit unit using the ADC built into the driving IC, so that screen abnormalities due to progressive connection failure of the driving circuit unit are prevented in advance. can be prevented in

1 is a block diagram schematically showing the configuration of an OLED display device according to an embodiment of the present invention.
2 is a diagram illustrating a bonding structure of a driving circuit unit in a display device according to an exemplary embodiment.
3 is an equivalent circuit diagram illustrating a bonding resistance sensing unit according to an embodiment of the present invention.
4 is a view showing various bonding resistance sensing paths of a driving circuit unit according to an embodiment of the present invention.
5 is an equivalent circuit diagram illustrating a part of a pixel circuit and a driving circuit unit according to an embodiment of the present invention.
6 is a flowchart illustrating a bonding resistance sensing method of an OLED display device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram schematically showing the configuration of an OLED display device according to an embodiment of the present invention, and FIG. 2 is a diagram showing an IC package for sensing bonding resistance according to an embodiment of the present invention.

Referring to FIG. 1 , an OLED display device according to an exemplary embodiment includes a panel 100 , a gate driver 200 , a data driver 300 , a timing controller 400 , a memory 500 , a power supply unit 600 , and the like. do.

The panel 100 displays an image through a pixel array in which sub-pixels SP are arranged in a matrix form. The basic pixel may be composed of at least three sub-pixels capable of expressing white by color mixing among white (W), red (R), green (G), and blue (B) sub-pixels. For example, a basic pixel is subpixels in R/G/B combination, subpixels in W/R/G combination, subpixels in B/W/R combination, subpixels in combination G/B/W or may be composed of sub-pixels of a W/R/G/B combination.

The power supply unit 600 generates and outputs various driving voltages required by the display device, such as the timing controller 400 , the gate driver 200 , the data driver 300 , the panel 100 , and the like by using the input voltage. For example, the power supply unit 600 uses a driving voltage of a digital circuit supplied to the data driver 300 and the timing controller 400 , a driving voltage of an analog circuit supplied to the data driver 300 , and the gate driver 200 . A gate-on voltage (gate high voltage) and a gate-off voltage (gate low voltage) are generated and supplied. The power supply unit 600 generates a plurality of driving voltages EVDD and EVSS and a reference voltage necessary for driving the panel 100 , and supplies them to the panel 100 through the data driver 300 .

The timing controller 400 receives image data and basic timing control signals from an external system. The system may be any one of a computer, a TV system, a set-top box, a system of a portable terminal such as a tablet or a mobile phone. The basic timing control signals may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

The timing controller 400 controls the driving timings of the data driver 300 and the gate driver 200 using basic timing control signals supplied from the outside and timing setting information (start timing, pulse width, etc.) stored in an internal register, respectively. Data control signals and gate control signals for controlling are generated and supplied.

The timing controller 400 compensates image data to be supplied to each sub-pixel SP using a compensation value stored in the memory 500 , and supplies the compensated image data to the data driver 300 . The timing controller 400 may further perform various image processing for compensating for deterioration of the OLED device, reducing power consumption, and the like.

The timing controller 400 receives a sensing command from the system to control the display device to operate in a pixel sensing mode for sensing characteristics of each sub-pixel, or the data driver 300 senses bonding resistance for sensing the bonding resistance of the driving circuit unit. mode can be controlled.

When a pixel sensing command is supplied from the system, the timing controller 400 may control the gate driver 200 , the data driver 300 , the panel 100 , and the like to operate in the pixel sensing mode. The timing controller 400 senses characteristics (Vth of the driving TFT, mobility, Vth of OLED, etc.) of each subpixel of the panel 100 through the data driver 300 and uses the sensing result to generate the memory 500 Update the compensation value of each subpixel stored in .

When the bonding resistance sensing command is supplied from the system, the timing controller 400 may control the data driver 300 to operate in the bonding resistance sensing mode, which will be described later.

The gate driver 200 receives a gate control signal from the timing controller 400 to drive a plurality of gate lines of the panel 100 . The gate driver 200 supplies a gate-on voltage pulse to the corresponding gate line in the driving period of each gate line, and supplies the gate-off voltage in the non-driving period. The gate driver 200 is disposed on both sides of the panel 100 and simultaneously supplies the gate signal from both sides of each gate line, thereby reducing the delay of the gate signal.

The gate driver 200 includes a plurality of gate integrated circuits (ICs) connected to one or both sides of the panel 100 to divide and drive the gate lines. The gate IC is individually mounted on a circuit film, provided in the form of a TCP (Tape Carrier Package), COF (Chip On Film), and is bonded to the panel 100 through an ACF (Anisotropic Conductive Film) in a TAB (Tape Automatic Bonding) method. can be connected. Alternatively, the gate driver 200 may be formed in a GIP (Gate In Panel) type that is directly formed in the non-display area of the substrate together with the TFT array of the pixel array of the panel 100 and is embedded in the panel 100 .

The data driver 300 converts the pixel data supplied from the timing controller 400 into an analog data voltage by using the data control signal supplied from the timing controller 400 , and supplies the data voltage to the panel 100 . The data driver 300 converts digital data into analog data voltages using the gamma voltage for each gray level supplied from the gamma voltage generator.

The data driver 300 may operate in a pixel sensing mode and a bonding resistance sensing mode under the control of the timing controller 400 .

In the pixel sensing mode under the control of the timing controller 400 , the data driver 300 converts the sensing data supplied from the timing controller 400 into a sensing data voltage and then supplies it to each sub-pixel through the data line. to drive each sub-pixel. The data driver 300 senses the pixel current representing the driving characteristics (Vth of the driving TFT, mobility, Vth of the OLED, etc.) of the driven sub-pixel SP as a voltage through a reference line, and analog-to-digital (ADC). converter) to convert it into sensed data and provide it to the timing controller 400 . The timing controller 400 updates the compensation value of each subpixel stored in the memory 500 using the sensing result supplied from the data driver 300 .

The data driver 300 includes a plurality of data ICs 350 ( FIG. 2 ) connected to one or both sides of the panel 100 to divide and drive data lines. As shown in FIG. 2 , each data IC 350 is individually mounted on a circuit film 360 to provide a TCP and COF type driving circuit unit 370 , and each driving circuit unit 370 is connected to the panel ( ) through the ACF. 100) and the PCB 700 are bonded and connected in a TAB manner.

In the bonding resistance sensing mode under the control of the timing controller 400 , the data driver 300 , that is, each data IC 350 , receives the input voltage Vin through the bonding resistance sensing path 10 of the driving circuit unit 370 . The voltage reflected by the bonding resistance is supplied as a sensing voltage by passing through, and is converted into sensing data through an ADC and provided to the timing controller 400 . The bonding resistance sensing path 10 of each driving circuit unit 370 includes a plurality of bonding pads 12 and 13 to which the driving circuit unit 370 and the PCB 700 are bonded, and the driving circuit unit 370 and the panel 100 . A plurality of bonded bonding pads 11 , 14 , and 15 are provided in a series-connected structure. The bonding resistance sensing path 10 may be provided on one side of the driving circuit unit 370 or provided on both sides of the driving circuit unit 370 .

As for the bonding state of the driving circuit unit 370 , the bonding state of the central portion is the best and the bonding state of both sides is relatively poor. By sensing the resistance, it is possible to determine whether bonding of the driving circuit unit 370 is defective.

The timing controller 400 determines whether the bonding of each driving circuit unit 370 is defective by using the sensing data supplied from each data IC 350 . The timing controller 400 outputs the determination result of whether the bonding is defective to the outside so that, when the bonding is defective, the operator can repair the bonding defect of each driving circuit unit 370 . If the voltage sensed by the bonding resistor is less than the preset reference value, the timing controller 400 determines that the bonding resistance is increased because the bonding resistance is increased. can be judged as

2 is a diagram schematically showing a bonding structure of each driving circuit unit 370 according to an embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram showing a bonding resistance sensing device of each driving circuit unit 370 .

Referring to FIG. 2 , in each driving circuit unit 370 including the data IC 350 mounted on the circuit film 360 , the first bonding unit 362 is the entire bonding unit 710 of the PCB 700 or Bonded by ACF in some areas. The plurality of bonding pads located in the first bonding unit 362 are individually connected to the plurality of bonding pads located at the bonding unit 710 of the PCB 700 through conductive particles included in the ACF.

In the driving circuit unit 370 , the first bonding unit 362 and the second bonding unit 364 facing in the first direction Y are formed by ACF in all or a part of the bonding unit 110 of the panel 100 . are bonded The plurality of bonding pads positioned at the second bonding unit 364 are individually connected to the plurality of bonding pads located at the bonding unit 110 of the panel 100 through conductive particles included in the ACF.

The bonding resistance sensing path 10 of each driving circuit unit 370 is formed between the first bonding pad 11 bonded between the circuit film 360 and the PCB 700 and the circuit film 360 and the panel 100 . The second and third bonding pads 12 and 13 bonded to each other and the fourth and fifth bonding pads 11, 14 and 15 bonded between the circuit film 360 and the PCB 700 are connected in series. have

The first bonding pad 11 receives the input voltage Vin from the power supply unit 600 . The first bonding pad 11 and the second bonding pad 12 are connected in series through the connection line 21 provided on the circuit film 360 . The second and third bonding pads 12 and 13 are connected in series through a connection line 22 provided on the panel 100 . The third and fourth bonding pads 13 and 14 are connected in series through a connection line 23 provided on the circuit film 360 . The fourth and fifth bonding pads 14 and 15 are connected in series through a connection line 24 provided on the PCB 700 . The fifth bonding pad 15 is connected in series with the input terminal of the data IC 350 through the connection line 25 provided on the circuit film 360 .

2, the first bonding pad 11 is a pair of pads 11-1 and 11-2 provided on the PCB 700 and the circuit film 360 facing each other and bonded and connected by ACF. have a structure A pair of pads 14-1 and 14-2 provided on the PCB 700 and the circuit film 360 also face the fourth bonding pad 14 adjacent to the first bonding pad 11 and are bonded by ACF. and a connected structure. The second bonding pad 15 also has a structure in which a pair of pads respectively provided on the PCB 700 and the circuit film 360 are bonded and connected by an ACF. Similarly, each of the second and third bonding pads 12 and 13 has a structure in which each pair of pads respectively provided on the panel 100 and the circuit film 360 is bonded and connected by ACF.

Referring to FIG. 3 , the first to fifth bonding pads 11 to 15 may be represented by a series structure of first to fifth bonding resistors R1 to R5 connected to the supply line of the input voltage Vin. . The sum (R2+R3) of the second and third bonding resistances R2 and R3 corresponding to the second and third bonding pads 12 and 13 is the bonding resistance between the driving circuit unit 370 and the PCB 700 ( Ra). The sum (R1+R4+R5) of the first, fourth, and fifth bonding resistors R1, R4, and R5 corresponding to the first, fourth, and fifth bonding pads 11, 14, and 15 is the driving circuit unit 370 ) and the bonding resistance Rb between the panel 100 . Accordingly, the bonding resistance sensing path 10 has a structure in which the bonding resistance Ra between the driving circuit unit 370 and the PCB 700 and the bonding resistance Rb between the driving circuit unit 370 and the panel 100 are connected in series. has

A reference resistor Rf is connected in series between the series structure of the first to fifth bonding resistors R1 to R5 and the ground GND, and a sensing node between the fifth bonding resistor R5 and the reference resistor Rf ( Ns) is connected to the input terminal of the ADC 310 through the switch SW. The reference resistor Rf and the switch SW are built into the data IC 350 together with the ADC 310 . The reference resistance Rf may be located on the circuit film 360 .

Since the input voltage Vin (1 to 2V) drops while passing through the bonding resistors R1 to R5, the sensing node Ns is connected to the bonding resistors R1 to R5 of the first to fifth bonding pads 11 to 15. ) reflected voltage, that is, a sensing voltage by the bonding resistor is generated. The ADC 320 receives the sensing voltage generated from the sensing node Ns through the switch SW, converts it into sensing data, and provides it to the timing controller 400 . The switch SW is turned on in the bonding resistance sensing mode under the control of the timing controller 400 .

4 is a view showing various bonding resistance sensing paths of a driving circuit unit according to an embodiment of the present invention.

Referring to FIG. 4A , in the driving circuit unit 370 bonded between the panel 100 and the substrate 700, first and second bonding resistance sensing paths ( 10A and 10B) may be located, respectively. The ADC built in the data IC 350 is respectively connected to the first and second bonding resistance sensing paths 10A and 10B, respectively, to receive sensing voltages by the bonding resistances of the respective paths, respectively, and the first and second bonding resistances. Sensing data for each of the resistance sensing paths 10A and 10B may be provided to the timing controller 400 .

Referring to FIGS. 4B and 4C , first and second driving voltages EVDD and EVSS are applied from the PCB 700 to the panel 100 on both sides of the driving circuit unit 370 in the second direction X. ) may be provided with a plurality of power supply wires 30 and 32 for supplying them.

In FIG. 4(a), when a plurality of power lines 30 and 32 are positioned between the bonding resistance sensing path 10 and the data IC 350 as shown in FIG. 4(b), a fifth bonding pad ( 15 ) and the connection line 25 connecting the data IC 350 should be formed on different layers from the power wirings 30 and 32 in the circuit film 360 to cross each other.

Meanwhile, the fifth bonding pads 15A and 15B and the data IC 350 are connected by changing the positions of the fifth bonding pads 15A and 15B in the driving circuit unit 370 as shown in FIGS. 4(b) and 4(c). The connecting lines 25A and 25B may be formed on the same layer without crossing the power lines 30 and 32 .

In FIG. 4B , the fifth bonding pad 15A is spaced apart from the fourth bonding pad 14 with the power wirings 30 interposed therebetween, and through a connection line 24 provided on the PCB 700 . The fourth and fifth bonding pads 14 and 15A are connected.

In FIG. 4( c ), the fifth bonding pad 15B may be located in the center of the driving circuit unit 370 , and the fourth and fifth bonding pads ( 15B) are connected through the connection line 24 provided on the PCB ( 700 ). 14, 15A) are connected. all. In this case, the ADC 310 ( FIG. 3 ) built in the data IC 350 may sense one or both sides of the driving circuit unit 370 by reflecting the bonding resistance of the central portion as well as the sensing voltage.

5 is an equivalent circuit diagram illustrating some configurations of a pixel circuit and a driving circuit unit according to an embodiment of the present invention.

Referring to FIG. 5 , the data IC 350 connected to the panel 100 senses characteristics of each subpixel SP using the built-in ADC 310 and senses the bonding resistance of the driving circuit unit 370 . do.

In the bonding resistance sensing mode under the control of the timing controller 400, the ADC 310 operates between the bonding resistance sensing path 10 of the driving circuit unit 370 and the reference resistance Rf between the sensing node Ns and the switch ( SW) to sense the sensing voltage by the bonding resistor. In the bonding resistance sensing path 10 , the bonding resistance Ra between the driving circuit unit 370 and the PCB 700 and the bonding resistance Rb between the driving circuit unit 370 and the panel 100 are the input voltage Vin. It is connected in series between the supply line and the sensing node Ns.

In the pixel sensing mode under the control of the timing controller 400 , the ADC 310 may sense the characteristics of each subpixel SP through the sampling switch SAM and the reference line REF.

Each subpixel SP positioned on the panel 100 is disposed between the high potential driving voltage (first driving voltage; hereinafter EVDD) line PW1 and the low potential driving voltage (second driving voltage; hereinafter EVSS) line PW2 . A pixel circuit including at least the OLED 10 connected to be prepared Meanwhile, various configurations different from the configuration of FIG. 5 may be applied to the pixel circuit.

The switching TFTs ST1 and ST2 and the driving TFT DT may be an amorphous silicon (a-Si) TFT, a poly-Si TFT, an oxide TFT, or an organic TFT. have.

The OLED 10 includes an anode connected to the source node N2 of the driving TFT DT, a cathode connected to the EVSS line PW2, and an organic light emitting layer between the anode and the cathode. The anode is independent for each subpixel, but the cathode may be a common electrode shared by all subpixels. In the OLED device 10, when a driving current is supplied from the driving TFT (DT), electrons from the cathode are injected into the organic emission layer, and holes from the anode are injected into the organic emission layer. By emitting the phosphor material, light having a brightness proportional to the current value of the driving current is generated.

The first switching TFT ST1 is driven by the first gate signal SCAN supplied from the gate driver 200 to the first gate line GLn1 and supplied from the data IC 350 to the data line DL. The data voltage Vdata is supplied to the gate node N1 of the driving TFT DT.

The second switching TFT ST2 is driven by the second gate signal SENSE supplied from the gate driver 200 to the second gate line GLn2 and supplied from the data IC 350 to the reference line REF. The reference voltage Vref is supplied to the source node N2 of the driving TFT DT. Also, when each subpixel SP is driven in the sensing mode, the second switching TFT ST2 outputs the current supplied from the driving TFT DT to the reference line REF in a floating state.

The storage capacitor Cst connected between the gate node N1 and the source node N2 of the driving TFT DT is connected to the gate node (ST1, ST2) through the first and second switching TFTs ST1 and ST2 turned on during the scan period. The difference voltage between the data voltage Vdata and the reference voltage Vref supplied to N1) and the source node N2, respectively, is charged to the driving voltage Vgs of the driving TFT DT, and the first and second switching TFTs ( The charged driving voltage Vgs is held during the light emission period when ST1 and ST2 are turned off.

The driving TFT DT controls the current supplied from the EVDD line PW1 according to the driving voltage Vgs supplied from the storage capacitor Cst to supply the driving current determined by the driving voltage Vgs to the OLED 10 . By doing so, the OLED 10 is made to emit light.

In the sub-pixel SP sensing mode, the driving TFT DT receives the data line DL and the first switching TFT from the data driver 300 during the scan period of the first and second gate signals SCAN and SENSE. The sensing data voltage Vdata supplied through ST1 and the reference voltage Vref supplied through the reference line REF and the second switching TFT ST2 are supplied and driven, and the OLED 10 is driven. can do. The pixel current in which the driving characteristics (Vth, mobility) of the driving TFT DT or the deterioration of the OLED 10 are reflected is charged to the line capacitor of the reference line REF through the second switching TFT ST2 as a voltage. The ADC 310 receives the sensing voltage from the reference line REF through the sampling switch SAM, converts it into sensing data of each sub-pixel SP, and outputs the converted data.

As described above, the data IC 350 according to an exemplary embodiment utilizes the built-in ADC 310 to sense the pixel characteristics, and is applied to the bonding resistance supplied through the bonding resistance sensing path 10 of the driving circuit unit 370 . The sensing voltage may be sensed and the sensing result may be provided to the timing controller 400 as sensing data.

6 is a flowchart illustrating a bonding resistance sensing method of a driving circuit unit according to an embodiment of the present invention.

The timing controller 400 controls the data IC 350 to operate in the bonding resistance sensing mode of the driving circuit unit 370 . In the bonding resistance sensing mode, not only the inspection process before product shipment, but also the progressive bonding defect can be detected after product shipment.

The input voltage Vin is supplied from the power supply unit 500 to the bonding resistance sensing path 10 of the driving circuit unit 370 ( S602 ).

The ADC 310 senses the sensing voltage by the bonding resistance generated at the sensing node Ns through the switch SW through the bonding resistance sensing path 10 of the driving circuit unit 370 ( S604 ). The ADC 320 receives the sensed voltage through the switch SW, converts it into sensed data, and provides it to the timing controller 400 .

The timing controller 400 determines whether bonding of each driving circuit unit 370 is defective by using the sensing data supplied from each data IC 350 ( S606 , S608 , and S6010 ). When the voltage sensed by the bonding resistor is smaller than the preset reference value (S606; Y), the timing controller 400 determines that the bonding resistance is increased and thus the bonding is defective (S610), and if the voltage sensed by the bonding resistor is greater than the reference value (S606; N) It can be determined as normal bonding (S608) in which the bonding resistance is relatively small.

The timing controller 400 outputs the determination result of whether the bonding is defective to the outside so that, when the bonding is defective, the operator can repair the bonding defect of each driving circuit unit 370 .

As described above, in one embodiment of the present invention, the bonding resistance of the driving circuit unit is sensed using the ADC built in the driving IC, and the bonding failure of the driving circuit unit can be easily checked using the sensing result, so there is a bonding failure risk. can reduce

An exemplary embodiment of the present invention can reduce the inspection time for inspecting the bonding resistance after the bonding process of the driving circuit unit, thereby reducing the process tact time and reducing the measurement error.

In an embodiment of the present invention, even after shipment of the product, progressive bonding failure can be detected by sensing the bonding resistance of the driving circuit unit using the ADC built into the driving IC, so that screen abnormalities due to progressive connection failure of the driving circuit unit are prevented in advance. can be prevented in

The above description is merely illustrative of the present invention, and various modifications may be made by those of ordinary skill in the art to which the present invention pertains without departing from the technical spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed by the following claims, and all technologies within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: panel 200: gate driver
300: data driver 400: timing controller
500: memory 600: power unit
700: PCB 310: ADC
350: data IC 360: circuit film
370: driving circuit unit 10: bonding resistance sensing path
11, 12, 13, 14, 15: bonding pad 21, 22, 23, 24, 25: connecting line
362; 364: first, second bonding unit 110: panel bonding unit
710: PCB bonding unit

Claims (10)

panels and printed circuit boards (PCBs);
a driving circuit unit including a driving integrated circuit (IC) mounted on a circuit film and bonded between the panel and the PCB;
A first bonding unit bonding and connecting the PCB and the circuit film, and a bonding resistance sensing path provided by serially connecting a plurality of bonding pads located in a second bonding unit bonding and connecting the panel and the circuit film do,
The driving IC is
In the first sensing mode, a signal in which the characteristics of each sub-pixel is reflected is sensed through the panel and first sensed data is output through an analog-to-digital converter (ADC),
In the second sensing mode, a signal to which the bonding resistance of the plurality of bonding pads is reflected is sensed through the bonding resistance sensing path, and second sensing data is output through the ADC;
A timing controller for controlling the driving IC to operate in the first and second sensing modes,
the timing controller
updating the compensation value of each sub-pixel by using the first sensing data;
A display device for determining and outputting a bonding failure of the driving circuit unit using the second sensing data. delete The method according to claim 1,
the driving circuit
a reference resistor connected in series between the bonding resistor sensing path and the ground;
and a switch connecting a sensing node between the bonding resistance sensing path and the reference resistance and an input terminal of the ADC in the second sensing mode. The method according to claim 1,
The bonding resistance sensing path is
a first bonding pad connected in series with a supply line of an input voltage and bonded between the PCB and the circuit film;
a second bonding pad connected in series with the first bonding pad and bonded between the panel and the circuit film;
a third bonding pad connected in series with the second bonding pad and disposed in parallel with the second bonding pad and bonded between the panel and the circuit film;
a fourth bonding pad connected in series with the third bonding pad and arranged in parallel with the first bonding pad, bonded between the PCB and the circuit film;
a fifth bonding pad connected in series with the fourth bonding pad and arranged in parallel with the fourth bonding pad, bonded between the PCB and the circuit film;
Each of the first to fifth bonding pads is
and a pair of pads facing the circuit film and the PCB or panel and bonded and connected by an anisotropic conductive film. 5. The method according to claim 4,
The first and second bonding pads are connected in series through a first connection line provided on the circuit film,
The second and third bonding pads are connected in series through a second connection line provided on the panel,
The third and fourth bonding pads are connected in series to the circuit film through a third connection line provided in parallel with the first connection line,
The fourth and fifth bonding pads are connected in series through a fourth connection line provided on the PCB,
and a fifth connection line provided on the circuit film to connect the fifth bonding pad to an input terminal of the driving IC. 6. The method of claim 5,
the driving circuit
Further comprising a plurality of power wiring for supplying a driving voltage from the PCB to the panel through the circuit film,
The fourth and fifth bonding pads are spaced apart from each other with the plurality of power lines interposed therebetween,
The fifth bonding pad is disposed on one side of the circuit film adjacent to the plurality of power lines or disposed on a central portion of the circuit film. 7. The method of claim 6,
The bonding resistance sensing path is
or disposed on one side of the driving circuit part;
a display device disposed on both sides of the driving circuit unit, respectively. A plurality of first bonding units including a driving circuit unit having a driving IC mounted on a circuit film, bonding and connecting the PCB and the circuit film, and a second bonding unit bonding and connecting the panel and the circuit film supplying an input voltage to a bonding resistance sensing path provided by connecting bonding pads in series;
generating a voltage in which the bonding resistances of the plurality of bonding pads are reflected at a sensing node between the bonding resistance sensing path and a reference resistance by the input voltage passing through the bonding resistance sensing path;
the ADC built in the driving IC receiving the voltage reflecting the bonding resistance from the sensing node, converting it into sensing data and outputting it;
using the sensing data to determine whether bonding of the driving circuit unit is defective;
The ADC built into the driving IC is
In the first sensing mode, a signal representing the characteristics of each sub-pixel is supplied through the panel through the first switch, converted into first sensing data, and output;
In the second sensing mode, the voltage in which the bonding resistance is reflected is supplied from the sensing node through the second switch and converted into second sensing data and output;
A timing controller for controlling the driving IC to operate in the first and second sensing modes,
the timing controller
updating the compensation value of each sub-pixel by using the first sensing data;
A bonding resistance sensing method of a display device for determining whether bonding of the driving circuit unit is defective using the second sensing data. delete 9. The method of claim 8,
The step of determining whether bonding of the driving circuit unit is defective using the sensing data includes:
comparing the sensed data with a reference value;
determining that bonding of the driving circuit unit is normal when the sensed data is greater than or equal to the reference value;
and determining that the bonding of the driving circuit unit is defective when the sensed data is less than the reference value.

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