KR20160078692A - Organic light emitting display device and method for the same - Google Patents

Abstract

Embodiments of the present invention relate to an organic light emitting display device and a driving method thereof, for monitoring a situation that an abnormal gate voltage is supplied to a sub pixel to handle the situation in advance before serious damage to a circuit, a panel bunt phenomenon or the like occurs due to the abnormal gate voltage applied to the sub pixel. The organic light emitting display device includes: an organic light emitting display panel on which data lines and gate lines are disposed and sub pixels are disposed in the type of a matrix; a data driving unit driving the data lines; a gate driving unit driving the gate lines; and a timing controller controlling the data driving unit and the gate driving unit.

Description

Technical Field [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present embodiments relate to an organic light emitting display and a driving method thereof.

2. Description of the Related Art In recent years, an organic light emitting diode (OLED) display device that has been popular as a display device has advantages of high response speed, high luminous efficiency, high brightness, and wide viewing angle by using an organic light emitting diode (OLED)

Such an organic light emitting display device arranges subpixels including organic light emitting diodes in a matrix form and controls the brightness of subpixels selected by the scan signals according to the gradation of data.

As described above, the organic light emitting display device applies a gate voltage (scan signal) to each subpixel for driving each subpixel. At this time, a situation in which a normal gate voltage is not applied to each subpixel due to various factors Lt; / RTI >

In this case, the subpixels can not be normally driven, and the picture quality may be greatly deteriorated. In severe cases, the circuit on the organic light emitting display panel may be seriously damaged, a burnt phenomenon may occur, and the organic light emitting display panel may be discarded.

The situation in which the abnormal gate voltage is supplied to the subpixel may be caused, for example, when there is a problem with the gate driver integrated circuit, when there is a problem in the bonding portion where the gate driver integrated circuit is connected to the OLED display panel, Problems may arise, and the like.

The situation in which the abnormal gate voltage is supplied to the subpixel is a problem in the case of a high resolution or high performance organic light emitting display device requiring a larger number of gate lines and an organic light emitting display device having a greater number of gate driver integrated circuits , Or when the organic light emitting display device is a flexible display device, and may occur more frequently in the organic light emitting display device or the organic light emitting display panel.

At present, a technique for monitoring whether a gate voltage is abnormally applied to a sub-pixel has not been developed.

It is an object of the present embodiments to provide a method and apparatus for monitoring an abnormal gate voltage supplied to a subpixel before a abnormal gate voltage is applied to the subpixel to cause serious circuit damage or a panel burnt phenomenon, There is.

One embodiment includes an organic light emitting display panel in which data lines and gate lines are arranged and the subpixels are arranged in a matrix type, a data driver for driving data lines, a gate driver for driving gate lines, a data driver, And a timing controller for controlling the gate driver.

In this organic light emitting display, each subpixel includes an organic light emitting diode, a driving transistor controlled by the data voltage applied to the gate node and electrically connected between the first electrode of the organic light emitting diode and the driving voltage line, And a sensor transistor which is controlled by a gate voltage applied to the organic light emitting diode and is electrically connected between the first electrode of the organic light emitting diode and the reference voltage line.

Such an organic light emitting display may further include an analog digital converter electrically connected to a reference voltage line.

In such an analog-to-digital converter, a gate voltage is applied to the gate node of the sensor transistor, and a reference node electrically connected to the sensor transistor and the reference voltage line is floated, and the voltage of the reference node is sensed. Can be output.

Another embodiment is an organic light emitting display comprising: an organic light emitting diode; a driving transistor controlled by a data voltage applied to a gate node and electrically connected between a first electrode of the organic light emitting diode and a driving voltage line; A subpixel including a sensor transistor electrically connected between reference voltage lines is arranged in a matrix type.

A method of driving an organic light emitting display includes applying a gate voltage to a gate node of a sensor transistor, applying a reference voltage to a reference node electrically connected to the sensor transistor and the reference voltage line, Increasing the voltage of the node, sensing the voltage of the reference node, and outputting sensing data obtained by converting the sensed voltage into a digital value.

According to the embodiments described above, the abnormal gate voltage is applied to the subpixel so that the abnormal gate voltage is supplied to the subpixel before the serious circuit damage or the panel bunch phenomenon occurs. So that it can be prepared in advance.

1 is a system configuration diagram of an organic light emitting display according to the present embodiments.
FIG. 2 is a view illustrating a sub-pixel structure of an OLED display according to an embodiment of the present invention. Referring to FIG.
3 is an exemplary diagram illustrating a gate voltage state monitoring configuration of an organic light emitting display according to the present embodiments.
4 is a view illustrating another example of the gate voltage state monitoring structure of the OLED display according to the present embodiments.
FIGS. 5 to 9 are views for explaining a gate voltage state monitoring method of the OLED display according to the present embodiments.
FIGS. 10 and 12 are diagrams for explaining a threshold voltage sensing method of a driving transistor of the organic light emitting display according to the present embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

FIG. 1 is a system configuration diagram of an organic light emitting diode display 100 according to the present embodiments.

1, the OLED display 100 includes an OLED display panel 110, a data driver 120, a gate driver 130, a timing controller 140, and the like .

A plurality of data lines DL are arranged in a first direction and a plurality of gate lines GL are arranged in a second direction intersecting the first direction in the OLED display panel 110. A plurality of sub- SP) are arranged in a matrix type.

The data driver 120 supplies the data voltages to the data lines to drive the data lines.

The gate driver 130 sequentially supplies the scan signals (also referred to as "gate voltages") to the gate lines to sequentially drive the gate lines.

The timing controller 140 supplies control signals to the data driver 120 and the gate driver 130 to control the operations of the data driver 120 and the gate driver 130.

The timing controller 140 starts scanning in accordance with the timing implemented in each frame and switches the image data Data input from the host system 160 according to the data signal format used by the data driver 120, And outputs the image data (Data ') and controls the data driving at a proper time according to the scan.

The gate driver 130 sequentially supplies the scan signals of the On voltage or the Off voltage to the gate lines sequentially according to the control of the timing controller 140 to sequentially drive the gate lines.

1, the gate driver 130 may be positioned on both sides of the organic light emitting display panel 110, or may be located only on one side, depending on the sub-pixel structure, the driving method, and the like.

In addition, the gate driver 130 may include a plurality of gate driver ICs (GDIC # 1, ..., GDIC #N, N: natural number) A bonding pad of the organic light emitting display panel 110 or a GIP (Gate In Panel) type by a tape automation bonding (TAB) method or a chip on glass (COG) method And may be directly disposed on the organic light emitting display panel 110, and may be integrated on the organic light emitting display panel 110, as the case may be.

Each of the plurality of gate driver integrated circuits mentioned above may include a shift register, a level shifter, and the like.

When the specific gate line is opened, the data driver 120 converts the video data Data 'received from the timing controller 140 into analog data voltages Vdata and supplies the data voltages to the data lines, thereby driving the data lines do.

The data driver 120 may include a plurality of source driver ICs (also referred to as a data driver IC, SDIC # 1, ..., SDIC #M, M: natural number) Such a plurality of source driver integrated circuits may be connected to a bonding pad of the organic light emitting display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, And may be directly disposed on the organic light emitting display panel 110, and may be integrated on the organic light emitting display panel 110, as the case may be.

Each of the plurality of source driver integrated circuits described above includes a shift register, a latch, a digital analog converter (DAC), an output buffer, and the like. In some cases, an analog voltage value is sensed And an analog digital converter (ADC) for converting the digital data into digital data and generating and outputting sensing data.

A plurality of source driver integrated circuits can be implemented by, for example, a chip on film (COF) method. In each of the plurality of source driver integrated circuits, one end is bonded to at least one source printed circuit board (S-PCB) and the other end is bonded to a bonding pad portion of the organic light emitting display panel 110 .

The host system 160 may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable (DE) signal, a clock signal (CLK), and the like to the timing controller 140. [

The timing controller 140 may switch the image data Data input from the host system 160 according to the data signal format used by the data driver 120 and output the converted image data Data ' In order to control the data driver 120 and the gate driver 130, a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal, and a clock signal is input to generate various control signals And outputs it to the data driver 120 and the gate driver 130.

For example, in order to control the gate driver 130, the timing controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE : Gate Output Enable), and the like. The gate start pulse GSP controls the operation start timing of the gate driver integrated circuits constituting the gate driver 130. [ The gate shift clock GSC is a clock signal commonly input to the gate driver integrated circuits, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies the timing information of the gate driver integrated circuits.

The timing controller 140 controls the data driver 120 such that a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, And the like. The source start pulse SSP controls the data sampling start timing of the source driver integrated circuits constituting the data driver 120. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120. The polarity control signal POL may be further included in the data control signals DCSs in order to control the polarity of the data voltage of the data driver 120. [ The source start pulse SSP and the source sampling clock SSC may be omitted if the video data Data 'input to the data driver 120 is transmitted according to the mini LVDS interface standard.

1, an organic light emitting display 100 includes a plurality of power supplies (not shown) for supplying or supplying various kinds of power (voltages or currents) to an organic light emitting display panel 110, a data driver 120 and a gate driver 130 And a power controller 150 for controlling power. These power controllers are also referred to as power management ICs (PMICs).

The power controller 150 is connected to the source printed circuit board (S-PCB) through a flexible flat cable (FFC) or a flexible printed circuit (FPC) together with the timing controller 140 And may be disposed on a control printed circuit board (C-PCB).

As described above, the OLED display 100 according to the present embodiment supplies a gate voltage (scan signal) to each sub-pixel in order to drive each sub-pixel.

Due to various factors, an abnormal gate voltage may be supplied to each subpixel. In this case, the subpixel can not be normally driven, and the screen quality may be deteriorated. In a severe case, the circuit on the organic light emitting display panel 110 may be seriously damaged, a burnt phenomenon may occur, and the organic light emitting display panel 110 may be discarded.

The situation in which the gate voltage is abnormally supplied to the subpixel may be, for example, a problem in the gate driver integrated circuit, a problem in the bonding portion where the gate driver integrated circuit is connected to the organic light emitting display panel 110, or A case where there is a problem in the gate line, and the like.

In the case where the abnormal gate voltage is supplied to the subpixel in the case of a high-resolution or high-performance organic light emitting display device 100 requiring a larger number of gate lines, an organic light emitting display having an even larger number of gate driver integrated circuits The organic light emitting display panel 100 or the organic light emitting display panel 110 may be more frequently generated when the organic light emitting display device 100 is a flexible display device or when the organic light emitting display panel 100 is a flexible display device. Step.

The abnormal gate voltage that may be caused by various factors may cause the subpixels not to be driven normally, which may seriously degrade the picture quality.

Accordingly, the present embodiments provide an organic light emitting device capable of monitoring an abnormal gate voltage supplied to a subpixel and monitoring the situation before an abnormal gate voltage is applied to the subpixel so that serious circuit damage or a panel- A display device (100) and a driving method of the organic light emitting diode display (100) are disclosed.

2 is an exemplary view of a sub-pixel structure of the OLED display 100 according to the present embodiments.

Referring to FIG. 2, each of the plurality of subpixels arranged in the OLED panel 110 according to the present embodiment includes an organic light emitting diode (OLED), a driving transistor A driving transistor (DT), and the like.

Referring to FIG. 2, the organic light emitting diode OLED includes a first electrode (e.g., an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (e.g., a cathode electrode or an anode electrode).

Referring to FIG. 2, a second electrode (for example, a cathode electrode or an anode electrode) of the organic light emitting diode OLED is connected to a node for supplying a ground voltage (EVSS) For example, an anode electrode or a cathode electrode) may be connected to a first node N1 (e.g., a source node or a drain node) of the driving transistor DT.

2, the driving transistor DT is controlled by the data voltage Vdata applied to the gate node and is connected between the first electrode of the organic light emitting diode OLED and the driving voltage line DVL As shown in FIG.

Referring to FIG. 2, the driving transistor DT includes a first node N1 connected to the first electrode of the organic light emitting diode OLED, which may be a source node or a drain node, And may have a second node N2 corresponding to a gate node and a third node N3 to which a driving voltage EVDD is applied and may be a drain node or a source node.

Referring to FIG. 2, each of the plurality of sub-pixels disposed in the organic light emitting display panel 110 according to the exemplary embodiments of the present invention may further include a sensor transistor (SENT).

2, this sensor transistor SENT is controlled by a gate voltage Vg_SENT applied to a gate node and is connected to the first electrode of the organic light emitting diode OLED and the reference voltage line RVL, As shown in FIG.

In other words, the gate node of the sensor transistor SENT is electrically connected to the corresponding gate line GL 'to receive the gate voltage Vg_SENT. The drain node (or source node) of the sensor transistor SENT may be electrically connected to the first electrode of the organic light emitting diode OELD and the N1 node of the driving transistor DT. The source node (or drain node) of the sensor transistor SENT may be electrically connected to the reference voltage line RVL.

Referring to FIG. 2, the source node (or drain node) of the sensor transistor SENT is referred to as a "reference node (RN)". A point electrically connected to the source node (or drain node) of the sensor transistor SENT and the reference voltage line RVL may be referred to as a reference node RN.

Referring to FIG. 2, each sub-pixel may further include a switching transistor (SWT), a storage capacitor (Cstg), and the like.

2, the switching transistor SWT is controlled by the gate voltage Vg_SWT applied to the gate node and is electrically connected between the gate node N2 node of the driving transistor DT and the data line DL .

When the switching transistor SWT is turned on by the gate voltage Vg_SWT applied to the gate node GL through the gate line GL, the data voltage Vdata supplied from the data line DL Can be applied to the gate node (N2 node) of the driving transistor DT to turn on the driving transistor DT.

2, the storage capacitor Cstg is connected between the gate node N2 of the driving transistor DT and the first electrode of the organic light emitting diode OLED (i.e., the node N1 of the driving transistor DT) And is electrically connected.

The storage capacitor Cstg serves to maintain a constant voltage for one frame.

2, using a 3T1C subpixel structure including three transistors DT, SENT and SWT and one capacitor Cstg, a subpixel structure can be used as a gate without a separate monitoring device, It is possible to monitor the voltage abnormality.

Referring to FIG. 2, the gate node of the sensor transistor SENT and the gate node of the switching transistor SWT can receive gate voltages individually from different gate lines.

In this case, the gate line GL 'electrically connected to the gate node of the sensor transistor SENT and the gate line GL electrically connected to the gate node of the switching transistor SWT may be different from each other.

Therefore, the gate voltage Vg_SENT applied to the gate node of the sensor transistor SENT and the gate voltage Vg_SWT applied to the gate node of the switching transistor SWT are different scan signals (Vg_SENT? Vg_SWT).

As described above, by making the gate node of the sensor transistor SENT and the gate node of the switching transistor SWT individually receive the gate voltage from the different gate lines, the sensor transistor SENT and the switching transistor SWT can be independently And can be individually controlled, enabling more efficient operation of the subpixel.

Alternatively, the gate node of the sensor transistor SENT and the gate node of the switching transistor SWT may receive the gate voltage from one gate line.

In this case, the gate line GL 'electrically connected to the gate node of the sensor transistor SENT and the gate line GL electrically connected to the gate node of the switching transistor SWT are the same gate line.

Therefore, the gate voltage Vg_SENT applied to the gate node of the sensor transistor SENT and the gate voltage Vg_SWT applied to the gate node of the switching transistor SWT are the same scan signal (Vg_SENT = Vg_SWT).

As described above, the gate node of the sensor transistor SENT and the gate node of the switching transistor SWT receive the gate voltage from one gate line, and thereby, on the organic light emitting display panel 110, Since only one gate line can be formed, there is an advantage that the aperture ratio can be increased.

The 3T1C subpixel structure shown in FIG. 2 may be a subpixel structure for realizing a function of sensing and compensating for a characteristic value (for example, threshold voltage, mobility, etc.) of the driving transistor DT. This will be described in more detail with reference to FIGS. 10 and 11. FIG.

3 is an exemplary diagram illustrating a gate voltage state monitoring configuration of the OLED display 100 according to the present embodiments.

Referring to FIG. 3, the OLED display 100 according to the present embodiment is configured to monitor the states of the gate voltages Vg_SENT and Vg_SWT applied to the respective subpixels, And a power supply abnormality checking unit 320 for checking the presence or absence of an abnormal gate voltage actually applied to the subpixel using the sensing result of the sensing unit 310. [

A sub-pixel structure (the 3T1C sub-pixel structure illustrated in FIG. 2) that allows the sensing portion 310 to sense the gate voltage actually applied to the sub-pixel may also be viewed as a gate voltage state monitoring configuration.

3, the memory 330 may further include a memory 330 for storing a result (for example, an abnormality in the gate voltage) confirmed by the power supply abnormality checking unit 320 .

The memory 330 may be included in the power supply abnormality checking unit 320.

Meanwhile, the sensing unit 310 may be implemented as an analog-to-digital converter (ADC), for example.

An analog-to-digital converter (ADC) may be included within the source driver integrated circuit (SDIC).

The power supply abnormality checking unit 320 may be included in the timing controller 140 or the power controller 150, for example.

Hereinafter, a method of monitoring the gate voltage state will be described assuming that the sensing unit 310 is implemented as an analog-to-digital converter (ADC), and the power supply abnormality checking unit 320 is included in the timing controller 140.

4 is another example of the gate voltage state monitoring configuration of the OLED display 100 according to the present embodiments.

4, the sensing unit 310 is implemented by an analog-to-digital converter (ADC). When the power-supply abnormality checking unit 320 is included in the timing controller 140, the analog- And is electrically connected to the line RVL.

4, reference voltage VREF is applied to the N1 node of the driving transistor DT through one reference voltage line RVL, the N1 node or the reference node RN is floated, (RVL) to a reference voltage supply node 410 or an analog-to-digital converter (ADC) so that a digital converter (ADC) can sense the voltage at the node N1 or the reference node RN SW).

Referring to FIG. 4, the switch SW includes a node 410 connected to the reference voltage line RVL and a node 430 connected to the reference voltage line VREF according to control information such as a light emission timing, a sensing timing, To one of the nodes 420 connected to the analog-to-digital converter (ADC).

By controlling the voltage application state of the N1 node or the reference node RN and controlling the connection position of the reference voltage line RVL in accordance with the switching operation of the switch SW, A sensing operation for driving characteristic of the sub-pixel (driving operation for emitting light), intrinsic characteristic value (threshold voltage, mobility) of the driving transistor DT in the sub-pixel, intrinsic characteristic value of the sensor transistor SENT , Mobility), a gate voltage state monitoring operation, and the like can normally be performed.

4, in order to monitor the gate voltage state, an analog-to-digital converter ADC applies a gate voltage Vg_SENT to the gate node of the sensor transistor SENT, The reference node RN electrically connected to the reference node RN is in a floating state and senses the voltage of the reference node RN and outputs sensing data obtained by converting the sensed voltage into a digital value. The sensing data output from the analog-to-digital converter (ADC) is transmitted to the timing controller 140.

Here, when the analog-to-digital converter ADC senses the voltage of the reference node RN, the gate voltage Vg_SENT applied to the gate node of the sensor transistor SENT turns on the sensor transistor SENT, On, and may be a high level gate voltage (VGH).

As described above, in the analog-to-digital converter (ADC), the gate voltage Vg_SENT is applied to the gate node of the sensor transistor SENT, and the reference node (RVL) RN) is floating, the voltage of the reference node RN is sensed. Since the sensed voltage includes the component of the gate voltage Vg_SENT actually applied to the gate node of the sensor transistor SENT , And the gate voltage (Vg_SENT).

In other words, after controlling the voltage application state on the circuit in the sub-pixel so that the voltage of the reference node RN on the circuit in the sub-pixel is included as the gate voltage component, the voltage of the reference node RN is sensed, The actual applied gate voltage is calculated and indirectly determined, thereby confirming whether or not the gate voltage is abnormal.

This indirect and calculated method of confirming the presence or absence of a gate voltage abnormality can reduce the number of necessary components and can prevent the occurrence of abnormalities in the gate voltage Can easily be confirmed.

Referring to FIG. 4, the timing controller 140 receives sensing data output from an electrically connected analog digital converter (ADC), and generates a gate signal It is possible to confirm whether or not the voltage Vg_SENT is abnormal and store the result of the verification in the memory 330. [

Here, the confirmation result may include the abnormality information of the gate voltage Vg_SENT.

As described above, the timing controller 140 checks whether or not the gate voltage Vg_SENT applied to the gate node of the sensor transistor SENT is abnormal based on the sensing data received from the analog-to-digital converter (ADC) By storing the result in the memory 330, it is possible to easily and conveniently monitor an abnormal gate voltage applied state, and it becomes possible to cope with such an abnormal gate voltage application situation effectively.

On the other hand, the timing controller 140 receives the voltage value information of the sensed gate voltage Vg_SENT, the voltage value information of the sensed gate voltage Vg_SENT, and the corresponding value of the gate voltage of the sensor transistor SENT, The identification information of the gate driver integrated circuit, the identification information of the corresponding gate line, the bonding position information of the gate driver integrated circuit, and the like.

As a result of the monitoring of the gate voltage state as described above, in addition to the information on the presence or absence of the gate voltage, information on the voltage value of the sensed gate voltage Vg_SENT, identification information of the corresponding subpixel, identification information of the gate driver integrated circuit, The bonding position information of the integrated circuit, the identification information of the gate line, and the like, so that it is possible to accurately diagnose the cause, position, and the like of the abnormal gate voltage application situation at a later time and take appropriate corrective measures.

On the other hand, the method of checking for the presence or absence of an abnormality of the gate voltage will be described in detail. The timing controller 140 controls the sensor transistor SENT based on sensing data received from the analog / digital converter (ADC) The calculated gate voltage is compared with a known reference gate voltage, and the presence or absence of the calculated gate voltage can be confirmed.

The sensed voltage of the reference node RN in the analog-to-digital converter ADC is the sum of the threshold voltage Vth_SENT of the sensor transistor SENT at the gate voltage Vg_SENT = VGH actually applied to the gate node of the sensor transistor SENT (VGH-Vth_SENT).

The timing controller 140 recognizes the voltage (VGH-Vth_SENT) obtained by sensing the reference node RN from the received sensing data and outputs the detected voltage VGH-Vth_SENT to a threshold The gate voltage Vg_SENT = VGH actually applied to the gate node of the sensor transistor SENT can be calculated by adding the threshold voltage Vth_SENT in the voltage data.

According to the foregoing, after controlling the voltage application state on the circuit in the sub-pixel so that the voltage of the reference node RN on the circuit within the sub-pixel is included as the gate voltage component, the voltage of the reference node RN is sensed, The actual applied gate voltage is calculated from the voltage and indirectly detected, thereby confirming whether or not the gate voltage is abnormal.

This indirect and calculated method of confirming the presence or absence of a gate voltage abnormality can reduce the number of necessary components and can prevent the occurrence of abnormalities in the gate voltage Can easily be confirmed.

On the other hand, in order for the timing controller 140 to calculate the gate voltage (Vg_SENT = VGH) actually applied to the gate node of the sensor transistor SENT, the threshold voltage data used together with the sensing data received from the analog / digital converter , And the threshold voltage Vth_SENT of the sensor transistor SENT.

In this way, since the voltage at which the analog digital converter ADC senses the reference node RN is "VGH-Vth_SENT ", the case where the threshold voltage data is data on the threshold voltage Vth_SENT of the sensor transistor SENT The accurate gate voltage Vg_SENT = VGH can be calculated.

However, there is a disadvantage in that a procedure for sensing the threshold voltage Vth_SENT of the sensor transistor SENT is separately required.

Therefore, in order to compensate for the luminance deviation between the sub-pixels, the threshold voltage Vth_DT of the drive transistor DT, which is already known, is set equal to the threshold voltage Vth_SENT of the sensor transistor SENT, It can be used instead.

This is because the threshold voltage Vth_DT of the driving transistor DT and the threshold voltage Vth_SENT of the sensor transistor SENT have substantially similar characteristics (for example, a distribution characteristic, a deviation characteristic, a movement characteristic, and the like).

Therefore, even when the gate voltage Vg_SENT = VGH is calculated using the threshold voltage Vth_DT of the drive transistor DT instead of the threshold voltage Vth_SENT of the sensor transistor SENT, there is no significant difference in terms of accuracy .

That is, in order for the timing controller 140 to calculate the gate voltage (Vg_SENT = VGH) actually applied to the gate node of the sensor transistor SENT, the threshold voltage data to be used together with the sensing data received from the analog / digital converter , And data on the threshold voltage Vth_DT of the driving transistor DT.

As described above, when the gate voltage Vg_SENT = VGH is calculated using the already known threshold voltage Vth_DT of the driving transistor DT instead of the threshold voltage Vth_SENT of the sensor transistor SENT, The gate voltage Vg_SENT = VGH can be accurately calculated without any other procedure for sensing the threshold voltage Vth_SENT of the transistor SENT.

Hereinafter, with reference to Figs. 5 to 9, the gate voltage state monitoring method briefly described above will be described in more detail.

5 to 9 are views for explaining a method of monitoring the gate voltage state of the OLED display 100 according to the present embodiments.

The method for monitoring the gate voltage state of the OLED display 100 according to the present embodiment includes four steps STEP 0, STEP 1, STEP 2, and STEP 3.

FIGS. 5 to 8 show the sub-pixel voltage application state and the transistor on-off state in the four steps STEP 0, STEP 1, STEP 2, and STEP 3, respectively. FIG. 9 is a graph showing the voltage change of the reference node RN corresponding to the sensing node in STEP 1, STEP 2, and STEP 3.

5, in STEP 0, under the control of the timing controller 140, the gate driver 130 applies a low-level gate voltage (Vg_SENT = VGL, for example, -6 V) to the gate node of the sensor transistor SENT, And a low level gate voltage (Vg_SWT = VGL, for example, -6 V) is applied to the gate node of the switching transistor SWT to turn off both the sensor transistor SENT and the switching transistor SWT .

6, in STEP 1, under the control of the timing controller 140, the gate driver 130 applies a high-level gate voltage (Vg_SENT = VGH, for example, 6 V) to the gate node of the sensor transistor SENT And turns on the sensor transistor SENT.

In STEP 1, under the control of the timing controller 140, the gate driver 130 applies a high-level gate voltage (Vg_SWT = VGL, for example, 24 V) to the gate node of the switching transistor SWT, And turns on the transistor SWT.

In STEP 1, under the control of the timing controller 140, the power controller 150 controls the source driver IC of the data driver 120 so that the sensor transistor SENT and the reference voltage line RVL are electrically A reference voltage (VREF, for example, 0 V) is applied to the connected reference node RN.

Therefore, as shown in Fig. 9, in STEP 1, the voltage of the reference node RN is the reference voltage VREF.

To this end, the switch SW is in a switching state connecting the reference voltage line RVL to the reference voltage supply node 410, as shown in Fig.

Further, in STEP 1, under the control of the timing controller 140, the data driver 120 outputs the data voltage (Vdata, for example, 16 V) to the data line DL.

The reference voltage VREF (for example, 0 V) is applied to the node N1 of the driving transistor DT and the data voltage Vdata (for example, 16 V) is applied to the node N2 of the driving transistor DT, The drive voltage EVDD (e.g., 12V) is applied to the node N3 of the transistor DT.

At this time, the data voltage Vdata applied to the N2 node which is the gate node of the driving transistor DT may be higher than the driving voltage EVDD applied to the N3 node of the driving transistor DT. This voltage magnitude relationship is obtained by sensing the voltage including the threshold voltage Vth_SENT of the sensor transistor SENT for monitoring the gate voltage state by sensing the voltage including the threshold voltage Vth_DT of the driving transistor DT This is the part that makes a difference.

7, in STEP 2, in response to the switch control signal of the timing controller 140, the switch SW changes its switching state so that the reference voltage line RVL is disconnected from the reference voltage supply node 410 do.

According to the switching operation of the switch SW, the reference node RN floats and the voltage of the reference node RN rises at the reference voltage VREF (e.g., 0 V).

Therefore, as shown in Fig. 9, in STEP 2, the voltage of the reference node RN gradually rises from the reference voltage VREF.

7, in STEP 2, the gate node voltage (N2 voltage) of the driving transistor DT is equal to the difference value EVDD-VDD between the driving voltage EVDD and the threshold voltage Vth_DT of the driving transistor DT, Vth_DT).

In addition, since the data voltage Vdata is higher than the driving voltage EVDD, the N1 node of the driving transistor DT is not floated, and the driving voltage EVDD corresponding to the constant voltage is applied. Instead, the reference node RN is floated.

As described above, referring to FIG. 9, the reference node RN floats, gradually rises in the reference voltage VREF, and saturates at a certain level.

9, when the reference node RN becomes lower than the gate voltage Vg_SENT = VGH applied to the gate node of the sensor transistor SENT by the threshold voltage Vth_SENT of the sensor transistor SENT, Stop the voltage rise.

That is, the saturated voltage of the reference node RN is "VGH-Vth_SENT ".

Thus, STEP 3 can be performed after the voltage of the reference node RN becomes saturated and the voltage rise ceases.

Referring to FIG. 8, in STEP 3, a switch SW connects the reference voltage line RVL to an analog-to-digital converter (ADC).

Accordingly, the analog-to-digital converter (ADC) senses the voltage of the reference node RN.

At this time, the sensed voltage is a voltage (VGH-Vth_SENT) in a state where voltage saturation occurs at the reference node RN as shown in FIG.

As described above, after passing through STEP0 to STEP4, the analog-to-digital converter (ADC) converts the sensed voltage (VGH-Vth_SENT) into a digital value and outputs sensing data including the converted digital value And outputs it to the timing controller 140.

By using the driving method of the OLED display 100 described above, the voltage application state on the circuit in the sub-pixel is controlled so that the voltage of the reference node RN on the circuit in the sub-pixel is included as the gate voltage component, It is unnecessary to check the presence or absence of an abnormality by measuring the gate voltage by providing a separate voltage measuring device so that the number of necessary components can be reduced and the gate voltage It is possible to easily confirm whether or not the abnormality is present.

7 and 8, the sensor node SENT and the first electrode of the organic light emitting diode OLED are electrically connected to each other at the node N1 (N1) in which the reference node RN is floating, Node) is supplied with the drive voltage EVDD supplied through the drive voltage line DVL.

Further, in a state in which the reference node RN is floating, the data voltage applied to the gate node of the driving transistor DT is higher than the driving voltage EVDD.

7 and 8, in STEPs 2 and 3, the gate node voltage (N2 voltage) of the driving transistor DT, i.e., the data voltage Vdata (e.g., 16V) For example, 12V).

As described above, since the data voltage Vdata is higher than the drive voltage EVDD in the gate voltage state monitoring mode section, the N1 node of the drive transistor DT is not floated and the drive voltage corresponding to the constant voltage EVDD) is applied, and instead, the reference node RN is floated. Accordingly, it is possible to monitor the gate voltage state by sensing the reference node RN.

This causes the voltage of the reference node RN corresponding to the source node (or drain node) of the sensor transistor SENT to follow the gate voltage applied to the gate node of the sensor transistor SENT, At this time, the voltage of the reference node RN is sensed, and the gate voltage applied to the gate node of the sensor transistor SENT can be monitored based on the sensed voltage.

On the other hand, in each subpixel, the driving transistor DT for driving the organic light emitting diode OLED has a threshold voltage Vth_DT affecting the switching operation. The threshold voltage Vth_DT may be a characteristic value inherent to the driving transistor DT, and may be deviated for each driving transistor DT.

Further, as the driving time of the driving transistor DT increases, the degradation of the driving transistor DT proceeds, and the threshold voltage Vth_DT can be changed.

As a result, the deviation of the threshold voltage Vth_DT between the driving transistors DT in each sub-pixel can be increased.

Such a deviation of the threshold voltage Vth_DT between the driving transistors DT may cause a luminance deviation between the subpixels, which may be a major factor for lowering the image quality.

Therefore, the OLED display 100 according to the present embodiment has a compensation function for sensing the threshold voltage Vth_DT of the driving transistor DT and compensating for a threshold voltage deviation between the driving transistors DT A compensation function or a luminance deviation compensation function, a threshold voltage compensation function or a data compensation function).

A method of sensing the threshold voltage Vth_DT of the driving transistor DT in each sub-pixel and compensating for the threshold voltage deviation will be briefly described below with reference to Figs. 10 and 11. Fig.

10 to 12 are diagrams for explaining a threshold voltage sensing method of the driving transistor DT of the OLED display 100 according to the present embodiments.

The method of sensing the threshold voltage Vth_DT of each sub-pixel driving transistor DT includes an initializing step STEP A, a voltage raising step STEP B, and a sensing step STEP C.

10 is a diagram showing an initializing step, and FIG. 11 is a diagram showing a voltage raising step and a sensing step. 12 is a graph showing the voltage change of the N1 node of the driving transistor DT corresponding to the sensing node.

Referring to Fig. 10, in the initialization step STEP A, the switching transistor SWT is turned on by the gate voltage Vg_SWT applied to the gate node GL from the corresponding gate line GL.

As a result, the data voltage Vdata supplied from the data line DL is applied to the node N2 corresponding to the gate node of the driving transistor DT through the turned-on switching transistor SWT.

Also, in the initialization step STEP A, the switch SW connects the connection point 430 between the reference voltage supply node 430 and the reference voltage line RVL. Then, the sensor transistor SENT is turned on by the gate voltage Vg_SENT applied to the gate node from the corresponding gate line GL '.

The reference voltage VREF supplied through the reference voltage supply node 430 is applied to the N1 node of the driving transistor DT through the sensor transistor SENT turned on via the reference voltage line RVL.

10, in the initializing step STEP A, the N2 node of the driving transistor DT is initialized to the data voltage Vdata, and the N1 node of the driving transistor DT is set to the reference Is initialized to the voltage VREF.

On the other hand, in the mode for sensing the threshold voltage Vth_DT of the driving transistor DT, the driving voltage EVDD applied to the N3 node of the driving transistor DT is the data voltage (Vdata) (EVDD > Vdata). This is in contrast to the voltage magnitude relationship (EVDD <Vdata) in the gate voltage state monitoring mode.

Referring to FIG. 11, the switch SW disconnects the reference voltage line RVL from the reference voltage supply node 430 in a voltage rising step (STEP B) after the initializing step STEP A.

Therefore, in the voltage raising step (STEP B), the N1 node of the driving transistor DT is floated. That is, the reference voltage VREF corresponding to the constant voltage applied to the N1 node of the driving transistor DT disappears.

In the voltage raising step (STEP B), the floating of the N1 node of the driving transistor DT causes a voltage boosting of the N1 node of the driving transistor DT as shown in Fig.

12, the voltage at the N1 node of the driving transistor DT rises to a voltage (Vdata-Vth_DT) that is lower than the data voltage Vdata by the threshold voltage Vth_DT of the driving transistor DT and saturates.

From this time, the sensing step STEP C can proceed.

11 and 12, after the voltage at the node N1 of the driving transistor DT is saturated to "Vdata-Vth_DT", the switch SW connects the reference voltage line RVL to the analog-to-digital converter (ADC) Connect.

11 and 12, the analog-to-digital converter (ADC) senses the saturated voltage (Vdata-Vth_DT) of the N1 node of the driving transistor DT, converts the sensed voltage into a digital value, Generates sensing data including the digital value (s), and transmits the sensing data to the timing controller 140.

Referring to Fig. 11, the timing controller 140 can determine the threshold voltage Vth_DT of the driving transistor DT in each sub-pixel from the received sensing data.

The timing controller 140 calculates a data compensation amount for compensating the threshold voltage deviation between the driving transistors DT in each sub pixel based on the found threshold voltage Vth_DT and supplies the calculated data compensation amount to the memory 330 ).

Then, when the data to be supplied to the corresponding subpixel is generated, the timing controller 140 changes the data based on the stored data compensation amount and supplies the data to the data driving unit 120.

According to the embodiments described above, the abnormal gate voltage is applied to the subpixel so that the abnormal gate voltage is supplied to the subpixel before the serious circuit damage or the panel bunch phenomenon occurs. So that it can be prepared in advance.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: organic light emitting display
110: organic light emitting display panel
120: Data driver
130: Gate driver
140: Timing controller

Claims (12)

An organic light emitting display panel in which data lines and gate lines are arranged and the subpixels are arranged in a matrix type;
A data driver for driving the data lines;
A gate driver for driving the gate lines; And
And a timing controller for controlling the data driver and the gate driver,
Each of the sub-
A driving transistor controlled by a data voltage applied to a gate node and electrically connected between a first electrode of the organic light emitting diode and a driving voltage line; a driving transistor controlled by a gate voltage applied to the gate node, And a sensor transistor electrically connected between the first electrode of the light emitting diode and the reference voltage line,
Further comprising an analog-to-digital converter electrically connected to the reference voltage line,
The analog-to-
A gate voltage is applied to a gate node of the sensor transistor, a reference node electrically connected to the sensor transistor and the reference voltage line is floated, a voltage of the reference node is sensed, and the sensed voltage is converted into a digital value And outputs the converted sensed data. The method according to claim 1,
The timing controller includes:
Wherein the sensing circuit is electrically connected to the analog-to-digital converter, and the presence or absence of a gate voltage applied to a gate node of the sensor transistor is checked based on sensing data output from the analog-to-digital converter, Emitting display device. 3. The method of claim 2,
The timing controller includes:
And further stores at least one of a voltage value of the sensed voltage, identification information of the gate driver integrated circuit, identification information of the gate line, and bonding position information of the gate driver integrated circuit together with the confirmation result Organic light emitting display. 3. The method of claim 2,
The timing controller includes:
Calculating a gate voltage applied to a gate node of the sensor transistor based on the threshold voltage data and the sensing data,
And comparing the calculated gate voltage with a previously-recognized reference gate voltage to confirm whether or not the identified gate voltage is abnormal. 5. The method of claim 4,
Wherein the threshold voltage data comprises:
Wherein the threshold voltage is data on a threshold voltage of the sensor transistor or data on a threshold voltage of the driving transistor. The method according to claim 1,
Wherein a drive voltage supplied through the drive voltage line is applied to a node where the sensor transistor and the first electrode of the organic light emitting diode are electrically connected in a state in which the reference node is floating. The method according to claim 6,
Wherein the data voltage applied to the gate node of the driving transistor is higher than the driving voltage in a state where the reference node is floating. The method according to claim 1,
Each of the sub-
A switching transistor which is controlled by a gate voltage applied to the gate node and is electrically connected between the gate node of the driving transistor and the data line,
And a storage capacitor electrically connected between the gate node of the driving transistor and the first electrode of the organic light emitting diode. 9. The method of claim 8,
Wherein a gate node of the sensor transistor and a gate node of the switching transistor receive gate voltages separately from different gate lines. 9. The method of claim 8,
Wherein a gate node of the sensor transistor and a gate node of the switching transistor receive a gate voltage from one gate line. The method according to claim 1,
Further comprising a switch for connecting the reference voltage supply node or the analog-digital converter with the reference voltage line. A driving transistor which is controlled by a data voltage applied to a gate node and is electrically connected between a first electrode of the organic light emitting diode and a driving voltage line and a driving transistor which is electrically connected between a first electrode of the organic light emitting diode and a reference voltage line A sub-pixel including a sensor transistor electrically connected to the organic light emitting display device is arranged in a matrix type,
Applying a gate voltage to a gate node of the sensor transistor and applying a reference voltage to a reference node electrically connected to the sensor transistor and the reference voltage line;
Floating the reference node to raise the voltage of the reference node;
Sensing a voltage of the reference node; And
And outputting sensed data obtained by converting the sensed voltage to a digital value.

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