KR102304355B1 - Organic light emitting display device and method for the same - Google Patents

Abstract

In the present exemplary embodiments, an organic light emitting diode (OLED) device that monitors and responds in advance to a situation in which an abnormal gate voltage is supplied to a sub-pixel before serious circuit damage or panel burnt occurs due to an abnormal gate voltage being applied to the sub-pixel. It relates to a display device and a driving method thereof.

Description

Organic light emitting display device and driving method thereof

The present embodiments relate to an organic light emitting display device and a driving method thereof.

Recently, an organic light emitting display device, which has been in the spotlight as a display device, has advantages of fast response speed, high luminous efficiency, luminance, and viewing angle by using an organic light emitting diode (OLED) that emits light by itself.

In such an organic light emitting display device, sub-pixels including organic light emitting diodes are arranged in a matrix form, and the brightness of the sub-pixels selected by a scan signal is controlled according to a gray level of data.

As such, in the organic light emitting display device, a gate voltage (scan signal) is applied to each sub-pixel to drive each sub-pixel. can occur

In this case, the sub-pixel may not be driven normally, and the screen quality may be greatly deteriorated. In severe cases, a circuit on the organic light emitting display panel may be seriously damaged, a burnt phenomenon may occur, and a situation in which the organic light emitting display panel must be discarded may occur.

A situation in which the gate voltage is abnormally supplied to the sub-pixels may be, for example, when there is a problem in the gate driver integrated circuit, when there is a problem in the bonding portion where the gate driver integrated circuit is connected to the organic light emitting display panel, or in the gate line. It can occur in a variety of cases, including when there is a problem.

In addition, a situation in which the gate voltage is abnormally supplied to sub-pixels is a case of a high-resolution or high-function organic light-emitting display device requiring more gate lines, or an organic light-emitting display device having a larger number of gate driver integrated circuits. , or may occur more frequently when the organic light emitting display device is a flexible display device, or may occur in the logistics stage of the organic light emitting display device or the organic light emitting display panel.

However, at present, a technology capable of monitoring whether a gate voltage is abnormally applied to a sub-pixel has not been developed.

The purpose of the present embodiments is to monitor the situation in which the abnormal gate voltage is supplied to the sub-pixel in advance and cope with it before serious circuit damage or panel burnt occurs due to the abnormal gate voltage being applied to the sub-pixel. there is

According to an exemplary embodiment, an organic light emitting display panel in which data lines and gate lines are disposed and subpixels are disposed in a matrix type, a data driver driving the data lines, a gate driver driving the gate lines, a data driver, and An organic light emitting diode display including a timing controller for controlling a gate driver is provided.

In such an organic light emitting diode display, each sub-pixel includes an organic light emitting diode, a driving transistor controlled by a data voltage applied to the gate node and electrically connected between a first electrode of the organic light emitting diode and a driving voltage line, and a gate node. and a sensor transistor controlled by the gate voltage applied to the , and electrically connected between the first electrode of the organic light emitting diode and the reference voltage line.

The organic light emitting diode display may further include an analog-to-digital converter electrically connected to the reference voltage line.

The analog-to-digital converter senses the voltage of the reference node in a state where a gate voltage is applied to the gate node of the sensor transistor and the reference node electrically connected to the sensor transistor and the reference voltage line is floating, and the sensed voltage is converted to a digital value. It is possible to output the sensed data converted to

Another embodiment includes an organic light emitting diode, a driving transistor controlled by a data voltage applied to a gate node and electrically connected between a first electrode of the organic light emitting diode and a driving voltage line, and a first electrode of the organic light emitting diode; Provided is a method of driving an organic light emitting diode display in which sub-pixels including a sensor transistor electrically connected between reference voltage lines are arranged in a matrix type.

The driving method of the organic light emitting display device includes applying a gate voltage to a gate node of a sensor transistor, applying a reference voltage to a reference node electrically connected to the sensor transistor and the reference voltage line, and floating the reference node to obtain a reference voltage. It may include raising the voltage of the node, sensing the voltage of the reference node, and outputting sensing data obtained by converting the sensed voltage into a digital value.

According to the present embodiments as described above, before the abnormal gate voltage is applied to the sub-pixel and serious circuit damage or panel burnt occurs, the situation in which the abnormal gate voltage is supplied to the sub-pixel is monitored in advance. It can help you prepare ahead of time.

1 is a system configuration diagram of an organic light emitting diode display according to example embodiments.
2 is an exemplary diagram of a sub-pixel structure of an organic light emitting diode display according to example embodiments.
3 is an exemplary diagram of a gate voltage state monitoring configuration of the organic light emitting diode display according to the present exemplary embodiment.
4 is another exemplary diagram of a gate voltage state monitoring configuration of the organic light emitting diode display according to the present exemplary embodiment.
5 to 9 are diagrams for explaining a method of monitoring a gate voltage state of an organic light emitting diode display according to the present exemplary embodiment.
10 and 12 are diagrams for explaining a method of sensing a threshold voltage of a driving transistor of an organic light emitting diode display according to the present exemplary embodiment.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a system configuration diagram of an organic light emitting diode display 100 according to the present exemplary embodiment.

Referring to FIG. 1 , the organic light emitting display device 100 according to the present exemplary embodiments includes an organic light emitting display panel 110 , a data driver 120 , a gate driver 130 , a timing controller 140 , and the like. .

In the organic light emitting display panel 110 , a plurality of data lines DL are disposed in a first direction, a plurality of gate lines GL are disposed in a second direction crossing the first direction, and a plurality of subpixels ( SP) is arranged in a matrix type.

The data driver 120 drives the data lines by supplying a data voltage to the data lines.

The gate driver 130 sequentially drives the gate lines by sequentially supplying a scan signal (also referred to as a “gate voltage”) to the gate lines.

The timing controller 140 supplies a control signal to the data driver 120 and the gate driver 130 to control operations of the data driver 120 and the gate driver 130 .

The timing controller 140 starts scanning according to the timing implemented in each frame, and converts the image data (Data) input from the host system 160 to match the data signal format used by the data driver 120 . It outputs the image data (Data') and controls the data drive at an appropriate time according to the scan.

The gate driver 130 sequentially drives the gate lines by sequentially supplying a scan signal of an on voltage or an off voltage to the gate lines under the control of the timing controller 140 .

The gate driver 130 may be positioned on both sides of the organic light emitting display panel 110 as shown in FIG. 1 , or, in some cases, only on one side, depending on the sub-pixel structure and driving method.

Also, the gate driver 130 may include a plurality of gate driver integrated circuits (Gate Driver IC, GDIC #1, ... , GDIC #N, N: natural number). , connected to the bonding pad of the organic light emitting display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method, or implemented as a GIP (Gate In Panel) type. It may be directly disposed on the organic light emitting display panel 110 or, in some cases, may be integrated and disposed on the organic light emitting display panel 110 .

Each of the plurality of gate driver integrated circuits mentioned above may include a shift register, a level shifter, and the like.

When a specific gate line is opened, the data driver 120 converts the image data Data' received from the timing controller 140 into an analog data voltage Vdata and supplies it to the data lines, thereby driving the data lines. do.

The data driver 120 may include a plurality of source driver ICs (also called data driver ICs, SDIC #1, ... , SDIC #M, M: natural numbers). However, the plurality of source driver integrated circuits are connected to the bonding pads of the organic light emitting display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method, or It may be directly disposed on the organic light emitting display panel 110 or, in some cases, may be integrated and disposed on the organic light emitting display panel 110 .

Each of the plurality of source driver integrated circuits mentioned above includes a shift register, a latch, a digital analog converter (DAC), an output butter, and the like, and in some cases, by sensing an analog voltage value for sub-pixel compensation. It may further include an analog-to-digital converter (ADC) that converts the digital value and generates and outputs sensed data.

The plurality of source driver integrated circuits may be implemented, for example, in a Chip On Film (COF) method. In each of the plurality of source driver integrated circuits, one end is bonded to at least one source printed circuit board (S-PCB), and the other end is bonded to the bonding pad unit of the organic light emitting display panel 110 . .

On the other hand, the above-mentioned host system 160, along with the image data (Data) of the input image, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, a clock signal Various timing signals including (CLK) and the like are transmitted to the timing controller 140 .

The timing controller 140 converts the image data (Data) input from the host system 160 according to the data signal format used by the data driver 120 to output the converted image data (Data'), In order to control the data driver 120 and the gate driver 130 , a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, a clock signal, etc. timing signals are received, and various control signals are generated. It outputs to the data driver 120 and the gate driver 130 .

For example, the timing controller 140 controls the gate driver 130 , a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Outputs gate control signals (GCS, GCS') including Gate Output Enable). The gate start pulse GSP controls the operation start timing of the gate driver integrated circuits constituting the gate driver 130 . The gate shift clock GSC is a clock signal commonly input to the gate driver integrated circuits and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies timing information of the gate driver integrated circuits.

The timing controller 140 controls the data driver 120 , a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). ) and the like, and output the data control signal DCS. The source start pulse SSP controls the data sampling start timing of the source driver integrated circuits constituting the data driver 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120 . In some cases, a polarity control signal POL may be further included in the data control signals DCSs to control the polarity of the data voltage of the data driver 120 . If the image data 'Data' input to the data driver 120 is transmitted according to the mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

Referring to FIG. 1 , the organic light emitting display device 100 supplies or supplies various power sources (voltage or current) to the organic light emitting display panel 110 , the data driver 120 , and the gate driver 130 . Power) may further include a power controller 150 for controlling the. Such a power controller is also referred to as a power management integrated circuit (PMIC).

The power controller 150, together with the timing controller 140, is connected through a source printed circuit board (S-PCB) and a flexible flat cable (FFC) or a flexible printed circuit (FPC). It may be disposed on a Control Printed Circuit Board (C-PCB).

As described above, the organic light emitting diode display 100 according to the present exemplary embodiments supplies a gate voltage (scan signal) to each subpixel to drive each subpixel.

A situation in which an abnormal gate voltage is supplied to each sub-pixel may occur due to various factors. In this case, the sub-pixel may not be driven normally, and the screen quality may be greatly deteriorated. In severe cases, a circuit on the organic light emitting display panel 110 may be seriously damaged, a burnt phenomenon may occur, and a situation in which the organic light emitting display panel 110 must be discarded may occur.

A situation in which the gate voltage is abnormally supplied to the sub-pixels is, for example, when there is a problem in the gate driver integrated circuit, when there is a problem in the bonding portion to which the gate driver integrated circuit is connected to the organic light emitting display panel 110 , or It may occur in various cases including a case where there is a problem with the gate line.

In addition, a situation in which the gate voltage is abnormally supplied to the sub-pixels is a high-resolution or high-function organic light-emitting display device 100 requiring more gate lines, an organic light-emitting display having a larger number of gate driver integrated circuits. It may occur more frequently in the case of the device 100 or the organic light emitting display device 100 is a flexible display device, and the distribution of the organic light emitting display device 100 or the organic light emitting display panel 110 . It can also occur in stages.

The abnormal gate voltage that may be caused by various factors as described above may cause the sub-pixels to not operate normally, which may significantly degrade the screen quality.

Accordingly, in the present embodiments, the organic light emitting diode system monitors a situation in which an abnormal gate voltage is supplied to the sub-pixels and responds in advance before serious circuit damage or panel burnt occurs due to an abnormal gate voltage being applied to the sub-pixels. A display device 100 and a driving method of the organic light emitting display device 100 are disclosed.

2 is an exemplary diagram of a sub-pixel structure of the organic light emitting diode display 100 according to the present exemplary embodiment.

Referring to FIG. 2 , each of the plurality of sub-pixels disposed in the organic light emitting display panel 110 according to the present exemplary embodiments basically includes an organic light emitting diode (OLED) and a driving transistor driving the same. (DT: Driving Transistor) may be included.

Referring to FIG. 2 , the organic light emitting diode (OLED) includes a first electrode (eg, an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (eg, a cathode electrode or an anode electrode).

Referring to FIG. 2 , a second electrode (eg, a cathode electrode or an anode electrode) of the organic light emitting diode (OLED) is connected to a node supplying a ground voltage (EVSS), and the first electrode ( For example, an anode electrode or a cathode electrode) may be connected to a first node N1 (eg, a source node or a drain node) of the driving transistor DT.

Referring to FIG. 2 , the driving transistor DT is controlled by the data voltage Vdata applied to the gate node, and is located between the first electrode of the OLED and the driving voltage line (DVL). can be electrically connected to.

Referring to FIG. 2 , the driving transistor DT is connected to the first electrode of the organic light emitting diode OLED, and a first node N1 , which may be a source node or a drain node, and a data voltage Vdata are applied. It may have a second node N2 corresponding to a gate node, a third node N3 to which the driving voltage EVDD is applied, and which may be a drain node or a source node.

Meanwhile, referring to FIG. 2 , each of the plurality of sub-pixels disposed on the organic light emitting display panel 110 according to the present exemplary embodiments may further include a sensor transistor (SENT).

Referring to FIG. 2 , the sensor transistor SENT is controlled by the gate voltage Vg_SENT applied to the gate node, and the first electrode of the organic light emitting diode OLED and the reference voltage line RVL (Reference Voltage Line) may be electrically connected between them.

In other words, the gate node of the sensor transistor SENT is electrically connected to the corresponding gate line GL' to receive the gate voltage Vg_SENT. A drain node (or a source node) of the sensor transistor SENT may be electrically connected to a first electrode of the organic light emitting diode OELD and a node N1 of the driving transistor DT. A source node (or a drain node) of the sensor transistor SENT may be electrically connected to the reference voltage line RVL.

Referring to FIG. 2 , a source node (or a drain node) of the sensor transistor SENT is referred to as a “reference node RN”. A point electrically connected to the source node (or drain node) of the sensor transistor SENT and the reference voltage line RVL may also be referred to as a reference node RN.

Referring to FIG. 2 , each subpixel may further include a switching transistor (SWT), a storage capacitor (Cstg), and the like.

Referring to FIG. 2 , the switching transistor SWT is controlled by the gate voltage Vg_SWT applied to the gate node, and is electrically connected between the gate node (N2 node) of the driving transistor DT and the data line DL. Connected.

When the switching transistor SWT is turned on by the gate voltage Vg_SWT applied to the gate node through the corresponding gate line GL, the data voltage Vdata supplied from the data line DL ) is applied to the gate node (N2 node) of the driving transistor DT to turn on the driving transistor DT.

Referring to FIG. 2 , the storage capacitor Cstg is disposed between the gate node (N2 node) of the driving transistor DT and the first electrode of the organic light emitting diode (OLED) (ie, the N1 node of the driving transistor DT). electrically connected.

The storage capacitor Cstg serves to maintain a constant voltage during one frame.

As shown in FIG. 2 , if the 3T1C sub-pixel structure including three transistors DT, SENT, and SWT and one capacitor Cstg is used, the gate is made using the sub-pixel structure as it is without a separate monitoring device. It is possible to monitor whether there is an abnormality in the voltage.

Referring to FIG. 2 , the gate node of the sensor transistor SENT and the gate node of the switching transistor SWT may be individually applied with gate voltages from different gate lines.

In this case, the gate line GL′ electrically connected to the gate node of the sensor transistor SENT and the gate line GL electrically connected to the gate node of the switching transistor SWT may be different from each other.

Accordingly, the gate voltage Vg_SENT applied to the gate node of the sensor transistor SENT and the gate voltage Vg_SWT applied to the gate node of the switching transistor SWT are different scan signals (Vg_SENT≠Vg_SWT).

As described above, by allowing the gate node of the sensor transistor SENT and the gate node of the switching transistor SWT to receive gate voltages from different gate lines separately, the sensor transistor SENT and the switching transistor SWT are independent of each other. can be individually and individually controlled, so that more efficient driving of sub-pixels can be made possible.

Meanwhile, different from this, the gate node of the sensor transistor SENT and the gate node of the switching transistor SWT may receive a gate voltage from one gate line.

In this case, the gate line GL' electrically connected to the gate node of the sensor transistor SENT and the gate line GL electrically connected to the gate node of the switching transistor SWT are the same gate line.

Accordingly, the gate voltage Vg_SENT applied to the gate node of the sensor transistor SENT and the gate voltage Vg_SWT applied to the gate node of the switching transistor SWT are the same scan signal (Vg_SENT=Vg_SWT).

As described above, the gate node of the sensor transistor SENT and the gate node of the switching transistor SWT receive a gate voltage from one gate line, so that on the organic light emitting display panel 110, each sub-pixel Since only one gate line may be formed, there is an advantage in that the aperture ratio can be increased.

The 3T1C sub-pixel structure shown in FIG. 2 may be a sub-pixel structure for realizing a function of sensing and compensating a unique characteristic value (eg, a threshold voltage, mobility, etc.) of the driving transistor DT. This will be described in more detail with reference to FIGS. 10 and 11 .

3 is an exemplary diagram of a gate voltage state monitoring configuration of the organic light emitting diode display 100 according to the present exemplary embodiment.

Referring to FIG. 3 , the organic light emitting diode display 100 according to the present exemplary embodiment monitors the state of the gate voltages Vg_SENT and Vg_SWT applied to each sub-pixel, and the gate voltage actually applied to the sub-pixels. It includes a sensing unit 310 that senses , and a power failure checking unit 320 that checks whether there is an abnormality in the gate voltage actually applied to the sub-pixel using the sensing result of the sensing unit 310 .

The sub-pixel structure (the 3T1C sub-pixel structure illustrated in FIG. 2 ) that allows the sensing unit 310 to sense the gate voltage actually applied to the sub-pixels may also be viewed as a gate voltage state monitoring configuration.

In addition, referring to FIG. 3 , as a gate voltage state monitoring configuration, the memory 330 may further include a memory 330 that stores the result (eg, whether there is an abnormality in the gate voltage, etc.) .

The memory 330 may be included in the power failure checking unit 320 .

Meanwhile, the above-described sensing unit 310 may be implemented as, for example, an analog-to-digital converter (ADC).

The analog-to-digital converter (ADC) may be included in the source driver integrated circuit (SDIC).

The above-described power failure checking unit 320 may be included in the timing controller 140 or the power controller 150 , for example.

Hereinafter, it is assumed that the sensing unit 310 is implemented as an analog-to-digital converter (ADC) and the power failure checking unit 320 is included in the timing controller 140 , and a method of monitoring the gate voltage state will be described.

4 is another exemplary diagram of a gate voltage state monitoring configuration of the organic light emitting diode display 100 according to the present exemplary embodiment.

Referring to FIG. 4 , when the sensing unit 310 is implemented as an analog-to-digital converter (ADC) and the power failure checking unit 320 is included in the timing controller 140 , the analog-to-digital converter (ADC) is a reference voltage It is electrically connected to the line RVL.

Referring to FIG. 4 , the reference voltage VREF is applied to the N1 node of the driving transistor DT through one reference voltage line RVL, the N1 node or the reference node RN is floated, or an analog Switch ( SW) may be further included.

Referring to FIG. 4 , the switch SW connects the node 430 connected to the reference voltage line RVL to the node 410 to which the reference voltage VREF is supplied, according to control information such as light emission timing and sensing timing. It connects to one of the nodes 420 connected to an analog-to-digital converter (ADC).

According to the switching operation of the switch SW, by controlling the voltage application state of the N1 node or the reference node RN, and controlling the connection position of the reference voltage line RVL, the organic light emitting diode display 100 is a general A driving operation of the sub-pixel (a driving operation for light emission), a sensing operation for the intrinsic characteristic values (threshold voltage, mobility) of the driving transistor DT in the sub-pixel, and the intrinsic characteristic value (threshold voltage) of the sensor transistor SENT in the sub-pixel , mobility) sensing operation, gate voltage state monitoring operation, etc. can be normally performed.

Meanwhile, referring to FIG. 4 , in order to monitor the gate voltage state, in the analog-to-digital converter ADC, a gate voltage Vg_SENT is applied to the gate node of the sensor transistor SENT, and the sensor transistor SENT and the reference voltage line In a state in which the reference node RN to which RVL is electrically connected is floating, the voltage of the reference node RN is sensed, and sensed data obtained by converting the sensed voltage into a digital value is output. The sensed data output from the analog-to-digital converter (ADC) is transmitted to the timing controller 140 .

Here, when the analog-to-digital converter ADC senses the voltage of the reference node RN, the gate voltage Vg_SENT applied to the gate node of the sensor transistor SENT turns on the sensor transistor SENT. As a voltage that can be turned on), it may be a high-level gate voltage (VGH).

As described above, in the analog-to-digital converter (ADC), the gate voltage (Vg_SENT) is applied to the gate node of the sensor transistor (SENT), and the sensor transistor (SENT) and the reference voltage line (RVL) are electrically connected to the reference node ( RN) is floating, the voltage of the reference node RN is sensed. At this time, the sensed voltage includes a component of the gate voltage Vg_SENT actually applied to the gate node of the sensor transistor SENT. , the gate voltage Vg_SENT may be monitored.

In other words, after controlling the voltage application state on the circuit in the subpixel so that the voltage of the reference node RN on the circuit in the subpixel includes the gate voltage component, the voltage of the reference node RN is sensed, and the By indirectly finding out by calculating the actually applied gate voltage, it is possible to check whether there is an abnormality in the gate voltage.

This indirect and calculation-based method of checking whether there is an abnormality in the gate voltage can reduce the number of parts required, and can reduce the number of necessary parts compared to the method in which a separate voltage measuring device is installed to directly measure the gate voltage to check whether the gate voltage is abnormal. can be checked easily.

Referring to FIG. 4 , the timing controller 140 receives sensing data output from an electrically connected analog-to-digital converter (ADC), and based on the received sensing data, a gate applied to the gate node of the sensor transistor SENT. It is possible to check whether there is an abnormality in the voltage Vg_SENT and store the check result in the memory 330 .

Here, the check result may include information on whether or not there is an abnormality in the gate voltage Vg_SENT.

As described above, the timing controller 140 checks whether there is an abnormality in the gate voltage Vg_SENT applied to the gate node of the sensor transistor SENT based on the sensed data received from the analog-to-digital converter ADC, and confirms that By storing the result in the memory 330 , a situation in which an abnormal gate voltage is applied can be easily and conveniently monitored, and an effective response to such an abnormal gate voltage application situation can be made possible.

On the other hand, the timing controller 140 applies the gate voltage to the gate node of the sensor transistor SENT, the voltage value information of the sensed gate voltage Vg_SENT, along with the confirmation result including the information on whether the gate voltage is abnormal. At least one of identification information of the gate driver integrated circuit, identification information of a corresponding gate line, and bonding position information of the corresponding gate driver integrated circuit may be further stored.

As described above, as a result of monitoring the gate voltage state, in addition to the gate voltage abnormality information, voltage value information of the sensed gate voltage (Vg_SENT), identification information of the corresponding sub-pixel, identification information of the corresponding gate driver integrated circuit, and the corresponding gate driver By further storing one or more of the bonding position information of the integrated circuit and identification information of the corresponding gate line, it is possible to accurately diagnose the cause and location of the abnormal gate voltage application situation and take appropriate countermeasures later.

On the other hand, if the method of checking whether the gate voltage is abnormal is described in detail, the timing controller 140, based on the sensed data received from the analog-to-digital converter (ADC) and the known threshold voltage data, the sensor transistor (SENT) By calculating the gate voltage applied to the gate node of , and comparing the calculated gate voltage with a previously known reference gate voltage, it is possible to check whether the calculated gate voltage is abnormal.

In the analog-to-digital converter ADC, the sensed voltage of the reference node RN is the threshold voltage Vth_SENT of the sensor transistor SENT from the gate voltage (Vg_SENT=VGH) actually applied to the gate node of the sensor transistor SENT. It is the subtracted value (VGH-Vth_SENT).

The timing controller 140 detects the voltage VGH-Vth_SENT sensed by the analog-to-digital converter ADC from the received sensing data at the reference node RN, the detected voltage VGH-Vth_SENT, and a previously known threshold. A gate voltage (Vg_SENT=VGH) actually applied to the gate node of the sensor transistor SENT may be calculated by adding the threshold voltage Vth_SENT in the voltage data.

As described above, after controlling the voltage application state on the circuit in the subpixel so that the voltage of the reference node RN on the circuit in the subpixel includes the gate voltage component, the voltage of the reference node RN is sensed, and the sensed By calculating and indirectly finding out the actually applied gate voltage from the voltage, it is possible to check whether there is an abnormality in the gate voltage.

This indirect and calculation-based method of checking whether there is an abnormality in the gate voltage can reduce the number of parts required, and can reduce the number of necessary parts compared to the method in which a separate voltage measuring device is installed to directly measure the gate voltage to check whether the gate voltage is abnormal. can be checked easily.

Meanwhile, in order for the timing controller 140 to calculate the gate voltage (Vg_SENT=VGH) actually applied to the gate node of the sensor transistor SENT, the threshold voltage data used together with the sensing data received from the analog-to-digital converter ADC is , may be data on the threshold voltage Vth_SENT of the sensor transistor SENT.

As described above, since the voltage sensed by the analog-to-digital converter (ADC) of the reference node RN is “VGH-Vth_SENT”, the threshold voltage data is data on the threshold voltage Vth_SENT of the sensor transistor SENT. The correct gate voltage (Vg_SENT=VGH) can be calculated.

However, for this purpose, there is a disadvantage that a separate procedure for sensing the threshold voltage Vth_SENT of the sensor transistor SENT is required.

Therefore, in order to compensate for the luminance deviation between sub-pixels, the known threshold voltage Vth_DT of the driving transistor DT is changed to the threshold voltage Vth_SENT of the sensor transistor SENT, and the threshold voltage Vth_SENT of the sensor transistor SENT is used. may be used instead.

This is because the threshold voltage Vth_DT of the driving transistor DT and the threshold voltage Vth_SENT of the sensor transistor SENT have very similar characteristics (eg, distribution characteristics, deviation characteristics, movement characteristics, etc.).

Therefore, even if the gate voltage Vg_SENT=VGH is calculated using the threshold voltage Vth_DT of the driving transistor DT instead of the threshold voltage Vth_SENT of the sensor transistor SENT, there is no significant difference in accuracy. .

That is, in order for the timing controller 140 to calculate the gate voltage (Vg_SENT=VGH) actually applied to the gate node of the sensor transistor SENT, the threshold voltage data used together with the sensing data received from the analog-to-digital converter ADC is , may be data on the threshold voltage Vth_DT of the driving transistor DT.

As described above, when the gate voltage Vg_SENT=VGH is calculated using the known threshold voltage Vth_DT of the driving transistor DT instead of the threshold voltage Vth_SENT of the sensor transistor SENT, the sensor The gate voltage Vg_SENT=VGH can be accurately calculated without a separate procedure for sensing the threshold voltage Vth_SENT of the transistor SENT.

Hereinafter, the gate voltage state monitoring method briefly described above will be described in more detail with reference to FIGS. 5 to 9 .

5 to 9 are diagrams for explaining a method of monitoring a gate voltage state of the organic light emitting diode display 100 according to the present exemplary embodiment.

The gate voltage state monitoring method of the organic light emitting diode display 100 according to the present exemplary embodiment includes four steps STEP 0, STEP 1, STEP 2, and STEP 3 .

5 to 8 show the voltage application state and the transistor on-off state in each of the four steps (STEP 0, STEP 1, STEP 2, STEP 3). 9 is a graph illustrating a voltage change of a reference node RN corresponding to a sensing node in STEP 1, STEP 2, and STEP 3;

Referring to FIG. 5 , in STEP 0, under the control of the timing controller 140 , the gate driver 130 has a low-level gate voltage (Vg_SENT=VGL, for example: -6V) at the gate node of the sensor transistor SENT. is applied and a low-level gate voltage (Vg_SWT=VGL, for example, -6V) is applied to the gate node of the switching transistor SWT to turn off both the sensor transistor SENT and the switching transistor SWT. .

Referring to FIG. 6 , in STEP 1 , under the control of the timing controller 140 , the gate driver 130 applies a high-level gate voltage (Vg_SENT=VGH, eg, 6V) to the gate node of the sensor transistor SENT. is applied to turn on the sensor transistor SENT.

Further, in STEP 1, under the control of the timing controller 140, the gate driver 130 applies a high-level gate voltage (Vg_SWT=VGL, eg, 24V) to the gate node of the switching transistor SWT to perform switching. Turn on the transistor (SWT).

Also, in STEP 1 , under the control of the timing controller 140 , the power controller 150 electrically connects the sensor transistor SENT and the reference voltage line RVL through the source driver integrated circuit of the data driver 120 . A reference voltage VREF, eg, 0V, is applied to the connected reference node RN.

Accordingly, as shown in FIG. 9 , in STEP 1, the voltage of the reference node RN is the reference voltage VREF.

To this end, the switch SW is in a switching state that connects the reference voltage line RVL to the reference voltage supply node 410 as shown in FIG. 6 .

Also, in STEP 1 , under the control of the timing controller 140 , the data driver 120 outputs a data voltage Vdata (eg, 16V) to the data line DL.

As described above, the reference voltage VREF (eg, 0V) is applied to the N1 node of the driving transistor DT, and the data voltage (Vdata, eg, 16V) is applied to the N2 node of the driving transistor DT, and driving A driving voltage EVDD (eg, 12V) is applied to the N3 node of the transistor DT.

In this case, the data voltage Vdata applied to the N2 node that is the gate node of the driving transistor DT may be higher than the driving voltage EVDD applied to the N3 node of the driving transistor DT. According to this voltage magnitude relationship, sensing the voltage including the threshold voltage Vth_SENT of the sensor transistor SENT is sensing the voltage including the threshold voltage Vth_DT of the driving transistor DT for monitoring the gate voltage state. That's the part that makes the difference.

Referring to FIG. 7 , in STEP 2 , according to the switch control signal of the timing controller 140 , the switching state of the switch SW is changed so that the reference voltage line RVL is separated from the reference voltage supply node 410 . do.

According to the switching operation of the switch SW, the reference node RN floats, and the voltage of the reference node RN rises from the reference voltage VREF, for example, 0V.

Accordingly, as shown in FIG. 9 , in STEP 2, the voltage of the reference node RN gradually increases from the reference voltage VREF.

Meanwhile, referring to FIG. 7 , in STEP 2 , the gate node voltage (N2 voltage) of the driving transistor DT is the difference value (EVDD−) between the driving voltage EVDD and the threshold voltage Vth_DT of the driving transistor DT. Vth_DT) is a higher voltage.

Also, since the data voltage Vdata is higher than the driving voltage EVDD, the N1 node of the driving transistor DT does not float, and the driving voltage EVDD corresponding to the constant voltage is applied. Instead, the reference node RN is floated.

As described above, referring to FIG. 9 , the reference node RN is floated, gradually rises from the reference voltage VREF, and becomes saturated when it reaches a certain level.

Referring to FIG. 9 , the reference node RN is lower than the gate voltage Vg_SENT=VGH applied to the gate node of the sensor transistor SENT by the threshold voltage Vth_SENT of the sensor transistor SENT. Stop the voltage rise.

That is, the saturated voltage of the reference node RN is "VGH-Vth_SENT".

In this way, after the voltage of the reference node RN is saturated and the voltage rise is stopped, STEP 3 may proceed.

Referring to FIG. 8 , in STEP 3, the switch SW connects the reference voltage line RVL to the analog-to-digital converter ADC.

Accordingly, the analog-to-digital converter ADC senses the voltage of the reference node RN.

In this case, the sensed voltage is a voltage (VGH-Vth_SENT) in a state in which voltage saturation occurs at the reference node RN, as shown in FIG. 9 .

As described above, after going through STEP 0 to STEP 4, the analog-to-digital converter (ADC) converts the sensed voltage (VGH-Vth_SENT) to a digital value, and the sensed data including the converted digital value(s). output to the timing controller 140 .

When the above-described driving method of the organic light emitting display device 100 is used, the voltage application state on the circuit in the sub-pixel is controlled so that the voltage of the reference node RN on the circuit in the sub-pixel is included as a gate voltage component, so that the reference node ( Since the gate voltage is checked by sensing the voltage of RN), there is no need to check whether there is an abnormality by measuring the gate voltage with a separate voltage measuring device, thereby reducing the number of parts required and the gate voltage You can easily check whether there is an abnormality.

As described above, as shown in FIGS. 7 and 8 , in a state in which the reference node RN is floating, the sensor transistor SENT and the first electrode of the organic light emitting diode OLED are electrically connected to the node N1 node), the driving voltage EVDD supplied through the driving voltage line DVL is applied.

Also, while the reference node RN is floating, the data voltage applied to the gate node of the driving transistor DT is higher than the driving voltage EVDD.

In other words, referring to FIGS. 7 and 8 , in STEPs 2 and 3, the gate node voltage (N2 voltage) of the driving transistor DT, that is, the data voltage Vdata, eg, 16V, is the driving voltage EVDD, Example: voltage higher than 12V).

As such, in the gate voltage state monitoring mode section, since the data voltage Vdata is used as a voltage higher than the driving voltage EVDD, the N1 node of the driving transistor DT is not floated and the driving voltage corresponding to the constant voltage ( EVDD) is applied, and instead, the reference node RN is floated. Accordingly, the gate voltage state may be monitored by sensing the reference node RN.

Due to this, the voltage of the reference node RN corresponding to the source node (or drain node) of the sensor transistor SENT follows the gate voltage applied to the gate node of the sensor transistor SENT, so that the voltage saturation is When generated, at this time, the voltage of the reference node RN is sensed, and the gate voltage applied to the gate node of the sensor transistor SENT can be monitored based on the sensed voltage.

Meanwhile, in each sub-pixel, the driving transistor DT for driving the organic light emitting diode OLED has a threshold voltage Vth_DT that affects the switching operation. The threshold voltage Vth_DT is a unique characteristic value of the driving transistor DT, and there may be a deviation for each driving transistor DT.

Also, as the driving time of the driving transistor DT increases, deterioration of the driving transistor DT may proceed, and thus the threshold voltage Vth_DT may change.

For this reason, the deviation of the threshold voltage Vth_DT between the driving transistors DT in each sub-pixel may increase.

The deviation of the threshold voltage Vth_DT between the driving transistors DT may cause a luminance deviation between sub-pixels, which may be a major factor in degrading image quality.

Accordingly, the organic light emitting diode display 100 according to the present exemplary embodiments senses the threshold voltage Vth_DT of the driving transistor DT, and a compensation function (sub-pixel) for compensating for a threshold voltage deviation between the driving transistors DT. A compensation function or a luminance deviation compensation function or a threshold voltage compensation function or a data compensation function) may be provided.

Hereinafter, a method of sensing the threshold voltage Vth_DT of the driving transistor DT in each sub-pixel and compensating for a threshold voltage deviation will be briefly described with reference to FIGS. 10 and 11 .

10 to 12 are diagrams for explaining a method of sensing the threshold voltage of the driving transistor DT of the organic light emitting diode display 100 according to the present exemplary embodiment.

The method of sensing the threshold voltage Vth_DT of the driving transistor DT in each subpixel includes an initialization step STEP A, a voltage rising step STEP B, and a sensing step STEP C.

10 is a diagram illustrating an initialization step, and FIG. 11 is a diagram illustrating a voltage rising step and a sensing step. 12 is a graph illustrating a voltage change at the N1 node of the driving transistor DT corresponding to the sensing node.

Referring to FIG. 10 , in the initialization step STEP A, the switching transistor SWT is turned on by the gate voltage Vg_SWT applied from the corresponding gate line GL to the gate node.

Accordingly, the data voltage Vdata supplied from the data line DL is applied to the N2 node corresponding to the gate node of the driving transistor DT through the turned-on switching transistor SWT.

Also, in the initialization step STEP A, the switch SW connects the reference voltage supply node 430 and the connection point 430 of the reference voltage line RVL. In addition, the sensor transistor SENT is turned on by the gate voltage Vg_SENT applied from the corresponding gate line GL′ to the gate node.

Accordingly, the reference voltage VREF supplied through the reference voltage supply node 430 is applied to the N1 node of the driving transistor DT through the turned-on sensor transistor SENT through the reference voltage line RVL.

Referring to FIG. 10 , in the initialization step STEP A, the N2 node of the driving transistor DT is initialized to the data voltage Vdata, and as shown in FIG. 11 , the N1 node of the driving transistor DT is the reference It is initialized to voltage VREF.

Meanwhile, in the mode of sensing the threshold voltage Vth_DT of the driving transistor DT, the driving voltage EVDD applied to the N3 node of the driving transistor DT is the data voltage applied to the N1 node of the driving transistor DT. It is a voltage higher than (Vdata) (EVDD>Vdata). This is the opposite of the voltage magnitude relationship (EVDD<Vdata) in the gate voltage condition monitoring mode.

Referring to FIG. 11 , in the voltage rising step STEP B that is performed after the initialization step STEP A, the switch SW releases the connection between the reference voltage line RVL and the reference voltage supply node 430 .

Accordingly, in the voltage rising step STEP B, the N1 node of the driving transistor DT is floated. That is, the reference voltage VREF corresponding to the constant voltage applied to the N1 node of the driving transistor DT disappears.

In the voltage increasing step STEP B, as shown in FIG. 12 , the voltage boosting of the N1 node of the driving transistor DT is caused by the floating of the N1 node of the driving transistor DT.

Referring to FIG. 12 , the voltage of the N1 node of the driving transistor DT rises to a voltage Vdata-Vth_DT that is lower than the data voltage Vdata by the threshold voltage Vth_DT of the driving transistor DT to be saturated.

From this point, the sensing step (STEP C) may proceed.

11 and 12 , after the voltage of the N1 node of the driving transistor DT is saturated with “Vdata-Vth_DT”, the switch SW connects the reference voltage line RVL with the analog-to-digital converter ADC it connects

11 and 12 , the analog-to-digital converter (ADC) senses the saturated voltage (Vdata-Vth_DT) of the N1 node of the driving transistor DT, converts the sensed voltage into a digital value, and converts the converted Sensing data including digital value(s) is generated and transmitted to the timing controller 140 .

Referring to FIG. 11 , the timing controller 140 may determine the threshold voltage Vth_DT of the driving transistor DT in each subpixel from the received sensing data.

The timing controller 140 calculates a data compensation amount for compensating for a threshold voltage deviation between the driving transistors DT in each sub-pixel based on the found threshold voltage Vth_DT, and stores the calculated data compensation amount in the memory 330 . ) is stored in

Thereafter, when data to be supplied to the corresponding sub-pixel is generated, the timing controller 140 changes the data based on the stored data compensation amount and supplies the data to the data driver 120 .

According to the present embodiments as described above, before the abnormal gate voltage is applied to the sub-pixel and serious circuit damage or panel burnt occurs, the situation in which the abnormal gate voltage is supplied to the sub-pixel is monitored in advance. It can help you prepare ahead of time.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine the configuration within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: organic light emitting display device
110: organic light emitting display panel
120: data driving unit
130: gate driver
140: timing controller

Claims (12)

an organic light emitting display panel in which data lines and gate lines are arranged, and subpixels are arranged in a matrix type;
a data driver for driving data lines;
a gate driver driving the gate lines; and
a timing controller controlling the data driver and the gate driver;
Each sub-pixel is
The organic light emitting diode, the driving transistor controlled by the data voltage applied to the gate node and electrically connected between the first electrode of the organic light emitting diode and a driving voltage line supplying the driving voltage, and the gate voltage applied to the gate node and a sensor transistor controlled by and electrically connected between the first electrode of the organic light emitting diode and a reference voltage line,
Further comprising an analog-to-digital converter electrically connected to the reference voltage line,
The analog-to-digital converter is
The data voltage greater than the driving voltage is applied to a gate node of the driving transistor, a turn-on gate voltage is applied to a gate node of the sensor transistor, and the sensor transistor and the reference voltage line are electrically connected An organic light emitting diode display comprising: sensing the voltage of the reference node in a state in which the reference node is floating; and outputting sensing data obtained by converting the sensed voltage into a digital value. According to claim 1,
The timing controller is
Organic, characterized in that it is electrically connected to the analog-to-digital converter, and checks whether there is an abnormality in the gate voltage applied to the gate node of the sensor transistor based on the sensed data output from the analog-to-digital converter, and stores the confirmation result. light emitting display device. 3. The method of claim 2,
The timing controller is
Further storing one or more of the voltage value of the sensed voltage, identification information of the corresponding gate driver integrated circuit, identification information of the corresponding gate line, and bonding position information of the corresponding gate driver integrated circuit together with the check result, organic light emitting display device. 3. The method of claim 2,
The timing controller is
calculating a gate voltage applied to a gate node of the sensor transistor based on the threshold voltage data and the sensing data,
and comparing the calculated gate voltage with a previously known reference gate voltage to check whether the checked gate voltage is abnormal. 5. The method of claim 4,
The threshold voltage data is
The organic light emitting display device, characterized in that the data on the threshold voltage of the sensor transistor or the data on the threshold voltage of the driving transistor. According to claim 1,
In a state in which the reference node is floating, a constant voltage is applied to a node electrically connected to the sensor transistor and the first electrode of the organic light emitting diode, and the constant voltage is a driving voltage supplied through the driving voltage line. . According to claim 1,
In a state in which the reference node is floating, the voltage of the reference node gradually rises from the reference voltage applied through the reference voltage line and then becomes saturated,
The saturated voltage of the reference node is a voltage as low as a threshold voltage of the sensor transistor at a turn-on level gate voltage applied to the gate node of the sensor transistor,
The analog-to-digital converter senses the saturated voltage of the reference node. According to claim 1,
Each sub-pixel is
a switching transistor controlled by a gate voltage applied to the gate node and electrically connected between the gate node of the driving transistor and a data line;
and a storage capacitor electrically connected between the gate node of the driving transistor and the first electrode of the organic light emitting diode. 9. The method of claim 8,
The gate node of the sensor transistor and the gate node of the switching transistor are respectively applied with gate voltages from different gate lines. 9. The method of claim 8,
The organic light emitting diode display device of claim 1, wherein the gate node of the sensor transistor and the gate node of the switching transistor receive a gate voltage from one gate line. According to claim 1,
and a switch connecting the reference voltage supply node or the analog-to-digital converter to the reference voltage line. An organic light emitting diode, a driving transistor controlled by a data voltage applied to a gate node and electrically connected between a first electrode of the organic light emitting diode and a driving voltage line supplying a driving voltage, and a first electrode of the organic light emitting diode A method of driving an organic light emitting display device in which sub-pixels including a sensor transistor electrically connected between and a reference voltage line are arranged in a matrix type, the method comprising:
The data voltage greater than the driving voltage is applied to the gate node of the driving transistor, a turn-on gate voltage is applied to the gate node of the sensor transistor, and the sensor transistor and the reference voltage line are electrically connected applying a reference voltage to the reference node;
increasing the voltage of the reference node by floating the reference node while the data voltage greater than the level of the driving voltage is applied to the gate node of the driving transistor;
sensing the voltage of the reference node; and
and outputting sensed data obtained by converting the sensed voltage into a digital value.

Images