KR20210085055A - Display device - Google Patents

Abstract

The present invention relates to a display device capable of detecting a short-circuit failure in a display device driving circuit in advance and quickly and accurately determining a short-circuit failure location. The display device includes a short-circuit sensing unit disposed on at least one of a flexible circuit board, a source drive IC, and a level shifter. The short-circuit failure sensing unit generates a flag signal in a sensing mode. The short-circuit failure sensing unit includes: a resistor to which a sample voltage is applied; and a comparator which compares a sensing voltage with a preset reference voltage, wherein the sensing voltage is received from one of wiring of the flexible circuit board, an output terminal of the level shifter, and an output terminal of the source drive IC.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device having a short-circuit failure sensing function.

Pixel data of a flat panel display (FPD) input image is written into pixels of a display panel to reproduce the input image on a pixel array.

A flat panel display device includes a display panel driving circuit for writing pixel data of an input image to pixels, a timing controller for controlling the display panel driving circuit, and the like. The display panel driving circuit includes a display panel driving circuit such as a data driving circuit for supplying a pixel data signal to data lines and a gate driving circuit for supplying a gate signal (or a scan signal) to the gate lines (or scan lines). include The data driving circuit may be implemented as an integrated circuit (IC).

A signal necessary for driving the display panel is supplied to the display panel driving circuit. Power wirings may be short circuited by conductive foreign substances or moisture on the signal transmission path. In this case, the display panel driving circuit and the pixels cannot be normally driven. A method for detecting defects in power wirings in a test process before shipment is known.

There is no way to detect a failure in the progress of power wiring that occurs after product shipment. After the product is shipped, power may be input to the display device without a circuit defect inspection step. A portion of the circuit components in which the short circuit is defective may be physically damaged when power is applied to the display device, and in severe cases, the circuit portion may be destroyed.

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned needs and/or problems.

The present invention provides a display device capable of detecting a short circuit failure in a display device driving circuit in advance and quickly and accurately determining a short circuit failure location.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device of the present invention includes: a display panel in which a plurality of data lines and a plurality of gate lines intersect and a pixel array is disposed; a gate driver disposed on the display panel to supply a gate signal to the gate lines using a shift register; a level shifter shifting the voltage level of the input signal and supplying it to the gate driver; a printed circuit board on which the level shifter is disposed; a source drive IC for supplying a data signal to the data lines in a display mode; and a flexible circuit board on which the source drive IC is disposed and connected between the display panel and the printed circuit board.

At least one of the flexible circuit board, the source drive IC, and the level shifter includes a short-circuit failure sensing unit generating a flag signal in a sensing mode.

The short-circuit failure sensing unit may include a resistor to which a sample voltage is applied; and a comparator for comparing the sensed voltage received from any one of the wiring of the flexible circuit board, the output terminal of the level shifter, and the output terminal of the source drive IC with a preset reference voltage.

According to the present invention, a short circuit failure of the display panel driving circuit may be sensed using a short circuit failure sensing unit disposed on at least one of the source drive IC, the flexible circuit board on which the source drive IC is disposed, and the level shifter.

According to the present invention, when a short circuit fault is sensed in the display panel driving circuit, the display panel driving circuit is disabled to prevent damage to the display panel driving circuit, thereby extending the lifespan of the display device. The present invention may transmit a warning message to the outside when a short circuit failure is sensed in the display panel driving circuit.

Effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included as a part of the detailed description to facilitate the understanding of the present invention, provide embodiments of the present invention, and together with the detailed description, explain the technical features of the present invention.
1 is a block diagram illustrating a display device according to an embodiment of the present invention.
2 is a circuit diagram showing switch elements of a demultiplexer array.
3 is a diagram illustrating an example of a pixel circuit in a liquid crystal display device.
4 is a diagram illustrating an example of a pixel circuit in an organic light emitting diode display.
FIG. 5 is a waveform diagram showing operations of the demultiplexer and the pixel circuit shown in FIG. 4 .
6 is a diagram schematically showing a shift register of a gate driving circuit.
7 and 8 are views showing wirings between the timing controller and the level shifter.
9 is a flowchart schematically illustrating a failure sensing method according to an embodiment of the present invention.
10 is a diagram illustrating an example of a screen in which a panel signal is blocked after an alarm message displayed on the screen when a short circuit is detected in the display panel driving circuit.
11 is a diagram illustrating an example in which an alarm message is transmitted to the outside through a network when a short circuit is detected in the display panel driving circuit.
12 is a circuit diagram illustrating a short-circuit failure sensing unit according to a first embodiment of the present invention.
13 is an equivalent circuit diagram showing a short circuit between the COF and the short circuit amount sensing unit when the wires and pads of the COF are shorted.
14A and 14B are circuit diagrams illustrating a short-circuit failure sensing unit according to a second embodiment of the present invention.
15A to 15C are circuit diagrams illustrating a short-circuit failure sensing unit embedded in a source drive IC and an operation mode of the source drive IC.
16A to 16C are circuit diagrams illustrating a short-circuit failure sensing unit embedded in the level shifter and an operation mode of the level shifter.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only the embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains It is provided to fully understand the scope of the invention, and the present invention is only defined by the scope of the claims.

Since the shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In the present invention, when "comprising", "including", "having", "consisting", etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be construed as the plural unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship between two components is described as 'on', 'on', 'on', 'beside', ' One or more other elements may be interposed between those elements in which 'directly' or 'directly' are not used.

1st, 2nd, etc. may be used to distinguish the components, but the functions or structures of these components are not limited to the ordinal number or component name attached to the front of the component. Since the claims are described based on essential elements, the ordinal numbers placed before the component names in the claims may not match the ordinal numbers placed before the component names of the embodiments.

The following embodiments can be partially or wholly combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

In the display device of the present invention, a display panel driving circuit, a pixel array, a level shifter, etc. may include transistors. The transistors may be implemented as an oxide TFT (Thin Film Transistor) including an oxide semiconductor, an LTPS TFT including a Low Temperature Poly Silicon (LTPS), or the like. Each of the transistors may be implemented as a transistor having a p-channel metal-oxide-semiconductor field effect transistor (MOSFET) or an n-channel MOSFET structure.

A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the transistor. In a transistor, the flow of carriers flows from source to drain. In the case of the n-channel transistor, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-channel transistor, the direction of current flows from drain to source. In the case of a p-channel transistor (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may be changed according to an applied voltage. Accordingly, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

The gate signal swings between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while turned-off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of the p-channel transistor, the gate-on voltage may be a gate low voltage VGL, and the gate-off voltage may be a gate high voltage VGH.

The present invention can be applied to any flat panel display such as a liquid crystal display (LCD) and an organic light emitting display (OLED display).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1 , a display device 1000 according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The screen of the display panel 100 includes a pixel array AA that displays pixel data of an input image. Pixel data of the input image is displayed on the pixels of the pixel array AA. The pixel array AA includes a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, and pixels arranged in a matrix form. In addition to the matrix form, the arrangement of pixels may be formed in various ways, such as a form in which pixels emitting the same color are shared, a stripe form, a diamond form, and the like.

When the resolution of the pixel array AA is n*m, the pixel array AA includes n pixel columns and m pixel lines L1 to Lm intersecting the pixel columns. The pixel column includes pixels arranged along the y-axis direction. The pixel line includes pixels arranged along the x-axis direction. One horizontal period 1H is a time obtained by dividing one frame period by the number of m pixel lines L1 to Lm. Pixel data is written to the pixels of one pixel line in one horizontal period (1H).

Each of the pixels may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels 101 includes a pixel circuit. The pixel circuit includes a pixel electrode, a plurality of thin film transistors (TFTs), and a capacitor. The pixel circuit is connected to the data line DL and the gate line GL.

Touch sensors are disposed on the screen of the display panel 100 to realize a touch screen. The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as in-cell type touch sensors arranged on the screen of a display panel or embedded in a pixel array as an on-cell type or an add-on type. can

The display panel driving circuit includes a data driver 110 , a gate driver 120 , and a timing controller 130 for controlling operation timings of the driving circuits 110 and 120 . The display panel driving circuit writes input image data to pixels of the display panel 100 under the control of the timing controller 130 in the display mode. The display panel driving circuit may sense the short circuit failure in the sensing mode by using the short circuit failure sensing unit ERC.

The data driver 110 converts pixel data of an input image received as a digital signal from the timing controller 130 every frame in the display mode to analog gamma using a digital-to-analog converter (hereinafter referred to as "DAC"). It is converted into a compensation voltage to output data signals Vdata1-3. The data signals Vdata1 to 3 are supplied to the data lines DL.

The data driver 110 may be integrated in the source drive IC (SIC) illustrated in FIGS. 7 and 8 . The source drive IC (SIC) may be mounted on a flexible circuit board, for example, a chip on film (COF). A touch sensor driver for driving the touch sensors may be embedded in each of the source drive ICs (SIC).

The gate driver 120 may be formed in the bezel region BZ in which an image is not displayed on the display panel 100 in the display mode. The gate driver 120 receives the gate timing control signal received from the level shifter 140 , generates gate signals GATE1 to 3 synchronized with the data signals Vdata1 to 3 , and supplies it to the gate lines GL. do. The gate signals GATE1 to 3 applied to the gate lines GL turn on the switch elements of the sub-pixels 101 so that the voltage of the data signals Vdata1 to 3 is charged. select The gate signals GATE1 to GATE3 may be generated as pulse signals swinging between the gate high voltage VGH and the gate low voltage VGL. The gate driver 120 shifts the gate signal using a shift register.

The timing controller 130 multiplies the input frame frequency by i to control the operation timing of the display panel drivers 110 and 120 with a frame frequency of the input frame frequency×i (i is a positive integer greater than 0) Hz. . The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme.

The timing controller 130 receives pixel data of an input image and a timing signal synchronized therewith from the host system 200 in the display mode. Pixel data of an input image received by the timing controller 130 is a digital signal. The timing controller 130 transmits pixel data to the data driver 110 . The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period (1H).

The display panel driving circuit may further include a demultiplexer array 112 disposed between the data driver 110 and the gate driver 120 .

The demultiplexer array 112 sequentially connects one channel of the data driver 110 to a plurality of data lines DL to time-divide a data voltage output from one channel of the data driver 110 to the data lines DL. By distributing the data, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 includes a plurality of switch elements as shown in FIG. 2 .

The timing controller 130 includes a data timing control signal for controlling the data driver 110 and a gate timing control signal for controlling the gate driver 120 based on the timing signal received from the host system 200 in the display mode. , a MUX control signal for controlling the switch elements of the demultiplexer array 112 , a control signal for sensing a short circuit failure, and the like may be generated.

The gate timing control signal may include a gate start pulse (VST), a shift clock (GCLK), and the like. The start pulse VST controls the start timing of the gate driver 120 in every frame period. The shift clock GCLK controls shift timing of the gate signal output from the gate driver 120 . The timing controller 130 may generate a control signal for controlling the level shifter 140 .

The host system 200 may be any one of a television (Television), a set-top box, a navigation system, a personal computer (PC), a home theater, a mobile system, and a wearable system. In the mobile device and the wearable device, the data driver 110 , the timing controller 130 , the level shifter 140 , etc. may be integrated into one drive IC (not shown).

In the mobile system, the host system 200 may be implemented as an application processor (AP). The host system 200 may transmit pixel data of an input image to the drive IC through a Mobile Industry Processor Interface (MIPI). The host system 200 may be connected to the drive IC through a flexible printed circuit, for example, a flexible printed circuit (FPC) 310 .

The level shifter 140 shifts and outputs the voltage of the input signal received from the timing controller 130 . The input signal of the level shifter 140 may be a transistor-transistor logic (TTL) level signal of a low level (0V) and a high level (3.3V). The level shifter 140 may convert the high level of the input signal into the gate high voltage VGH and the low level of the input signal into the gate low voltage VGL. The input signal of the level shifter 140 may include a gate timing control signal and a MUX control signal. The gate timing control signal whose voltage is shifted by the level shifter 140 is supplied to the gate driver 120 . The MUX control signal whose voltage is shifted by the level shifter 140 is supplied to the demultiplexer 1120 .

The display device 1000 of the present invention further includes a power supply unit 400 .

The power supply unit 400 generates a DC voltage required for driving the pixel array of the display panel 100 and the display panel driving circuit using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, a buck-boost converter, and the like. The power supply unit 400 adjusts the DC input voltage from the host system 200 to obtain a gamma reference voltage (VGMA) and gate high voltages (VGH, VEH). DC voltages such as gate low voltages VGL and VEL, half VDD (HVDD), and a common voltage of pixels may be generated. The gamma reference voltage VGMA is supplied to the data driver 110 . The half VDD voltage is half voltage compared to VDD and can be used as an output buffer driving voltage of the source drive IC. The gamma reference voltage VGMA is divided for each gray level through a voltage dividing circuit and supplied to the DAC of the data driver 110 . Power generated from the power supply unit 400 may be supplied to the display panel 100 through the COF as shown in FIG. 9 .

FIG. 2 is a circuit diagram showing the switch elements M1 and M2 of the demultiplexer array 112 .

Referring to FIG. 2 , in the data driver 110 , the output buffer AMP included in one channel CH1 and CH2 may be connected to the adjacent data lines DL1 to 4 through the demultiplexer array 112 . . The data lines DL1 to 4 may be connected to the pixel electrodes 1011 to 1014 of the sub-pixels through a thin film transistor (TFT).

The demultiplexer array 112 includes a plurality of demultiplexers (Demultiplexer). The demultiplexers 21 and 22 may be 1:N demultiplexers having one input node and N output nodes (N being two or more positive integers). The MUX control signals MUX1 and MUX2 are input to the control nodes of the demultiplexers 21 and 22 and applied to the gates of the switch elements M1 and M2. The MUX control signals MUX1 and MUX2 control on/off timing of the switch elements M1 and M2.

The demultiplexers 21 and 22 are illustrated as 1:2 demultiplexers in FIG. 2 , but are not limited thereto. For example, each of the demultiplexers 21 and 22 may be implemented as a 1:3 demultiplexer so that one channel may be sequentially connected to three data lines in the data driver 110 . The demultiplexer array 112 may be directly formed on the substrate of the display panel 100 , or may be integrated into one drive IC together with the data driver 110 .

The demultiplexer array 112 transmits the data signal Vdata1 output through the first channel CH1 of the data driver 110 to the first and second data lines DL1 and DL1 using the switch elements M1 and M2. The data signal Vdata1 output through the second channel CH2 of the data driver 110 is outputted through the first demultiplexer 21 for time-division distribution to the DL2 and the switch elements M1 and M2 by the third and and a second demultiplexer 22 for time division distribution to the fourth data lines DL3 and DL4.

Each of the switch elements M1 and M2 may be implemented as a transistor. The switch elements M1 and M2 are turned on according to the gate high voltage VGH of the MUX control signals MUX1 and MUX2 applied to the gates through the level shifter 140 to be turned on to the data driver 110 . ) to the data lines DL1 to DL4.

The first switch element M1 is turned on in response to the gate high voltage VGH of the first MUX signal MUX1. In this case, the output buffer AMP of the first channel CH1 is connected to the first data line DL1 through the first switch element M1 . At the same time, the output buffer AMP of the second channel CH2 is connected to the third data line DL3 through the first switch element M1 .

The second switch element M2 is turned on in response to the gate high voltage VGH of the second MUX signal MUX2. In this case, the output buffer AMP of the first channel CH1 is connected to the second data line DL2 through the second switch element M2 . At the same time, the output buffer AMP of the second channel CH2 is connected to the fourth data line DL4 through the second switch element M2 .

3 is a diagram illustrating an example of a pixel circuit in a liquid crystal display device.

Referring to FIG. 3 , each of the sub-pixels includes a pixel electrode 1 , a common electrode 2 , a liquid crystal cell Clc, a TFT connected to the pixel electrode 31 , and a storage capacitor Cst. The TFT is formed at the intersection of the data lines DL1 to 3 and the gate line GL1. The TFT supplies the voltage of the data signal Vdata from the data lines DL1 to 3 to the pixel electrode 31 in response to the gate signal GATE from the gate line GATE.

A data signal, that is, a data voltage of pixel data is applied to the pixel electrode 1 . A common voltage Vcom, which is a reference potential of pixels, is applied to the common electrode 2 .

As in the example of FIG. 4 , the sub-pixels of the organic light emitting diode display generate light according to pixel data of an input image by using an organic light emitting diode (referred to as “OLED”) to display an image. The organic light emitting diode display does not require a backlight unit and may be implemented on a plastic substrate, a thin glass substrate, or a metal substrate, which are flexible materials. Accordingly, the flexible display may be implemented as an organic light emitting display device.

In the flexible display, the size and shape of the screen may be changed by winding, folding, or bending the display panel. The flexible display may be implemented as a rollable display, a bendable display, a foldable display, a slideable display, and the like. The field of application of these flexible displays is expanding.

The flexible display may be implemented as an OLED panel using a flexible substrate such as a plastic panel. A pixel array may be formed on an organic thin film adhered to a back plate of a plastic panel. The back plate may be a polyethylene terephthalate (PET) substrate. An organic thin film is formed on the back plate. A pixel array and a touch sensor array may be formed on the organic thin film. The back plate blocks the moisture permeation towards the organic thin film so that the pixel array is not exposed to humidity. The organic thin film may be a thin PI (Polyimide) film substrate. A multi-layered buffer film may be formed of an insulating material (not shown) on the organic thin film. Wires for supplying power or signals applied to the pixel array and the touch sensor array may be formed on the organic thin film.

Pixels of the organic light emitting display device may include an OLED, a driving device that drives the OLED by controlling a current flowing through the OLED according to a gate-source voltage (Vgs), and a storage capacitor that maintains the gate voltage of the driving device. .

The driving device may be implemented as a transistor. In order to make the image quality of the entire screen of the organic light emitting diode display uniform, the driving element must have uniform electrical characteristics among all pixels. Due to process variation and device characteristic variation caused in the manufacturing process of the display panel, there may be a difference in electrical characteristics of the driving device between pixels, and the difference may increase as the driving time of the pixels elapses. An internal compensation technique and/or an external compensation technique may be applied to the organic light emitting diode display in order to compensate for variations in electrical characteristics of the driving element between pixels.

The external compensation technology senses in real time a current or voltage of a driving device that changes according to electrical characteristics of the driving device using an external compensation circuit. The external compensation technology compensates for the deviation (or change) in the electrical characteristics of the driving element in each pixel in real time by modulating the pixel data (digital data) of the input image as much as the electric characteristic deviation (or change) of the driving element sensed for each pixel.

The internal compensation technology senses the threshold voltage of the driving device for each sub-pixel using an internal compensation circuit built into each pixel, and compensates the gate-source voltage (Vgs) of the driving device by the threshold voltage. The internal compensation circuit includes a storage capacitor Cst connected to the gate of the driving element DT, and one or more switch elements T1 to 5 connecting the storage capacitor Cst, the driving element DT, and the light emitting element EL. includes

The multiplexers 21 and 22 may be applied to both an organic light emitting diode display to which an internal compensation technique or an external compensation technique is applied. 4 illustrates an example in which the multiplexer 21 is disposed in an organic light emitting diode display to which internal compensation technology is applied, but the present invention is not limited thereto.

4 and 5 , the gate signal may include a scan signal and a light emission control signal (hereinafter, referred to as an “EM signal”) in the organic light emitting diode display. In FIG. 4 , GL11 to GL13 are gate lines connected to sub-pixels of one pixel line. In FIG. 5 , D1(N) and D2(N) are data signals Vdata applied to pixels of an Nth pixel line. D1(N+1) and D2(N+1) are data signals Vdata applied to pixels of the N+1th pixel line. X is a section in which there is no data signal Vdata.

The power supply 400 may output pixel power such as a pixel driving voltage ELVDD, a low potential voltage ELVSS, and a reference voltage Vref applied to pixels in the organic light emitting diode display.

One horizontal period 1H may include an initialization period Tini, a data writing period Twr, and a sustain period Th.

The pixels may emit light during the light emission period Tem. The light emission period Tem corresponds to most of the time of one frame period except for one horizontal period 1H in one frame period. A sustain period Th may be added between the data writing period Twr and the light emission period Tem.

In order to accurately express the luminance of a low gray scale, the EM signal [EM(N)] has a gate-on voltage VEL and a gate-off voltage at a predetermined duty ratio during the light emission period Tem. You can swing between (VEH).

The pulse of the second scan signal [SCAN2(N)] is inverted to the gate-on voltage VGL before the first scan signal [SCAN1(N)], and is simultaneously gated with the pulse of the first scan signal [SCAN1(N)] It is inverted to the off voltage VGH. The pulse widths of the first and second scan signals SCAN1(N) and SCAN2(N) may be set to less than or equal to one horizontal period (1H).

The pulse of the EM signal EM may be generated as a gate high voltage VEH to suppress light emission of the light emitting device EL during the data writing period Twr and the sustain period Th. The EM signal EM is inverted to the gate high voltage VEH when the first scan signal SCAN1(N) is inverted to the gate low voltage VGL, and the first and second scan signals SCAN1(N), SCAN2(N)] may be inverted to the gate high voltage VEH and then inverted to the gate low voltage VEL.

During the initialization period Tini, the second scan signal SCAN2(N) is inverted to the gate low voltage VGL. At this time, main nodes of the pixel circuit may be initialized.

During the data writing period Twr, the first scan signal SCAN1(N) is inverted to the gate low voltage VGL. At this time, the data signal Vdata is applied to the first electrode of the capacitor Cst, and ELVDD-Vth is applied to the second electrode of the capacitor Cst. During the data writing period Twr, when the gate-source voltage Vgs of the driving device DT reaches the threshold voltage Vth of the driving device DT, the driving device DT is turned off. ), the threshold voltage Vth of the driving element DT is sampled in the capacitor Cst, and the data voltage Vdata compensated for by the threshold voltage Vth is charged in the capacitor Cst.

The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer of the OLED may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light emitting element EL is connected to the fourth and fifth switch elements T4 and T5 through the fourth node n4.

A low potential power voltage VSS is applied to the cathode of the light emitting element EL. The driving device DT drives the light emitting device EL by supplying a current to the light emitting device EL according to the gate-source voltage Vgs. The light emitting element EL emits light with a current controlled by the driving element DT according to the voltage of the data signal Vdata. The current path of the light emitting element EL is switched by the fourth switch element T4 .

The capacitor Cst is connected between the first node n1 and the second node n2. The voltage of the data signal Vdata compensated by the threshold voltage Vth of the driving element DT is charged in the capacitor Cst. Since the voltage of the data signal Vdata in each of the sub-pixels is compensated by the threshold voltage Vth of the driving device DT, the threshold voltage deviation of the driving device DT in the sub-pixels may be compensated.

The first switch element T1 is turned on in response to the gate low voltage VGL of the first scan signal SCAN1(N) to transfer the voltage of the data signal Vdata to the first node n1 ) is supplied to The first switch element T1 includes a gate connected to the first gate line GL11 to which the first scan signal SCAN1(N) is applied, a first electrode connected to the data lines DL1 and DL2, and a first node ( and a second electrode connected to n1).

The second switch element T2 is turned on in response to the gate low voltage VGL of the second scan signal SCAN2(N) to connect the gate and the second electrode of the driving element DT. The second switch element T2 has a gate connected to the second gate line GL12 to which the second scan signal SCAN2(N) is applied, a first electrode connected to the second node n2 , and a third node n3 . ) and a second electrode connected to the

The third switch element T3 is turned on in response to the gate low voltage VEL of the EM signal EM(N) and is referenced to the first node n1 during the initialization period Tini and the light emission period Tem. A voltage Vref is supplied. Due to the third switch element T3 , the voltage of the first electrode of the capacitor Cst is initialized to Vref during the initialization period Tini and the light emission period Tem. The third switch element T3 is connected to the gate connected to the third gate line G13 to which the EM signal [EM(N)] is applied, the first electrode connected to the first node n1, and the Vref line to which Vref is applied. and a second electrode connected thereto.

The fourth switch element T4 is turned on in response to the gate low voltage VEL of the EM signal EM(N) to turn on the third node n3 during the initialization period Tini and the light emission period Tem. 4 is connected to node n4. The gate of the fourth switch element T4 is connected to the third gate line GL13 . The first electrode of the fourth switch element T4 is connected to the third node n3 , and the second electrode of the fourth switch element T4 is connected to the fourth node n4 .

The fifth switch element T5 is turned on in response to the gate low voltage VGL of the second scan signal SCAN2(N) to apply Vref to the fourth node during the initialization period Tini and the data writing period Twr. (n4) is supplied. The gate of the fifth switch element T5 is connected to the second gate line GL12. A first electrode of the fifth switch element T5 is connected to the Vref line, and a second electrode of the fifth switch element T5 is connected to the fourth node n4 .

The driving element DT is operated as a diode by the second switch element T2 turned on in the data writing period Twr. The threshold voltage Vth of the driving element DT is sampled during the data writing period Twr. The driving device DT drives the light emitting device EL by controlling a current flowing through the light emitting device EL according to the gate-source voltage Vgs during the light emission period Tem. The driving element DT includes a gate connected to the second node n2 , a first electrode connected to the ELVDD line to which ELVDD is applied, and a second electrode connected to the third node n3 .

The gate driver 120 may include a shift register. The timing controller 130 may control the gate driver 120 by generating the gate timing control signals VST and GCLK as shown in FIG. 6 . The gate timing control signals VST and GCLK may be input to the shift register of the gate driver 120 .

6 is a diagram schematically illustrating a shift register of the gate driver 120 . The shift register of the gate driver 120 includes dependently connected stages SR(n-1) to (n+2). The shift register receives the start pulse VST or the carry signal CAR and generates output signals [OUT(n-1)) to (n+2)] according to the timing of the shift clock GCLK. The carry signal CAR may be output from a previous stage.

Each of the stages [SR(n-1) to (n+2)] includes a control unit 60 for charging and discharging the Q node and the QB node, and charging the gate line according to the Q node voltage to increase the waveform of the gate signal ( rising) and includes a buffer that discharges the gate line according to the QB node voltage. The buffer includes a pull-up transistor Tup and a pull-down transistor Tdn. The output signals OUT(n-1) to (n+2) of the stages SR(n-1) to (n+2) are gate signals sequentially applied to the gate lines.

In the large screen display device, the control board may be connected to two or more source printed circuit boards (printed circuit boards) as shown in FIGS. 7 and 8 .

7 and 8 , the control board 150 is to be connected to the first and second source PCBs through a flexible circuit board, for example, a flexible flat cable (FFC) 151 and connectors 151a and 151b. can

The COF on which the source drive IC (SIC) is mounted is connected between the source PCB and the display panel 100 . The input pads of the COF are connected to the output terminals of the source PCB. Output pads of the COF are connected to input pads of the display panel. The output pads of the COF may be adhered to the input pads of the display panel 100 through an anisotropic conductive film (ACF).

The timing controller 130 and the level shifter 140 may be mounted on the control board 150 as shown in FIG. 7 . Input terminals of the level shifter 140 are connected to the timing controller 130 through wires formed on the control board 150 . Output terminals of the level shifter 140 may be connected to the gate driver 120 through the FFC 151 , the source PCB, the COF, and line on glass (LOG) wires on the display panel 100 .

The level shifter 140 may be mounted on each of the source PCBs as shown in FIG. 8 . In this case, the level shifter 140 may include the first level shifter 141 mounted on the first source PCB and the second level shifter 142 mounted on the second source PCB. Input terminals of each of the level shifters 141 and 142 may be connected to the timing controller 130 through wires connecting the control board 150 , the FFC 151 and the source PCB. Output terminals of the level shifters 141 and 142 may be connected to the gate driver 120 through the source PCB, the COF, and LOG lines on the display panel 100 .

As shown in FIG. 9 , the COF disposed on the leftmost and/or rightmost side of the display panel 100 close to the gate driver 120 includes power lines to which power or pixel power of the gate driver 120 is applied and the clock. Wirings may be formed.

In the display panel driving circuit, in particular, in a bonding portion between the COF and the display panel 100 , a short circuit defect may occur between power lines due to conductive foreign matter or moisture. If a short circuit occurs in the COF or bonding part, short circuit generation is also generated in the source drive IC or level shifter. When power is input (Power ON) to the display device 1000 having such a short-circuit defect and the display panel driving circuit is driven to generate a panel signal, the panel signal is applied to the short-circuited circuit. The panel signal includes a scene necessary for driving the pixels, such as a data signal, a gate signal, and a pixel driving power source. When a panel signal is generated in a display device having a short circuit defect, the short circuit may be damaged, and in severe cases, the source drive IC and the level shifter may be physically destroyed.

The display device of the present invention includes a short-circuit failure sensing unit. The present invention monitors whether the display panel driving circuit is short-circuited in real time using a short-circuit failure sensing unit, and when a short circuit of the display panel driving circuit is detected, the display panel driving circuit is disabled to block the panel signal generation. When the display panel driving circuit is short-circuited, the display device displays an alarm message on the screen.

9 is a flowchart schematically illustrating a failure sensing method according to an embodiment of the present invention. 10 is a diagram illustrating an example of a screen in which a panel signal is blocked after an alarm message displayed on the screen when a short circuit is detected in the display panel driving circuit. 11 is a diagram illustrating an example in which an alarm message is transmitted to the outside through a network when a short circuit is detected in the display panel driving circuit.

9 to 10 , the display device 1000 self-diagnoses the display panel driving circuit and monitors the short circuit of the display panel driving circuit (S00 and S01). When the power of the display device 1000 is input, the display device 1000 drives the short-circuit failure sensing unit to determine whether the display panel driving circuit, in particular, the source drive IC), the COF, the level shifter LS, and the like are short-circuited.

When the display panel driving circuit is short-circuited, the display device 1000 displays a preset alarm message on the screen as shown in FIG. 10 and then disables the display panel driving circuit to block the panel signal ( S02 ).

When the panel signal is blocked, the screen appears black. The display device 1000 may transmit the alarm message AM to the outside through a wired/wireless network connected to the communication module of the host system 2000 (SO2). The alarm message may be transmitted to the process control system 2000 connected to the process line in the module assembly process of the display device. After the display device is shipped, the alarm message may be transmitted to a warranty and repair service center 3000 through a wired/wireless network.

When a short circuit of the display panel driving circuit is not detected when the power of the display device 1000 is input, the display panel driving circuit is normally driven to generate a panel signal to display the input image signal on the screen (S03 and S04) .

12 is a circuit diagram illustrating a short-circuit failure sensing unit according to a first embodiment of the present invention.

Referring to FIG. 12 , the display panel driving circuit includes a COF connected between the display panel 100 and the PCB.

The pixel array AA and the gate driver 120 may be disposed on the display panel 100 . The level shifter LS may be disposed on the PCB. The short circuit fault sensing unit ERC may be disposed on the PCB, but is not limited thereto. For example, the short-circuit failure sensing unit ERC may be embedded in the level shifter LS and/or the source drive IC SIC as shown in FIGS. 14A to 16C .

A source drive IC (SIC) may be disposed on the COF. The COF includes clock wires 30 , dummy wires 33 , data input wires 34 , data output wires 35 , input pads 31 connected to the connector of the PCB, and the display panel 100 . output pads 32 connected to The input pads 31 are connected to one end of each of the clock wires 30 , one end of each of the dummy wires 33 , and one end of each of the data input wires 34 , and are connected to an output pad of the PCB through a connector. are connected 1:1. The output pads 32 are connected to the other end of each of the clock lines 30 , the other end of each of the dummy lines 33 , and one end of each of the data output lines 35 , and are connected to the display panel 100 through the ACF. ) to the pads.

The clock wires 30 connect clock output terminals of the level shifter LS to clock input terminals of the gate driver 120 . A line on glass (LOG) clock line CL connecting the COF and the gate driver 120 is formed on the display panel substrate.

Pads connected to the other end of each of the data input lines 34 are connected to input terminals of the source drive IC (SIC). Pads connected to the other end of each of the data output wirings 34 are connected to output terminals of the source drive IC (SIC). The data input wires 34 are connected to data output terminals of the timing controller 130 and input terminals of the source drive IC (SIC).

In a bonding process of the dummy wires 30 and the COF connected to the dummy wires 30 and the display panel 100 , the dummy wires 30 may be used for checking alignment between them. The dummy wires 30 may be used for purposes other than alignment.

The level shifter LS includes buffers connected to an output terminal in each of the channels of the level shifter LS. The buffer of the level shifter LS outputs a signal swinging between the gate high voltage VGH and the gate low voltage VGL through the output terminal in the display mode using the first and second transistors M11 and M12. do. The first transistor M11 is turned on under the control of the timing controller 130 to supply the gate high voltage VGH to the output terminal. The second transistor M12 is turned on under the control of the timing controller 130 to connect the output terminal to the VGL node to discharge the output terminal to the gate low voltage VGH.

The level shifter LS further includes a third transistor M13 that is turned on in the ground mode.

The third transistor M13 is synchronized with the short-circuit failure sensing unit ERC by the timing controller 130 . The third transistor M13 is turned on when the short circuit fault sensing unit ERC is driven under the control of the timing controller 130 to connect the output terminal of the level shifter LS to the ground GND.

The start pulse and shift clock output from the level shifter LS are supplied to the data driver 120 through the clock lines 30 .

The source drive IC (SIC) includes output buffers AMP and a fourth transistor M31 connected to respective output terminals of the source drive IC (SIC) to output the data signal Vdata.

The fourth transistor M31 is synchronized with the short-circuit failure sensing unit ERC by the timing controller M31. The fourth transistor M31 is turned on when the short circuit fault sensing unit ERC is driven under the control of the timing controller 130 to connect the output terminal of the source drive IC SIC to the ground GND.

The short-circuit failure sensing unit ERC includes a current limiting resistor R1 to which the sample voltage Vsam is applied, and a comparator COMP connected to the current limiting resistor R1. The short-circuit failure sensing unit ERC may generate a flag signal Vflag indicating a short-circuit failure of at least one of the COF, the source drive IC, and the level shifter in the sensing mode.

The current limiting resistor R1 is connected between the sample voltage input node and the input pad 32 of the COF to limit the current flowing into the COF to increase the short-circuit sensing sensitivity. The current limiting resistor R1 may be connected to the input pad 32 of the COF through an output pad or connector of the PCB. Without the current limiting resistor R1, the short-circuit sensing sensitivity is lowered because the voltage level difference is small whether the input voltage of the comparator COMP has a short circuit or not. The resistance value of the current limiting resistor R1 and the voltage level of the reference voltage Vr of the comparator COMP may be appropriately selected according to desired short-circuit sensing sensitivity and short-circuit determination level.

The power supply unit 400 supplies the sample voltage Vsam to the short circuit fault sensing unit ERC when power of the display device 100 is input (Power ON). The sample voltage Vsam may be 3.3V, but is not limited thereto.

The comparator COMP is connected to a node between the first input terminal (-) to which the reference voltage Vr is applied, the current limiting resistor R1 and the input pad of the COF to receive the sensed voltage Vsen as input. 2 It includes an input terminal (+) and an output terminal for outputting a flag signal (Vflag).

The first input terminal (−) of the comparator COMP1 to which the sensing voltage Vsen is applied and the current limiting resistor R1 may be connected to the input pad 31 of the COF.

When power is applied to the display device 1000 (Power ON), the short circuit fault sensing unit ERC and the transistors M13 and M31 are driven under the control of the timing controller 130 . When the transistors M13 and M31 are turned on, the COF wires are connected to the ground GND.

When the conductive foreign material 40 is present in the bonding portion between the COF and the display panel 100 , the sensing voltage Vsen decreases. When the wires and pads of the COF are short-circuited, the sensing voltage Vsen at the node between the current limiting resistor R1 and the resistance R2 caused by the conductive foreign material is determined according to the voltage division law as shown in FIG. 13 . Compared to the case in which there is no conductive foreign material, when the COF is short-circuited due to the conductive foreign material, the sample sensing voltage Vsen is lowered.

The comparator COMP compares the reference voltage Vr with the sensing voltage Vsen and outputs a high level flag signal Vflag when the sensing voltage Vsen is equal to or greater than the reference voltage Vr. The comparator COMP compares the reference voltage Vr with the sensing voltage Vsen and outputs a low level flag signal Vflag when the sensing voltage Vsen becomes lower than the reference voltage Vr. Accordingly, when the COF wires and pads are short-circuited, the voltage of the flag signal Vflag is at a low level.

The short-circuit determination level may vary according to the reference voltage Vref of the comparator COMP. For example, when Vsam = Vr = 3.3V, R1 = 10KΩ, R2 < 10KΩ, a short fault is detected when Vsen < 3.3V. A short fault is detected when Vsen < 1.6V when Vsam = 3.3V, Vr = 1.6 V, R1 = 10KΩ, R2 < 10KΩ.

When the low-level flag signal Vflag is input to the timing controller 130 , preset warning message data may be transmitted to the source drive IC (SIC) to display the warning message on the screen. The warning message data may be stored in the internal memory of the source drive IC (SIC). In this case, the source drive IC (SIC) may output the data voltage of the warning message data in response to the flag signal Vflag to display the warning message on the screen. When the low level flag signal Vflag is received, the host system 200 may transmit a preset warning message AM to the outside through the communication module and the network.

14A and 14B are circuit diagrams illustrating a short-circuit failure sensing unit according to a second embodiment of the present invention. 14A and 14B, the current limiting resistor is omitted.

14A and 14B , at least one of the source drive IC SIC and the level shifter LS may include a short-circuit failure sensing unit.

Each of the channels of the source drive IC SIC may include a comparator COMP and a current limiting resistor R1 of the short-circuit failure sensing unit ERC. The first input terminal (+) of the comparator COMP to which the sensing voltage Vsen is applied in each of the channels of the source drive IC SIC, and the current limiting resistor RC are connected to the output terminal of the source drive IC SIC. Connected. The output terminal is connected to the output pad 32 of the COF.

In the sensing mode, each of the channels of the source drive IC (SIC) may detect a short circuit failure through an output terminal. The sensing mode may be divided into a first step and a second step. In the first step and the second step, it should be noted that although short circuit failures are sequentially sensed by channels of the source drive IC (SIC) and the level shifter (LS) in a preset order, the order is not limited thereto.

In a first step, the source drive IC SIC outputs the sample voltage Vsam through the output terminal of the odd-th channel CODD as shown in FIG. 14A , and senses the sensing voltage Vsen with the comparator COMP. At this time, the output terminal of the even-th channel CEVEN is connected to the ground GND through the transistor M31. The sample voltage Vsam output from the odd-th channel CODD is applied to the odd-th wirings 35 on the COF. In the first step, the short circuit amount of the odd-th channel CODD of the source drive IC SIC may be sensed by the comparator COMP.

In the first step, the level shifter LS outputs the sample voltage Vsam through the output terminal of the odd-th channel LODD as shown in FIG. 14B and senses the sensing voltage Vsen with the comparator COMP. At this time, the output terminal of the odd-th channel LEVEN is connected to the ground GND through the transistor M13. The sample voltage Vsam output from the odd-th channel LODD is applied to the odd-th wirings 30 on the COF. At this time, the short circuit amount of the odd-th channel LODD of the level shifter LS may be detected by the comparator COMP.

In the second step, the source drive IC SIC outputs the sample voltage Vsam through the output terminal of the even-th channel CEVEN as shown in FIG. 14B and senses the sensing voltage Vsen with the comparator COMP. At this time, the output terminal of the even-th channel CEVEN is connected to the ground GND through the transistor M31. The sample voltage Vsam output from the even-th channel CEVEN is applied to the even-th wirings 35 on the COF. In the second step, the short circuit amount of the even-th channel CEVEN of the source drive IC SIC may be sensed by the comparator COMP.

In the second step, the level shifter LS outputs the sample voltage Vsam through the output terminal of the even-th channel LEVEN as shown in FIG. 14B and senses the sensing voltage Vsen by the comparator COMP. In this case, the output terminal of the odd-th channel LODD is connected to the ground GND through the transistor M13. The sample voltage Vsam output from the even-th channel LODD is applied to the even-th wirings 30 on the COF. At this time, the short circuit amount of the even-th channel LEVEN of the level shifter LS may be sensed by the comparator COMP.

The level shifter LS may generate the sample voltage Vsam by using the buffers M11 and M12 without adding additional circuit elements as shown in FIGS. 14A and 14B . For example, the sample voltage may be output as an output voltage determined according to the gate-source voltage by adjusting the gate voltage of the first transistor M11. In this case, the current limiting resistor R1 may be replaced by a channel resistance of the first transistor M11. In another embodiment, a separate current limiting resistor and a switch element may be added as shown in FIGS. 16A to 16C .

15A to 15C are circuit diagrams illustrating a short-circuit failure sensing unit embedded in a source drive IC (SIC) and an operation mode of the source drive IC.

15A to 15C , each of the channels of the source drive IC (SIC) may operate in a sensing mode, a ground mode, and a display mode under the control of the timing controller 130 .

In the sensing mode, the sample voltage Vsam is output through the channel of the source drive IC (SIC), and the short circuit fault is sensed by receiving the sensing voltage Vsen. The ground mode connects the corresponding channel to the ground (GND) in conjunction with the sensing mode of other channels of the source drive IC (SIC), or interworks with the sensing mode of the short circuit fault sensing unit (ERC) or other display panel driving circuits to connect the corresponding channel connect to ground (GND).

In the display mode, pixel data of an input image is written to pixels to display an image on the pixel array AA. The channel of the source drive IC (SIC) outputs the data voltage Vdata output from the DAC in the display mode. In the sensing mode, a short circuit fault in the display panel driving circuit is sensed. In the sensing mode, the channel of the source drive IC (SIC) outputs a sample voltage Vsam and compares the sensing voltage Vsen with a reference value Vr to sense a short circuit failure. In the ground mode, the channel of the source drive IC (SIC) is connected to the ground (GND).

Each of the channels of the source drive IC (SIC) includes a DAC, an output buffer (AMP), a current limiting resistor (R1), a comparator (COMP), switch elements (SW1 to SW6), a transistor (M31) and the like. The switch elements SW1 to SW6 may be implemented as transistors.

The DAC converts pixel data into a gamma compensation voltage and outputs a data voltage Vdata. The output buffer AMP transfers the data voltage Vdata to the output terminal OUT1 without loss.

The current limiting resistor R1 is connected between the output buffer AMP and the output terminal OUT1 of the source drive IC. The comparator COMP is connected between the current limiting resistor R1 and the flag signal output terminal OUT2. The first input terminal (−) of the comparator COMP is connected to a node between the first current limiting resistor R1 and the output terminal OUT1 to receive the sensing voltage Vsen from the output terminal OUT1 .

The switch elements SW1 to SW6 switch a data signal path, a sample voltage path, and a sensing voltage path.

The first and second switch elements SW1 and SW2 are turned on in the display mode. The first and second switch elements SW1 and SW2 may maintain an off state in the sensing mode and the ground mode. The first switch element SW1 is connected between the DAC and the output buffer AMP to connect the output terminal of the DAC to the output buffer AMP in the display mode. The second switch element SW2 is connected between the output buffer AMP and the output terminal OUT1 . The first and second switch elements SW1 and SW2 connect the data signal path through which the data voltage Vdata output from the DAC is transmitted in the display mode under the control of the timing controller 130, and in the sensing mode and the ground mode Block the data signal path.

The transistor M31 is turned on in the ground mode under the control of the timing controller 130 to connect the output terminal OUT1 of the corresponding channel to the ground GND. The transistor M31 maintains an off state in the sensing mode and the display mode.

The third to sixth switch elements SW3 to SW6 are turned on in the sensing mode. The third to sixth switch elements SW3 to SW6 may maintain an off state in the display mode and the ground mode. The third switch element SW3 is connected between the sample voltage source and the input terminal (+) of the output buffer AMP and is turned on in the sensing mode to connect the sample voltage source to the input terminal (+) of the output buffer AMP . The power supply 400 may output a sample voltage Vsam. The timing controller 130 transmits the sensed voltage data to the source drive IC (SIC) in the sensing mode, and the DAC converts the sensed voltage data into a gamma reference voltage from the power supply 400 to output the sample voltage Vsam. have. The sample voltage source may be the power supply 400 or the DAC.

The fourth switch element SW4 is connected between the output buffer AMP and the current limiting resistor R1 and is turned on in the sensing mode to connect the output terminal of the output buffer AMP and the current limiting resistor R1. The fifth switch element SW5 is connected between the node between the current limiting resistor R1 and the output terminal OUT1 and the input terminal (-) of the comparator COMP to be turned on in the sensing mode and turned on to the output terminal OUT1 ) to the input terminal (-) of the comparator (COMP). The sixth switch element SW6 is connected between the output terminal of the comparator COMP and the flag signal output terminal OUT2 and is turned on in the sensing mode to connect the output terminal of the comparator COMP and the flag signal output terminal OUT2 Connect.

16A to 16C are circuit diagrams illustrating a short-circuit failure sensing unit built in the level shifter LS and an operation mode of the level shifter LS.

16A to 16C , each of the channels of the level shifter LS may operate in a sensing mode, a ground mode, and a display mode under the control of the timing controller 130 .

In the sensing mode, a sample voltage Vsam is output through a channel of the level shifter LS, and a short circuit failure is sensed by receiving the sensing voltage Vsen. The ground mode connects the corresponding channel to the ground (GND) in conjunction with the sensing mode of other channels of the level shifter (LS), or connects the corresponding channel with the sensing mode of the short circuit fault sensing unit (ERC) or other display panel driving circuits. Connect to ground (GND).

In the display mode, pixel data of an input image is written to pixels to display an image on the pixel array AA. The channel of the level shifter LS shifts the voltage level of the input signal in the display mode to swing between the gate high voltage VGH and the gate low voltage VGL using the first and second transistors M11 and M12. output a signal to In the sensing mode, a short circuit fault in the display panel driving circuit is sensed. In the sensing mode, the channel of the level shifter LS outputs a sample voltage Vsam and compares the sensing voltage Vsen with a reference value Vr to sense a short circuit failure. In the ground mode, the channel of the level shifter LS is connected to the ground GND.

Each of the channels of the level shifter LS includes transistors M11 to M13, a current limiting resistor R1, a comparator COMP, and switch elements SW11 and SW12. The switch elements SW11 and SW12 may be implemented as transistors.

The current limiting resistor R1 is connected between the output terminal OUT11 of the level shifter LS and the sample voltage source. The sample voltage source may be the power supply unit 400 . The comparator COMP is connected between the current limiting resistor R1 and the flag signal output terminal OUT12. The first input terminal (-) of the comparator COMP is connected to a node between the first current limiting resistor R1 and the output terminal OUT11 to receive the sensing voltage Vsen from the output terminal OUT11.

The first switch element SW11 is connected between the buffer output node between the first transistor M11 and the second transistor and the output terminal OUT11 of the level shifter LS. The first switch element SW11 is turned on in the display mode under the control of the timing controller 130 to connect the buffer output node to the output terminal OUT11 . The first switch element SW11 maintains an off state in the sensing mode and the ground mode.

The second switch element SW12 is connected between the current limiting resistor R1 and the output terminal OUT11 of the level shifter. The second switch element SW12 is turned on in the sensing mode under the control of the timing controller 130 to connect the current limiting resistor R1 to the output terminal OUT11 . The second switch element SW12 maintains an off state in the display mode and the ground mode.

The third transistor M13 is turned on in the ground mode under the control of the timing controller 130 to connect the output terminal OUT11 of the corresponding channel to the ground GND. The third transistor M31 maintains an off state in the sensing mode and the display mode.

The above-described embodiments may be applied alone or in combination.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: comparator 21, 22: demultiplexer
100: display panel 110, SIC: data driver (source drive IC)
120: gate driver 130: timing controller
140, LS: level shifter 200: host system
400: power supply R1: current limiting resistor
ERC: short circuit fault sensing unit

Claims (14)

a display panel in which a plurality of data lines and a plurality of gate lines cross and a pixel array is disposed;
a gate driver disposed on the display panel to supply a gate signal to the gate lines using a shift register;
a level shifter shifting the voltage level of the input signal and supplying it to the gate driver;
a printed circuit board on which the level shifter is disposed;
a source drive IC for supplying a data signal to the data lines in a display mode; and
and a flexible circuit board on which the source drive IC is disposed and connected between the display panel and the printed circuit board;
At least one of the flexible circuit board, the source drive IC, and the level shifter includes a short-circuit failure sensing unit generating a flag signal in a sensing mode;
The short-circuit failure sensing unit,
a resistor to which a sample voltage is applied; and
and a comparator for comparing a sensed voltage received from any one of the wiring of the flexible circuit board, an output terminal of the level shifter, and an output terminal of the source drive IC with a preset reference voltage. The method of claim 1,
The flexible circuit board,
a plurality of clock wires connecting output terminals of the level shifter to clock input terminals of the gate driver;
a plurality of dummy wires;
data input wires connected to data input terminals of the source drive IC;
a plurality of data output wires connected to data output terminals of the source drive IC;
a plurality of input pads coupled to the printed circuit board; and
A display device including a plurality of output pads bonded to the display panel. 3. The method of claim 2,
the resistor and the comparator are disposed on the printed circuit board;
A first input terminal of the comparator to which the sensing voltage is applied and the resistor are connected to the input pad,
the reference voltage is applied to the second input terminal of the comparator;
The comparator outputs a flag signal indicating a short circuit of at least one of a wiring of the flexible circuit board, an output terminal of the level shifter, and an output terminal of the source drive IC in a sensing mode. 4. The method of claim 3,
At least one of the wiring of the flexible circuit board, the output terminal of the level shifter, and the output terminal of the source drive IC is short-circuited when the flag signal is at a specific level. 4. The method of claim 3,
a timing controller that transmits pixel data of an input image to the source drive IC in the display mode and controls operation timings of the source drive IC and the gate driver; and
A display device comprising: a communication module; and a host system configured to transmit pixel data of the input image and a timing signal to the timing controller. 6. The method of claim 5,
A warning message is displayed on the pixel array when the flag signal is at a specific level. 6. The method of claim 5,
A display device for transmitting a warning message to the outside through the communication module when the flag signal is at a specific level. 4. The method of claim 3,
In the sensing mode, the level shifter and the source drive IC operate in a ground mode so that an output terminal of the level shifter and an output terminal of the source drive IC are connected to a ground. 3. The method of claim 2,
each of the channels of the source drive IC includes the resistor and the comparator;
Each of the channels of the source drive IC further includes a transistor for connecting an output terminal to the ground in a ground mode,
a first input terminal of the comparator to which the sensing voltage is applied and the resistor are connected to an output terminal of the source drive IC in the sensing mode;
the reference voltage is applied to the second input terminal of the comparator;
an output terminal of the comparator is connected to a flag signal output terminal of the source drive IC;
The comparator outputs a flag signal indicating a short circuit of each of the channels of the source drive IC. 10. The method of claim 9,
The sensing mode includes a first step and a second step,
In the first step, the sample voltage is applied to the resistor in each of the odd-th channels of the source drive IC, and a sensing voltage is applied to the comparator;
In the first step, each of the even-th channels of the source drive IC operates in the ground mode so that an output terminal of the source drive IC is connected to the ground;
In the second step, in each of the even channels of the source drive IC, the sample voltage is applied to the resistor, and a sensing voltage is applied to the comparator;
In the second step, each of the odd-numbered channels of the source drive IC operates in the ground mode so that an output terminal of the source drive IC is connected to the ground. 10. The method of claim 9,
Each of the channels of the source drive IC,
a digital-to-analog converter for outputting a data signal in the display mode;
a first switch element connected between the output terminal of the digital-to-analog converter and the output buffer of the source drive IC and turned on in the display mode to connect the output terminal of the digital-to-analog converter to the output buffer;
a second switch element connected between the output buffer and the output terminal of the source drive IC and turned on in the display mode to connect the output buffer to the output terminal of the source drive IC;
a third switch element connected between the sample voltage source generating the sample voltage and the input terminal of the output buffer and turned on in the sensing mode to connect the sample voltage source to the input terminal of the output buffer;
a fourth switch element connected between the output terminal of the output buffer and the resistor and turned on in the sensing mode to connect the output terminal of the output buffer and the resistor;
It is connected between a node between the resistor and an output terminal of the source drive IC and a first input terminal of the comparator and is turned on in the sensing mode to connect the output terminal of the source drive IC to the first input terminal of the comparator. a fifth switch element for connecting; and
and a sixth switch element connected between the output terminal of the comparator and the flag signal output terminal and turned on in the sensing mode to connect the output terminal of the comparator to the flag signal output terminal. 3. The method of claim 2,
each of the channels of the level shifter comprises the resistor and the comparator;
Each of the channels of the level shifter further comprises a transistor for connecting the output terminal to the ground in the ground mode,
a first input terminal of the comparator and the resistor are connected to an output terminal of the level shifter in the sensing mode;
the reference voltage is applied to the second input terminal of the comparator;
an output terminal of the comparator is connected to a flag signal output terminal of the level shifter;
The comparator outputs a flag signal indicating a short circuit of each of the channels of the level shifter. 13. The method of claim 12,
The sensing mode includes a first step and a second step,
In the first step, in each of the odd-th channels of the level shifter, the sample voltage is applied to the resistor, and a sensing voltage is applied to the comparator;
In the first step, each of the even-th channels of the level shifter operates in the ground mode so that an output terminal of the level shifter is connected to the ground;
In the second step, in each of the even channels of the level shifter, the sample voltage is applied to the resistor, and a sensing voltage is applied to the comparator,
In the second step, each of the odd-numbered channels of the level shifter operates in the ground mode so that an output terminal of the level shifter is connected to the ground. 13. The method of claim 12,
Each of the channels of the level shifter,
a buffer configured to output a signal swinging between the high voltage and the low voltage to an output terminal of the level shifter in the display mode using a first transistor for switching a high voltage and a second transistor for switching a low voltage;
a first transistor connected between a buffer output node between the first transistor and the second transistor and an output terminal of the level shifter to be turned on in the display mode to connect the buffer output node to an output terminal of the level shifter switch element; and
and a second switch element connected between the resistor and the output terminal of the level shifter and turned on in the sensing mode to connect the resistor to the output terminal of the level shifter.

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