CN101162570A - Power supply circuit, driver circuit, electro-optical device, electronic instrument, and common electrode drive method - Google Patents
Power supply circuit, driver circuit, electro-optical device, electronic instrument, and common electrode drive method Download PDFInfo
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- CN101162570A CN101162570A CNA2007101631326A CN200710163132A CN101162570A CN 101162570 A CN101162570 A CN 101162570A CN A2007101631326 A CNA2007101631326 A CN A2007101631326A CN 200710163132 A CN200710163132 A CN 200710163132A CN 101162570 A CN101162570 A CN 101162570A
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Abstract
A power supply circuit which outputs a common electrode voltage to a common electrode of an electro-optical device provided opposite to pixel electrodes through an electro-optical material includes a voltage booster circuit which generates a boost voltage boosted by a charge-pump operation in synchronization with a charge clock signal, and a common electrode voltage generation circuit which outputs a high-potential-side voltage or a low-potential-side voltage generated based on the boost voltage to the common electrode as the common electrode voltage. The charge clock signal has a rising edge and a falling edge in a period in which a sign of voltages between the pixel electrode and the common electrode are either positive or negative.
Description
Technical field
The present invention relates to power circuit, driving circuit, electrooptical device, electronic equipment and opposite electrode driving method etc.
Background technology
In recent years, as liquid crystal display (Liquid Crystal Display:LCD) panel (the sensu lato display panel that carries on electronic equipments such as pocket telephone.More sensu lato electrooptical device), the known LCD panel that the LCD panel of simple matrix mode is arranged and used the active matrix mode of thin film transistor (TFT) on-off elements such as (Thin Film Transistor: be designated hereinafter simply as TFT).
The simple matrix mode is compared with the active matrix mode and is easy to realize low power consumption, but is difficult to but realize that multicolourization and live image show.On the other hand, the active matrix mode is suitable for multicolourization and live image shows, but is difficult to realize low power consumption.
When driving the LCD panel of this active matrix mode, drive so that the impressed voltage that is added on outward on the liquid crystal (sensu lato photoelectric material) that constitutes pixel is interchange.At this moment, according to inversion driving timing (timing, sequential), change the opposed electrode voltage (common electric voltage) that offers and constitute the opposed opposite electrode of pixel electrode (public electrode) of pixel, can reduce the outer voltage level that is added on pixel electrode, and realize low power consumption.
But, when driving the LCD panel of active matrix mode, being used to select to need high-tension supply voltage on the gate line of pixel, at the supply voltage that on the source electrode line that gray scale voltage is provided on the pixel, needing to be used for low-voltage.Therefore, the booster system supply voltage by the charge pump action that can low-power consumption realizes, thus generate these various supply voltages.For example, the voltage of the less purposes that is used to load, by the cycle of lengthening charge pump action, can further reduce power consumption.Being added to the high-tension supply voltage on the gate line, for example is by the charge pump action of two lines (2 horizontal scan period) as one-period generated.
But, with the cycle synchronisation of the charge pump signal that is used to carry out the charge pump action, the voltage change of the booster voltage that obtains by this charge pump action.Therefore, for example in patent documentation 1, the cycle that son field (subfield) is set is the integral multiple of charge pump signal period.Like this, can spatially disperse the display optical inequality (showing MURA) of the striation that occurs in each son field, eliminate the display optical inequality in the frame.
Patent documentation 1: TOHKEMY 2004-252022 communique
But, as ground wave simulation color television for play signal have NTSC (NationalTelevision Standards Committee: vision signal (sensu lato TV signal) NTSC), at CRT (Cathode Ray Tube: cathode-ray tube (CRT)) need be based on the output action of ntsc video signal in the device for image output and sound.In recent years, (DSC (Digital StiillCamera: digital camera)) for example also need be according to the demonstration of the LCD panel of ntsc video signal to load the portable electric appts of LCD panel.
But, the quantity (number of scanning lines) of the horizontal scan period in ntsc video signal one vertical scanning period is that a frame even number one frame odd number ground repeats.On the other hand, in the prior art, be that the identical situation of number of scanning lines of each frame is a prerequisite with the driving circuit that drives the LCD panel, carry out display driver.Therefore, for example with two lines as one-period, when generating the high-tension supply voltage of gate line, per two lines of booster voltage that are used to generate opposed electrode voltage change, the voltage that opposite electrode takes place changes, and scintillation takes place also make and show the grade deterioration.
In addition, even patent documentation 1 disclosed technology, as the number of scanning lines difference of TV signal, each frame, the timing number (charge pump sonar signal along number) that then carries out charge pump action in each frame is also different.Therefore, it is different that the voltage of the opposite electrode that causes based on the difference of frame changes part, and consequently the impressed voltage of liquid crystal changes based on frame.Thus, scintillation taking place and makes demonstration grade deterioration.
Summary of the invention
Even technical matters to be solved by this invention is to provide under the different situation of the number of scanning lines of each frame, flicker be can suppress and the power circuit of steady display grade, driving circuit, electrooptical device, electronic equipment and opposite electrode driving method reduced.
In order to solve the problems of the technologies described above, the present invention relates to a kind of power circuit, this power circuit is used for to opposite electrode output opposed electrode voltage, a plurality of pixel electrodes that described opposite electrode and electrooptical device had are provided with across photoelectric material, this power circuit comprises: booster circuit, be used to generate booster voltage, described booster voltage is the voltage by boosting with the charge pump action of charging clock synchronization; And the opposed electrode voltage generative circuit, will export to described opposite electrode as described opposed electrode voltage based on hot side voltage or low potential side voltage that described booster voltage generated; Wherein, be between each polarity epoch of positive polarity and negative polarity in the polarity of the voltage between described a plurality of pixel electrodes and the described opposite electrode, have the rising edge of described charging clock and the negative edge of described charging clock.
The power circuit that the present invention relates to also comprises: the scanning voltage generative circuit, be used to generate the scanning voltage on the gate line that is added to described electrooptical device, wherein, described scanning voltage generative circuit can generate described scanning voltage by the charge pump action with described charging clock synchronization.
In this external power circuit that the present invention relates to, each vertical scanning period all has been arranged alternately even number horizontal scan period and odd number horizontal scan period, and described opposed electrode voltage generative circuit can be exported described opposed electrode voltage to described opposite electrode by a line inversion driving.
In this external power circuit that the present invention relates to, the one-period of described charging clock is equivalent to the length of two horizontal scan period.
According to above-mentioned each invention, even at mutual conversion number of scanning lines is under the situation of the frame of odd number and the frame that number of scanning lines is even number, also can offset the influence of variation of the charging clock of the hot side voltage that feeds through to opposed electrode voltage and low potential side voltage.Therefore, the fixing voltage level of the hot side voltage of opposed electrode voltage and low potential side voltage in each frame, when gray scale voltage identical in each frame is added on the pixel electrode, can avoids the situation of the impressed voltage change of photovalve, thereby prevent the image quality deterioration.That is to say,, also can provide and suppressing that flicker reduces, the power circuit of steady display grade even not simultaneously at the number of scanning lines of each frame.And, the signal wire of signal wire, low potential side voltage of signal wire, the hot side voltage of signal wire, the opposed electrode voltage of charging clock and the signal wire of the booster voltage that generates by the charge pump action can be considered to dispose according to the present invention, also the image quality deterioration can be prevented.
In this external power circuit that the present invention relates to, the variation of described charging clock is regularly regularly identical with the variation of described opposed electrode voltage.
According to the present invention, because of same change takes place in the hot side voltage and the low potential side voltage of opposed electrode voltage in each frame, so the change of the voltage level of opposed electrode voltage can periodically not take place, consequently, even in each frame, on pixel electrode, add identical gray scale voltage, the situation that also can avoid the impressed voltage of photovalve to change.
The present invention relates to a kind of driving circuit in addition, be used to drive electrooptical device, described electrooptical device comprises: many gate lines; Many source electrode lines; A plurality of pixel electrodes; And a plurality of on-off elements, each on-off element of selecting by each gate line is used to be electrically connected each source electrode line and each pixel electrode; Described driving circuit comprises: source line driving circuit is used to drive described many source electrode lines; And according to each above-mentioned described power circuit.
In driving circuit involved in the present invention, also comprise: gate line drive circuit is used to scan described many gate lines.
Each invention according to above-mentioned can provide the change that suppresses opposed electrode voltage, prevents the driving circuit of image quality deterioration.
The invention still further relates to a kind of electrooptical device, described electrooptical device comprises: many gate lines; Many source electrode lines; A plurality of pixel electrodes; A plurality of on-off elements, each on-off element of selecting by each gate line is used to be electrically connected each source electrode line and each pixel electrode; Opposite electrode is provided with across photoelectric material with described a plurality of pixel electrodes; And according to above-mentioned each described power circuit.
In this external electrooptical device that the present invention relates to, also comprise: source line driving circuit is used to drive described many source electrode lines.
Each invention according to above-mentioned can provide the change that suppresses opposed electrode voltage, prevents the driving circuit of image quality deterioration.
The invention still further relates to a kind of electronic equipment, described electronic equipment comprises according to each above-mentioned described power circuit.
The invention still further relates to a kind of electronic equipment, described electronic equipment comprises according to above-described electrooptical device.
Each invention according to above-mentioned can provide the change that suppresses opposed electrode voltage, prevents the driving circuit of image quality deterioration.
The invention still further relates to a kind of opposite electrode driving method, be used to drive opposite electrode, a plurality of pixel electrodes that this opposite electrode and electrooptical device had are provided with across photoelectric material, described opposite electrode driving method is characterised in that following steps: generate booster voltage, described booster voltage is the voltage by boosting with the charge pump action of charging clock synchronization; The hot side voltage or the low potential side voltage that will generate based on described booster voltage are exported to described opposite electrode as opposed electrode voltage; Polarity at the voltage between described a plurality of pixel electrodes and the described opposite electrode is between each polarity epoch of positive polarity and negative polarity, has the rising edge of described charging clock and the negative edge of described charging clock.
In addition, in the driving method that the present invention relates to, each vertical scanning period all has been arranged alternately even number horizontal scan period and odd number horizontal scan period, can export described opposed electrode voltage to described opposite electrode by a line inversion driving.
In addition, in the opposite electrode driving method that the present invention relates to, the one-period of described charging clock can be equivalent to the length of two horizontal scan period.
In addition, in the opposite electrode driving method that the present invention relates to, the variation of described charging clock regularly can be regularly identical with the variation of described opposed electrode voltage.
Description of drawings
Fig. 1 is the structure example block diagram of the liquid-crystal apparatus of present embodiment.
Fig. 2 is the block diagram example of the liquid-crystal apparatus of Fig. 1.
Fig. 3 is other structure example block diagrams of the liquid-crystal apparatus of present embodiment.
Fig. 4 is the structure example block diagram of the gate drivers of Fig. 2 or Fig. 3.
Fig. 5 is the structure example block diagram of the source electrode driver of Fig. 2 or Fig. 3.
Fig. 6 is the structure example key diagram of reference voltage generating circuit, DAC and the source line driving circuit of Fig. 5.
Fig. 7 is the structure example key diagram of the power circuit of Fig. 2 or Fig. 3.
Fig. 8 is the structure example circuit diagram of the positive dirction twice booster circuit of Fig. 7.
Fig. 9 shows an example of the sequential of charging clock and each transistorized state of a control.
Figure 10 is the structure example block diagram of the opposed electrode voltage generative circuit of Fig. 7.
Show to Figure 11 pattern the relation of the supply voltage that power circuit generated of present embodiment.
Figure 12 is the example of drive waveforms of the display panel of Fig. 2 or Fig. 3.
Figure 13 is the key diagram that the reversal of poles of present embodiment drives.
Figure 14 is the summary description figure of action of the TV signal I/F of present embodiment.
Figure 15 is the structure example block diagram of TV signal I/F circuit.
Figure 16 is the mensuration example oscillogram of opposed electrode voltage situation about changing.
Figure 17 is the cause description figure that the voltage level of opposed electrode voltage changes.
Figure 18 shows the charging clock of present embodiment and the relation between the opposed electrode voltage.
Figure 19 is the structure example block diagram of power circuit of first variation of present embodiment.
Figure 20 is the structure example block diagram of the charging clock forming circuit of Figure 19.
Figure 21 illustrates the charging clock of second variation of present embodiment and the relation of opposed electrode voltage.
Figure 22 is the structural outline block diagram of electronic equipment, and this electronic equipment has been suitable for the display driver of present embodiment, first or second variation.
Embodiment
Accompanying drawing with reference to following is elaborated to embodiments of the invention.In addition, below the embodiment of explanation does not limit improperly to the content of putting down in writing in claims of the present invention.Below Shuo Ming all structures might not all be necessary constitutive requirements of the present invention.
1, liquid-crystal apparatus
Fig. 1 illustrates the structural outline of the liquid-crystal apparatus of the display driver that is suitable for present embodiment.
Liquid-crystal apparatus 10 (the liquid crystal indicators of Fig. 1.Sensu lato display device) comprises display panel 12 (sense stricto liquid crystal panel, LCD (Liquid Crystal Display) panel) and the display driver 60 that drives display panel 12.In addition, liquid-crystal apparatus 10 can comprise the main frame 40 that is made of central arithmetic processing apparatus (Central Processing Unit:CPU).Main frame 40 can be read program stored in the inside that is arranged on liquid-crystal apparatus 10 or the outside storer, to should the routine processes step handling.This main frame 40 generates vertical synchronizing signal VDO, horizontal-drive signal HDO and view data (luma data) GDO according to NTSC mode or PAL (Phase Alternating Line) mode, and supplies with and give display driver 60.
2, concrete formation
Fig. 2 is the block diagram example of the liquid-crystal apparatus of Fig. 1.
Liquid-crystal apparatus 10 comprises: display panel 12, source electrode driver 20 (sensu lato data line drive circuit), gate drivers 30 (sensu lato scan line drive circuit), main frame 40 and power circuit 50.In addition, on liquid-crystal apparatus 10, do not need to comprise all these circuit modules, can omit partial circuit module wherein yet.
Here, display panel 12 (sensu lato electrooptical device) comprising: many gate lines (sensu lato sweep trace), many source electrode lines (sensu lato data line) and by the pixel electrode of gate line and source electrode line appointment.In this case, (Thin Film Transistor: sensu lato on-off element) be connected with source electrode line, pixel electrode is connected with this TFT, thereby can constitute the liquid-crystal apparatus of active array type by thin film transistor (TFT) TFT.
More particularly, display panel 12 is on active-matrix substrate (for example glass substrate), is formed with the amorphous silicon liquid crystal panel of amorphous silicon membrane.On active-matrix substrate, dispose many gate lines G of arranging and extending to directions X respectively along the Y direction of Fig. 2
1～G
M(M is the natural number more than or equal to 2), and many source electrode line S that arrange and extend to the Y direction respectively along directions X
1～S
N(N is the natural number more than or equal to 2).In addition, with gate lines G
K(1≤K≤M, K are natural numbers) and source electrode line S
LThe position of the point of crossing correspondence of (1≤L≤N, L are natural numbers) is provided with thin film transistor (TFT) TFT
KL(sensu lato on-off element).
TFT
KLGate electrode be connected in gate lines G
K, TFT
KLThe source electrode be connected in source electrode line S
L, TFT
KLDrain electrode be connected in pixel electrode PE
KLAt this pixel electrode PE
KLAnd formation liquid crystal capacitance CL between the opposite electrode CE (common electrode, public electrode)
KL(liquid crystal cell) and auxiliary capacitor CS
KL, wherein, this opposite electrode CE and pixel electrode PE
KLOpposed across liquid crystal (sensu lato photoelectric material).And, be formed with TFT
KL, pixel electrode PE
KLDeng active-matrix substrate and be formed with to form between the counter substrate of opposite electrode CE and enclose liquid crystal, the penetrance of pixel is according to pixel electrode PE
KLAnd the impressed voltage between the opposite electrode CE and changing.
In addition, the voltage level of the opposed electrode voltage VCOM of given opposite electrode CE (hot side voltage VCOMH, low potential side voltage VCOML) is to be generated by the opposed electrode voltage generative circuit that power circuit 50 is comprised.For example, opposite electrode CE forms one side on counter substrate.
The liquid-crystal apparatus 10 of this structure, under the control of main frame 40, based on the view data that provides from the outside, coordinates operation of source driver 20, gate drivers 30 and power circuit 50, and drive display panel 12.
In Fig. 2, liquid-crystal apparatus 10 is the structures that comprise main frame 40, but also can be arranged on main frame 40 outside of liquid-crystal apparatus 10.Perhaps, also can be that part or all of source electrode driver 20, gate drivers 30, main frame 40 and power circuit 50 is formed on the display panel 12.
Among this external Fig. 2, also can be that source electrode driver 20, gate drivers 30 and power circuit 50 is integrated, thereby constitute display driver 60 as semiconductor device (integrated circuit, IC).
Fig. 3 is the block diagram of other structure example of the liquid-crystal apparatus in the present embodiment.
In Fig. 3, (on the display panel substrate) forms the display driver 60 that comprises source electrode driver 20, gate drivers 30 and power circuit 50 on display panel 12.Like this, display panel 12 constitutes and comprises: a plurality of pixels (pixel electrode) of each source electrode line of many gate lines, many source electrode lines, each gate line that is connected in many gate lines and many source electrode lines, the source electrode driver that drives many source electrode lines and the gate drivers that scans many gate lines.Pixel at display panel 12 forms on the zone 44, forms a plurality of pixels.Each pixel can comprise and connect the pixel electrode that connects the TFT of gate line on source electrode line, the grid and be connected in the drain electrode of this TFT on the source electrode.
In addition, in Fig. 3, also can be the structure of on display panel 12, having omitted in gate drivers 30 and the power circuit 50 at least one.
In addition, in Fig. 2 or Fig. 3, display driver 60 can be built-in with main frame 40.Perhaps in Fig. 2 or Fig. 3, display driver 60 can be the semiconductor device that any one and power circuit in source electrode driver 20 and the gate drivers 30 50 is integrated.
2.1 gate drivers
Fig. 4 shows the structure example of the gate drivers 30 of Fig. 2 or Fig. 3.
The scanning voltage that output buffer 36 buffering has been shifted by level shifter 34, and output to gate line, thus the driving grid line.
2.2 source electrode driver
Fig. 5 shows the module map of configuration example of the source electrode driver 20 of Fig. 2 or Fig. 3.
From main frame 40 to line latch 24 input image datas (DIO).This view data for example every bit is represented with six.Line latch 24 with enable input/output signal EIO and latch this picture number (DIO) synchronously, wherein, this enables each trigger that input/output signal EIO is shifted register 22 and is shifted successively.In addition, view data can be to arrive line latch 24 with the Dot Clock synchronous driving from main frame 40, can also be sent to line latch 24 according to NTSC mode or PAL mode.
TV signal I/F circuit 62 generates inside the vertical synchronizing signal VDI and the horizontal-drive signal HDI of display driver 60 based on vertical synchronizing signal VDO and horizontal-drive signal HDO from main frame 40.
The edge (rising edge or negative edge) of the horizontal-drive signal HDI that line latch 26 is generated at TV signal I/F circuit 62 latchs the view data of a horizontal scanning unit being latched by line latch 24.
Reference voltage generating circuit 27 generates 64 (=2
6) reference voltage of planting.64 kinds of reference voltages that reference voltage generating circuit 27 is generated offer DAC 28.
DAC (data voltage generative circuit) 28 generates the simulation data voltage that offer each source electrode line.Specifically, DAC 28 is based on the Digital Image Data from line latch 26, selects from the reference voltage of reference voltage generating circuit 27 any one, output digital image data corresponding simulating data voltage.
Source line driving circuit 29 cushions from the data voltage of DAC 28 and exports to source electrode line, thus the drive source polar curve.Specifically, source line driving circuit 29 comprises the operational amplifier OPC (sensu lato impedance inverter circuit) that connects in the voltage follower mode of corresponding each source electrode line setting, these operational amplifiers OPC impedance transformation is from the data voltage of DAC 28, and exports to each source electrode line.
In addition, in Fig. 5, adopted Digital Image Data has been carried out the digital-to-analog conversion, and exported to the structure of source electrode line by source line driving circuit 29, but also can adopt the analog image signal is taken a sample/kept, and export to the structure of source electrode line by source line driving circuit 29.
Fig. 6 shows the structure example of reference voltage generating circuit 27, DAC 28 and the source line driving circuit 29 of Fig. 5.In Fig. 6, view data is six data D0 to D5, and XD0 to XD5 represents the reversal data of everybody data.In addition, in Fig. 6, part same as shown in Figure 5 is represented with identical Reference numeral, in this suitable explanation of omitting it.
Reference voltage generating circuit 27 carries out resistance to voltage VDDH, the VSSH at two ends to be cut apart, and generates 64 kinds of reference voltages.Represented each the GTG value of each reference voltage and six view data is corresponding.Each reference voltage is offered source electrode line S jointly
1～S
NEach source electrode line.
2.3 power circuit
Fig. 7 shows the structure example of the power circuit 50 of Fig. 2 or Fig. 3.
System earth supply voltage VSS and system power supply voltage VDD are provided on positive dirction twice booster circuit 52.And positive dirction twice booster circuit 52 is a benchmark with system earth supply voltage VSS, generates the supply voltage VOUT that system power supply voltage VDD is boosted to twice on positive dirction.That is to say that positive dirction twice booster circuit 52 is with the twice of boosting of the voltage difference between system earth supply voltage VSS and the system power supply voltage VDD.This positive dirction twice booster circuit 52 can be made of the known charge pump circuit.Supply voltage VOUT is provided for source electrode driver 20, scanning voltage generative circuit 54 and opposed electrode voltage generative circuit 56.In addition, preferred following mode, promptly positive dirction twice booster circuit 52 is adjusted voltage level with after boosting more than or equal to the multiplying power of boosting of twice by voltage stabilizer, and output boosts to system power supply voltage VDD the supply voltage VOUT of twice on positive dirction.
Charging clock forming circuit 58 generates the charging clock CHPMP of specified period based on not shown reference clock.Positive dirction twice booster circuit 52 is synchronous with charging clock CHPMP, carries out the charge pump action.
System earth supply voltage VSS and supply voltage VOUT are provided on scanning voltage generative circuit 54.And scanning voltage generative circuit 54 generates scanning voltage.Scanning voltage is the outer voltage that is added on the gate line that gate drivers 30 drives.The hot side voltage of this scanning voltage is VDDHG, and low potential side voltage is VEE.
Opposed electrode voltage generative circuit 56 generates opposed electrode voltage VCOM.Opposed electrode voltage generative circuit 56, is exported as opposed electrode voltage VCOM hot side voltage VCOMH or low potential side voltage VCOML according to polarity inversion signal POL.Polarity inversion signal POL is according to reversal of poles regularly, is generated by main frame 40.
Fig. 8 shows the structure example of the positive dirction twice booster circuit 52 of Fig. 7.In Fig. 8, represent with identical Reference numeral with same section shown in Figure 7, in this suitable explanation of omitting to it.Among this external Fig. 8, charge pump circuit is described as carrying out the circuit that twice boosts, but present embodiment not boosted multiplying power limit.
The transistor that positive dirction twice booster circuit 52 comprises as on-off element, the charging clock CHPMP that each transistor is generated by charging clock forming circuit 58 carries out switch control.Charging clock CHPMP comprises charging clock CK1 to CK3.
Positive dirction twice booster circuit 52 comprise to the P type that system power supply voltage VDD is provided on the source electrode (first conductivity type) burning film semiconductor (Metal OxideSemiconductor:MOS) transistor (below, be called for short " transistor ") PTr1, with and drain electrode be connected in N type (second conductivity type) transistor NTr1 in the drain electrode of transistor PTr1.System earth supply voltage VSS is provided on the source electrode of transistor NTr1.Charging clock CK1 is provided on the grid of transistor PTr1, NTr1.
In addition, positive dirction twice booster circuit 52 also comprises P transistor npn npn PTr2, PTr3.System power supply voltage VDD is provided in the drain electrode of transistor PTr2, and the source electrode of transistor PTr2 is connected with the drain electrode of P transistor npn npn PTr3.The source electrode of transistor PTr3 is connected in the splicing ear TC3 of power circuit 50 (or display driver 60) by output signal line SLX.Charging clock CK2 is provided on the grid of transistor PTr2.Charging clock CK3 is provided on the grid of transistor PTr3.
Power circuit 50 (or display driver 60) comprises splicing ear TC1～TC3.The connected node of splicing ear TC1 and transistor PTr1, NTr1 (drain node) is electrically connected by signal wire SL1.The connected node of splicing ear TC2 and transistor PTr2, PTr3 is electrically connected by signal wire SL2.
Between splicing ear TC1, TC2, connect flying capacitor FC1 in the outside of power circuit 50 (or display driver 60).At splicing ear TC3 with provide and be connected with the stable capacitor SC that uses between the power lead of system earth supply voltage VSS.
Positive dirction twice booster circuit shown in Figure 8 52 is exported to splicing ear TC3 with booster voltage 2V, and this booster voltage 2V is with the voltage of the boost in voltage between system power supply voltage VDD and the system earth supply voltage VSS to twice.
Fig. 9 represent to charge example of sequential of clock CK1～CK3 and each transistorized state of a control.In Fig. 9, the rising edge of each clock that charges is shown identical timing with the timing indicator of negative edge, but the timing of rising edge and negative edge of clock of charging of in fact preferably staggering is so that the not conducting simultaneously of two transistors (so that having during the so-called OFFOFF) that is connected in series.
At first, because transistor NTr1 conducting, transistor PTr1 end in period P H1, so system earth supply voltage VSS is provided on the end of the flying capacitor FC1 that is connected in splicing ear TC1.At this moment, transistor PTr2 conducting, transistor PTr3 end, so be connected in the other end of the flying capacitor FC1 of splicing ear TC2, connect the power lead that provides system power supply voltage VDD by signal wire SL2.Therefore, the pairing electric charge of voltage V between flying capacitor FC1 savings system power supply voltage VDD and the system earth supply voltage VSS in period P H1.
Secondly, in period P H2, transistor NTr1 ends, transistor PTr1 conducting, so an end that is connected in the flying capacitor FC1 of splicing ear TC1 is connected with the power lead that provides system power supply voltage VDD.Transistor PTr2 ends, transistor PTr3 conducting, so voltage 2V offers a stable end with capacitor SC by output signal line SLX, afterwards, sustaining voltage in stablizing with capacitor SC.
Figure 10 shows the structure example of the opposed electrode voltage generative circuit 56 of Fig. 7.
Opposed electrode voltage generative circuit 56 generates the outer opposed electrode voltage VCOM that is added on the opposite electrode CE, and wherein, the pixel electrode of opposite electrode CE and display panel (electrooptical device) 12 is opposed across liquid crystal cell (photoelectric material).This opposed electrode voltage generative circuit 56 comprises the operational amplifier that connects in the voltage follower mode, is first and second operational amplifier OP1, OP2 and selection change-over circuit SEL.Export the hot side voltage VCOMH of opposed electrode voltage VCOM as the first operational amplifier OP1 of the first opposed electrode voltage generation circuit.Export the low potential side voltage VCOML of opposed electrode voltage VCOM as the second operational amplifier OP2 of the second opposed electrode voltage generation circuit.Change-over circuit SEL according to the reversal of poles of the polarity of the outer voltage that is added on liquid crystal cell (photoelectric material) of counter-rotating regularly, with hot side voltage VCOMH and low potential side voltage VCOML one exports as opposed electrode voltage VCOM.In addition, the first operational amplifier OP1 and the second operational amplifier OP2 are moved as voltage stabilizer.
And input is used for the polarity inversion signal POL of specified polarity counter-rotating timing or the reverse signal of polarity inversion signal POL on opposed electrode voltage generative circuit 56.In Figure 10, input has polarity inversion signal POL.
Change-over circuit SEL can comprise P transistor npn npn PTr and N type (second conductivity type) transistor NTr.The source electrode of transistor PTr is connected in the output of the first operational amplifier OP1.The drain electrode of transistor PTr is electrically connected with opposite electrode CE.Polarity inversion signal POL is provided on the grid of transistor PTr.The source electrode of transistor NTr is connected with the output of the second operational amplifier OP2.The drain electrode of transistor NTr is electrically connected with opposite electrode CE.Polarity inversion signal POL is provided on the grid of transistor NTr.
This opposed electrode voltage generative circuit 56 can comprise VCOMH generative circuit (opposite electrode hot side voltage generation circuit) 72 and VCOML generative circuit (opposite electrode low potential side voltage generation circuit) 74.VCOMH generative circuit 72 can be for example based on system earth supply voltage VSS and supply voltage VOUT, the formation voltage VCOMH0 by the action of known charge pump.Voltage VCOMH0 offers the input of the first operational amplifier OP1.VCOML generative circuit 74 can be for example based on system earth supply voltage VSS and supply voltage VOUT, the formation voltage VCOML0 by the action of known charge pump.Voltage VCOML0 offers the input of the second operational amplifier OP2.Change-over circuit SEL exports among hot side voltage VCOMH or the low potential side voltage VCOML any one according to polarity inversion signal POL as opposed electrode voltage VCOM.
The relation of the supply voltage that generates according to the power circuit in the present embodiment 50 is shown to Figure 11 pattern.Among this external Figure 11, omit the diagram of voltage VDDHG, VEE, show the electric potential relation of voltage VOUT, VDDHS, VCOMH, VCOM, VCOML and VOUTM.
Voltage VOUT is with the voltage between system power supply voltage VDD and the system earth supply voltage VSS, is benchmark boosts to twice on positive dirction voltage with system earth supply voltage VSS.The positive dirction twice booster circuit 52 of power circuit 50 can comprise the operational amplifier REG1 as voltage stabilizer performance function.The hot side supply voltage of operational amplifier REG1 is voltage VOUT, and the low potential side supply voltage is system earth supply voltage VSS.Operational amplifier REG1 output voltage V DDHS.
In addition, the opposed electrode voltage generative circuit 56 of power circuit 50 comprises the first operational amplifier OP1 and the second operational amplifier OP2 as voltage stabilizer performance function.The hot side supply voltage of the first operational amplifier OP1 is voltage VOUT, and the low potential side supply voltage is system earth supply voltage VSS.The first operational amplifier OP1 output voltage V COMH.Voltage VOUTM is with the voltage between system power supply voltage VDD and the system earth supply voltage VSS, is boost on the negative direction voltage of one times (1 times) of benchmark with system earth supply voltage VSS.The hot side supply voltage of the second operational amplifier OP2 is voltage VDD, and the low potential side supply voltage is voltage VOUTM.The second operational amplifier OP2 output voltage V COML.As shown in figure 10, opposed electrode voltage generative circuit 56 hot side voltage VCOMH that will be generated by the first operational amplifier OP2 and the second operational amplifier OP3 according to polarity inversion signal POL or any one among the low potential side voltage VCOML are exported as opposed electrode voltage VCOM.
Figure 12 illustrates the example of drive waveforms of the display panel 12 of Fig. 2 or Fig. 3.
On source electrode line, add the gray scale voltage DLV of the GTG value that satisfies view data.In Figure 12, with system earth supply voltage VSS (=0V) be benchmark, add the gray scale voltage DLV of the amplitude of 5V.
On gate line, when non-select, add low potential side voltage VEE (=-10V), when selecting, add hot side voltage VDDHG (=15V) scanning voltage GLV.
On opposite electrode CE, add hot side voltage VCOMH (=3V), low-potential voltage VCOML (=-2V) opposed electrode voltage VCOM.And, with given voltage the polarity of voltage level of the opposed electrode voltage VCOM of benchmark, corresponding reversal of poles is regularly reversed.In Figure 12, the waveform of the opposed electrode voltage VCOM when so-called sweep trace inversion driving is shown.To should reversal of poles regularly, the gray scale voltage DLV of source electrode line also can be to be that benchmark, its polarity are reversed with given voltage.
, liquid crystal cell has the character that long-time impressed DC voltage will deterioration.Therefore, need the counter-rotating of every interval stipulated time to be added to the type of drive of the polarity of the voltage on the liquid crystal cell.As such type of drive, comprise frame inversion driving, scanning (grid) line inversion driving, data (source electrode) line inversion driving, some inversion driving etc.
Wherein, though the frame inversion driving is low in energy consumption, there is the so not desirable shortcoming of image quality.In addition, though data line inversion driving and some inversion driving image quality are good, exist the driving display panel to need high-tension shortcoming.
In the present embodiment, adopt sweep trace inversion driving (a line inversion driving).In this sweep trace inversion driving, make the outer voltage corresponding each scan period (corresponding each gate line) that is added on liquid crystal cell carry out reversal of poles.For example, as shown in figure 13, at first scan period (gate line), the voltage of positive polarity is added on the liquid crystal cell, in second scan period, the voltage of negative polarity is added on the liquid crystal cell,, the voltage of positive polarity is added on the liquid crystal cell in the 3rd scan period.On the other hand, at next frame, be that the voltage with negative polarity is added on the liquid crystal cell in first scan period specifically, the voltage in second scan period with positive polarity is added on the liquid crystal cell, and the voltage in the 3rd scan period with negative polarity is added on the liquid crystal cell.
And in this sweep trace inversion driving, the voltage level of the opposed electrode voltage VCOM of opposite electrode CE corresponding each scan period is carried out reversal of poles.
Here, during the positive pole T1 provide source electrode line gray scale voltage pixel electrode voltage level than the voltage level of opposed electrode CE high during.In this period T1, the outer voltage that is added with positive polarity on the liquid crystal cell.On the other hand, during the negative pole T2 provide source electrode line gray scale voltage pixel electrode voltage level than the voltage level of opposed electrode CE low during.In this period T2, the outer voltage that is added with negative polarity on the liquid crystal cell.
Like this, by reversal of poles opposed electrode voltage VCOM, can reduce driving the required voltage of display panel.In view of the above, can reduce the withstand voltage of driving circuit, thereby manufacturing process that can simplified driving circuit realizes low-cost.
The explanation of 3 present embodiments
In the present embodiment, ntsc video signal or PAL vision signal that display driver 60 receives from main frame 40 generate the synchronizing signal that drives usefulness as the display panel of inner usefulness.And, the view data that display driver 60 uses from main frame 40,, driving display panel 12 synchronous with this synchronizing signal.Thus, main frame 40 can carry out the demonstration control at not shown CRT device, and display driver 60 can directly use the display control signal (view data or synchronizing signal) of 40 pairs of CRT devices of main frame to carry out the display driver of display panel 12.
But, each mode of NTSC mode and PAL mode all is that the number of scanning lines of each frame (vertical scanning period) is an odd number, carries out based on interleaved demonstration.Therefore, can to replace view data, number of scanning lines that output scanning line number is the frame of even number be the view data of the frame of odd number to main frame 40.That is to say,, be arranged alternately the horizontal scan period of even number and the horizontal scan period of odd number in each vertical scanning period.So, display driver 60 comprises TV signal I/F circuit 62, vertical synchronizing signal VDO and horizontal-drive signal HDO from main frame 40 can be converted to vertical synchronizing signal VDI and the horizontal-drive signal HDI that display panel drives usefulness, synchronous with vertical synchronizing signal VDI and horizontal-drive signal HDI, use and carry out the driving of display panel 12 from the view data of main frame 40.
Figure 14 is the main action summary description figure of the TV signal I/F circuit 62 of present embodiment.
In Figure 14, for the purpose of simplifying the description, be that 25 situation describes to the number of scanning lines of a frame.When main frame 40 generated vertical synchronizing signal VDO and horizontal-drive signal HDO, alternately generating number of scanning lines every a frame was that the view data GDO and the number of scanning lines of the frame of odd number is the view data GDO of the frame of even number.In Figure 14, number of scanning lines alternately appear be 13 frame and number of scanning lines and be 12 frame.
TV signal I/F circuit 62 generates vertical synchronizing signal VDI and horizontal-drive signal HDI based on vertical synchronizing signal VDO and horizontal-drive signal HDO.At this moment, generate vertical synchronizing signal VDI, thereby be benchmark, with identical number of scanning lines (horizontal scan period number) pickup image data GDO with the edge (rising edge or negative edge) of vertical synchronizing signal VDI.In Figure 14, generate vertical synchronizing signal VDI, so that be that benchmark, number of scanning lines are 5 with the negative edge of vertical synchronizing signal VDI.
Figure 15 illustrates the structure example block diagram of TV signal I/F circuit 62.
TV signal I/.F circuit 62 comprises: negative edge testing circuit 120, counter 122, begin picked-up register 124, comparator circuit 126, electrical level judgment circuit 128 and VDI generative circuit 130 regularly are set.
Negative edge testing circuit 120 detects the negative edge from the vertical synchronizing signal VDO of main frame 40, detection signal is exported to counter 122 when detecting this rising edge.Counter 122 and given reference clock or the Dot Clock DCLK counting count value of appreciating synchronously, wherein, Dot Clock DCLK is with from the transmission of the view data of main frame 40 regularly synchronously.When the detection signal from negative edge testing circuit 120 when being active, this counter 122 counting count value that begins to appreciate.Regularly be provided with in the register 124 beginning picked-up, the picked-up that is used for edge with vertical synchronizing signal VDI and is benchmark regulation view data begins clock number regularly, for example is provided with by main frame 40.Comparator circuit 126 compares from the count value of counter 122 and begins to absorb the value of setting that register 124 regularly is set, and exports consistent pulse when both are consistent.
Input is from the horizontal-drive signal HDO of main frame 40 on electrical level judgment circuit 128, when being active, judges the logic level of horizontal-drive signal HDO in the consistent pulse from comparator circuit 126.The result of determination of electrical level judgment circuit 128 offers VDI generative circuit 130 and counter 122.When the horizontal-drive signal HDO when electrical level judgment circuit 128 judges that consistent pulse from comparator circuit 126 is active is the H level, the count value of count initialized device 122.When the horizontal-drive signal HDO when electrical level judgment circuit 128 judges that consistent pulse from comparator circuit 126 is active is the L level, generate the pulse of vertical synchronizing signal VDI by VDI generative circuit 130.Horizontal-drive signal HDI exports horizontal-drive signal HDO as it is.
By said structure, in the timing shown in Figure 14, can generate vertical synchronizing signal VDI and horizontal-drive signal HDI.
But, analysis according to the inventor, distinguish the following situation that exists: when correspondence every a frame scan line number alternately be converted to even number, odd number (that is to say, number of scanning lines is an odd number in a frame, in next frame, number of scanning lines is an even number) time, exist with ... the relation between reversal of poles cycle of cycle of charge pump action and opposite electrode, opposed electrode voltage is changed, cause taking place scintillation owing to put on the change in voltage of liquid crystal.
Figure 16 illustrates the test case waveform of the situation that opposed electrode voltage changes.
Originally, with given voltage VCOMC is the center, hot side voltage VCOMH and low potential side voltage VCOML are fixing voltage level, with reversal of poles regularly synchronously, the hot side voltage VCOMH or the low potential side voltage VCOML of fixed level exported as opposed electrode voltage VCOM.But in Figure 16, as one-period, the voltage level of the hot side voltage VCOMH of opposed electrode voltage VCOM and low potential side voltage VCOML changes with two vertical scanning period of vertical synchronizing signal VDI regulation.
Consequently, per 2 frames of potential difference (PD) between hot side voltage VCOMH and the low potential side voltage VCOML change, and also per 2 frames of the impressed voltage of liquid crystal change.For example the potential difference (PD) Δ VC1 between hot side voltage VCOMH and low potential side voltage VCOML during and the potential difference (PD) Δ VC2 between hot side voltage VCOMH and the low potential side voltage VCOML during in, even the gray scale voltage of source electrode line (or voltage of pixel electrode) is identical, the impressed voltage of liquid crystal also can change.Based on this, scintillation will take place, and make the image quality deterioration of display image.
Can think this be because the signal wire of the signal wire of the charging clock by being used for the regulation charge pump action cycle and opposed electrode voltage VCOM in abutting connection with configuration, thereby cause forming the capacitive coupling of electric capacity between wiring, in the variation timing of charging clock, the voltage level of opposed electrode voltage VCOM (hot side voltage VCOMH or low potential side voltage VCOML) changes.Can think that perhaps this is because provide because charge pump moves the signal wire of the signal wire of scanning voltage of the gate line generate and opposed electrode voltage VCOM in abutting connection with configuration, thereby the capacitive coupling of the electric capacity between wiring of causing being coupled, with the variation of charging clock regularly the variation of synchronous high-tension scanning voltage the voltage level of opposed electrode voltage VCOM (hot side voltage VCOMH or low potential side voltage VCOML) is changed.
Figure 17 illustrates the change cause description figure of the voltage level of opposed electrode voltage VCOM.
In Figure 17, for the purpose of simplifying the description, the number of scanning lines that a frame has been described is 11 situation, and wherein, number of scanning lines is that 5 frame and number of scanning lines are that 6 frame alternately occurs.In addition, as charging clock CHPMP, for example show the charging clock CK1 of Fig. 8 or Fig. 9.The charging clock CHPMP (CK1) with two horizontal scan period as one-period.Making by horizontal scan period of the opposed electrode voltage VCOM of line inversion driving is that hot side voltage VCOMH, a horizontal scan period are low potential side voltage CCOML.
But, number of scanning lines be the frame of odd number, promptly first frame and number of scanning lines be the frame of even number, promptly in second frame, as shown in figure 17, opposed electrode voltage VCOM be hot side voltage VCOMH during the regularly certain rising edge of beginning with charging clock CHPMP (CK1) overlapping.In addition, as shown in figure 17, opposed electrode voltage VCOM be low potential side voltage VCOML during the regularly certain negative edge of beginning with charging clock CHPMP (CK1) overlapping.
Therefore, pass through capacitive coupling, the voltage level of hot side voltage VCOMH, with the hot side voltage VCOMH0 that should export originally is that benchmark changes at hot side (Δ VH1), and the voltage level of low potential side voltage VCOML is benchmark change at low potential side (Δ VL1) with the low potential side voltage VCOML0 that should export originally.Therefore, in first frame and second frame, the amplitude of comparing original opposed electrode voltage VCOM is bigger amplitude (Δ VCOM1).
But, in the 3rd frame and the 4th frame, as shown in figure 17, opposed electrode voltage VCOM be hot side voltage VCOMH during the regularly certain negative edge of beginning with charging clock CHPMP (CK1) overlapping.In addition, as shown in figure 17, opposed electrode voltage VCOM be low potential side voltage VCOML during the regularly certain rising edge of beginning with charging clock CHPMP (CK1) overlapping.
Therefore, pass through capacitive coupling, the voltage level of hot side voltage VCOMH, with the hot side voltage VCOMH0 that should export originally is that benchmark changes at low potential side (Δ VH2), and the voltage level of low potential side voltage VCOML is benchmark change at hot side (Δ VL2) with the current potential side voltage VCOML0 that should export originally.Therefore, in the 3rd frame and the 4th frame, comparing original opposed electrode voltage VCOM amplitude is less amplitude (Δ VCOM2＜Δ VCOM1).
2 frames are carried out the change of above-mentioned voltage level as one-period.Its result can think to have determined waveform shown in Figure 16.Like this, because the hot side voltage VCOMH of opposed electrode voltage VCOM and low potential side voltage VCOML change voltage level by frame, even so on each frame identical gray scale voltage is applied on the pixel electrode, the impressed voltage of liquid crystal also can change.
For this reason, in the present embodiment, polarity at the impressed voltage (voltage between pixel electrode and the opposite electrode) of liquid crystal is between each polarity epoch of positive polarity and negative polarity, to have the mode of one or more rising edge and negative edge, generates charging clock CHPMP (CK1).Like this, the fixing voltage level of the hot side voltage VCOMH of opposed electrode voltage VCOM and low potential side voltage VCOML, thereby when being added with same gray level voltage outside avoiding in each frame on the pixel electrode, the situation that the impressed voltage of liquid crystal changes prevents the image quality deterioration.
Figure 18 illustrates the relation of charging in the present embodiment between clock and the opposed electrode voltage.
In Figure 18, for the purpose of simplifying the description, the number of scanning lines that a frame has been described is 11 situation, wherein, number of scanning lines alternately occurs and be 5 frame and number of scanning lines and be 6 frame.In addition, as charging clock CHPMP, show the charging clock CK1 of Fig. 8 for example or Fig. 9.The charging clock CHPMP (CK1) with two horizontal scan period as one-period.In addition, hot side voltage VCOMH only is shown in Figure 18, has omitted the diagram of low potential side voltage VCOML.In addition, be hot side voltage VCOMH by horizontal scan period of the opposed electrode voltage VCOM of line inversion driving, a horizontal scan period is low potential side voltage VCOML.
In the present embodiment, even number of scanning lines be the frame of odd number, promptly first frame and number of scanning lines be the frame of even number, promptly in the 2nd frame, opposed electrode voltage VCOM be hot side voltage VCOMH during, also have rising edge and the negative edge of charging clock CHPMP (CK1).In addition, opposed electrode voltage VCOM be low potential side voltage VCOML during, have rising edge and the negative edge of charging clock CHPMP (CK1).Therefore, the influence of the variation of the charging clock CHPMP that feeds through to hot side voltage VCOMH can be offset, simultaneously, the influence of the variation of the charging clock CHPMP that feeds through to low potential side voltage VCOML can be offset.Therefore, in each frame, the fixing voltage level of the hot side voltage VCOMH of opposed electrode voltage VCOM and low potential side voltage VCOML, thereby when being added with same gray level voltage outside avoiding in each frame on pixel electrode, the situation that the impressed voltage of liquid crystal changes, and prevent the image quality deterioration.That is to say, even under the different situation of the number of scanning lines of each frame, also can provide suppress that flicker reduces, the power circuit of steady display grade and the display driver etc. that comprises this power circuit.In addition, according to present embodiment, the signal wire of signal wire, low potential side voltage VCOML of signal wire, the hot side voltage VCOMH of signal wire, the opposed electrode voltage VCOM of charging clock CHPMP and the signal wire of the booster voltage that generates by the charge pump action need not be considered to dispose, also the image quality deterioration can be prevented.
3.1 variation
In the present embodiment, the charging clock forming circuit 58 to power circuit 50 describes, but not only is defined in this with the cycle of fixing, the situation that generates charging clock CHPMP.
Figure 19 illustrates the structure example block diagram of the power circuit 50 in first variation of present embodiment.
Part identical with Fig. 7 in Figure 19 is with identical Reference numeral, in the explanation of this omission to it.The difference of power circuit in first variation and the power circuit of Fig. 7 50 is to have increased the charging clock period register 200 is set.In addition, the charging clock forming circuit 202 that replaces charging clock forming circuit 58 to be provided with generates with the clock period of charging the set controlling value of the register 200 charging clock CHPMP in corresponding cycle is set.
Charging is provided with register 200 and constitutes and can carry out access by main frame 40 clock period, is provided for specifying the controlling value of the Cycle Length (frequency) of charging clock CHPMP by main frame 40.The charging clock period is provided with register 200 the pairing control signal CKMODE of controlling value is offered charging clock forming circuit 202.
Figure 20 shows the structure example block diagram of the charging clock forming circuit 202 of Figure 19.
Charging clock forming circuit 202 comprises a plurality of frequency dividers 210
1～210
P(P is the integer more than or equal to 2) and selector switch 220.At frequency divider 210
1On Dot Clock DCLK as reference clock for example is provided, output frequency division the frequency-dividing clock DKO1 of Dot Clock DCLK.At frequency divider 210
2On frequency divider 210 is provided
1Output, be frequency-dividing clock DKO1, output frequency division the frequency-dividing clock DKO2 of frequency-dividing clock DKO1.Equally, on frequency divider 210p, provide frequency divider 210
P-1Output, be frequency-dividing clock DKO (P-1), the frequency-dividing clock DKOP of output frequency division frequency-dividing clock DKO (P-1).
On selector switch 220, input frequency-dividing clock DKO1～DKOP and control signal CKMODE, according to control signal CKMODE with among frequency-dividing clock DKO1～DKOP any one, as charging clock CK1, CK30 output.In addition, counter-rotating charging clock CK1, output charging clock CK20.
Charging clock CK30, CK20 export as charging clock CK3, CK2 after the changing voltage level.
According to above structure, charging clock forming circuit 202 can generate charging clock CK1～CK3 for example shown in Figure 9.
In addition, in the present embodiment, to the polarity at the impressed voltage (voltage between pixel electrode and the opposite electrode) of liquid crystal is between each polarity epoch of positive polarity and negative polarity, to have the mode of one or more rising edge and negative edge, the situation that generates charging clock CHPMP (CK1) is illustrated, but not only is defined in this.
Figure 21 illustrates charging clock in second variation of present embodiment and the relation between the opposed electrode voltage.
In Figure 21, the same with Figure 18, for the purpose of simplifying the description, the number of scanning lines that a frame has been described is 11 situation, wherein, number of scanning lines alternately occurs and be 5 frame and number of scanning lines and be 6 frame.In addition, as charging clock CHPMP, show the charging clock CK1 of Fig. 8 for example or Fig. 9.The charging clock CHPMP (CK1) with two horizontal scan period as one-period.In addition, in Figure 21, only show hot side voltage VCOMH, and omitted the diagram of low potential side voltage VCOML.
As shown in figure 21, in second variation, the variation of charging clock CHPMP (CK1) is regularly regularly identical with the variation of opposed electrode voltage VCOM.
Like this, number of scanning lines be the frame of odd number, promptly first frame and number of scanning lines be the frame of even number, promptly in second frame, opposed electrode voltage VCOM be hot side voltage VCOMH during the regularly certain rising edge of beginning with charging clock CHPMP (CK1) overlapping.In addition, as shown in figure 21, opposed electrode voltage VCOM be low potential side voltage VCOML during beginning regularly (timing, constantly) certain negative edge with charging clock CHPMP (CK1) is overlapping.
Therefore, the same with Figure 17, pass through capacitive coupling, the voltage level of hot side voltage VCOMH, with the former hot side voltage that should export is that benchmark changes at hot side, and the voltage level of low potential side voltage VCOML is that benchmark changes at low potential side with the former low potential side voltage that should export.Therefore, in first frame and second frame, be in a ratio of bigger amplitude with the amplitude of originally opposed electrode voltage VCOM.
Be directed to this, in 2 frames that the next one connects, as shown in figure 21, opposed electrode voltage VCOM be hot side voltage VCOMH during the regularly certain rising edge of beginning with charging clock CHPMP (CK1) overlapping.In addition, as shown in figure 21, opposed electrode voltage VCOM be low potential side voltage VCOML during the regularly certain negative edge of beginning with charging clock CHPMP (CK1) overlapping.In this with shown in Figure 17 different.Therefore, opposed electrode voltage VCOM changes, so that these 2 continuous frames are identical with second frame with the first above-mentioned frame.But, because of same change takes place in each frame, thus not the change that the voltage level of opposed electrode voltage VCOM periodically takes place, consequently, even in each frame, be added with identical gray scale voltage outside on pixel electrode, the situation that also can avoid the impressed voltage of liquid crystal to change.
4. electronic equipment
Figure 22 illustrates the structural outline block diagram of the electronic equipment of the display driver that has been suitable for the present embodiment first or second variation.Here, as electronic equipment, show the structural outline of digital camera.In Figure 22, the part identical with Fig. 1 represented with identical Reference numeral, and suitably omitted the explanation to it.
Vertical synchronizing signal VDO, horizontal-drive signal HDO and view data GDO that main frame 40 generates according to NTSC mode or PAL mode, and offer display driver 60.Display driver 60 is converted to vertical synchronizing signal VDI and the horizontal-drive signal HDI that display panel drives usefulness to vertical synchronizing signal VDO and horizontal-drive signal HDO, and drives display panel 12.
In addition, digital camera 600 comprises splicing ear TL1, TL2, by splicing ear TL1, TL2, is connected with CRT device 700.Vertical synchronizing signal VDO that main frame 40 is generated and horizontal-drive signal HDO by splicing ear TL1, offer CRT device 700.The view data that the CRT device that main frame 40 is generated shows usefulness by splicing ear TL2, offer CRT device 700.CRT device 700 is based on vertical synchronizing signal VDO, horizontal-drive signal HDO and view data from main frame 40, display image.
Like this, digital camera 600 can offer CRT device 700 at the display synchronization signal that main frame 40 is generated, and on CRT device 700 display image, simultaneously, on display panel 12, show by display driver 60.
And the present invention is not limited to the foregoing description, in invention aim scope of the present invention various modification can be arranged.For example, the present invention not merely is applicable to the driving of above-mentioned display panels, also goes for the driving of electroluminescence, plasma display system.
In addition, in the related technical scheme of dependent claims in the present invention, can be the structure of omitting the structure important document part of the claim of being quoted.In addition, the portion that of the related technical scheme of independent claims of the present invention 1 also can be subordinated to other independent claims.
Description of reference numerals
10 liquid-crystal apparatus, 12 display floaters
20 source electrode drive circuits 22,32 shift registers
24,26 line latch, 27 reference voltage generating circuits
28 DAC, 29 source line driving circuit
30 gate drivers, 34 level shifters
36 output buffers, 40 main frames
50 power circuits, 60 display drivers
62 vision signal I/F circuit CE opposite electrodes
G
1～G
MGate lines G DI, GDO view data
HDI, HDO horizontal-drive signal S1～S
NSource electrode line
VCOM hot side voltage VCOML low potential side voltage
VDI, VDO vertical synchronizing signal
Claims (15)
1. a power circuit is used for to opposite electrode output opposed electrode voltage, and a plurality of pixel electrodes that described opposite electrode and electrooptical device had are provided with across photoelectric material, and described power circuit is characterised in that, comprising:
Booster circuit is used to generate booster voltage, and described booster voltage is the voltage by boosting with the charge pump action of charging clock synchronization; And
The opposed electrode voltage generative circuit, the hot side voltage or the low potential side voltage that will generate based on described booster circuit are exported to described opposite electrode as described opposed electrode voltage;
Wherein, be between each polarity epoch of positive polarity and negative polarity in the polarity of the voltage between described a plurality of pixel electrodes and the described opposite electrode, have the rising edge of described charging clock and the negative edge of described charging clock.
2. power circuit according to claim 1 is characterized in that, also comprises:
The scanning voltage generative circuit, described scanning voltage generative circuit is used to generate the scanning voltage on the gate line that is added to described electrooptical device,
Wherein, described scanning voltage generative circuit generates described scanning voltage by the charge pump action with described charging clock synchronization.
3. power circuit according to claim 1 and 2 is characterized in that:
Each vertical scanning period all has been arranged alternately even number horizontal scan period and odd number horizontal scan period,
Described opposed electrode voltage generative circuit is exported described opposed electrode voltage by a line inversion driving to described opposite electrode.
4. according to each described power circuit in the claim 1 to 3, it is characterized in that:
The one-period of described charging clock is equivalent to the length of two horizontal scan period.
5. according to each described power circuit in the claim 1 to 3, it is characterized in that:
The variation of described charging clock is regularly regularly identical with the variation of described opposed electrode voltage.
6. a driving circuit is used to drive electrooptical device, and described electrooptical device comprises: many gate lines; Many source electrode lines; A plurality of pixel electrodes; And a plurality of on-off elements, each on-off element of selecting by each gate line is electrically connected each source electrode line and each pixel electrode, and described driving circuit is characterised in that, comprising:
Source line driving circuit is used to drive described many source electrode lines; And
According to each described power circuit in the claim 1 to 5.
7. driving circuit according to claim 6 is characterized in that, also comprises: gate line drive circuit is used to scan described many gate lines.
8. an electrooptical device is characterized in that, comprising:
Many gate lines;
Many source electrode lines;
A plurality of pixel electrodes;
A plurality of on-off elements, each on-off element of selecting by each gate line is electrically connected each source electrode line and each pixel electrode;
Opposite electrode is provided with across photoelectric material with described a plurality of pixel electrodes; And
According to each described power circuit in the claim 1 to 5.
9. electrooptical device according to claim 8 is characterized in that, also comprises:
Source line driving circuit is used to drive described many source electrode lines.
10. an electronic equipment is characterized in that: comprise according to each described power circuit in the claim 1 to 5.
11. an electronic equipment is characterized in that: comprise according to Claim 8 or 9 described power circuits.
12. an opposite electrode driving method is used to drive the opposite electrode that a plurality of pixel electrodes of being had with electrooptical device are provided with across photoelectric material, described opposite electrode driving method is characterised in that and may further comprise the steps:
Generate booster voltage, described booster voltage is the voltage by boosting with the charge pump action of charging clock synchronization;
The hot side voltage or the low potential side voltage that will generate based on described booster voltage are exported to described opposite electrode as opposed electrode voltage;
Polarity at the voltage between described a plurality of pixel electrodes and the described opposite electrode is between each polarity epoch of positive polarity and negative polarity, has the rising edge of described charging clock and the negative edge of described charging clock.
13. opposite electrode driving method according to claim 12 is characterized in that:
Each vertical scanning period all has been arranged alternately even number horizontal scan period and odd number horizontal scan period,
Export described opposed electrode voltage by a line inversion driving to described opposite electrode.
14., it is characterized in that according to claim 12 or 13 described opposite electrode driving methods:
The one-period of described charging clock is equivalent to the length of two horizontal scan period.
15., it is characterized in that according to claim 12 or 13 described opposite electrode driving methods:
The variation of described charging clock is regularly regularly identical with the variation of described opposed electrode voltage.
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| CNA2007101631326A Pending CN101162570A (en) | 2006-10-10 | 2007-10-10 | Power supply circuit, driver circuit, electro-optical device, electronic instrument, and common electrode drive method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110675801A (en) * | 2019-05-23 | 2020-01-10 | 友达光电股份有限公司 | Display device and common electrode signal generating circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110675801A (en) * | 2019-05-23 | 2020-01-10 | 友达光电股份有限公司 | Display device and common electrode signal generating circuit |
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