TWI675359B

TWI675359B - Gate driving apparatus

Info

Publication number: TWI675359B
Application number: TW107141083A
Authority: TW
Inventors: 林志隆; 曾金賢; 賴柏成; 鄭貿薰; 馬玫生
Original assignee: 友達光電股份有限公司
Priority date: 2018-06-14
Filing date: 2018-11-19
Publication date: 2019-10-21
Also published as: TW202001849A; TWI673704B; TWI699742B; TW202001863A; TWI677865B; TW202001862A; TWI670707B; TW202001840A; TW202001839A; TW202001848A; TWI688943B; TW202001865A; TWI688942B; TW202001864A

Abstract

The gate driving device includes a plurality of shift temporary storage circuits. In the N-th stage temporary storage circuit, the output stage circuit generates the N-th gate driving signal according to the first control signal, the second control signal, and the first mode selection signal. The first voltage regulator adjusts the first control signal according to the second control signal. The second voltage regulator adjusts the first control signal according to a second mode selection signal, a previous-stage gate driving signal, or a start pulse signal. The third voltage regulator adjusts the first control signal according to the gate driving signal of the subsequent stage. The fourth voltage regulator adjusts the second control signal according to the first mode selection signal. The fifth voltage regulator adjusts the second control signal according to the reverse clock signal, the second mode selection signal, and the first control signal.

Description

Gate drive

The present invention relates to a gate driving device, and more particularly, to a gate driving device for driving a display panel.

In the synchronous light emitting active pixel circuit, all pixels need to be turned on for a long time during the compensation phase, so that the variation of the on-voltage of the thin film transistor in the pixels can be compensated simultaneously. In the subsequent data access phase, the pixel circuits need to be turned on one by one to perform data writing operations on the pixel circuits one by one.

In the conventional technical field, pixel circuits that emit light synchronously often face various problems. First, a special signal needs to be set in the pixel circuit that emits light synchronously to indicate the progress of the compensation phase and the data access phase. Second, when it is applied to a high-resolution display panel, a sufficient data writing time is required; Third, when a thin-film transistor manufactured by a low-temperature polycrystalline silicon process is used in the gate driving circuit, when the thin-film transistor is disconnected, it can still have a relatively high electron mobility and easily cause leakage at the circuit node. phenomenon.

The invention provides a gate driving device, which can be applied to a high-resolution display panel.

The gate driving device of the present invention includes a plurality of shift temporary storage circuits. A plurality of shift temporary storage circuits are coupled in series with each other and generate a plurality of gate driving signals respectively. The N-th stage shift temporary storage circuit includes an output stage circuit, a first voltage regulator, a second voltage regulator, Three voltage regulators, a fourth voltage regulator, and a fifth voltage regulator. The output stage circuit has a first control terminal and a second control terminal to receive the first control signal and the second control signal, respectively. The output stage circuit charges the output terminal according to the first control signal, the second control signal and the first mode selection signal to provide a clock signal, a high gate voltage or a low gate voltage to generate an Nth stage gate driving signal. The first voltage regulator is coupled between the first control terminal and the second control terminal, and provides a gate high voltage to adjust the first control signal according to the second control signal. The second voltage regulator is coupled to the first control terminal, and adjusts the first control signal according to the second mode selection signal, the previous-stage gate driving signal, or the start pulse signal. The third voltage regulator is coupled to the first control terminal, and provides a gate high voltage to adjust the first control signal according to a subsequent gate driving signal. The fourth voltage regulator is coupled to the second control terminal, and selects a signal according to the first mode to provide a high gate voltage to adjust the second control signal. The fifth voltage regulator is coupled to the second control terminal and provides a reverse clock signal or a high gate voltage to adjust the second control signal according to the reverse clock signal, the second mode selection signal, and the first control signal.

Based on the above, the gate driving device of the present invention adjusts the control signal on the control terminal through a plurality of voltage regulators, and controls the output stage circuit to generate a gate driving signal by the control signal. In this way, the gate driver can generate a plurality of gate driving signals with a consistent waveform during the compensation phase, and generate a plurality of gate driving signals that are sequentially enabled in the subsequent writing phase.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

Please refer to FIG. 1, which is a schematic diagram of a gate driving device according to an embodiment of the present invention. The gate driving device includes a plurality of shift temporary storage circuits coupled in series with each other, and generates a plurality of gate driving signals respectively. Taking the N-stage shift register circuit 100 as an example, the shift register circuit 100 includes an output stage circuit 110 and voltage regulators 120-160. The output stage circuit 110 has a first control terminal CE1 and a second control terminal CE2. The first control terminal CE1 and the second control terminal CE2 receive the first control signal Q _[N] and the second control signal P _{[N], respectively} . The output stage circuit 110 provides the clock signal CK, the gate high voltage V _GH or the gate low voltage V _GL to output according to the first control signal Q _[N] , the second control signal P _[N], and the mode selection signal SS The terminal OE is charged, and the N-th gate driving signal G _{[N] is} generated. Wherein, when the mode selection signal SS is at a low voltage level, the output stage circuit 110 may provide the gate low voltage V _GL to charge the output terminal OE to pull down the voltage value of the Nth gate drive signal G _[N] . In this embodiment, the mode selection signals SS and SR are used to instruct the shift register circuit 100 to operate in a compensation phase or a write phase.

In this embodiment, the output stage circuit 110 includes transistors T3, T4, T11, and a capacitor C1. The first terminal of the transistor T3 receives the clock signal CK, the second terminal of the transistor T3 is coupled to the output terminal OE, and the control terminal of the transistor T3 receives the first control signal Q _[N] . A first terminal of the transistor T11 is coupled to the output terminal OE, a second terminal of the transistor T11 receives the gate high voltage V _GH , and a control terminal of the transistor T11 receives a second control signal P _[N] . The first terminal of the transistor T4 receives the gate low voltage V _GL , the second terminal of the transistor T4 is coupled to the output terminal OE, and the control terminal of the transistor T4 receives the mode selection signal SS. In addition, the capacitor C1 is connected in series between the control terminal of the transistor T3 and the output terminal OE.

The voltage regulator 120 is coupled between the first control terminal CE1 and the second control terminal CE2. A second voltage regulator 120 based on a control signal P _[N] in order to provide a very high gate voltage V _GH to adjust the first control signal Q _[N], wherein, when the second control signal P _[N] to a low voltage level, The voltage regulator 120 may provide a gate high voltage V _GH to pull up the voltage value of the first control signal Q _[N] .

In this embodiment, the voltage regulator 120 includes transistors T10 and T12. The transistors T10 and T12 are connected in series between the first control terminal CE1 and the gate high voltage V _GH in this order. The control terminals of the transistors T10 and T12 jointly receive the second control signal P _[N] .

In other embodiments of the present invention, the voltage regulator 120 may include only a single transistor. In fact, the voltage regulator 120 may be provided with one or more transistors connected in series, and the number of the transistors is not limited. The circuit structure of multiple transistors in series can reduce the leakage between nodes.

The voltage regulator 130 is coupled to the first control terminal CE1. The voltage regulator 130 adjusts the first control signal Q _[N] according to the mode selection signal SR, the previous-stage gate driving signal G _[N-1] or the start pulse signal ST, wherein the current-stage gate driving signal G _{[ N-1]} or the start pulse signal ST is at a low voltage level, and the mode selection signal SR is also at a low voltage level, the voltage regulator 130 may be based on the previous gate driving signal G _[N-1] or from The pulse signal ST is used to pull down the voltage value of the first control signal Q _[N] .

To explain in detail, the voltage regulator 130 of this embodiment includes transistors T1 and T2. The control terminal of the transistor T1 is coupled to the first terminal of the transistor T1, and forms a coupling configuration of a diode configuration. In this embodiment, the cathode of the diode constructed by transistor T1 receives the previous gate driving signal G _[N-1] or the starting pulse signal ST, and its anode is coupled to the first of transistor T2. end. The first terminal of the transistor T2 is coupled to the second terminal of the transistor T1, the second terminal of the transistor T2 is coupled to the first control terminal CE1, and the control terminal of the transistor T2 receives the mode selection signal SR.

The voltage regulator 140 is coupled to the first control terminal CE1. The voltage regulator 140 provides the gate high voltage V _GH to adjust the first control signal Q _[N] according to the gate driving signal G _{[N + 1] of the} rear stage, and when the gate driving signal G _{[N + 1 of the} rear stage is adjusted _{When the} voltage is at a low voltage level, the voltage regulator 140 may provide a gate high voltage V _GH to pull up the voltage value of the first control signal Q _[N] .

In this embodiment, the voltage regulator 140 includes transistors T7 and T13. The transistors T7 and T13 are connected in series between the first control terminal CE1 and the gate high voltage V _GH in this order. The control terminals of the transistors T7 and T13 jointly receive the gate driving signal G _{[N + 1] of the} subsequent stage.

In other embodiments of the present invention, the voltage regulator 140 may include only a single transistor. In fact, the voltage regulator 140 can also be provided with one or more transistors connected in series, and there is no fixed limit on the number of the transistors, so as to reduce the leakage between nodes through the circuit structure of the transistors connected in series.

The voltage regulator 150 is coupled to the second control terminal CE2. The voltage regulator 150 provides the gate high voltage V _GH to adjust the second control signal P _{[N] according to the} mode selection signal SS, where the voltage regulator 150 provides the gate high when the mode selection signal SS is at a low voltage level. The voltage V _GH increases the voltage value of the second control signal P _[N] .

In the present embodiment, the voltage regulator 150 includes a transistor T9. The transistor T9 is connected in series between the second control terminal CE2 and the gate high voltage V _GH . The control terminal of the transistor T9 receives the mode selection signal SS. It is worth mentioning that the number of transistors included in the voltage regulator 150 may be one or more. The illustration in FIG. 1 is for illustrative purposes only, and is not intended to limit the scope of the present invention.

The voltage regulator 160 is coupled to the second control terminal CE2. The voltage regulator 160 adjusts the second control signal P _[N] according to the reverse clock signal XCK, the mode selection signal SR, and the first control signal Q _[N] to provide the reverse clock signal XCK or the gate high voltage V _GH _. . The voltage regulator 160 includes transistors T5, T6, and T8. The control terminal of the transistor T5 is coupled to the first terminal of the transistor T5, and forms a coupling configuration of a diode configuration. In this embodiment, the cathode of the diode constructed by the transistor T5 receives the reverse clock signal XCK, and the anode thereof is coupled to the first terminal of the transistor T6. The first terminal of transistor T6 is coupled to the anode of the diode constructed by transistor T5, the second terminal of transistor T6 is coupled to the second control terminal CE2, and the control terminal of transistor T6 receives the mode selection signal SR. The first terminal of the transistor T8 is coupled to the second terminal of the transistor T6. The second terminal of the transistor T8 receives the gate high voltage V _GH , and the control terminal of the transistor T8 receives the first control signal Q _[N] .

For details of the operation of the shift register circuit 100, please refer to FIG. 2 and FIG. 3A to FIG. 3H at the same time. FIG. An equivalent circuit diagram of a shift register circuit according to an embodiment of the invention.

Please refer to FIG. 2 and FIG. 3A. In the initial time interval TA0, the gate driving device is in a normal operation stage. At this time, the mode selection signal SS is at a high voltage level (equal to the gate high voltage V _GH ), and the mode selection signal SR is Low voltage level (equal to the gate low voltage V _GL ). When the reverse clock signal XCK is at a low voltage level (equal to the gate low voltage V _GL ), the transistor T5 in the voltage regulator 150 conducts reversely and the transistor T6 selects the signal according to the mode of the low voltage level. SR is turned on, so that the voltage value of the second control signal P _[N] is equal to V _GL + | V _{TH_T5} |, where V _{TH_T5} is the on voltage of the transistor T5.

The transistors T10 and T12 in the voltage regulator 120 are turned on according to the second control signal P _[N] which is the voltage value V _GL + | V _{TH_T5} | to provide the gate high voltage V _GH to pull up the first The voltage value of the control signal Q _[N] . At this time, the transistor T11 in the output stage circuit 110 is turned on according to the second control signal P _[N] , and the transistor T3 in the output stage circuit 110 is turned off according to the first control signal Q _[N] , and the output stage circuit 110 corresponds to the N-th stage gate driving signal G _[N] generated as a high voltage level. At the same time, the gate driving signal G _{[N + 1]} generated by the post-stage shift register is also at a high voltage level (equal to the gate high voltage V _GH ). In addition, when the output stage circuit 110 does not belong to the first stage shift register circuit, the previous stage gate driving signal G _[N-1] generated by the previous stage shift register is also at a high voltage level.

Incidentally, in the initial time interval TA0, the transistor T1 in the voltage regulator 130 is based on the previous-stage gate driving signal G _[N-1] equal to the high voltage level (equal to the gate high voltage V _GH ) or higher. The pulse wave signal ST is turned off. The transistors T7 and T13 in the voltage regulator 140 are turned off according to the gate driving signal G _{[N + 1]} of the subsequent stage equal to the high voltage level. The transistor T9 in the voltage regulator 150 and the transistor T4 in the output stage circuit 110 are turned off according to the mode selection signal SS equal to the high voltage level. The transistor T8 in the voltage regulator 160 is turned off according to the first control signal Q _[N] equal to the high voltage level (equal to the gate high voltage V _GH ).

It is worth mentioning that the voltage regulator 130 may receive the starting pulse wave signal ST, or may also receive the previous-stage gate driving signal G _[N-1] . The voltage regulator 130 may decide to receive the starting pulse wave signal ST or the previous-stage gate driving signal G _[N-1] according to the position of the shift register circuit to which it belongs. To put it simply, when the voltage regulator 130 belongs to the first stage of the temporary storage circuit, the voltage regulator 130 can receive the start pulse signal ST, and when the voltage regulator 130 does not belong to the first stage of the temporary storage circuit. In the circuit, the voltage regulator 130 can receive the previous-stage gate driving signal G _[N-1] .

Please refer to FIG. 2 and FIG. 3B. In the time interval TA1 after the initial time interval TA0, the gate driving device enters a compensation phase. At the same time, the mode selection signal SR transitions to the high voltage level (equal to the gate high voltage V _GH ), and the mode selection signal SS transitions from the gate high voltage V _GH to the voltage value V _{GL_L} , where the voltage value V _{GL_L is} lower than the gate low voltage V _GL . Based on the transition of the mode selection signal SS to be equal to the voltage value V _{GL_L} , the transistor T4 in the output stage circuit 110 will be turned on according to the mode selection signal SS to provide the gate low voltage V _GL to charge the output terminal OE, and The voltage value of the N-th gate driving signal G _[N] is pulled down to generate an N-th gate driving signal G _[N] equal to the gate low voltage V _GL .

It is worth noting that the mode selection signal SS received by all the shift temporary storage circuits is the same. Therefore, in the time interval TA1, the voltage value of the gate driving signal G _[N-1] of the N-1th stage will be Synchronously pulled down to the gate low voltage V _GL according to the mode selection signal SS, and the voltage value of the N + 1th stage gate drive signal G _{[N + 1]} is also pulled down to the gate synchronously according to the mode selection signal SS Low voltage V _GL . In this way, the gate driving device enables all the gate driving signals to be enabled (pulled down) at the same time, and can perform the compensation action of the thin film transistors of all pixel circuits.

On the other hand, at this time, the voltage regulator 140 is turned on according to the pulled-down gate driving signal G _{[N + 1]} , and provides the gate high voltage V _GH to continue to pull up the first control signal Q _{[N ]} . The transistor T9 in the voltage regulator 150 is turned on according to the mode selection signal SS which is the voltage level V _{GL_L} and provides the gate high voltage V _GH to pull up the second control signal P _[N] . At this time, the voltage regulator 120 is turned off according to the second control signal P _[N] being pulled up. The transistor T11 in the output stage circuit 110 is also turned off according to the second control signal P _[N] , and the transistor T3 in the output stage circuit 110 is continuously turned off according to the first control signal Q _[N] .

Incidentally, the transistor T5 in the voltage regulator 160 can be turned on or off according to the reverse clock signal XCK, and the transistor T6 can be turned off according to the mode selection signal SR which is a high voltage level. And the transistor T8 continues to be turned off according to the first control signal Q _[N] being pulled up. The transistor T9 in the voltage regulator 150 is turned off according to the mode selection signal SS which is the voltage level V _{GL_L} . The transistor T2 in the voltage regulator 130 is turned off according to the mode selection signal SR which is a high voltage level.

Please refer to FIG. 2 and FIG. 3C. In the time interval TA2 after the time interval TA1, the gate driving device is reset to end the compensation phase of the gate driving device. In the time interval TA2, the mode selection signal SR transitions from the gate high voltage V _GH to a low voltage level (equal to the gate low voltage V _GL ), and the mode selection signal SS transitions from the gate low voltage V _GL to high Voltage level (equal to gate high voltage V _GH ). At this time, the transistor T5 in the voltage regulator 150 is turned on according to the reverse clock signal XCK of the low voltage level (equal to the gate low voltage V _GL ), and the transistor T6 is based on the low voltage level. The mode selection signal SR is turned on so that the voltage value of the second control signal P _[N] is pulled down to be equal to V _GL + | V _{TH_T5} |. At the same time, the transistors T10 and T12 in the voltage regulator 120 will be turned on according to the second control signal P _[N], which is the voltage value V _GL + | V _{TH_T5} | to pull up the first control signal Q _[N The voltage value of _] is pulled up to be equal to the gate high voltage V _GH .

At this time, the transistor T11 in the output stage circuit 110 is turned on according to the second control signal P _[N] , and the transistor T3 in the output stage circuit 110 is turned off according to the first control signal Q _[N] , and the output stage circuit 110 generates an N-th gate driving signal G _[N] which is a high voltage level (equal to the gate high voltage V _GH ). At the same time, the gate driving signal G _{[N + 1]} generated by the post-stage shift register is simultaneously pulled up to a high voltage level. In addition, when the output stage circuit 110 is not a first-stage shift register circuit, the previous-stage gate drive signal G _[N-1] generated by the previous-stage shift register is also pulled up to high simultaneously. Voltage level.

It should be noted that the operation waveforms and operation modes of the other gate driving devices in this time interval TA2 are similar to the aforementioned operation waveforms and operation modes in the initial time interval TA0 (also in the normal operation phase), so they are not described here. Repeat.

Please refer to FIG. 2 and FIG. 3D. In the time interval TA3, the gate driving device enters the first sub-phase of the writing phase. In the time interval TA3, the mode selection signal SS is maintained at a high voltage level (equal to the gate high voltage V _GH ), and the mode selection signal SR is maintained at a low voltage level (equal to the gate low voltage V _GL ). At this time, the transistor T2 in the voltage regulator 130 is turned on according to the mode selection signal SR that is a low voltage level, and the transistor T1 in the voltage regulator 130 is turned to a low voltage level (equal to the gate) Low voltage V _GL ) is turned on by the starting pulse wave signal ST or the previous gate driving signal G _[N-1] to transmit the starting pulse wave signal ST or the previous stage through the turned-on transistors T1 and T2. The gate driving signal G _[N-1] pulls down the voltage value of the first control signal Q _[N] . At this time, the voltage value of the first control signal Q _[N] is equal to V _GL + | V _{TH_T1} |, where V _{TH_T1} is the on-voltage of transistor T1.

As the voltage value of the first control signal Q _[N] is pulled down, the transistor T8 in the voltage regulator 160 is turned on, and the transistor T5 is switched from the gate high voltage V _GH to the gate low voltage V The reverse clock signal XCK of _GL is turned on, and the transistor T6 is turned on according to the mode selection signal SR, thereby providing the reverse clock signal XCK and the gate high voltage V _GH to pull up the second control signal P _{[ N]} . Thus, in the present embodiment, the second control signal P _[N] in the time interval can be pulled TA3 slightly lower than the voltage level equal to V _GH- DV2 gate voltage V _GH is high. Among them, DV2 is an offset value, and V _GH > V _GH- DV2> V _GL + | V _{TH_T5} |. At the same time, the voltage regulator 120 is turned off according to the second control signal P _[N] that is pulled up. Incidentally, the voltage regulator 140 keeps being turned off according to the post-stage gate driving signal G _{[N + 1] which} is a high voltage level. The voltage regulator 150 is kept turned off according to the mode selection signal SS which is a high voltage level.

At the same time, the transistor T3 in the output stage circuit 110 is turned on according to the first control signal Q _[N] being pulled down, so that the clock signal CK equal to the gate high voltage V _GH charges the output terminal OE. The transistor T11 is turned off according to the second control signal P _[N] equal to the voltage level V _GH- DV2, and the transistor T4 is kept turned off according to the mode selection signal SS. Therefore, the voltage value of the N-th gate driving signal G _[N] is maintained equal to the gate high voltage V _GH .

Please refer to FIG. 2 and FIG. 3E. In the time interval TA4, the gate driving device enters the second sub-phase of the writing phase. In the time interval TA4, the voltage value of the starting pulse wave signal ST or the previous-stage gate driving signal G _[N-1] is pulled up to be equal to the gate-level high voltage V _GH . The transistor T1 in the voltage regulator 130 is turned off according to the pulled-up start pulse signal ST or the previous-stage gate driving signal G _[N-1] . On the other hand, the clock signal CK transitions from the gate high voltage V _GH to the gate low voltage V _GL . By maintaining the transistor T3 that is turned on, the output stage circuit 110 provides a clock signal CK to charge the output terminal OE, so that the voltage value of the N-th gate drive signal G _[N] is pulled down to the gate low voltage V _GL .

Please note here that based on the pull-down action of the voltage value of the Nth-level gate drive signal G _[N] , the first control signal Q _[N] will be pulled down by an offset according to the clock signal CK being pulled down The value is DV1. To explain in detail, through the coupling effect generated by the capacitor C1, the voltage value of the first control signal Q _[N] can be further _reduced to V _GL + | V _{TH_T1} | -DV1, where the magnitude of the offset value DV1 depends on the capacitor The ratio of the capacitance value of C1 to the equivalent capacitance value on the first control terminal CE1 is determined.

Under the condition that the voltage value of the first control signal Q _[N] can be further pulled down, the transistor T8 in the voltage regulator 160 can be continuously turned on to continue to provide the gate high voltage V _GH . At the same time, the transistor T5 will be turned off according to the reverse clock signal XCK which transitions from the gate low voltage V _GL to the gate high voltage V _GH . Therefore, the voltage value of the second control signal P _[N] is pulled up by an offset value DV2 according to the gate high voltage V _GH , so that the voltage value of the second control signal P _[N] is equal to the gate high voltage V _GH . The transistors T10 and T12 in the voltage regulator 120 and the transistor T11 in the output stage circuit 110 will continue to be turned off according to the second control signal P _[N] . Incidentally, the voltage regulator 140 continues to be cut off in accordance with the gate driving signal G _{[N + 1] of the} subsequent stage, and the transistor T9 in the voltage regulator 150 and the transistor T4 in the output stage circuit 110 depend on the mode. The selection signal SS remains turned off.

Please refer to FIG. 2 and FIG. 3F. In the time interval TA5, the gate driving device enters the third sub-phase of the writing phase. In the time interval TA5, the clock signal CK transitions from the gate low voltage V _GL to the gate high voltage V _GH , and the reverse clock signal XCK transitions from the gate high voltage V _GH to the gate low voltage V _GL . By maintaining the transistor T3 that is turned on, the output stage circuit 110 provides a clock signal CK to charge the output terminal OE, so that the voltage value of the N-th gate drive signal G _[N] is pulled up to the gate high voltage V _GH .

It is worth noting that the first control signal Q _[N] will be pulled up to equal to the clock signal CK which is pulled up based on the voltage value of the Nth stage gate driving signal G _[N] being pulled up. The voltage value V _GL + | V _{TH_T1} |. In this embodiment, the first control signal Q _[N] can be pulled up to be equal to the voltage value V _GL + | V _{TH_T1} | in the time interval TA5, where V _GH > V _GL + | V _{TH_T1} |> V _GL + | V _{TH_T1} | -DV1.

On the other hand, the voltage value of the subsequent gate driving signal G _{[N + 1]} is pulled down to be equal to the gate low voltage V _GL . The transistors T7 and T13 in the voltage regulator 140 are turned on according to the pulled-down gate driving signal G _{[N + 1]} to provide the gate high voltage V _GH to the first control signal Q _[N] . Charging. At the same time, the transistor T5 in the voltage regulator 160 is turned on according to the reverse clock signal XCK, the transistor T6 is turned on according to the mode selection signal SR, and the gate low voltage V _{GL is provided} to match the transistor T8. The provided gate high voltage V _GH charges the second control signal P _[N] together to continue to maintain the second control signal P _[N] at the gate high voltage V _GH . The voltage regulator 120 continues to be turned off in accordance with the second control signal P _{[N], which} is the gate high voltage V _GH . Incidentally, the voltage regulator 130 and the voltage regulator 150 continue to be cut off.

Please refer to FIG. 2 and FIG. 3G. In the time interval TA6, the gate driving device enters the fourth sub-phase of the writing phase. In the time interval TA6, the clock signal CK is maintained at the gate high voltage V _GH , and the reverse clock signal XCK is maintained at the gate low voltage V _GL . The voltage value of the subsequent gate driving signal G _{[N + 1]} is maintained equal to the gate low voltage V _GL . The transistors T7 and T13 in the voltage regulator 140 are continuously turned on according to the gate-driving signal G _{[N + 1] of the} rear stage, so as to continue to charge the first control signal Q _[N] and make the first control signal Q _{[ N]} is pulled up to a gate-level high voltage V _GH . At the same time, the transistor T8 in the voltage regulator 160 will be cut off according to the first control signal Q _[N] equal to the gate-level high voltage V _GH , and the transistor T5 will be cut off according to the inverse of the gate-low voltage V _GL The clock signal XCK is kept turned on, and a reverse clock signal XCK is provided to pull down the second control signal P _[N] to be equal to the voltage value V _GL + | V _{TH_T5} |.

At the same time, the voltage regulator 120 is turned on according to the pulled-down second control signal P _[N] , and provides a gate-level high voltage V _GH to charge the first control signal Q _{[N] to} make the first control signal The voltage value of Q _[N] is maintained at the gate-level high voltage V _GH . Incidentally, the voltage regulator 130 and the voltage regulator 150 continue to be cut off.

At the same time, the transistor T3 in the output stage circuit 110 is cut off according to the first control signal Q _[N] being pulled up, the transistor T4 remains disconnected according to the mode selection signal SS, and the transistor T11 is based on The second control signal P _[N] equal to the voltage level V _GL + | V _{TH_T5} | is turned on to provide the gate-level high voltage V _GH to charge the output terminal OE, so that the N-th gate driving signal G _[N] The voltage value remains equal to the gate high voltage V _GH .

Please refer to FIG. 2 and FIG. 3H. In the time interval TA7, the gate driving device enters a voltage holding stage. In the time interval TA7, the voltage regulator 140 is switched according to the gate driving signal G _{[N + 1]} of the subsequent stage which is equal to the gate high voltage V _GH . Off. The transistor T5 in the voltage regulator 160 is turned on periodically according to the reverse clock signal XCK with a periodic transition (when the reverse clock signal XCK transition is equal to the gate low voltage V _GL ), and The two control signals P _{[N] are} periodically charged, driving the voltage value of the second control signal P _[N] to drop and maintain the voltage at V _GL + | V _{TH_T5} |, and the voltage regulator 120 according to the second control signal P _[N] Continue to be turned on to charge the first control signal Q _[N] , driving the voltage value of the first control signal Q _[N] to be pulled up and maintained at the gate high voltage V _GH .

Incidentally, the transistor T8 in the voltage regulator 160 is turned off according to the first control signal Q _[N] being pulled up. The voltage regulator 130 continues to be turned off according to the previous-stage gate driving signal G _[N-1] or the start pulse wave signal ST. The transistor T9 in the voltage regulator 150 and the transistor T4 in the output stage circuit 110 continue to be turned off according to the mode selection signal SS. It is worth noting that the transistor T3 in the output stage circuit 110 is turned off according to the first control signal Q _[N] being pulled up, and the transistor T11 in the output stage circuit 110 is turned off according to the second being pulled down The control signal P _[N] is kept turned on. In this way, the output stage circuit 110 will charge the output terminal OE with the gate high voltage V _GH through the turned-on transistor T11, so that the Nth stage gate driving signal G _{[N] is} maintained at the gate high voltage. V _GH .

From the above description, it is not difficult to know that the gate driving signal that is pulled down is transmitted step by step. During the writing phase, the gate driving device can generate the gate driving signals that are sequentially enabled (pull down) and follow The sequence performs a data writing operation on a plurality of pixel lines.

In summary, the present invention provides a shift temporary storage circuit, and forms a gate driving signal through a multi-stage serially connected shift temporary storage circuit. The gate driving signal provided by the present invention can provide multiple gate driving signals that are commonly enabled during the compensation phase, and generate sequentially enabled gate driving signals during the writing phase to provide a sufficient time to perform data writing Into action. The display panel can be effectively matched with a synchronous active organic light emitting diode to compensate the variation of the threshold voltage at the compensation time without being limited by the panel resolution, and is applied to a high-resolution display panel. In addition, in the embodiment of the present invention, the voltage regulator is constructed by using a plurality of transistors in series, which can reduce the leakage phenomenon of internal nodes and save power consumption.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧ shift temporary storage circuit

110‧‧‧Output stage circuit

120 ~ 160‧‧‧Voltage Regulator

C1‧‧‧capacitor

CE1, CE2‧‧‧Control terminal

CK‧‧‧Clock signal

XCK‧‧‧Reverse clock signal

G _[N] ‧‧‧Grade N gate drive signal

G _[N-1] ‧‧‧ Fore-stage gate drive signal

G _{[N + 1]} ‧‧‧ Gate driver signal

OE‧‧‧ output

Q _[N] , P _[N] ‧‧‧ control signal

SS, SR‧‧‧ mode selection signal

ST‧‧‧Start pulse signal

T1 ~ T13‧‧‧Transistors

TA0 ~ TA7‧‧‧Time zone

V _GH ‧‧‧Gate high voltage

V _GL ‧‧‧Gate low voltage

DV1, DV2‧‧‧Offset value

FIG. 1 is a schematic diagram of a gate driving device according to an embodiment of the present invention. FIG. 2 is an operation waveform diagram of a gate driving device according to an embodiment of the present invention. 3A to 3H are equivalent circuit diagrams of a shift register circuit according to an embodiment of the present invention.

Claims

A gate driving device includes: a plurality of shift temporary storage circuits which are connected in series with each other to generate a plurality of gate driving signals respectively, wherein the N-th stage shift temporary storage circuit includes: an output stage The circuit has a first control terminal and a second control terminal to receive a first control signal and a second control signal, respectively, and provides according to the first control signal, the second control signal, and a first mode selection signal to provide A clock signal, a high gate voltage or a low gate voltage charges an output terminal to generate an Nth-level gate driving signal; a first voltage regulator is coupled to the first control terminal and the second Between the control terminals, according to the second control signal to provide the gate high voltage to adjust the first control signal; a second voltage regulator is coupled to the first control terminal, and selects a signal according to a second mode, a A front-stage gate driving signal or an initial pulse signal to adjust the first control signal; a third voltage regulator is coupled to the first control terminal, and provides the gate height according to a back-stage gate driving signal. Voltage to adjust The first control signal; a fourth voltage regulator coupled to the second control terminal, providing a high gate voltage to adjust the second control signal according to the first mode selection signal; and a fifth voltage adjustment A device coupled to the second control terminal to provide the reverse clock signal or the gate high voltage to adjust the second according to a reverse clock signal, the second mode selection signal, and the first control signal control signal.
The gate driving device according to item 1 of the patent application scope, wherein in a compensation stage, the second voltage regulator is cut off according to the second mode selection signal, and the first voltage regulator is cut according to the second control signal. When it is cut off, the third voltage regulator is turned on according to the pulled-down gate driving signal and provides the gate high voltage to pull up the first control signal.
The gate driving device according to item 2 of the scope of patent application, wherein in the compensation stage, the fourth voltage regulator is turned on according to the first mode selection signal and provides the gate high voltage to pull up the second voltage. A control signal, the fifth voltage regulator is cut off according to the first control signal and the second mode selection signal.
The gate driving device according to item 3 of the scope of patent application, wherein in the compensation stage, the output stage circuit selects a signal according to the first mode to provide the gate low voltage to charge the output terminal, and generates the first N-level gate drive signal.
The gate driving device according to item 2 of the patent application scope, wherein in a first sub-phase of a writing phase, the second voltage regulator selects the signal according to the second mode and the front-stage gate that is pulled down The pole driving signal or the starting pulse wave signal is turned on, and the pre-stage gate driving signal or the starting pulse wave signal is transmitted to pull down the first control signal. The first voltage regulator is based on the second control signal When it is cut off, the third voltage regulator is cut off according to the rear gate driving signal.
The gate driving device according to item 5 of the patent application scope, wherein in the first sub-phase of the writing phase, the fourth voltage regulator is cut off according to the first mode selection signal, and the fifth voltage adjustment Based on the first control signal, the second The mode selection signal and the reverse clock signal pulled down are turned on, and the reverse clock signal and the gate high voltage are provided to pull up the second control signal.
The gate driving device according to item 5 of the scope of patent application, wherein in a second sub-phase of the writing phase, the second voltage regulator is based on the previous-stage gate driving signal or the start-up which is pulled up. The pulse wave signal is cut off, the first voltage regulator is cut off according to the second control signal, the third voltage regulator is cut off according to the rear gate driving signal, and the first control signal is pulled low according to The clock signal is pulled down by a first offset value.
The gate driving device according to item 7 of the scope of patent application, wherein in the second sub-phase of the writing phase, the fourth voltage regulator is kept cut off, and the fifth voltage regulator is controlled according to the first control. The signal continues to be turned on, and the gate high voltage is provided to pull the second control signal to a second offset value.
The gate driving device according to item 8 of the scope of patent application, wherein the output stage circuit provides the clock signal to charge the output terminal according to the first control signal, and generates the Nth stage gate driving signal.
The gate driving device according to item 9 of the scope of patent application, wherein in a third sub-phase of the writing phase, the second voltage regulator is switched on according to the previous-stage gate driving signal or the starting pulse signal. Cut off, the first voltage regulator is cut off according to the second control signal, the third voltage regulator is turned on according to the pulled-down gate driving signal, and provides the gate high voltage to the The first control signal is charged, the fourth voltage regulator is switched off according to the first mode selection signal, the fifth voltage regulator is switched off according to the first control signal, the second mode selection signal, and the pulled down The reverse clock signal is turned on, and the gate high voltage and the reverse clock signal are provided to charge the second control signal.
According to the gate driving device of claim 10, in a fourth sub-phase of the writing phase, the second voltage regulator continues to be cut off, and the first voltage regulator is pulled down based on The second control signal is turned on, and the gate high voltage is provided to charge the first control signal. The third voltage regulator continues to be turned on to charge the first control signal according to the subsequent-stage gate driving signal. The fourth voltage regulator continues to be switched off, the fifth voltage regulator continues to be turned on according to the reverse clock signal and the second mode selection signal, and provides the reverse clock signal to pull down the second control signal.
The gate driving device according to item 2 of the scope of patent application, wherein in a voltage holding stage, the second voltage regulator is cut off according to the previous gate driving signal or the starting pulse signal, and the first The voltage regulator is turned on according to the second control signal to charge the first control signal, the third voltage regulator is cut off according to the rear gate driving signal, and the fourth voltage regulator selects the signal according to the first mode After being cut off, the fifth voltage regulator is periodically turned on according to the reverse clock signal and the second mode selection signal, and periodically charges the second control signal.
The gate driving device according to item 12 of the application, wherein in the voltage holding stage, the output stage circuit provides the gate high voltage to generate the N-th gate driving signal according to the second control signal.
The gate driving device according to item 1 of the patent application scope, wherein the output stage circuit includes: A first transistor whose first terminal receives the clock signal, a second terminal of the first transistor is coupled to the output terminal, and a control terminal of the first transistor receives the first control signal; a first A capacitor is coupled between the control terminal of the first transistor and the output terminal; a second transistor whose first terminal is coupled to the output terminal, and a second terminal of the second transistor receives the gate height Voltage, the control terminal of the second transistor receives the second control signal; and a third transistor whose first terminal receives the gate low voltage, and the second terminal of the third transistor is coupled to the output terminal The control terminal of the third transistor receives the first mode selection signal.
The gate driving device according to item 1 of the patent application scope, wherein the first voltage regulator includes: at least one transistor, coupled to the first control terminal and configured to receive the gate high voltage, the at least one electric voltage The control terminal of the crystal receives the second control signal.
The gate driving device according to item 1 of the scope of patent application, wherein the second voltage regulator includes: a diode whose cathode receives the previous gate driving signal or the starting pulse signal; and a first A transistor having a first terminal coupled to the anode of the diode, a second terminal of the first transistor coupled to the first control terminal, and a control terminal of the first transistor receiving the second mode selection signal.
The gate driving device according to item 1 of the patent application scope, wherein the third voltage regulator includes: at least one transistor, coupled to the first control terminal and configured to receive the high voltage of the gate, the at least one power The control terminal of the crystal receives the gate driving signal of the subsequent stage.
The gate driving device according to item 1 of the patent application scope, wherein the fourth voltage regulator includes: at least one transistor, coupled to the second control terminal and configured to receive the high voltage of the gate, the at least one power The control terminal of the crystal receives the first mode selection signal.
The gate driving device according to item 1 of the patent application scope, wherein the fifth voltage regulator includes: a diode whose cathode receives the reverse clock signal; a first transistor whose first terminal is coupled Connected to the anode of the diode, the second terminal of the first transistor is coupled to the second control terminal, and the control terminal of the first transistor receives the second mode selection signal; and a second transistor, A first terminal thereof is coupled to a second terminal of the first transistor, a second terminal of the second transistor receives the gate high voltage, and a control terminal of the second transistor receives the first control signal.
According to the gate driving device described in the first item of the patent application scope, in a compensation phase, the gate driving signals are simultaneously enabled, and in a writing phase, the gate driving signals are sequentially enabled, During a voltage holding phase, the gate driving signals are maintained at a disabled voltage value. The compensation phase, the writing phase, and the voltage holding phase occur sequentially.