KR101255269B1 - Shift register and method for driving the same and display device using the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display device and a driving method thereof capable of stabilizing circuit characteristics of a shift register while increasing its lifespan. Wherein each stage includes a pull-up switching element for supplying a first clock pulse as an output signal and an output unit for supplying a first driving voltage to the output signal in response to a second clock pulse. A control unit for controlling a pull-up switching element according to a start signal from an external source or an output pulse from a previous stage and an output pulse from a next stage, and the pull-up switching using at least two clock pulses. And a compensating unit for maintaining the disabled state of the device.

Shift register, built-in circuit, a-si, coupling phenomenon, channel width, lifetime

Description

Shift register and method for driving the same and display device using the same}

1 is a block diagram showing a shift register according to an embodiment of the present invention.

2 is an equivalent circuit diagram showing a first stage according to the first embodiment of the present invention.

FIG. 3 is a waveform diagram illustrating input / output waveforms of the first stage shown in FIG. 2. FIG.

4 is an equivalent circuit diagram showing a first stage according to the second embodiment of the present invention.

5 is a block diagram showing a liquid crystal display device having a shift register according to an embodiment of the present invention.

＊ Description of symbols for main parts of the drawings ＊

10 TFT array substrate 20 liquid crystal panel

50: circuit film SP: start signal

N1: first node N2: second node

ST1 to STn: First to n < th > stages

CLK1 to CLK4: first to fourth clock pulses

Vout1 to Voutn: First to nth output pulses

Tr1 to Tr8: first to eighth switching elements

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a display device. More particularly, the present invention relates to a shift register, a driving method thereof, and a display device using the same, which can increase a lifetime while stabilizing an output signal.

Conventional liquid crystal displays display images by adjusting the light transmittance of liquid crystals having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines and a plurality of data lines, and a liquid crystal capacitor connected to the TFT. The liquid crystal capacitor includes a liquid crystal and a pixel electrode and a common electrode for applying an electric field to the liquid crystal. The pixel electrodes are connected to a TFT which is a switching element. The TFT supplies the data signal from the data line to the pixel electrode in response to the output pulse from the gate line. The liquid crystal capacitor charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. The storage capacitors are connected to the liquid crystal capacitors in parallel so that the voltage charged in the liquid crystal capacitors is maintained until the next data signal is supplied. The storage capacitor is formed by overlapping pixel electrodes with a previous gate line and an insulating layer interposed therebetween. In contrast, the storage capacitor may be formed by overlapping pixel electrodes with a storage line and an insulating layer therebetween.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply unit for supplying power signals required for the liquid crystal display.

Here, the gate driver includes a shift register for sequentially outputting output pulses. The shift register is composed of a number of stages connected dependently to each other.

The liquid crystal display device forms a gate driver in the liquid crystal panel using amorphous silicon (a-si). Each stage of the shift register is composed of a plurality of TFTs. However, a plurality of TFTs formed of a-si have parasitic capacitance as the gate electrode has an overlapping structure with a source electrode and a drain electrode interposed therebetween. In particular, the TFTs constituting the output of each stage are relatively large by determining the output signal, so that the parasitic capacitance is further increased and the output signal is distorted due to the coupling phenomenon of the parasitic capacitance.

On the other hand, a method of using a compensation TFT for preventing distortion of an output signal due to a parasitic capacitance coupling phenomenon has been proposed, but has a short life due to its limited size in order to minimize the influence of the compensation TFT on the output signal.

The problem of the shift register is the same in the other display devices including the shift register as well as the liquid crystal display device (Organic Electro Luminescence Display Device).

Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a shift register, a driving method thereof, and a display device using the same, which can increase a lifetime while stabilizing an output signal.

A shift register of a liquid crystal display according to the present invention for achieving the above object is a shift register of a display device having a plurality of stages connected to each other, wherein each stage supplies a first clock pulse as an output signal. An output unit including a pull-up switching element and a pull-down switching element for supplying a first driving voltage to the output signal in response to a second clock pulse, and an external start signal or an output pulse from a previous stage. And a controller for controlling the pull-up switching device according to the output pulse from the next stage, and a compensator for maintaining the disable state of the pull-up switching device by using at least two clock pulses. do.

In addition, the shift register driving method of the liquid crystal display according to the present invention for achieving the above object is a shift register having a plurality of stages for sequentially outputting output pulses for driving a plurality of gate lines for one frame period. A driving method of the method comprising: enabling a pull-up switching device according to a start signal from an external source or an output pulse from a previous stage, and generating at least one clock pulse according to an enable state of the pull-up switching device. Generating an output signal, disabling the pull-up switching element according to an output pulse from a next stage, and disabling the pull-up switching element using at least two clock pulses. And maintaining the same.

Hereinafter, a shift register, a driving method thereof, and a display device using the same according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a shift register according to an exemplary embodiment of the present invention.

The shift register illustrated in FIG. 1 includes n stages ST1 to STn and one dummy stage DST connected to each other.

The n stages ST1 to STn sequentially output the n output pulses Vout1 to Voutn, and one dummy stage DST outputs one dummy output pulse Vout + 1.

To this end, each of the n stages ST1 to STn and one dummy stage DST is supplied with at least one clock pulse among a plurality of clock pulses having a sequential phase difference from each other. For example, when the first to fourth clock pulses CLK1 to CLK4 are used, each of the n stages ST1 to STn and one dummy stage DST may be the first to fourth clock pulses CLK1 to CLK4. Three clock pulses are supplied. Specifically, the 4i-3th stages ST1, ST5, and STn-3 are supplied with the fourth, first and second clock pulses CLK4, CLK1 and CLK2, and the 4i-2nd stage ( ST2, ST2 ,,, and STn-2 are supplied with the first, second and first clock pulses CLK1, CLK1 and CLK1. The 4i-1st stages ST3, ST6, and STn-1 are supplied with the second, third and fourth clock pulses CLK2, CLK3 and CLK4, and the 4ith stages ST4, ST8, (STn) is supplied with the third, fourth and first clock pulses (CLK3, CLK4, CLK1). Where i is a natural number.

In addition, the n stages ST1 to STn and one dummy stage DST are commonly supplied with the first and second driving voltages VDD and VSS. Here, the first driving voltage VDD may mean a gate-on voltage VG-ON, and the second driving voltage VSS may also mean a gate-off voltage VG-OFF.

The first stage ST1 receives the start signal SP from the outside, and the second to nth stages ST2 to STn receive the output pulse of the previous stage as a trigger signal. The nth stage STn is a dummy output pulse Vout + 1 from the dummy stage DST, and the first to n-1th stages ST1 to STn-1 use the output pulse of the next stage as a reset signal. To be supplied.

2 is an equivalent circuit diagram showing a first stage according to the first embodiment of the present invention.

The first stage ST1 illustrated in FIG. 2 includes a control unit C1 for controlling the first node N1 according to a start signal SP from the outside and an output signal from a next stage, and at least one clock pulse. Compensation unit C2 for maintaining the disabled state of first node N1 using CLK1 to CLK4, and first output voltage Vout1 according to the first and second clock pulses CLK1 and CLK2. It consists of an output unit (C3) for controlling.

The control unit C1 is a charge switching element as a first switching element Tr1 for enabling the first node N1 with the first driving voltage VDD according to a start signal SP from the outside, and as a discharge switching element. The second switching device Tr2 disables the first node N1 with the second driving voltage VSS according to the second output pulse Vout2 from the second stage ST2.

The compensator C2 includes a third switching element Tr3 which periodically disables the first node N1 with the second driving voltage VSS to maintain the disable state of the first node N1, and the third switching element Tr3. A fourth switching element Tr4 for turning on the third switching element Tr3 with the first driving voltage VDD using the first clock pulse CLK1 or the fourth clock pulse CLK4, and the first node The fifth switching element Tr5 for turning off the third switching element Tr3 by the second driving voltage VSS when the N1 is enabled, and the second node N2 according to the second clock pulse CLK2. ) Is configured as a sixth switching element Tr6 for disabling).

The output unit C3 is a pull-up switching element and a seventh switching element Tr7 that outputs the first clock pulse CLK1 to the first output pulse Vout1 according to the enable state of the first node N1. And an eighth switching element Tr8 that disables the first output voltage Vout1 to the second driving voltage VSS according to the second clock pulse CLK2 as a pull-down switching element.

Here, the first to eighth switching elements Tr1 to Tr8 formed in the control unit C1, the compensator C2, and the output unit C3 may be a switching element such as a PMOS transistor or an NMOS transistor. Hereinafter, only the NMOS transistor will be described as an example.

FIG. 3 is a waveform diagram illustrating another input / output waveform of the first stage illustrated in FIG. 2.

The first to fourth clock pulses CLK1 to CLK4 shown in FIG. 3 have the same pulse width and amplitude in the 1H period, have a phase difference of 90 degrees sequentially with each other, and are periodically supplied with a 4H period. The start signal SP is generated in synchronization with the fourth clock pulse CLK4.

Another operation of the shift register according to the first embodiment of the present invention will be described with reference to FIGS. 2 and 3 by dividing each section (T1, T2, T3) as follows.

Here, since the configurations of the n stages ST1 to STn and the one dummy stage DST are the same, only the first stage ST1 will be representatively described.

First, when the high level start signal SP is supplied to the gate terminal of the first switching element Tr1 in the T1 period, the first switching element Tr1 is turned on so that the first driving voltage VDD is the first node. Precharged to (N1). Accordingly, the first node N1 is enabled and the seventh switching element Tr7 is turned on so that the low voltage of the first clock pulse CLK1 is supplied to the first output voltage Vout1. In this case, since the fifth switching device Tr5 is turned on by the enabled first node N1, the third switching device Tr3 is the second driving voltage VSS via the fifth switching device Tr5. It is turned off by

In the T2 section, the first clock pulse CLK1 having a high level is supplied to the seventh switching element Tr7 turned on by the enabled first node N1, and the first clock pulse CLK1 having a high level is supplied. Is output to the first output pulse Vout1. At this time, the first node N1, which is floated according to the high voltage of the first clock pulse CLK1 due to the coupling action of the parasitic capacitance of the seventh switching element Tr7, bootstraps, thereby increasing the voltage higher than the T1 interval. As a result, the current passing through the seventh switching element Tr4 increases, so that the output pulse Vout1 is rapidly charged to a high voltage. Meanwhile, the fourth switching device Tr4 is also turned on by the first clock pulse CLK1. However, since the third switching device Tr3 is turned off by the turned-on fifth switching device Tr5, the third switching device Tr3 does not interfere with the bootstrapping operation of the first node N1. The output first output pulse Vout1 is supplied to the first switching element Tr1 of the second stage ST2 while scanning the first gate line.

In the T3 section, the second switching device Tr2 is turned on by the second output pulse Vout2 supplied to the first stage ST1 as a reset signal. Accordingly, the second switching element Tr2 disables the first node N1 to the second driving voltage VSS. At this time, since the eighth switching device Tr8 included in the output unit C3 is also turned on by the second clock pulse CLK2, the first output voltage Vout1 is disabled by the second driving voltage VSS. do. Here, as the first node N1 is disabled with the second driving voltage VSS, the fifth switching device Tr5 maintains a turn-off state.

Thereafter, the fourth switching device Tr4 is periodically turned on by the first clock pulse CLK1 which is periodically supplied while the first node N1 maintains the disabled state. Accordingly, the fourth switching device Tr4 periodically turns on the third switching device Tr3 with the first driving voltage VDD, and the third switching device Tr3 is stably provided with the first node N1. To keep it disabled. That is, the third switching device Tr3 periodically disables the first node N1 to the second driving voltage VSS to the first clock pulse CLK1 periodically supplied to the seventh switching device Tr7. This prevents the first node N1 from becoming unstable.

Meanwhile, the sixth switching element Tr6 is periodically turned on by the second clock pulse CLK2 to periodically disable the second node N2.

In the shift register according to the first embodiment of the present invention, the compensation unit C2 is provided in each of the stages ST1 to DST so that the first node N1 is stably disabled in the disable period of the first node N1. To be maintained.

The third to sixth switching elements Tr3 to Tr6 included in the compensator C2 disable the first node N1 without being directly connected to the respective gate lines. Accordingly, the lifetime of each stage ST1 to DST is formed by forming the channel width of the third to sixth switching elements Tr3 to Tr6, in particular, the third switching element Tr3 to be larger than the other switching elements Tr1 to Tr8. Can be increased.

4 is an equivalent circuit diagram illustrating a first stage according to a second embodiment of the present invention.

The first stage ST1 illustrated in FIG. 4 is the first switching element Tr1 of the controller C1 and the fourth switching element of the compensator C2 as compared to the first stage ST1 illustrated in FIG. 2. The same components are provided except that Tr4 is formed in the diode type. Duplicate components will not be described.

The operation of the shift register according to the second embodiment of the present invention will be described with reference to FIGS. 3 and 4 by dividing into sections T1, T2, and T3.

Here, since the configurations of the n stages ST1 to STn and the one dummy stage DST are the same, only the first stage ST1 will be representatively described.

First, when the high level start signal SP is supplied to the gate and drain terminals of the first switching element Tr1 in the T1 section, the first switching element Tr1 is turned on to generate the high level start signal SP. It is precharged to the first node N1. Accordingly, the first node N1 is enabled and the seventh switching element Tr7 is turned on so that the low voltage of the first clock pulse CLK1 is supplied to the first output voltage Vout1. In this case, since the fifth switching device Tr5 is turned on by the enabled first node N1, the third switching device Tr3 is the second driving voltage VSS passing through the fifth switching device Tr5. It is turned off by

In the T2 section, the first clock pulse CLK1 having a high level is supplied to the seventh switching element Tr7 turned on by the enabled first node N1, and the first clock pulse CLK1 having a high level is supplied. It is output by the 1st output pulse Vout1. At this time, the first clock pulse CLK1 bootstrap the floating voltage of the first clock pulse CLK1 according to the high voltage due to the coupling action of the parasitic capacitance of the seventh switching element Tr7. Accordingly, the current passing through the seventh switching element Tr7 increases, so that the first output pulse Vout1 is quickly charged to a high voltage. On the other hand, the fourth switching device Tr4 is also turned on by the first clock pulse CLK1. However, since the third switching device Tr3 is turned off by the turned-on fifth switching device Tr5, the third switching device Tr3 does not prevent the bootstrapping operation of the first node N1. In addition, the output first output pulse Vout1 scans the first gate line and is supplied to the first switching element Tr1 of the second stage ST2 as a trigger signal.

In the T3 section, the second switching device Tr2 is turned on by the second output pulse Vout2 supplied to the first stage ST1 as a reset signal. Accordingly, the second switching element Tr2 disables the first node N1 to the second driving voltage VSS. In this case, since the eighth switching element Tr8 included in the output unit C3 is also turned on by the second clock pulse CLK2, the first gate line is disabled by the second driving voltage VSS. Here, as the first node N1 is disabled with the second driving voltage VSS, the fifth switching device Tr5 maintains a turn-off state.

Thereafter, the fourth switching device Tr4 is periodically turned on by the first clock pulse CLK1 which is periodically supplied while the first node N1 maintains the disabled state. Accordingly, the fourth switching device Tr4 periodically turns on the third switching device Tr3 with the first clock pulse CLK1, and the third switching device Tr3 is stably provided with the first node N1. To keep it disabled. That is, the third switching device Tr3 periodically disables the first node N1 to the second driving voltage VSS to the first clock pulse CLK1 periodically supplied to the seventh switching device Tr7. This prevents the first node N1 from becoming unstable. Meanwhile, the sixth switching element Tr6 is periodically turned on by the second clock pulse CLK2 to periodically disable the second node N2.

In the shift register according to the second exemplary embodiment of the present invention, the first switching element Tr1 and the fourth switching element Tr4 of each stage ST1 to DST are formed in the form of a diode. Accordingly, each first node N1 is enabled by using the start signal SP or the output pulse of the previous stage, that is, the trigger signal, without using the first driving voltage VDD. In addition, the fourth switching device Tr4 may also periodically turn on the third switching device Tr3 by using at least one clock pulse without using the first driving voltage VDD.

In the shift register according to the second exemplary embodiment of the present invention, a compensation unit C2 is provided in each of the stages ST1 to DST so that the first node N1 is stably disabled in the disable period of the first node N1. To be maintained.

The third to sixth switching elements Tr3 to Tr6 included in the compensator C2 disable the first node N1 without being directly connected to each output terminal, that is, the gate line connection terminal. Accordingly, the lifetime of each stage ST1 to DST is formed by forming the channel width of the third to sixth switching elements Tr3 to Tr6, in particular, the third switching element Tr3 to be larger than the other switching elements Tr1 to Tr8. Can be increased.

5 is a block diagram illustrating a liquid crystal display device having a shift register according to an exemplary embodiment of the present invention.

In the liquid crystal display shown in FIG. 5, an image panel 20 including a plurality of gate lines and data lines on a TFT array substrate 10 and a data driver 30 for driving a plurality of data lines are mounted. A plurality of circuit films 50 and a gate driver 30 for driving a plurality of gate lines.

The liquid crystal panel 20 includes a thin film transistor (TFT) formed in each pixel area defined by a plurality of gate lines and a plurality of data lines, and a liquid crystal capacitor Clc connected to the TFT. The liquid crystal capacitor Clc is composed of a pixel electrode connected to a TFT and a common electrode facing each other with the pixel electrode and the liquid crystal interposed therebetween. The TFT supplies a data signal from each data line to the pixel electrode in response to an output pulse from each gate line. The liquid crystal capacitor charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. The storage capacitors are connected to the liquid crystal capacitors in parallel so that the voltage charged in the liquid crystal capacitors is maintained until the next data signal is supplied. The storage capacitor is formed by overlapping pixel electrodes with a previous gate line and an insulating layer interposed therebetween. In contrast, the storage capacitor may be formed by overlapping pixel electrodes with a storage line and an insulating layer therebetween.

The data driver 30 converts digital image data from a timing controller (not shown) into analog image data in accordance with a data control signal from the timing controller. In addition, analog image data for one horizontal line is supplied to the data line every horizontal period in which the output pulse is supplied to each gate line. That is, the data driver 30 selects a gamma voltage having a predetermined level according to the gray value of the analog image data, and supplies the selected gamma voltage to each data line.

The gate driver 40 includes a shift register that sequentially generates an output pulse, that is, a gate high pulse, in response to a gate control signal from the timing controller, and causes the TFT to be turned on in response to this output pulse.

The shift register is formed on the TFT array substrate 10 together with the TFT array of the liquid crystal panel 20. That is, in the shift register, even if the shift register of the present invention described above with reference to FIGS. 1 to 4 is applied and amorphous silicon (a-si) is used, the output signal is stabilized. The shift register of the present invention can also be applied to the data driver 40. Meanwhile, the shift register of the present invention may be applied not only to a liquid crystal display device but also to other types of display devices including an organic electroluminescence display device.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the shift register and the driving method thereof of the liquid crystal display according to the present invention have the following effects.

The present invention can include a compensation unit not directly connected to each output line to stably maintain the disable state of the first node. Accordingly, it is possible to stabilize the output signal and increase the channel width of the switching elements formed in the compensator to increase the life of the shift register.

Claims (16)

In the shift register of the display device having a plurality of stages connected to each other, Each stage includes an output unit including a pull-up switching device for supplying a first clock pulse as an output signal and a pull-down switching device for supplying a first driving voltage to the output signal in response to a second clock pulse; A control unit controlling the pull-up switching element according to a start signal from the outside or an output pulse from the previous stage and an output pulse from the next stage; And Compensating unit for maintaining the disabled state of the pull-up switching device using at least two clock pulses, The compensation unit A first switching element for disabling the pull-up switching element with the first driving voltage; A second switching element for enabling the first switching element according to the at least one clock pulse; A third switching element for disabling the gate electrode of the first switching element according to the enable state of the gate electrode of the pull-up switching element, and And a fourth switching device for disabling the gate electrode of the first switching device according to the at least one clock pulse. The method of claim 1, The control unit A charging switching element for enabling the pull-up switching element with a second driving voltage or at least one clock pulse in accordance with a start signal from an external stage or an output pulse from a previous stage; And a discharge switching element for disabling the pull-up switching element at the first driving voltage in response to an output pulse from the next stage. The method of claim 2, The charge switching device is And a diode configured to enable the pull-up switching element using the start signal. delete The method of claim 2, The second switching device The shift register of claim 1, wherein the first switching element is enabled using the at least one clock pulse. The method of claim 2, The second switching device And the first switching element is enabled by using the first clock pulse or a third clock pulse having a phase difference of 180 degrees with the first clock pulse. The method according to any one of claims 2, 3, 5 and 6, And the second clock pulse has a phase difference of 90 degrees with the first clock pulse. The method according to any one of claims 2, 3, 5 and 6, And the at least one clock pulse has a phase difference of 90 degrees sequentially and has a 4H period. The method according to any one of claims 2, 3, and 5, The first to fourth switching device is A shift register of a display device, characterized in that it is a PMOS or NMOS transistor. In the driving method of the shift register having a plurality of stages for sequentially outputting output pulses for driving a plurality of gate lines for one frame period, Enabling a pull-up switching element according to a start signal from an external source or an output pulse from a previous stage; Generating an output signal using at least one clock pulse according to an enable state of the pull-up switching device; Disabling the pull-up switching element in accordance with an output pulse from a next stage; And Maintaining the disabled state of the pull-up switching element using at least two clock pulses; Maintaining the disabled state of the pull-up switching device Enabling a first switching device using the at least one clock pulse according to the disable state of the pull-up switching device, and And disabling the pull-up switching device by using the second driving voltage through the enabled first switching device. 11. The method of claim 10, Enabling the pull-up switching device Enabling a charging switching device according to an output pulse from the previous stage or a start signal from the outside; And And supplying a first driving voltage to the pull-up switching device through the enabled charge switching device. 11. The method of claim 10, Enabling the pull-up switching device Enabling a charging switching device according to an output pulse from the previous stage or a start signal from the outside; And And supplying an output pulse from the previous stage or a start signal from the outside to the pull-up switching element. 11. The method of claim 10, Maintaining the disabled state of the pull-up switching device And driving the first switching element by using the first driving voltage in addition to the at least one clock pulse according to the disable state of the pull-up switching element. Way. delete The method of claim 13, And disabling the first switching element by using the at least one clock pulse. The method of claim 13, The first and second switching device A shift register driving method for a display device, characterized in that it is a PMOS or NMOS transistor.

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