KR101192795B1 - Driving circuit for liquid crystal display device and method for driving the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a liquid crystal display device and a driving method thereof capable of preventing a phenomenon of poor image quality generated when a built-in gate panel (GIP) is driven. A gate driver for driving the gate line of the panel, a timing controller for controlling the gate driver by generating at least one clock pulse and a start signal having a different phase, and an auxiliary scan according to the at least one clock pulse and the start signal At least one auxiliary stage for generating a pulse to supply the gate driver.

GIP (Gate In Panel), Auxiliary Stage, Auxiliary Scan Pulse,

Description

Driving device for liquid crystal display and driving method thereof {Driving circuit for liquid crystal display device and method for driving the same}

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a shift register provided in the gate driver of FIG. 1. FIG.

3 is an equivalent circuit diagram showing the first auxiliary stage shown in FIG.

4 is a waveform diagram illustrating input / output waveforms of the shift register shown in FIG. 2;

＊ Explanation of symbols for main parts of drawing *

10 TFT array substrate 20 liquid crystal panel

30: data IC 40: gate driver

AST1: first secondary stage AST2: second secondary stage

AVout1: first auxiliary scan pulse AVoutn2: second auxiliary scan pulse

ST1 to STn: first to nth stages

CLK1 to CLK4: first to fourth clock pulses

Vout1 to Voutn: first to nth scan pulses

The present invention relates to a driving device of a liquid crystal display device and a driving method thereof, which can prevent a phenomenon of poor image quality generated when driving an embedded gate panel (GIP).

Conventional liquid crystal displays display images by adjusting the light transmittance of liquid crystals having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed. Each of the pixel electrodes is connected to a thin film transistor (TFT) which is a switching element. The TFT is turned on by the scan pulse of the gate line, so that the data signal of the data line is charged to the pixel electrode.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a timing controller for supplying control signals for controlling the gate driver and the data driver.

The gate driver has a shift register for sequentially outputting scan pulses. The shift register consists of a number of stages that are connected to each other dependently. The plurality of stages sequentially output scan pulses to sequentially scan the gate lines of the liquid crystal panel.

Specifically, the first stage of the plurality of stages receives the start signal from the timing controller as the trigger signal, and the remaining stages except the first stage receive the output signal from the previous stage as the trigger signal. In addition, each of the plurality of stages receives at least one clock pulse among a plurality of clock pulses having a sequential phase difference from each other. Accordingly, scan pulses are sequentially output from the first stage to the last stage.

However, when using a GIP integrated with a shift register embedded in a TFT array substrate forming a liquid crystal panel, the GIP must be connected to a driving circuit in which an existing timing controller is formed in order to reduce manufacturing costs. At this time, since the gate driving signal from the timing controller is not matched with the GIP, a defect occurs in the displayed image quality that does not match the signal characteristics of the GIP.

Specifically, a plurality of clock pulses and a start signal used when driving the shift register of the gate driver are generated by using the data enable signal from the timing controller. A plurality of clock pulses from the timing controller convert the pulse width of the data enable signal having one horizontal section and are supplied with sequential phase differences to each other in the pulse width of the two horizontal sections. In addition, a plurality of clock pulses are supplied such that pulse widths overlap each other for a predetermined period between clock pulses adjacent to each other. However, since the start signal supplied as the trigger signal to the first stage cannot be directly converted and supplied with the data enable signal, the start signal is supplied with the pulse width of one horizontal section like the data enable signal. Accordingly, since the first stage has a precharge section for outputting the scan pulse only for one horizontal section, the output scan pulse is generated in two horizontal sections depending on the pulse width of the first clock pulse, but its amplitude, that is, the voltage As the size is reduced, the filling rate of the image data in the pixel area is reduced.

The image data filling rate of the first gate line supplied with the scan pulse from the first stage is lower than that of the gate lines supplied with the scan pulse of the amplitude which is not degraded for two horizontal periods later. In the case of TN mode (Twisted Nematic Mode) driven in normally white mode, the bright band appears in the pixel area of the first gate line as the gray level of the image data decreases, especially during low temperature driving. There is a problem that is noticeable.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and provides a driving apparatus of a liquid crystal display device and a driving method thereof having at least one auxiliary stage, which can prevent a phenomenon of poor quality caused when driving a GIP. have.

The driving device of the liquid crystal display according to the present invention for achieving the above object is a liquid crystal panel for displaying an image, a gate driver for driving the gate line of the liquid crystal panel, at least one clock pulse of different phase and A timing controller configured to generate a start signal to control the gate driver, and at least one auxiliary stage configured to generate an auxiliary scan pulse according to the at least one clock pulse and the start signal and to supply the gate driver to the gate driver. do.

In addition, the driving method of the liquid crystal display according to the present invention for achieving the above object comprises the steps of generating at least one clock pulse and a start signal of a different phase, the auxiliary according to the at least one clock pulse and the start signal Generating a scan pulse, generating a scan pulse according to the auxiliary scan pulse and the at least one clock pulse, and supplying the scan pulse to a gate line.

Hereinafter, a driving apparatus and a driving method thereof of a liquid crystal display according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

1 includes a liquid crystal panel 20 having a plurality of gate lines and data lines formed on a TFT array substrate 10, and a data driver 30 for driving a plurality of data lines. A plurality of circuit films 50 and a gate driver 40 for driving a plurality of gate lines.

The liquid crystal panel 20 includes TFTs formed in each pixel region defined by a plurality of gate lines and a plurality of data lines, and pixel electrodes driving liquid crystal molecules. The TFT supplies the data signal from the data line to the pixel electrode in response to the scan pulse from the gate line.

The data driver 30 is mounted on a plurality of data circuit films 50 and connected between the liquid crystal panel 20 and the data PCB. The data driver 30 converts the digital image data from the outside into analog image data and supplies one horizontal line of analog image data to the data lines every horizontal period in which scan pulses are supplied to the gate lines. That is, the data driver 30 selects a gamma voltage having a predetermined level according to the gray value of the analog image data and supplies the selected gamma voltage to the data lines.

The gate driver 40 includes a shift register that sequentially generates scan pulses and causes the TFT to be turned on in response to the scan pulses. The shift register is integrated in the TFT array substrate 10 forming the liquid crystal panel 20.

As described above, in the GIP application in which the gate driver 40 is integrated in the TFT array substrate 10, the GIP is connected to a driving circuit in which an existing timing controller is formed in order to reduce the manufacturing cost. Therefore, when designing the GIP, it is necessary to design such that image quality defects do not appear in the pixel areas PXL of the gate line in which signal characteristics are degraded.

FIG. 2 is a diagram illustrating a shift register included in the gate driver illustrated in FIG. 1.

In the shift register illustrated in FIG. 2, the first and second auxiliary stages AST1 and AST2, the odd-numbered stages ST1 to STn-1 and the even-numbered stages ST2 to STn are connected to each other independently of each other. N stages ST1 to STn which are alternately positioned, and first and second dummy stages DST1 and DST2.

The first and second auxiliary stages AST1 and AST2 output the first and second auxiliary scan pulses AVout1 and AVout2 and supply them to the first stage ST1 and the second stage ST2, respectively.

The n stages ST1 to STn and the two dummy stages DST1 and DST2 sequentially output n scan pulses Vout1 to Voutn. Here, the n scan pulses Vout1 to Voutn output from the n stages ST1 to STn are sequentially supplied to the gate lines of the liquid crystal panel 20 to sequentially scan the gate lines. The dummy scan pulses output from the first and second dummy stages DST1 and DST2 are used as signals for disabling, or resetting, odd and even previous stages STn-1 and STn.

The n stages ST1 to STn and the first and second dummy stages DST1 and DST2, including the first and second auxiliary stages AST1 and AST2, may have a gate-on voltage VDD and a gate-off voltage VSS. It is supplied in common. At least one of the plurality of clock pulses, that is, the first to fourth clock pulses CLK1 to CLK4, which are overlapped with each other for a predetermined period, is applied.

The first auxiliary stage AST1 and the second auxiliary stage AST2 receive the start signal SP from a timing controller (not shown), and the first to nth stages ST1 to STn and the first and second dummy stages ( DST1 and DST2 receive scan pulses of each previous stage of odd and even numbers as a trigger signal. The first to nth stages ST1 to STn receive the scan pulses of the next and next odd stages as reset signals.

Specifically, the n stages ST1 to STn and the first and second dummy stages DST1 and DST2 including the first and second auxiliary stages AST1 and AST2 are odd-numbered stages ST1 to STn-1. And are evenly connected to each other by being divided into even-numbered stages ST2 to STn. Accordingly, odd-numbered stages ST1 to STn-1 except for the first auxiliary stage AST1 receive scan pulses from odd-numbered previous stages as trigger signals. The scan pulse of the next odd stage is supplied as a reset signal.

In addition, the even-numbered stages ST2 to STn except for the second auxiliary stage AST2 receive the scan pulses from the even-numbered previous stage as a trigger signal. The scan pulses of the even-numbered next stage are supplied as reset signals.

Referring to the configuration and operation of the shift register of the present invention configured as described above in detail. Here, since the configuration and operation of the remaining stages AST2 to DST2 including the first auxiliary stage AST1 are all the same, only the first auxiliary stage AST1 will be representatively described.

3 is an equivalent circuit diagram illustrating the first auxiliary stage illustrated in FIG. 2, and FIG. 4 is a waveform diagram illustrating input / output waveforms of the shift register illustrated in FIG. 2.

The first auxiliary stage AST1 shown in FIG. 3 outputs a Q-node controller for controlling the Q-node Q, a QB-node controller for controlling the QB-node QB, and a scan pulse. It consists of a scan pulse output unit.

The Q-node controller includes a first switching element Tr1 for precharging the Q-node Q to the gate-on voltage VDD according to the start signal SP from the timing controller, and an odd next stage, that is, The second switching element Tr2 for disabling the Q-node Q with the gate-off voltage VSS according to the first scan pulse Vout1 from the first stage ST1, and the QB-node QB. The third switching element Tr3 is configured to disable the Q-node Q by the gate-off voltage VSS according to the enable state of the N-th transistor.

The QB-node controller according to the fourth switching element Tr4 for enabling the QB-node QB with the gate-on voltage VDD, the start signal SP and the gate-on voltage VDD from the timing controller. The fifth switching device Tr5 for disabling the QB-node QB to the gate-off voltage VSS and the gate-off voltage VSS are applied to the QB-node QB according to the start signal SP from the timing controller. A sixth switching device (Tr6) for disabling with (). The fourth switching device Tr4 may enable the QB-node QB using one of the gate-on voltages VDD or one of the first to fourth clock pulses CLK1 to CLK4.

The scan pulse output unit includes a seventh switching element Tr7 that outputs the first clock pulse CLK1 to the first scan pulse Vout1 according to the enable state of the Q-node Q, and the QB node QB. The eighth switching element Tr8 is configured to disable the gate line connected to each end with the gate-off voltage VSS according to the enable state of the gate line. However, the second auxiliary stage AST2 including the first auxiliary stage AST1 is not connected to the gate line. Accordingly, the first and second stages to use the respective first output scan pulses AVout1 and the second auxiliary scan pulses AVout2 as the trigger signals of the first and second stages ST1 and ST2, respectively. It is supplied to the gate terminal of the first switching element Tr1 provided in (ST1, ST2).

The plurality of stages ST1 to DST2 including the first and second auxiliary stages AST1 and AST2 of the present invention configured as described above have a plurality of clock pulses overlapped with each other for a predetermined period, that is, the first to fourth clock pulses ( At least one clock pulse of CLK1 to CLK4) is applied. Specifically, the first auxiliary stage AST1 receives the first and third clock pulses CLK1 to CLK3, and in the case of the second stage AST2, the second and fourth clock pulses CLK2 to CLK4. Receive.

In the plurality of stages AST1 to DST2 configured as described above, as shown in FIG. 4, the start signal SP from the timing controller is equal to 1 as the data enable signal having the pulse width of 1 horizontal section 1H. The pulse width of the horizontal section 1H is supplied. The data enable signal is modulated and supplied to the first to fourth clock pulses CLK1 to CLK4 at a pulse width of two horizontal sections 2H.

As the first to eighth switching elements Tr1 to Tr8 formed in the plurality of stages ST1 to DST2 including the first and second auxiliary stages AST1 and AST2 of the present invention, a switching element such as a PMOS or NMOS transistor is used. Can be. Hereinafter, only the NMOS transistor will be described as an example.

An operation of the first auxiliary stage according to the present invention will be described with reference to FIGS. 3 and 4 as follows.

First, in the enabling step of the Q-node Q, the start signal SP is supplied to the gate terminal of the first switching element Tr1 and the first switching element Tr1 is turned on so that the gate-on voltage VDD is turned on. This is supplied to the Q-node Q. That is, the Q-node Q is precharged. At this time, the fifth switching element Tr5 and the sixth switching element Tr6 are also turned on by the gate-on voltage VDD to disable the QB-node QB to the ground voltage VSS. The seventh switching element Tr7 connected to the precharged Q-node Q is turned on.

In the step of outputting the first auxiliary scan pulse AVout1, the third clock pulse CLK3 is supplied to the drain terminal of the turned-on seventh switching element Tr7 so that the third clock pulse CLK3 is the first auxiliary scan pulse. Output as (AVout1). However, since the first auxiliary scan pulse AVout1 is not connected to the gate line, the first auxiliary scan pulse AVout1 is directly supplied to the first stage ST1.

Thereafter, when the first stage ST1 operates in the same manner as the first auxiliary stage AST1 described above to output the first scan pulse Vout1, the first scan pulse Vout1 is supplied to the gate line and at the same time, the first auxiliary stage ST1 is operated. It is supplied to the stage AST1 to turn on the second switching element Tr.

 As a result, the second switching element Tr2 disables the Q-node Q to the ground voltage VSS. Meanwhile, the fifth and sixth switching elements Tr5 and Tr6 are turned off so that the gate-on voltage ADD from the fourth switching element Tr4 precharges the QB-node QB.

Since the Q-node Q is disabled and the seventh switching element Tr7 is also turned off, the seventh switching element Tr7 has the first auxiliary scan pulse AVout1 even when no more third clock pulses CLK3 are supplied. ) Is not output.

Here, it is preferable that the fifth switching element Tr5 and the sixth switching element Tr6 formed in the QB-node controller have a larger capacity, that is, a larger channel width than the fourth switching element Tr4. Since the gate-on voltage VDD continues to be applied, it is faster to disable the QB-node QB when the QB-node QB is enabled when the Q-node QB is disabled. To prevent that.

Unlike the first and second auxiliary stages AST1 and AST2, the first to nth stages ST1 to STn having the output terminal connected to the gate line have the eighth switching element Tr8 when the QB-node QB is precharged. As turned on, each gate line is disabled to the ground voltage VSS.

As described above, odd-numbered stages ST1 to STn-1 sequentially supply scan pulses Vout1 to Voutn-1 to odd-numbered gate lines.

On the other hand, even-numbered stages ST2 to STn are also supplied with scan pulses Vout2 to Voutn to the even-numbered gate lines in the same operation process as for odd-numbered stages ST1 to STn-1.

However, the second sub-stage AST2, which is the first of the even-numbered stages ST2 to STn, receives the start signal SP at the same time as the first sub-stage AST1, but receives the fourth clock pulse CLK4. Since it outputs to the auxiliary scan pulse AVout2, the 2nd auxiliary scan pulse AVout2 is output one horizontal period 1H later than the 1st auxiliary scan pulse AVout1.

Accordingly, the shift register in which the odd stages ST1 through STn-1 and the even stages ST2 through STn are alternately arranged may have a scan pulse such that adjacent scan pulses overlap each other for a predetermined period with the same pulse width. Vout1 to Voutn) are sequentially output.

As shown in Fig. 4, the start signal SP from the timing controller is supplied with a pulse width of one horizontal section 1H in the same manner as the data enable signal having a pulse width of one horizontal section. The first to fourth clock pulses CLK1 to CLK4 are supplied with a pulse width of two horizontal sections 2H in which the data enable signal of the timing controller is modulated.

Accordingly, the Q-node Q of the first auxiliary stage AST1 and the second auxiliary stage AST2, which receives the start signal SP of one horizontal section 1H, is gated on for one horizontal section 1H. Precharged to voltage VDD. When the third clock pulse CLK3 is supplied, the first auxiliary stage AST1 outputs the third clock pulse CLK3 to the first auxiliary scan pulse AVout1. However, since the section in which the Q-node Q provided in the first auxiliary stage AST1 is enabled by the gate-on voltage VDD is one horizontal section 1H, the charging rate of the Q-node Q is low. The output characteristic of the first auxiliary scan pulse AVout1 is lowered as shown in FIG.

Meanwhile, the Q-node of the second auxiliary stage AST2 is also supplied to the gate-on voltage VDD by receiving the start signal SP of one horizontal section 1H. When the fourth clock pulse CLK4 is supplied, the second auxiliary stage AST2 outputs the fourth clock pulse CLK4 as the second auxiliary scan pulse Vout2. In this case, the charging rate of the Q-node Q is low because the Q-node Q provided in the second auxiliary stage AST2 is also enabled to the gate-on voltage VDD as one horizontal section 1H. The output characteristic of the second auxiliary scan pulse AVout2 is also degraded as shown in FIG.

Thereafter, the first stage ST1 receiving the first auxiliary scan pulse AVout1 from the first auxiliary stage AST1 as a trigger signal outputs the first clock pulse CLK1 to the first scan pulse Vout1. do. At this time, since the Q-node Q of the first stage ST1 is enabled by the gate-on voltage VDD during the two horizontal sections 2H, the output characteristic of the first scan pulse Vout1 is normal without being distorted. .

In addition, the second stage ST2 receiving the second auxiliary scan pulse AVout2 from the second auxiliary stage AST2 as the trigger signal outputs the second clock pulse CLK2 to the second scan pulse Vout2. . In this case, since the Q-node Q of the second stage ST2 is enabled by the gate-on voltage VDD during two horizontal sections 2H, the output characteristic of the second scan pulse Vout2 is also shown in FIG. 4. As shown in the normal output.

Of course, the scan pulses Vout3 to Voutn output characteristics of the remaining stages ST3 to DSTn including the third stage ST3 are not shown in the drawing, but are normally normal as the first and second scan pulses Vout1 and Vout2. Has output characteristics.

As described above, the GIP according to the present invention is provided with first and second auxiliary stages AST1 and AST2, and prevents a poor image quality even when used in connection with an existing driving circuit including a timing controller. can do. That is, stages that generate an output signal whose output characteristics are deteriorated by receiving the start signal SP of one horizontal period 1H are set as auxiliary stages, so that only output signals from stages having normal output characteristics are used as scan pulses.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the driving device of the liquid crystal display device and the driving method thereof according to the present invention have the following effects.

According to the present invention, even when a GIP is connected to a driving circuit including an existing timing controller by using at least one auxiliary stage, the characteristics of the output signal may be normally output. As a result, the filling rate of the image data of each pixel area is not lowered, and thus the display quality can be prevented from being poor.

Claims (10)

A liquid crystal panel displaying an image; A gate driver for driving a gate line of the liquid crystal panel; A timing controller generating at least one clock pulse and a start signal having different phases to control the gate driver; And And at least one auxiliary stage configured to generate an auxiliary scan pulse according to the at least one clock pulse and the start signal, and to supply the auxiliary scan pulse to a gate driver. The method of claim 1, The at least one auxiliary stage is And a pre-charged period during which the start signal is supplied to output an auxiliary scan pulse synchronized with the at least one clock pulse. The method of claim 2, The at least one clock pulse 2. The driving apparatus of a liquid crystal display device having a pulse width of two horizontal sections and being overlapped with each other for a predetermined period. The method of claim 2, And the start signal is generated with a pulse width of one horizontal section. The method of claim 1, The gate driver And a shift register composed of at least one stage connected dependently to each other. 6. The method of claim 5, The at least one auxiliary stage is And a driving device of the liquid crystal display device, wherein the shift register is built in the shift register. Generating at least one clock pulse and a start signal that are out of phase with each other; Generating an auxiliary scan pulse according to the at least one clock pulse and the start signal; Generating a scan pulse according to the auxiliary scan pulse and the at least one clock pulse; And And supplying the scan pulse to a gate line. The method of claim 7, wherein Generating the auxiliary scan pulse Precharging for a period during which the start signal is supplied; Receiving the at least one clock pulse; And And generating an auxiliary scan pulse synchronized with the at least one clock pulse. 9. The method of claim 8, The at least one clock pulse 2. A method of driving a liquid crystal display device, the pulse width of which is generated so as to overlap each other for a predetermined period. The method of claim 9, And the start signal is generated with a pulse width of one horizontal section.

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