TWI713008B - Driving circuit and the operation method thereof - Google Patents

Abstract

The present disclosure is related to a driving circuit. The driving circuit includes a first driving element, a second driving element, and a control circuit. The first driving element is enabled in response to a first control signal and a switch signal and generates a first driving signal. The second driving element is enabled in response to a second control signal and generates a second driving signal. The control circuit is coupled between the first driving element and the second driving element, and outputs selectively, based on the first control signal and the second control signal, the first driving signal from the first driving element or the second driving signal from the second driving element to a pixel array. Multiple pixel arrays in the pixel array in response to the first driving signal are driven simultaneously and being driven sequentially based on the second driving signal.

Description

Drive circuit and its operation method

This case is about a driving circuit applied to pixel circuits, especially a driving circuit including progressive and simultaneous driving pixel circuits.

Progressive scanning mode and simultaneous mode driving circuits have been widely used in circuits for driving pixel arrays, so that the pixel arrays emit light in response to progressive driving signals and simultaneous driving signals, respectively. However, in some conventional technologies, the shorting bar control circuit (shorting bar control circuit) used to switch the pixel array to receive the above two types of signals is too bulky, and the complicated circuit also causes the output signal of the shorting bar control circuit. The reaction time is too long. In other technologies, it is necessary to configure a set of voltages different from the supply voltage of the drive circuit to control the short-circuit control circuit.

The present disclosure provides a driving circuit. The driving circuit includes at least one first driving unit, at least one second driving unit, and a control circuit. At least one first driving unit is used to be enabled in response to the first control signal and the switching signal And generate the first driving signal. At least one second driving unit is used for being enabled in response to the second control signal and generating a second driving signal. The control circuit is coupled between at least one first driving unit and at least one second driving unit, and the control circuit is used for selecting to output the first driving signal from the at least one first driving unit according to the first control signal and the second control signal or The second driving signal is output from the at least one second driving unit as an output signal to the at least one pixel array. Wherein, each column of pixels in at least one pixel array is simultaneously driven in response to the first driving signal, or each column of pixels in at least one pixel array is sequentially driven according to the second driving signal.

The present disclosure provides a driving circuit operation method. The method includes the following steps: turning off the control circuit in response to a first control signal and a second control signal, and simultaneously driving a pixel array according to the first driving signal output from the first driving unit Each row of pixels in the pixel array; and by turning on the control circuit, each row of pixels in the pixel array is gradually driven according to the second driving signal output from the second driving unit.

The above-mentioned driving circuit and its operation method can output signals from the simultaneous driving unit and the progressive scan driving unit through selective conduction of the simplified control circuit, and drive the pixel array in the simultaneous driving mode and the progressive scan driving mode respectively through the output signals .

100‧‧‧Drive circuit

110‧‧‧Control circuit

120‧‧‧Simultaneous drive unit

130, 1301~130n‧‧‧Scan drive unit

111、112‧‧‧Switch

200, 2001~200n‧‧‧Pixel array

CL1, CL2‧‧‧Control signal

SC‧‧‧Switch signal

CK‧‧‧clock signal

OUT, OUT[0]~OUT[n]‧‧‧output signal

IN‧‧‧Scan signal

DS1, DS2‧‧‧Drive signal

121‧‧‧Inverter

122‧‧‧Reverse or gate

123‧‧‧Pull-down control circuit

124‧‧‧Pull up control circuit

125‧‧‧Pull-up circuit

126‧‧‧Pull-down circuit

T1, T2, T3, T4, T5, T6, T7, T8, T9, T10‧‧‧Transistor

Q, N, K‧‧‧node

VGH, VGL‧‧‧Supply voltage terminal

T1, T2‧‧‧Time interval

T11, T12, T13‧‧‧sub interval

In order to make the above and other purposes, features, advantages and embodiments of the content of this case more obvious and understandable, the description of the attached drawings is as follows:

FIG. 1 is a block diagram of a driving circuit and pixel array according to an embodiment of the present application;

Figure 2 is a schematic diagram of the simultaneous driving unit shown in Figure 1 according to an embodiment of the present case;

FIG. 3 is a circuit diagram of the simultaneous driving unit shown in FIG. 2 according to an embodiment of the present case;

Figure 4 is a schematic diagram of waveforms of various control signals and node levels according to an embodiment of the present case;

5A to 5D are schematic diagrams of the equivalent circuit operation of the simultaneous driving unit shown in FIG. 3 in operation according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of the scan driving unit shown in FIG. 1 according to an embodiment of the present case; and

FIG. 7 is a block diagram of a driving circuit and pixel array according to another embodiment of the present application.

The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

Regarding the "coupling" or "connection" used in this article, it can mean that two or more components make physical or electrical contact with each other directly, or make physical or electrical contact with each other indirectly, or can refer to two or more Interoperability or action of components.

In this article, the term "circuit" generally refers to an object that is connected in a certain manner by one or more transistors and/or one or more active and passive components to process signals.

Certain words are used in the specification and the scope of the patent application to refer to specific elements. However, those with general knowledge in the technical field should be able to Understand that the same element may be called by different terms. The specification and the scope of the patent application do not use the difference in names as a way of distinguishing elements, but the difference in function of the elements as the basis for distinguishing. The "including" mentioned in the specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to".

Please refer to Figure 1. FIG. 1 is a block diagram of a driving circuit 100 and a pixel array 200 according to an embodiment of the present application. As shown in FIG. 1, the driving circuit 100 and the pixel array 200 are coupled to the output terminal of the driving circuit 100. The driving circuit 100 includes a control circuit 110, a simultaneous driving unit 120 and a scanning driving unit 130. In terms of connection relationship, the control circuit 110 is coupled between the output terminal of the driving circuit 100 and the scan driving unit 130, while the driving unit 120 is coupled with the output terminal of the driving circuit 100.

As shown in Figure 1, the control circuit 110 includes switches 111 to 112. In some embodiments, the switch 111 can be implemented by any suitable type of P-type transistor, such as a P-type thin-film transistor (TFT) or a P-type metal oxide semiconductor transistor, etc. The switch 112 can be Any suitable type of N-type transistor can be implemented. In the embodiment shown in Figure 1, the first end of the switch 111 is coupled to the scan driving unit 130, the second end of the switch 111 is coupled to the simultaneous driving unit 120, and the control end of the switch 111 is used to receive the control signal CL1. In addition, the first terminal and the second terminal of the switch 112 are coupled to the first terminal and the second terminal of the switch 111, and the control terminal of the switch 112 is used to receive the control signal CL2. The foregoing description of the components in the control circuit 110 is used as an example for understanding the implementation of the case, and is not intended to limit the case. Other different ways of implementing this case are also within the scope of this case.

In some embodiments, the scan driving unit 130 is implemented by display panel driving scan (Gate driver on array, GOA). The scan driving unit 130 is used to drive a column of pixels in the pixel array 200 through the output driving signal. In other words, the output drive signal turns on a row of transistors corresponding to the row of pixels, so that data signals such as controlling brightness, grayscale, color, etc. are input to the row of pixels, and then the output drive signal turns off the row of pixels. Columns of pixels and turn on the next column of pixels until the data writing of each column of pixels in the pixel array 200 is completed. The specific operation of the scan driving unit 130 provided in this case will be described in detail later.

In terms of operation, the driving unit 120 is also used to respond to the control signal CL1 and the switching signal SC being enabled and generate a driving signal DS1, and the scan driving unit 130 is used to respond to the control signal CL2 being enabled and generate a driving signal DS2, and then The control circuit 110 is used to select the simultaneous driving unit 120 to output the driving signal DS1 or the scan driving unit 130 to output the driving signal DS2 as the output signal OUT to the pixel array 200 according to the control signals CL1 and CL2. Each pixel is simultaneously driven in response to the driving signal DS1 as the output signal OUT, or sequentially driven according to the driving signal DS2 as the output signal OUT to receive a data signal.

For example, in some embodiments, when the simultaneous driving unit 120 outputs the driving signal DS1 as the output signal OUT to the pixel array 200, each column of pixels in the pixel array 200 is driven to perform reset and reset simultaneously. / Or compensation, in other words, the simultaneous driving unit 120 outputs a pulse wave with the same waveform to each pixel in the pixel array 200 at a time, so that these pixels are simultaneously driven to perform operations; in addition, , The scan drive unit 130 outputs drive information When DS2 is used as the output signal OUT to the pixel array 200, each row of pixels in the pixel array 200 is sequentially driven to be written with data, emit light, etc. The above embodiments are provided only for the purpose of easy understanding of this case, but the implementation of this case is not limited to this. The specific operations of the control circuit 110, the simultaneous driving unit 120, and the scanning driving unit 130 provided in this case will be described in detail later.

Please refer to Figure 2. FIG. 2 is a schematic diagram of the simultaneous driving unit 120 shown in FIG. 1 according to an embodiment of the present application. As shown in FIG. 2, the simultaneous driving unit 120 includes an inverter 121, an inverter 122, a pull-down control circuit 123, a pull-up control circuit 124, a pull-up circuit 125 and a pull-down circuit 126. The input terminal of the inverter 121 is used to receive the control signal CL1, the output terminal of the inverter 121 is coupled to the first input terminal of the inverter 122, and the second input terminal of the inverter 122 is used to receive the switching signal SC. The control circuit 123 is coupled between the pull-down circuit 126 and the second output terminal of the NOR gate 122, and the pull-up control circuit 124 is coupled between the pull-up circuit 125 and the output terminal of the NOR gate 122.

Please refer to Figure 3. FIG. 3 is a circuit diagram of the simultaneous driving unit 120 shown in FIG. 2 according to an embodiment of the present application. As shown in Figure 3, inverter 121 includes transistors T1 and T2, inverter 122 includes transistors T3, T4, T5, and T6, pull-down control circuit 123 includes transistor T7, and pull-up control circuit 124 includes transistors T8, the pull-up circuit 125 includes a transistor T9, and the pull-down circuit 126 includes a transistor T10, wherein the transistors T1, T3, T4, T7, and T9 are P-type transistors, and the transistors T2, T5, T6, T8, T10 are N Type transistor. It should be noted that the implementations of the inverter 121, the inverter 122, the pull-down control circuit 123, and the pull-up control circuit 124 are used as examples for easy understanding of this case, and other circuit configurations are also within the scope of implementation of this case. For example, transistor T1, T3, T4, T7, and T9 can be implemented with N-type transistors. Accordingly, the transistors T2, T5, T6, T8, and T10 are P-type transistors, and the control signals applied to these transistors will be adjusted accordingly.

Specifically, in some embodiments, as shown in Figure 3, the first end of the transistor T1 is coupled to the first end of the transistor T2, and the second end of the transistor T1 is coupled to the second end of the transistor T2. The third terminal of the transistor T1 is coupled to the supply voltage terminal VGH, the third terminal of the transistor T2 is coupled to the supply voltage terminal VGL, and the level of the supply voltage terminal VGH is high The level of the supply voltage terminal VGL. .

Continuing the above embodiment, the first end of the transistor T3 in the inverter 122 is coupled to the first end of the transistor T4, and the second end of the transistor T4 is connected to the first end of the transistor T5 and the second end of the transistor T6. One end is coupled and used as the output terminal of the NOR gate 122 (node N), and the second end of the transistor T3 is coupled to the second end of the transistor T5 and used as the first input terminal (node Q) of the NAND 122 , The third terminal of the transistor T4 and the second terminal of the transistor T6 are coupled to serve as the second input terminal of the inverter 122, the third terminal of the transistor T3 is coupled to the supply voltage terminal VGH, and the second terminal of the transistor T5 The three terminals and the third terminal of the transistor T6 are coupled to the supply voltage terminal VGL.

In addition, the first end of the transistor T7 in the pull-down control circuit 123 is coupled to the second end of the transistor T4 and the second end of the transistor T6. The first end of the transistor T7 is used to couple the switching signal SC. The second terminal of the crystal T7 is coupled to the supply voltage terminal VGH. A first end of the transistor T8 in the pull-up control circuit 124 is coupled to the third end of the transistor T7 at the node K. The transistor T8 is used to receive the control signal CL1, and the third end of the transistor T8 is coupled to the second end of the transistor T4, the first end of the transistor T5, and the first end of the transistor T6.

Following the above embodiment, the first terminal of the transistor T9 in the pull-up circuit 125 is coupled to the supply voltage terminal VGH, and the second terminal of the transistor T9 is coupled to the third terminal of the transistor T7 and the first terminal of the transistor T8 . The first terminal of the transistor T10 in the pull-down circuit 126 is coupled to the third terminal of the transistor T9 and the output terminal of the simultaneous driving unit 120, the second terminal of the transistor T10 is coupled to the supply voltage terminal VGL, and the second terminal of the transistor T10 The three terminals are coupled to the third terminal of the transistor T8.

Please refer to Figure 4. FIG. 4 is a schematic diagram of various control signals and waveforms of each node level according to an embodiment of the present case. In some embodiments, the control signal shown in FIG. 4 may be implemented in the driving circuit 100 shown in FIG. 1, and the simultaneous driving unit 120 in the driving circuit 100 responds to The operation of the various signals shown will be as shown in the embodiments in FIGS. 5A to 5D.

As shown in Figure 4, in the time interval T1, the control signal CL1 has a high level and the control signal CL2 has a low level, and the driving circuit 100 operates in a simultaneous mode to output the driving signal DS1 as the output signal OUT to the pixel The array 200, and in the time interval T2, the control signal CL1 has a low level and the control signal CL2 has a high level, and the driving circuit 100 operates in a progressive mode to output the driving signal DS2 as the output signal OUT to the pixel array 200 In other words, the time of operating the pixel array 200 in each mode can be changed by adjusting the time when the control signals CL1 and CL2 have high and low levels respectively, which means that the simultaneous driving time and the progressive driving time of the pixel array 200 can be changed. It is important to note that the output signal OUT can include output signals OUT[0]~OUT[n] corresponding to the n columns of pixels in the pixel array 200, but for the sake of brevity, only the pixels are shown in Figure 4. Of 200 in array The output signal OUT received by a column of pixels.

Please refer to Figure 5A to Figure 5D. FIGS. 5A to 5D are schematic diagrams of equivalent circuit operation of the simultaneous driving unit 120 shown in FIG. 3 in operation according to an embodiment of the present invention. For ease of understanding, the same elements in FIGS. 5A to 5D as in FIG. 3 will be marked with the same reference signs. Unless it is necessary to explain the cooperative relationship with the elements shown in FIGS. 5A to 5D, for the sake of brevity, specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted here.

Please refer to Figure 4 and Figure 5A together. Specifically, in the sub-interval T11 in the time interval T1, the control signal CL1 has a high level. Accordingly, the transistor T1 is turned off, the transistor T2 is turned on, and the node Q level is at a low potential (compared with a low potential The supply voltage terminal VGL is turned on), in other words, the control signal CL1 with a high level is outputted as a signal with a low level after passing through the inverter 121. Then, in response to the low potential of the node Q, the transistor T3 is turned on and the transistor T5 is turned off, and in response to the switching signal SC with a high potential, the transistor T4 is turned off and the transistor T6 is turned on, and accordingly the node N has a low potential (Connected to the supply voltage terminal VGL with a low potential). In other words, the first input terminal (node Q) of the NOR gate 122 receives a low potential, and its second input terminal (the switching signal SC) receives a high potential. The output terminal (node N) outputs a low potential. The switching signal SC corresponding to the high potential of the transistor T7 is turned off, and the control signal CL1 of the corresponding high potential of the transistor T8 is turned on, so that the node K has a low potential, the transistor T9 is turned on and the transistor T10 is turned off, and the unit is driven at the same time The output terminal of 120 outputs a high-level driving signal DS1 from the supply voltage terminal VGH as the output signal OUT.

Continuing the above embodiment, please refer to Fig. 4 and Fig. 5B together Figure. In the sub-interval T12 in the time interval T1, the control signal CL1 has a high level, the transistor T1 is turned off, the transistor T2 is turned on, and the node Q is at a low level. In other words, the inverter 121 still outputs a low level Signal. Then, in response to the low potential of the node Q, the transistor T3 turns on and the transistor T5 turns off, and in response to the switching signal SC that switches to the low potential, the transistor T4 turns on and the transistor T6 turns off. Accordingly, the node N has a high Potential (connected to the supply voltage terminal VGH with a high potential). In other words, the first input terminal (node Q) of the NOR gate 122 receives a low potential, and the second input terminal (switching signal SC) receives a low potential, then The output terminal (node N) outputs a high potential. The switching signal SC corresponding to the low potential of the transistor T7 is turned on, so that the node K has a high potential, the control signal CL1 of the corresponding high potential of the transistor T8 and the high potential of the node K are turned off, the transistor T9 is turned off accordingly, and the transistor T10 is turned on. At this time, at the same time, the output terminal of the driving unit 120 outputs the low-level driving signal DS1 from the supply voltage terminal VGL as the output signal OUT.

Next, please refer to Figure 4 and Figure 5C together. In the sub-interval T13 in the time interval T1, the control signal CL1 has a high level, the transistor T1 is turned off, the transistor T2 is turned on, the node Q is at a low potential, and the inverter 121 outputs a signal with a low potential. Then, in response to the low potential of the node Q, the transistor T3 is turned on and the transistor T5 is turned off, and in response to the switching signal SC with a high potential, the transistor T4 is turned off and the transistor T6 is turned on, and accordingly the node N has a low potential In other words, the output terminal (node N) of the inverter 122 outputs a low level. The switching signal SC corresponding to the high potential of the transistor T7 is turned off, the control signal CL1 corresponding to the high potential of the transistor T8 is turned on, the node K has a low potential, the transistor T9 is turned on accordingly, and the transistor T10 is turned off. At this time, the unit 120 is driven at the same time The output terminal of the voltage supply terminal VGH outputs a high-level driving signal DS1 as the output signal OUT.

As described above, the driving circuit 100 works in the simultaneous mode. In the time interval T1, the driving unit 120 responds to the high-level control signal CL1 to output the output signal OUT, and at the same time, the control circuit 110 is turned off in response to the control signals CL1 and CL2. As a result, each column of the pixel array 200 receives the output signal OUT from the simultaneous driving unit 120 and operates at the same time. For example, in some embodiments, a transistor included in each column of the pixel array 200 is turned on or off in response to the output signal OUT to perform the pixel circuit Vth compensation. Those with ordinary knowledge in the art should understand the related technology of pixel circuit Vth compensation, which will not be repeated here.

It should be noted that, as shown in Figure 4, in the time interval T1, that is, in the simultaneous mode, the driving signal DS1 output from the simultaneous driving unit 120 and the switching signal SC have the same phase level, in other words By changing the duty cycle of the switching signal SC, the duty cycle of the driving signal DS1 can be changed to further change the simultaneous driving time.

Continuing the above embodiment, please refer to Fig. 4 and Fig. 5D together. In the time interval T2, the control signal CL1 has a low level, the transistor T1 is turned on, the transistor T2 is turned off, and the node Q is at a high level. In other words, the control signal CL1 with a low level passes through the inverter 121 It is output as a signal with high potential. Then, in response to the high potential of the node Q, the transistor T3 is turned off, the transistor T5 is turned on, and in response to the switching signal SC that switches to the low potential, the transistor T4 is turned on and the transistor T6 is turned off, and accordingly the node N has a low potential (Connected to the supply voltage terminal VGL with a low potential). In other words, the first input terminal (node Q) of the NOR gate 122 receives a high potential, and its second input terminal (the switching signal SC) receives a low potential. The output terminal (node N) outputs a low potential. The switching signal SC corresponding to the low potential of the transistor T7 is turned on, so that the node K has a high potential, and the transistor T8 corresponds to The low-potential control signal CL1 is turned off, the transistor T9 is turned off accordingly, and the transistor T10 is turned off. At this time, the driving unit 120 does not output any signal. In some embodiments, the output terminal of the driving unit 120 is in a floating state. But this case is not limited to this.

Please refer to Figure 6. FIG. 6 is a schematic diagram of the scan driving unit 130 shown in FIG. 1 according to an embodiment of the present application. As shown in FIG. 6, the scan driving unit 130 includes transistors T11, T12, T13, T14, T15, T16, and capacitors C1, C2. Transistor T11 is coupled to transistors T12, T15, T16, transistor T12 is coupled to capacitor C1, transistor T14 is coupled to transistors T15, T16, and transistor T13 is coupled to capacitors C1, C2. The scan driving unit 130 is used for responding to the operation of the scan signal IN and the pulse signals CK1 and CK2 to output the driving signal DS2 as the output signal OUT to the pixel array 200. It should be noted that the scan driving unit 130 shown in Figure 6 is only for example. Any circuit that sequentially provides pulse signals during different enabling periods to drive multiple columns of pixels, such as any GOA circuit, Both can be used to implement this case. Those with ordinary knowledge in the field should understand the principle of GOA operation. The operation process of the GOA circuit will not be repeated here.

Please refer to Figure 4 again. In the time interval T2, the control signal CL1 has a low potential and the control signal CL2 has a high potential, so that the scan driving unit 130 is enabled and the control circuit 110 is turned on, so that the driving signal DS2 generated by the scan driving unit 130 is used as the output signal OUT. As shown in Figure 4, when the scan signal IN is a pulse signal, the corresponding pulse signal is output as the driving signal DS2 through the cooperative operation of the components in the scan driving unit 130, and the control circuit 110 is turned on in response to the control signals CL1 and CL2. Then the control circuit 110 outputs the output signal OUT from the scan driving unit 130.

Please refer to Figure 7. FIG. 7 is a block diagram of the driving circuit 100 and the pixel array 200 according to another embodiment of the present invention. As shown in Figure 7, the driving circuit 100 includes a plurality of scan driving units 1301~130n, the control circuit 110 correspondingly includes a plurality of sets of coupled switches 111~112, a pixel array 2001~200n and a plurality of sets in the control circuit 110 The switches 111 to 112 are coupled, and at least one simultaneous driving unit 120 is coupled to the scan driving units 1301 to 130n. In some embodiments, in the simultaneous mode, the simultaneous driving unit 120 simultaneously drives the pixel arrays 2001 to 200n. In some embodiments, the number of simultaneous driving units 110 and scan driving included in the driving circuit 100 is 1 to N, and N is a positive integer equal to or greater than 1.

In summary, the driving circuit and its operation method of the present case can output signals from the simultaneous driving unit and the progressive scanning driving unit through the selective conduction of the simplified control circuit, and drive the pixel array in the simultaneous driving mode through the output signals. Compared with the progressive scan driving mode, in this way, by applying the control circuit provided in this case in the driving circuit, the volume of the driving circuit will be greatly reduced.

In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case.

The above are only the preferred embodiments of the present disclosure, and all equal changes and modifications made in accordance with the requirements of the present disclosure should fall within the scope of the disclosure.

100‧‧‧Drive circuit

110‧‧‧Control circuit

120‧‧‧Simultaneous drive unit

130‧‧‧Scan Drive Unit

111、112‧‧‧Switch

200‧‧‧Pixel array

CL1, CL2‧‧‧Control signal

SC‧‧‧Switch signal

CK‧‧‧clock signal

OUT‧‧‧Output terminal

Claims (12)

A drive circuit, including: At least one first driving unit for being enabled in response to a first control signal and a switching signal and generating a first driving signal; At least one second driving unit for being enabled in response to a second control signal and generating a second driving signal; and A control circuit, the control circuit is coupled between the at least one first driving unit and the at least one second driving unit, and the control circuit is used to select from the at least one according to the first control signal and the second control signal A first drive unit outputs the first drive signal or outputs the second drive signal from the at least one second drive unit as an output signal to at least one pixel array; Wherein, each column of pixels in the at least one pixel array is simultaneously driven in response to the first driving signal, or each column of pixels in the at least one pixel array is sequentially driven according to the second driving signal. The driving circuit according to claim 1, wherein the control circuit includes: A first switch, a first end of the first switch is coupled to the at least one first driving unit, a second end of the first switch is coupled to the at least one second driving unit, and the A control terminal for receiving the first control signal; and A second switch, a first terminal and a second terminal of the second switch are respectively coupled to the first terminal and the second terminal of the first switch, and a control terminal of the second switch is used for receiving the The second control signal. The driving circuit according to claim 1, wherein the at least one first driving unit includes: A reverse OR gate, a first input terminal of the reverse OR gate is used to receive the switching signal; An inverter, an input terminal of the inverter for receiving the first control signal, and an output terminal of the inverter coupled to a second input terminal of the inverter; A pull-down circuit; A pull-down control circuit, which is coupled between the pull-down circuit and the first input terminal of the inverter; A pull-up circuit; and A pull-up control circuit, the pull-up control circuit is coupled between the pull-up circuit and an output terminal of the inverter. The driving circuit according to claim 3, wherein The inverter includes a first transistor and a second transistor, wherein a first end of the first transistor is coupled to a first end of the second transistor, and a first end of the first transistor is Two ends and a second end of the second transistor are used as the input end of the inverter; The reverse OR gate includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein a first end of the third transistor and a first end of the fourth transistor Terminal is coupled, a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor, and a first terminal of the sixth transistor is coupled to serve as the output terminal of the inverter, the A second end of the third transistor and the fifth transistor A second end of the crystal is coupled and used as the second input end of the NOR gate, a third end of the fourth transistor and a second end of the sixth transistor are used as the NOR gate The first input terminal; The pull-down control circuit includes a seventh transistor, wherein a first end of the seventh transistor is coupled to the second end of the fourth transistor and the second end of the sixth transistor, and the seventh transistor The first end of the transistor is used for receiving the switching signal; The pull control circuit includes an eighth transistor, wherein a first end of the eighth transistor is coupled to a second end of the seventh transistor, and a second end of the eighth transistor is used for receiving For the first control signal, a third end of the eighth transistor is coupled to the first end of the sixth transistor; The pull-up circuit includes a ninth transistor, wherein a first end of the ninth transistor is coupled to the second end of the seventh transistor and the first end of the eighth transistor; and The pull-down circuit includes a tenth transistor, wherein a first terminal of the tenth transistor and a second terminal of the ninth transistor are coupled to an output terminal of the first driving unit. The driving circuit according to claim 1, wherein the at least one first driving unit includes: A first transistor and a second transistor, a first end of the first transistor is coupled to a first end of the second transistor, and a second end of the first transistor is coupled to a first end A supply voltage terminal, a second terminal of the second transistor is coupled to a second supply voltage terminal, a third terminal of the first transistor and the second transistor A third terminal of is coupled to an input terminal for receiving the first control signal; A third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, a first end of the third transistor is coupled to a first end of the fourth transistor, the first A second terminal of the three transistors is coupled to the first supply voltage terminal, and a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor and a first terminal of the sixth transistor. Connected, a second terminal of the fifth transistor, a second terminal of the sixth transistor are coupled to the second supply voltage terminal, and a third terminal of the fifth transistor is coupled to the second terminal of the third transistor. A third end is coupled, and a third end of the fourth transistor is coupled to a third end of the sixth transistor to receive the switching signal; A seventh transistor, a first terminal of the seventh transistor is coupled to the first supply voltage terminal, and a second terminal of the seventh transistor is used for receiving the switching signal; An eighth transistor, a first end of the eighth transistor is coupled to a third end of the seventh transistor, a second end of the eighth transistor and the first end of the sixth transistor Coupled, a third end of the eighth transistor is used to receive the first control signal; A ninth transistor, a first end of the ninth transistor is coupled to the first supply voltage end, a second end of the ninth transistor is connected to the third end of the seventh transistor, the The first end of the eight transistor is coupled; and A tenth transistor, a first terminal of the tenth transistor is coupled to a third terminal of the ninth transistor, and a second terminal of the tenth transistor is coupled to the second supply voltage terminal, A third end of the tenth transistor is coupled to the second end of the eighth transistor. The driving circuit according to claim 1, wherein When the first control signal has a high level and the second control signal has a low level, the control circuit is used for outputting the first driving signal from the at least one first driving unit; The first driving signal has a high level or a low level in response to the switching signal. The driving circuit according to claim 1, wherein When the first control signal has a low level and the second control signal has a high level, the control circuit is used to output the second driving signal from the at least one second driving unit. The driving circuit according to claim 1, wherein The number of the at least one first driving unit and the at least one second driving unit is 1 to N, and N is a positive integer equal to or greater than 1. A driving circuit operation method, including: By turning off a control circuit in response to a first control signal and a second control signal, simultaneously driving each row of pixels in a pixel array according to a first driving signal output from a first driving unit; and By turning on the control circuit, each row of pixels in the pixel array is gradually driven according to a second driving signal output from a second driving unit. The driving circuit operation method as described in claim 9, including Include: Generating the first driving signal in response to the first control signal and a switching signal through the first driving unit; The first driving signal and the switching signal have the same level. The operating method of the driving circuit as described in claim 9 further includes: When the first control signal has a low level and the second control signal has a high level, the second driving signal is output from the second driving unit to the pixel array. The operating method of the driving circuit as described in claim 9 further includes: The first control signal and the second control signal are adjusted to change a simultaneous driving time and a progressive driving time of the pixel array.

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