TWI713008B - Driving circuit and the operation method thereof - Google Patents

Driving circuit and the operation method thereof Download PDF

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Publication number
TWI713008B
TWI713008B TW108140503A TW108140503A TWI713008B TW I713008 B TWI713008 B TW I713008B TW 108140503 A TW108140503 A TW 108140503A TW 108140503 A TW108140503 A TW 108140503A TW I713008 B TWI713008 B TW I713008B
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Taiwan
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transistor
terminal
driving
coupled
signal
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TW108140503A
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Chinese (zh)
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郭庭瑋
洪嘉澤
林振祺
奚鵬博
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友達光電股份有限公司
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Priority claimed from CN202010326433.1A external-priority patent/CN111402777A/en
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Publication of TWI713008B publication Critical patent/TWI713008B/en

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Abstract

The present disclosure is related to a driving circuit. The driving circuit includes a first driving element, a second driving element, and a control circuit. The first driving element is enabled in response to a first control signal and a switch signal and generates a first driving signal. The second driving element is enabled in response to a second control signal and generates a second driving signal. The control circuit is coupled between the first driving element and the second driving element, and outputs selectively, based on the first control signal and the second control signal, the first driving signal from the first driving element or the second driving signal from the second driving element to a pixel array. Multiple pixel arrays in the pixel array in response to the first driving signal are driven simultaneously and being driven sequentially based on the second driving signal.

Description

驅動電路和其操作方法Drive circuit and its operation method

本案是關於一種應用於畫素電路的驅動電路,特別是關於一種包含漸進式及同時式驅動畫素電路的驅動電路。 This case is about a driving circuit applied to pixel circuits, especially a driving circuit including progressive and simultaneous driving pixel circuits.

漸進掃描式(progressive scanning mode)以及同時式(simultaneous mode)驅動電路已被廣泛應用於驅動畫素陣列的電路中,使得畫素陣列分別響應漸進式驅動訊號以及同時式驅動訊號而發光。然而,在一些習知的技術中,用以切換畫素陣列接收上述二種訊號的短路線控制電路(shorting bar control circuit)的體積過於龐大,同時複雜的電路亦造成短路線控制電路的輸出訊號反應時間過長。而在另一些技術中,需要另外配置一組與驅動電路之供應電壓不同的電壓原來控制該短路線控制電路。 Progressive scanning mode and simultaneous mode driving circuits have been widely used in circuits for driving pixel arrays, so that the pixel arrays emit light in response to progressive driving signals and simultaneous driving signals, respectively. However, in some conventional technologies, the shorting bar control circuit (shorting bar control circuit) used to switch the pixel array to receive the above two types of signals is too bulky, and the complicated circuit also causes the output signal of the shorting bar control circuit. The reaction time is too long. In other technologies, it is necessary to configure a set of voltages different from the supply voltage of the drive circuit to control the short-circuit control circuit.

本揭示文件提供一種驅動電路,驅動電路包含至少一第一驅動單元、至少一第二驅動單元以及控制電路。至少一第一驅動單元用以響應於第一控制訊號和切換訊號被致能 並產生第一驅動訊號。至少一第二驅動單元用以響應於第二控制訊號被致能並產生第二驅動訊號。控制電路耦接於至少一第一驅動單元以及至少一第二驅動單元之間,並且控制電路用以根據第一控制訊號和第二控制訊號選擇自至少一第一驅動單元輸出第一驅動訊號或自至少一第二驅動單元輸出第二驅動訊號作為一輸出訊號至至少一畫素陣列。其中,至少一畫素陣列中的每一列畫素同時響應於第一驅動訊號被驅動,或至少一畫素陣列中的每一列畫素根據第二驅動訊號被先後驅動。 The present disclosure provides a driving circuit. The driving circuit includes at least one first driving unit, at least one second driving unit, and a control circuit. At least one first driving unit is used to be enabled in response to the first control signal and the switching signal And generate the first driving signal. At least one second driving unit is used for being enabled in response to the second control signal and generating a second driving signal. The control circuit is coupled between at least one first driving unit and at least one second driving unit, and the control circuit is used for selecting to output the first driving signal from the at least one first driving unit according to the first control signal and the second control signal or The second driving signal is output from the at least one second driving unit as an output signal to the at least one pixel array. Wherein, each column of pixels in at least one pixel array is simultaneously driven in response to the first driving signal, or each column of pixels in at least one pixel array is sequentially driven according to the second driving signal.

本揭示文件提供一種驅動電路操作方法,此方法包含以下步驟:藉由響應第一控制訊號和第二控制訊號關斷控制電路,根據自第一驅動單元輸出的第一驅動訊號同時驅動畫素陣列中的每一列畫素;以及藉由導通控制電路,根據自第二驅動單元輸出的第二驅動訊號漸進地驅動畫素陣列中的每一列畫素。 The present disclosure provides a driving circuit operation method. The method includes the following steps: turning off the control circuit in response to a first control signal and a second control signal, and simultaneously driving a pixel array according to the first driving signal output from the first driving unit Each row of pixels in the pixel array; and by turning on the control circuit, each row of pixels in the pixel array is gradually driven according to the second driving signal output from the second driving unit.

上述的驅動電路和其操作方法能透過精簡的控制電路選擇性導通而分別自同時驅動單元與漸進掃描驅動單元輸出訊號,並透過輸出訊號將畫素陣列分別驅動於同時驅動模式與漸進掃描驅動模式。 The above-mentioned driving circuit and its operation method can output signals from the simultaneous driving unit and the progressive scan driving unit through selective conduction of the simplified control circuit, and drive the pixel array in the simultaneous driving mode and the progressive scan driving mode respectively through the output signals .

100‧‧‧驅動電路100‧‧‧Drive circuit

110‧‧‧控制電路110‧‧‧Control circuit

120‧‧‧同時驅動單元120‧‧‧Simultaneous drive unit

130、1301~130n‧‧‧掃描驅動單元130, 1301~130n‧‧‧Scan drive unit

111、112‧‧‧開關111、112‧‧‧Switch

200、2001~200n‧‧‧畫素陣列200, 2001~200n‧‧‧Pixel array

CL1、CL2‧‧‧控制訊號CL1, CL2‧‧‧Control signal

SC‧‧‧切換訊號SC‧‧‧Switch signal

CK‧‧‧時脈訊號CK‧‧‧clock signal

OUT、OUT[0]~OUT[n]‧‧‧輸出訊號OUT, OUT[0]~OUT[n]‧‧‧output signal

IN‧‧‧掃描訊號IN‧‧‧Scan signal

DS1、DS2‧‧‧驅動訊號DS1, DS2‧‧‧Drive signal

121‧‧‧反向器121‧‧‧Inverter

122‧‧‧反或閘122‧‧‧Reverse or gate

123‧‧‧下拉控制電路123‧‧‧Pull-down control circuit

124‧‧‧拉升控制電路124‧‧‧Pull up control circuit

125‧‧‧拉升電路125‧‧‧Pull-up circuit

126‧‧‧下拉電路126‧‧‧Pull-down circuit

T1、T2、T3、T4、T5、T6、T7、T8、T9、T10‧‧‧電晶體T1, T2, T3, T4, T5, T6, T7, T8, T9, T10‧‧‧Transistor

Q、N、K‧‧‧節點Q, N, K‧‧‧node

VGH、VGL‧‧‧供應電壓端VGH, VGL‧‧‧Supply voltage terminal

T1、T2‧‧‧時間間隔T1, T2‧‧‧Time interval

T11、T12、T13‧‧‧子間隔T11, T12, T13‧‧‧sub interval

為讓本案內容之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下: In order to make the above and other purposes, features, advantages and embodiments of the content of this case more obvious and understandable, the description of the attached drawings is as follows:

第1圖為根據本案一實施例所繪示的一種驅動電路及畫素陣列的方塊示意圖; FIG. 1 is a block diagram of a driving circuit and pixel array according to an embodiment of the present application;

第2圖為根據本案一實施例所繪示如第1圖中所示的同時驅動單元的示意圖; Figure 2 is a schematic diagram of the simultaneous driving unit shown in Figure 1 according to an embodiment of the present case;

第3圖為根據本案一實施例所繪示如第2圖中所示的同時驅動單元的電路圖; FIG. 3 is a circuit diagram of the simultaneous driving unit shown in FIG. 2 according to an embodiment of the present case;

第4圖為根據本案一實施例所繪示的多種控制信號以及節點位準的波形示意圖; Figure 4 is a schematic diagram of waveforms of various control signals and node levels according to an embodiment of the present case;

第5A圖至第5D圖為根據本案一實施例所繪示如第3圖中所示之同時驅動單元於運作時的等效電路操作示意圖; 5A to 5D are schematic diagrams of the equivalent circuit operation of the simultaneous driving unit shown in FIG. 3 in operation according to an embodiment of the present invention;

第6圖為根據本案一實施例所繪示如第1圖中所示的掃描驅動單元的示意圖;以及FIG. 6 is a schematic diagram of the scan driving unit shown in FIG. 1 according to an embodiment of the present case; and

第7圖為根據本案另一實施例所繪示的一種驅動電路及畫素陣列的方塊示意圖。 FIG. 7 is a block diagram of a driving circuit and pixel array according to another embodiment of the present application.

以下將配合相關圖式來說明本揭示文件的實施例。在圖式中,相同的標號表示相同或類似的元件或方法流程。 The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

關於本文中所使用之『耦接』或『連接』,均可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,亦可指二或多個元件相互操作或動作。 Regarding the "coupling" or "connection" used in this article, it can mean that two or more components make physical or electrical contact with each other directly, or make physical or electrical contact with each other indirectly, or can refer to two or more Interoperability or action of components.

在本文中,用語『電路』泛指由一或多個電晶體與/或一或多個主被動元件按一定方式連接以處理訊號的物件。 In this article, the term "circuit" generally refers to an object that is connected in a certain manner by one or more transistors and/or one or more active and passive components to process signals.

在說明書及申請專利範圍中使用了某些詞彙來指稱特定的元件。然而,所屬技術領域中具有通常知識者應可 理解,同樣的元件可能會用不同的名詞來稱呼。說明書及申請專利範圍並不以名稱的差異做為區分元件的方式,而是以元件在功能上的差異來做為區分的基準。在說明書及申請專利範圍所提及的「包含」為開放式的用語,故應解釋成「包含但不限定於」。 Certain words are used in the specification and the scope of the patent application to refer to specific elements. However, those with general knowledge in the technical field should be able to Understand that the same element may be called by different terms. The specification and the scope of the patent application do not use the difference in names as a way of distinguishing elements, but the difference in function of the elements as the basis for distinguishing. The "including" mentioned in the specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to".

請參照第1圖。第1圖為根據本案一實施例所繪示的一種驅動電路100及畫素陣列200的方塊示意圖。如第1圖所示,驅動電路100與畫素陣列200耦接於驅動電路100的輸出端。驅動電路100包含控制電路110、同時驅動單元120以及掃描驅動單元130。在連接關係上,控制電路110耦接於驅動電路100的輸出端與掃描驅動單元130之間,同時驅動單元120與驅動電路100的輸出端耦接。 Please refer to Figure 1. FIG. 1 is a block diagram of a driving circuit 100 and a pixel array 200 according to an embodiment of the present application. As shown in FIG. 1, the driving circuit 100 and the pixel array 200 are coupled to the output terminal of the driving circuit 100. The driving circuit 100 includes a control circuit 110, a simultaneous driving unit 120 and a scanning driving unit 130. In terms of connection relationship, the control circuit 110 is coupled between the output terminal of the driving circuit 100 and the scan driving unit 130, while the driving unit 120 is coupled with the output terminal of the driving circuit 100.

如第1圖所示,控制電路110包含開關111~112。在一些實施例中,開關111可以任何合適種類的P型電晶體來實現,例如P型薄膜電晶體(Thin-film Transistor,簡稱TFT)或是P型金氧半導體電晶體等等,開關112可以任何合適種類的N型電晶體來實現。在如第1圖所示的實施例中,開關111的第一端與掃描驅動單元130耦接,開關111的第二端與同時驅動單元120耦接,開關111的控制端用以接收控制訊號CL1,此外,開關112的第一端與第二端與開關111的第一端、第二端耦接,開關112的控制端用以接收控制訊號CL2。上述關於控制電路110中各元件的描述是作為了解本案之實施方式的舉例用,並不用以限制本案。其他不同實施本案的方式亦屬本案的涵蓋範圍。 As shown in Figure 1, the control circuit 110 includes switches 111 to 112. In some embodiments, the switch 111 can be implemented by any suitable type of P-type transistor, such as a P-type thin-film transistor (TFT) or a P-type metal oxide semiconductor transistor, etc. The switch 112 can be Any suitable type of N-type transistor can be implemented. In the embodiment shown in Figure 1, the first end of the switch 111 is coupled to the scan driving unit 130, the second end of the switch 111 is coupled to the simultaneous driving unit 120, and the control end of the switch 111 is used to receive the control signal CL1. In addition, the first terminal and the second terminal of the switch 112 are coupled to the first terminal and the second terminal of the switch 111, and the control terminal of the switch 112 is used to receive the control signal CL2. The foregoing description of the components in the control circuit 110 is used as an example for understanding the implementation of the case, and is not intended to limit the case. Other different ways of implementing this case are also within the scope of this case.

在一些實施例中,掃描驅動單元130以顯示面板驅動掃描(Gate driver on array,GOA)實施,掃描驅動單元130用以透過所輸出的驅動訊號驅動該畫素陣列200中一列畫素,具體來說,所輸出的驅動訊號導通相應該列畫素的一列電晶體,使得如控制亮度、灰階、色彩等的資料訊號被輸入至該列畫素中,接著,所輸出的驅動訊號關斷該列畫素並導通下一列畫素,直至完成畫素陣列200中每一列畫素的資料寫入。關於本案提供之掃描驅動單元130的具體運作將於後續的篇幅詳述之。 In some embodiments, the scan driving unit 130 is implemented by display panel driving scan (Gate driver on array, GOA). The scan driving unit 130 is used to drive a column of pixels in the pixel array 200 through the output driving signal. In other words, the output drive signal turns on a row of transistors corresponding to the row of pixels, so that data signals such as controlling brightness, grayscale, color, etc. are input to the row of pixels, and then the output drive signal turns off the row of pixels. Columns of pixels and turn on the next column of pixels until the data writing of each column of pixels in the pixel array 200 is completed. The specific operation of the scan driving unit 130 provided in this case will be described in detail later.

在運作關係上,同時驅動單元120用以響應控制訊號CL1以及切換訊號SC被致能並產生驅動訊號DS1,以及掃描驅動單元130用以響應於控制訊號CL2被致能並產生驅動訊號DS2,接著,控制電路110用以根據控制訊號CL1、CL2選擇自同時驅動單元120輸出驅動訊號DS1或自掃描驅動單元130輸出驅動訊號DS2作為輸出訊號OUT至畫素陣列200,其中,畫素陣列200中的每一畫素同時響應於作為輸出訊號OUT的驅動訊號DS1被驅動,或先後地根據作為輸出訊號OUT的驅動訊號DS2被驅動以接收一資料訊號。 In terms of operation, the driving unit 120 is also used to respond to the control signal CL1 and the switching signal SC being enabled and generate a driving signal DS1, and the scan driving unit 130 is used to respond to the control signal CL2 being enabled and generate a driving signal DS2, and then The control circuit 110 is used to select the simultaneous driving unit 120 to output the driving signal DS1 or the scan driving unit 130 to output the driving signal DS2 as the output signal OUT to the pixel array 200 according to the control signals CL1 and CL2. Each pixel is simultaneously driven in response to the driving signal DS1 as the output signal OUT, or sequentially driven according to the driving signal DS2 as the output signal OUT to receive a data signal.

舉例而言,在一些實施例中,在同時驅動單元120輸出驅動訊號DS1作為輸出訊號OUT至畫素陣列200時,畫素陣列200中的每一列畫素被驅動同時進行重置(reset)和/或補償等,換句話說,同時驅動單元120在一時間中輸出具有相同波型的脈波至畫素陣列200中的每一畫素,使得該些畫素同時被驅動而執行操作;此外,在掃描驅動單元130輸出驅動訊 號DS2作為輸出訊號OUT至畫素陣列200時,畫素陣列200中的每一列畫素被先後驅動以被寫入資料、發光等。上述的實施例僅為易於了解本案之目的而提供,但本案的實施方式並不以此為限。關於本案提供之控制電路110、同時驅動單元120、掃描驅動單元130的具體運作將於後續的篇幅詳述之。 For example, in some embodiments, when the simultaneous driving unit 120 outputs the driving signal DS1 as the output signal OUT to the pixel array 200, each column of pixels in the pixel array 200 is driven to perform reset and reset simultaneously. / Or compensation, in other words, the simultaneous driving unit 120 outputs a pulse wave with the same waveform to each pixel in the pixel array 200 at a time, so that these pixels are simultaneously driven to perform operations; in addition, , The scan drive unit 130 outputs drive information When DS2 is used as the output signal OUT to the pixel array 200, each row of pixels in the pixel array 200 is sequentially driven to be written with data, emit light, etc. The above embodiments are provided only for the purpose of easy understanding of this case, but the implementation of this case is not limited to this. The specific operations of the control circuit 110, the simultaneous driving unit 120, and the scanning driving unit 130 provided in this case will be described in detail later.

請參照第2圖。第2圖為根據本案一實施例所繪示如第1圖中所示的同時驅動單元120的示意圖。如第2圖所示,同時驅動單元120包含反向器121、反或閘122、下拉控制電路123、拉升控制電路124、拉升電路125以及下拉電路126。反向器121的輸入端用以接收控制訊號CL1,反向器121的輸出端耦接反或閘122的第一輸入端,反或閘122的第二輸入端用以接收切換訊號SC,下拉控制電路123耦接於下拉電路126以及反或閘122的第二輸出端之間,拉升控制電路124耦皆於拉升電路125與反或閘122的輸出端之間。 Please refer to Figure 2. FIG. 2 is a schematic diagram of the simultaneous driving unit 120 shown in FIG. 1 according to an embodiment of the present application. As shown in FIG. 2, the simultaneous driving unit 120 includes an inverter 121, an inverter 122, a pull-down control circuit 123, a pull-up control circuit 124, a pull-up circuit 125 and a pull-down circuit 126. The input terminal of the inverter 121 is used to receive the control signal CL1, the output terminal of the inverter 121 is coupled to the first input terminal of the inverter 122, and the second input terminal of the inverter 122 is used to receive the switching signal SC. The control circuit 123 is coupled between the pull-down circuit 126 and the second output terminal of the NOR gate 122, and the pull-up control circuit 124 is coupled between the pull-up circuit 125 and the output terminal of the NOR gate 122.

請參照第3圖。第3圖為根據本案一實施例所繪示如第2圖中所示的同時驅動單元120的電路圖。如第3圖所示,反向器121包含電晶體T1、T2,反或閘122包含電晶體T3、T4、T5、T6,下拉控制電路123包含電晶體T7,拉升控制電路124包含電晶體T8,拉升電路125包含電晶體T9,下拉電路126包含電晶體T10,其中電晶體T1、T3、T4、T7、T9為P型電晶體,電晶體T2、T5、T6、T8、T10為N型電晶體。需注意的是,上述反向器121、反或閘122、下拉控制電路123以及拉升控制電路124的實施方式為易於了解本案而作舉例之用,其他電路配置亦在本案的實施範圍內,例如,電晶體 T1、T3、T4、T7、T9可以N型電晶體實施,相應地電晶體T2、T5、T6、T8、T10為P型電晶體,而應用於該些電晶體之控制訊號將相應調整。 Please refer to Figure 3. FIG. 3 is a circuit diagram of the simultaneous driving unit 120 shown in FIG. 2 according to an embodiment of the present application. As shown in Figure 3, inverter 121 includes transistors T1 and T2, inverter 122 includes transistors T3, T4, T5, and T6, pull-down control circuit 123 includes transistor T7, and pull-up control circuit 124 includes transistors T8, the pull-up circuit 125 includes a transistor T9, and the pull-down circuit 126 includes a transistor T10, wherein the transistors T1, T3, T4, T7, and T9 are P-type transistors, and the transistors T2, T5, T6, T8, T10 are N Type transistor. It should be noted that the implementations of the inverter 121, the inverter 122, the pull-down control circuit 123, and the pull-up control circuit 124 are used as examples for easy understanding of this case, and other circuit configurations are also within the scope of implementation of this case. For example, transistor T1, T3, T4, T7, and T9 can be implemented with N-type transistors. Accordingly, the transistors T2, T5, T6, T8, and T10 are P-type transistors, and the control signals applied to these transistors will be adjusted accordingly.

具體來說,在一些實施例中,如第3圖所示,電晶體T1的第一端與電晶體T2的第一端耦接,電晶體T1的第二端與電晶體T2的第二端耦接並用以作為反向器121的輸入端,電晶體T1的第三端耦接供應電壓端VGH,電晶體T2的第三端耦接供應電壓端VGL,其中供應電壓端VGH的位準高於供應電壓端VGL的位準。. Specifically, in some embodiments, as shown in Figure 3, the first end of the transistor T1 is coupled to the first end of the transistor T2, and the second end of the transistor T1 is coupled to the second end of the transistor T2. The third terminal of the transistor T1 is coupled to the supply voltage terminal VGH, the third terminal of the transistor T2 is coupled to the supply voltage terminal VGL, and the level of the supply voltage terminal VGH is high The level of the supply voltage terminal VGL. .

接續上述實施例,反或閘122中的電晶體T3的第一端與電晶體T4的第一端耦接,電晶體T4的第二端與電晶體T5的第一端、電晶體T6的第一端耦接並作為反或閘122的輸出端(節點N),電晶體T3的第二端與電晶體T5的第二端耦接並作為反或閘122的第一輸入端(節點Q),電晶體T4的第三端與電晶體T6的第二端耦接用以作為反或閘122的第二輸入端,電晶體T3的第三端耦接供應電壓端VGH,電晶體T5的第三端以及電晶體T6的第三端耦接供應電壓端VGL。 Continuing the above embodiment, the first end of the transistor T3 in the inverter 122 is coupled to the first end of the transistor T4, and the second end of the transistor T4 is connected to the first end of the transistor T5 and the second end of the transistor T6. One end is coupled and used as the output terminal of the NOR gate 122 (node N), and the second end of the transistor T3 is coupled to the second end of the transistor T5 and used as the first input terminal (node Q) of the NAND 122 , The third terminal of the transistor T4 and the second terminal of the transistor T6 are coupled to serve as the second input terminal of the inverter 122, the third terminal of the transistor T3 is coupled to the supply voltage terminal VGH, and the second terminal of the transistor T5 The three terminals and the third terminal of the transistor T6 are coupled to the supply voltage terminal VGL.

此外,下拉控制電路123中的電晶體T7的第一端與電晶體T4的第二端、電晶體T6的第二端耦接,電晶體T7的第一端用以耦接切換訊號SC,電晶體T7的第二端耦接供應電壓端VGH。拉升控制電路124中的電晶體T8的一第一端耦接電晶體T7的第三端於節點K。電晶體T8用以接收控制訊號CL1,電晶體T8的第三端與電晶體T4的第二端、電晶體T5的第一端以及電晶體T6的第一端耦接。 In addition, the first end of the transistor T7 in the pull-down control circuit 123 is coupled to the second end of the transistor T4 and the second end of the transistor T6. The first end of the transistor T7 is used to couple the switching signal SC. The second terminal of the crystal T7 is coupled to the supply voltage terminal VGH. A first end of the transistor T8 in the pull-up control circuit 124 is coupled to the third end of the transistor T7 at the node K. The transistor T8 is used to receive the control signal CL1, and the third end of the transistor T8 is coupled to the second end of the transistor T4, the first end of the transistor T5, and the first end of the transistor T6.

接續上述實施例,拉升電路125中的電晶體T9的第一端耦接供應電壓端VGH,電晶體T9的第二端與電晶體T7的第三端、電晶體T8的第一端耦接。下拉電路126中的電晶體T10的第一端耦接電晶體T9的第三端在同時驅動單元120的輸出端,電晶體T10的第二端與供應電壓端VGL耦接,電晶體T10的第三端與電晶體T8的第三端耦接。 Following the above embodiment, the first terminal of the transistor T9 in the pull-up circuit 125 is coupled to the supply voltage terminal VGH, and the second terminal of the transistor T9 is coupled to the third terminal of the transistor T7 and the first terminal of the transistor T8 . The first terminal of the transistor T10 in the pull-down circuit 126 is coupled to the third terminal of the transistor T9 and the output terminal of the simultaneous driving unit 120, the second terminal of the transistor T10 is coupled to the supply voltage terminal VGL, and the second terminal of the transistor T10 The three terminals are coupled to the third terminal of the transistor T8.

請參照第4圖。第4圖為根據本案一實施例所繪示的多種控制信號以及各節點位準的波形示意圖。在一些實施例中,如第4圖中所示的控制信號可被實施在如第1圖中所示的驅動電路100中,並且驅動電路100中的同時驅動單元120響應於如第4圖中所示各種訊號而運作的方式將如在第5A圖至第5D圖中的實施例所示。 Please refer to Figure 4. FIG. 4 is a schematic diagram of various control signals and waveforms of each node level according to an embodiment of the present case. In some embodiments, the control signal shown in FIG. 4 may be implemented in the driving circuit 100 shown in FIG. 1, and the simultaneous driving unit 120 in the driving circuit 100 responds to The operation of the various signals shown will be as shown in the embodiments in FIGS. 5A to 5D.

如第4圖所示,在時間間隔T1中,控制訊號CL1具有高位準且控制訊號CL2具有低位準,驅動電路100操作於同時模式(simultaneous mode)以輸出驅動訊號DS1作為輸出訊號OUT至畫素陣列200,而在時間間隔T2中,控制訊號CL1具有一低位準且控制訊號CL2具有高位準,驅動電路100操作於漸進模式(progressive mode)以輸出驅動訊號DS2作為輸出訊號OUT至畫素陣列200,換句話說,可透過調整控制訊號CL1及CL2分別具有高低位準的時間改變操作畫素陣列200於各模式的時間,意即改變畫素陣列200的同時驅動時間以及漸進驅動時間。需特別注意的是,輸出訊號OUT可包含對應畫素陣列200中n列畫素的輸出訊號OUT[0]~OUT[n],但為簡潔之故,在第4圖中僅繪示畫素陣列200中之 一列畫素所接收的輸出訊號OUT。 As shown in Figure 4, in the time interval T1, the control signal CL1 has a high level and the control signal CL2 has a low level, and the driving circuit 100 operates in a simultaneous mode to output the driving signal DS1 as the output signal OUT to the pixel The array 200, and in the time interval T2, the control signal CL1 has a low level and the control signal CL2 has a high level, and the driving circuit 100 operates in a progressive mode to output the driving signal DS2 as the output signal OUT to the pixel array 200 In other words, the time of operating the pixel array 200 in each mode can be changed by adjusting the time when the control signals CL1 and CL2 have high and low levels respectively, which means that the simultaneous driving time and the progressive driving time of the pixel array 200 can be changed. It is important to note that the output signal OUT can include output signals OUT[0]~OUT[n] corresponding to the n columns of pixels in the pixel array 200, but for the sake of brevity, only the pixels are shown in Figure 4. Of 200 in array The output signal OUT received by a column of pixels.

請參照第5A圖至第5D圖。第5A圖至第5D圖為根據本案一實施例所繪示如第3圖中所示之同時驅動單元120於運作時的等效電路操作示意圖。為便於理解,在第5A圖至第5D圖中與第3圖中相同的元件將用相同的參考符號標記。除非有需要說明與第5A圖至第5D圖中所示之元件的協作關係,否則為了簡潔起見,在此省略在上面的段落中已經詳細討論之類似元件的具體操作。 Please refer to Figure 5A to Figure 5D. FIGS. 5A to 5D are schematic diagrams of equivalent circuit operation of the simultaneous driving unit 120 shown in FIG. 3 in operation according to an embodiment of the present invention. For ease of understanding, the same elements in FIGS. 5A to 5D as in FIG. 3 will be marked with the same reference signs. Unless it is necessary to explain the cooperative relationship with the elements shown in FIGS. 5A to 5D, for the sake of brevity, specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted here.

請一併參照第4圖以及第5A圖。具體來說,在時間間隔T1中的子間隔T11中,控制訊號CL1具有高位準,相應地,電晶體T1關斷、電晶體T2導通,而節點Q位準為低電位(與具低電位的供應電壓端VGL導通),換句話說,具高位準的控制訊號CL1經過反向器121後被輸出為具低電位的訊號。接著,響應於節點Q的低電位,電晶體T3導通、電晶體T5關斷,以及響應於具高電位的切換訊號SC,電晶體T4關斷、電晶體T6導通,相應地節點N具低電位(與具低電位的供應電壓端VGL導通),換句話說,反或閘122的第一輸入端(節點Q)接收低電位,其第二輸入端(切換訊號SC)接收高電位,則其輸出端(節點N)輸出低電位。電晶體T7相應高電位的切換訊號SC關斷,電晶體T8相應高電位的控制訊號CL1導通,使得節點K具低電位,電晶體T9相應地導通、電晶體T10關斷,此時同時驅動單元120的輸出端自供應電壓端VGH輸出去高電位的驅動訊號DS1作輸出訊號OUT。 Please refer to Figure 4 and Figure 5A together. Specifically, in the sub-interval T11 in the time interval T1, the control signal CL1 has a high level. Accordingly, the transistor T1 is turned off, the transistor T2 is turned on, and the node Q level is at a low potential (compared with a low potential The supply voltage terminal VGL is turned on), in other words, the control signal CL1 with a high level is outputted as a signal with a low level after passing through the inverter 121. Then, in response to the low potential of the node Q, the transistor T3 is turned on and the transistor T5 is turned off, and in response to the switching signal SC with a high potential, the transistor T4 is turned off and the transistor T6 is turned on, and accordingly the node N has a low potential (Connected to the supply voltage terminal VGL with a low potential). In other words, the first input terminal (node Q) of the NOR gate 122 receives a low potential, and its second input terminal (the switching signal SC) receives a high potential. The output terminal (node N) outputs a low potential. The switching signal SC corresponding to the high potential of the transistor T7 is turned off, and the control signal CL1 of the corresponding high potential of the transistor T8 is turned on, so that the node K has a low potential, the transistor T9 is turned on and the transistor T10 is turned off, and the unit is driven at the same time The output terminal of 120 outputs a high-level driving signal DS1 from the supply voltage terminal VGH as the output signal OUT.

接續上述實施例,請一併參照第4圖以及第5B 圖。在時間間隔T1中的子間隔T12中,控制訊號CL1具有高位準,電晶體T1關斷、電晶體T2導通,而節點Q位準為低電位,換句話說,反向器121仍輸出低電位訊號。接著,響應於節點Q的低電位,電晶體T3導通、電晶體T5關斷,以及響應於切換至低電位的切換訊號SC,電晶體T4導通、電晶體T6關斷,相應地節點N具高電位(與具高電位的供應電壓端VGH導通),換句話說,反或閘122的第一輸入端(節點Q)接收低電位,其第二輸入端(切換訊號SC)接收低電位,則其輸出端(節點N)輸出高電位。電晶體T7相應低電位的切換訊號SC導通,使得節點K具高電位,電晶體T8相應高電位的控制訊號CL1以及節點K的高電位關斷,電晶體T9相應地關斷、電晶體T10導通,此時同時驅動單元120的輸出端自供應電壓端VGL輸出去低電位的驅動訊號DS1作輸出訊號OUT。 Continuing the above embodiment, please refer to Fig. 4 and Fig. 5B together Figure. In the sub-interval T12 in the time interval T1, the control signal CL1 has a high level, the transistor T1 is turned off, the transistor T2 is turned on, and the node Q is at a low level. In other words, the inverter 121 still outputs a low level Signal. Then, in response to the low potential of the node Q, the transistor T3 turns on and the transistor T5 turns off, and in response to the switching signal SC that switches to the low potential, the transistor T4 turns on and the transistor T6 turns off. Accordingly, the node N has a high Potential (connected to the supply voltage terminal VGH with a high potential). In other words, the first input terminal (node Q) of the NOR gate 122 receives a low potential, and the second input terminal (switching signal SC) receives a low potential, then The output terminal (node N) outputs a high potential. The switching signal SC corresponding to the low potential of the transistor T7 is turned on, so that the node K has a high potential, the control signal CL1 of the corresponding high potential of the transistor T8 and the high potential of the node K are turned off, the transistor T9 is turned off accordingly, and the transistor T10 is turned on. At this time, at the same time, the output terminal of the driving unit 120 outputs the low-level driving signal DS1 from the supply voltage terminal VGL as the output signal OUT.

接著,請一併參照第4圖以及第5C圖。在時間間隔T1中的子間隔T13中,控制訊號CL1具有高位準,電晶體T1關斷、電晶體T2導通,節點Q位準為低電位,反向器121輸出具低電位的訊號。接著,響應於節點Q的低電位,電晶體T3導通、電晶體T5關斷,以及響應於具高電位的切換訊號SC,電晶體T4關斷、電晶體T6導通,相應地節點N具低電位,換句話說,反或閘122的輸出端(節點N)輸出低電位。電晶體T7相應高電位的切換訊號SC關斷,電晶體T8相應高電位的控制訊號CL1導通,節點K具低電位,電晶體T9相應地導通、電晶體T10關斷,此時同時驅動單元120的輸出端自供應電壓端VGH輸出去高電位的驅動訊號DS1作輸出訊號OUT。 Next, please refer to Figure 4 and Figure 5C together. In the sub-interval T13 in the time interval T1, the control signal CL1 has a high level, the transistor T1 is turned off, the transistor T2 is turned on, the node Q is at a low potential, and the inverter 121 outputs a signal with a low potential. Then, in response to the low potential of the node Q, the transistor T3 is turned on and the transistor T5 is turned off, and in response to the switching signal SC with a high potential, the transistor T4 is turned off and the transistor T6 is turned on, and accordingly the node N has a low potential In other words, the output terminal (node N) of the inverter 122 outputs a low level. The switching signal SC corresponding to the high potential of the transistor T7 is turned off, the control signal CL1 corresponding to the high potential of the transistor T8 is turned on, the node K has a low potential, the transistor T9 is turned on accordingly, and the transistor T10 is turned off. At this time, the unit 120 is driven at the same time The output terminal of the voltage supply terminal VGH outputs a high-level driving signal DS1 as the output signal OUT.

如以上所述,驅動電路100工作於同時模式,在時間間隔T1中,同時驅動單元120響應高電位的控制訊號CL1輸出輸出訊號OUT,同時,控制電路110響應控制訊號CL1、CL2被關斷,使得畫素陣列200中的每一列接收自同時驅動單元120的輸出訊號OUT而同時作動。舉例而言,在一些實施例中,畫素陣列200中每一列畫素所包含的一電晶體響應輸出訊號OUT被導通或關斷以進行畫素電路Vth補償。本領域具通常知識者應理解畫素電路Vth補償之相關技術,在此不再贅述。 As described above, the driving circuit 100 works in the simultaneous mode. In the time interval T1, the driving unit 120 responds to the high-level control signal CL1 to output the output signal OUT, and at the same time, the control circuit 110 is turned off in response to the control signals CL1 and CL2. As a result, each column of the pixel array 200 receives the output signal OUT from the simultaneous driving unit 120 and operates at the same time. For example, in some embodiments, a transistor included in each column of the pixel array 200 is turned on or off in response to the output signal OUT to perform the pixel circuit Vth compensation. Those with ordinary knowledge in the art should understand the related technology of pixel circuit Vth compensation, which will not be repeated here.

需注意的是,如第4圖所示,在時間間隔T1中,也就是在同時模式中,自同時驅動單元120所輸出之驅動訊號DS1與切換訊號SC具有相同相位的位準,換句話說,可藉由改變切換訊號SC的工作週期而改變驅動訊號DS1的工作週期,進一步改變同時驅動時間。 It should be noted that, as shown in Figure 4, in the time interval T1, that is, in the simultaneous mode, the driving signal DS1 output from the simultaneous driving unit 120 and the switching signal SC have the same phase level, in other words By changing the duty cycle of the switching signal SC, the duty cycle of the driving signal DS1 can be changed to further change the simultaneous driving time.

接續上述實施例,請一併參照第4圖以及第5D圖。在時間間隔T2中,控制訊號CL1具有低位準,電晶體T1導通、電晶體T2關斷,而節點Q位準為高電位,換句話說,具低位準的控制訊號CL1經過反向器121後被輸出為具高電位的訊號。接著,響應於節點Q的高電位,電晶體T3關斷、電晶體T5導通,以及響應切換至低電位的切換訊號SC,電晶體T4導通、電晶體T6關斷,相應地節點N具低電位(與具低電位的供應電壓端VGL導通),換句話說,反或閘122的第一輸入端(節點Q)接收高電位,其第二輸入端(切換訊號SC)接收低電位,則其輸出端(節點N)輸出低電位。電晶體T7相應低電位的切換訊號SC導通,使得節點K具高電位,電晶體T8相應 低電位的控制訊號CL1關斷,電晶體T9相應地關斷、電晶體T10關斷,此時同時驅動單元120不輸出任何訊號。在一些實施例中,同時驅動單元120的輸出端為浮動狀態(floating)。但本案並不以此為限。 Continuing the above embodiment, please refer to Fig. 4 and Fig. 5D together. In the time interval T2, the control signal CL1 has a low level, the transistor T1 is turned on, the transistor T2 is turned off, and the node Q is at a high level. In other words, the control signal CL1 with a low level passes through the inverter 121 It is output as a signal with high potential. Then, in response to the high potential of the node Q, the transistor T3 is turned off, the transistor T5 is turned on, and in response to the switching signal SC that switches to the low potential, the transistor T4 is turned on and the transistor T6 is turned off, and accordingly the node N has a low potential (Connected to the supply voltage terminal VGL with a low potential). In other words, the first input terminal (node Q) of the NOR gate 122 receives a high potential, and its second input terminal (the switching signal SC) receives a low potential. The output terminal (node N) outputs a low potential. The switching signal SC corresponding to the low potential of the transistor T7 is turned on, so that the node K has a high potential, and the transistor T8 corresponds to The low-potential control signal CL1 is turned off, the transistor T9 is turned off accordingly, and the transistor T10 is turned off. At this time, the driving unit 120 does not output any signal. In some embodiments, the output terminal of the driving unit 120 is in a floating state. But this case is not limited to this.

請參照第6圖。第6圖為根據本案一實施例所繪示如第1圖中所示的掃描驅動單元130的示意圖。如第6圖所示,掃描驅動單元130包含電晶體T11、T12、T13、T14、T15、T16以及電容器C1、C2。電晶體T11與電晶體T12、T15、T16耦接,電晶體T12與電容器C1耦接,電晶體T14與電晶體T15、T16耦接,以及電晶體T13與電容器C1、C2耦接。掃描驅動單元130用以響應掃描訊號IN、脈衝訊號CK1、CK2操作以輸出驅動訊號DS2作輸出訊號OUT至畫素陣列200。需注意的是,如第6圖中所示的掃描驅動單元130僅為作事例用,任何用以在不同致能時段依序提供脈衝訊號以驅動多列畫素的電路,如任何GOA電路,均可用以實施本案,本領域具通常知識者應理解GOA作動原理,在此將不再贅述GOA電路的運作過程。 Please refer to Figure 6. FIG. 6 is a schematic diagram of the scan driving unit 130 shown in FIG. 1 according to an embodiment of the present application. As shown in FIG. 6, the scan driving unit 130 includes transistors T11, T12, T13, T14, T15, T16, and capacitors C1, C2. Transistor T11 is coupled to transistors T12, T15, T16, transistor T12 is coupled to capacitor C1, transistor T14 is coupled to transistors T15, T16, and transistor T13 is coupled to capacitors C1, C2. The scan driving unit 130 is used for responding to the operation of the scan signal IN and the pulse signals CK1 and CK2 to output the driving signal DS2 as the output signal OUT to the pixel array 200. It should be noted that the scan driving unit 130 shown in Figure 6 is only for example. Any circuit that sequentially provides pulse signals during different enabling periods to drive multiple columns of pixels, such as any GOA circuit, Both can be used to implement this case. Those with ordinary knowledge in the field should understand the principle of GOA operation. The operation process of the GOA circuit will not be repeated here.

請再參照第4圖。在時間間隔T2中,控制訊號CL1具低電位、控制訊號CL2具高電位,使得掃描驅動單元130被致能且控制電路110導通,使得掃描驅動單元130產生的驅動訊號DS2作為輸出訊號OUT。如第4圖所示,當掃描訊號IN為一脈衝訊號,經掃描驅動單元130內各元件的協同操作以輸出相應的脈衝訊號作為驅動訊號DS2,而控制電路110響應控制訊號CL1、CL2導通,接著控制電路110自掃描驅動單元130輸出輸出訊號OUT。 Please refer to Figure 4 again. In the time interval T2, the control signal CL1 has a low potential and the control signal CL2 has a high potential, so that the scan driving unit 130 is enabled and the control circuit 110 is turned on, so that the driving signal DS2 generated by the scan driving unit 130 is used as the output signal OUT. As shown in Figure 4, when the scan signal IN is a pulse signal, the corresponding pulse signal is output as the driving signal DS2 through the cooperative operation of the components in the scan driving unit 130, and the control circuit 110 is turned on in response to the control signals CL1 and CL2. Then the control circuit 110 outputs the output signal OUT from the scan driving unit 130.

請參照第7圖。第7圖為根據本案另一實施例所繪示的驅動電路100及畫素陣列200的方塊示意圖。如第7圖所示,驅動電路100包含多個掃描驅動單元1301~130n,控制電路110相應地包含多組耦接的開關111~112,畫素陣列2001~200n與控制電路110中的多組開關111~112耦接,以及至少一同時驅動單元120與掃描驅動單元1301~130n耦接。在一些實施例中,於同時模式時,同時驅動單元120同時驅動畫素陣列2001~200n。而在一些實施例中,驅動電路100包含的同時驅動單元110與掃描驅動的數量為1比N,N為等於或大於1的一正整數。 Please refer to Figure 7. FIG. 7 is a block diagram of the driving circuit 100 and the pixel array 200 according to another embodiment of the present invention. As shown in Figure 7, the driving circuit 100 includes a plurality of scan driving units 1301~130n, the control circuit 110 correspondingly includes a plurality of sets of coupled switches 111~112, a pixel array 2001~200n and a plurality of sets in the control circuit 110 The switches 111 to 112 are coupled, and at least one simultaneous driving unit 120 is coupled to the scan driving units 1301 to 130n. In some embodiments, in the simultaneous mode, the simultaneous driving unit 120 simultaneously drives the pixel arrays 2001 to 200n. In some embodiments, the number of simultaneous driving units 110 and scan driving included in the driving circuit 100 is 1 to N, and N is a positive integer equal to or greater than 1.

綜合以上所述,本案的驅動電路及其操作方法,透過精簡的控制電路選擇性導通而分別自同時驅動單元與漸進掃描驅動單元輸出訊號,並透過輸出訊號將畫素陣列分別驅動於同時驅動模式與漸進掃描驅動模式,如此,藉由在驅動電路中應用本案所提供的控制電路,將大幅減少驅動電路的體積。 In summary, the driving circuit and its operation method of the present case can output signals from the simultaneous driving unit and the progressive scanning driving unit through the selective conduction of the simplified control circuit, and drive the pixel array in the simultaneous driving mode through the output signals. Compared with the progressive scan driving mode, in this way, by applying the control circuit provided in this case in the driving circuit, the volume of the driving circuit will be greatly reduced.

另外,除非說明書中特別指明,否則任何單數格的用語都同時包含複數格的涵義。 In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case.

以上僅為本揭示文件的較佳實施例,凡依本揭示文件請求項所做的均等變化與修飾,皆應屬本揭示文件的涵蓋範圍。 The above are only the preferred embodiments of the present disclosure, and all equal changes and modifications made in accordance with the requirements of the present disclosure should fall within the scope of the disclosure.

100‧‧‧驅動電路100‧‧‧Drive circuit

110‧‧‧控制電路110‧‧‧Control circuit

120‧‧‧同時驅動單元120‧‧‧Simultaneous drive unit

130‧‧‧掃描驅動單元130‧‧‧Scan Drive Unit

111、112‧‧‧開關111、112‧‧‧Switch

200‧‧‧畫素陣列200‧‧‧Pixel array

CL1、CL2‧‧‧控制訊號CL1, CL2‧‧‧Control signal

SC‧‧‧切換訊號SC‧‧‧Switch signal

CK‧‧‧時脈訊號CK‧‧‧clock signal

OUT‧‧‧輸出端OUT‧‧‧Output terminal

Claims (12)

  1. 一種驅動電路,包含: A drive circuit, including:
    至少一第一驅動單元,用以響應於一第一控制訊號和一切換訊號被致能並產生一第一驅動訊號; At least one first driving unit for being enabled in response to a first control signal and a switching signal and generating a first driving signal;
    至少一第二驅動單元,用以響應於一第二控制訊號被致能並產生一第二驅動訊號;以及At least one second driving unit for being enabled in response to a second control signal and generating a second driving signal; and
    一控制電路,該控制電路耦接於該至少一第一驅動單元以及該至少一第二驅動單元之間,並且該控制電路用以根據該第一控制訊號和該第二控制訊號選擇自該至少一第一驅動單元輸出該第一驅動訊號或自該至少一第二驅動單元輸出該第二驅動訊號作為一輸出訊號至一至少一畫素陣列; A control circuit, the control circuit is coupled between the at least one first driving unit and the at least one second driving unit, and the control circuit is used to select from the at least one according to the first control signal and the second control signal A first drive unit outputs the first drive signal or outputs the second drive signal from the at least one second drive unit as an output signal to at least one pixel array;
    其中該至少一畫素陣列中的每一列畫素同時響應於該第一驅動訊號被驅動,或該至少一畫素陣列中的每一列畫素根據該第二驅動訊號被先後驅動。 Wherein, each column of pixels in the at least one pixel array is simultaneously driven in response to the first driving signal, or each column of pixels in the at least one pixel array is sequentially driven according to the second driving signal.
  2. 如請求項1所述的驅動電路,其中該控制電路包含: The driving circuit according to claim 1, wherein the control circuit includes:
    一第一開關,該第一開關的一第一端與該至少一第一驅動單元耦接,該第一開關的一第二端與該至少一第二驅動單元耦接,該第一開關的一控制端用以接收該第一控制訊號;以及 A first switch, a first end of the first switch is coupled to the at least one first driving unit, a second end of the first switch is coupled to the at least one second driving unit, and the A control terminal for receiving the first control signal; and
    一第二開關,該第二開關的一第一端與一第二端分別與該第一開關的該第一端以及該第二端耦接,該第二開關的一控制端用以接收該第二控制訊號。 A second switch, a first terminal and a second terminal of the second switch are respectively coupled to the first terminal and the second terminal of the first switch, and a control terminal of the second switch is used for receiving the The second control signal.
  3. 如請求項1所述的驅動電路,其中該至少一第一驅動單元包含: The driving circuit according to claim 1, wherein the at least one first driving unit includes:
    一反或閘,該反或閘的一第一輸入端用以接收該切換訊號; A reverse OR gate, a first input terminal of the reverse OR gate is used to receive the switching signal;
    一反向器,該反向器的一輸入端用以接收該第一控制訊號,該反向器的一輸出端耦接於該反或閘的一第二輸入端; An inverter, an input terminal of the inverter for receiving the first control signal, and an output terminal of the inverter coupled to a second input terminal of the inverter;
    一下拉電路; A pull-down circuit;
    一下拉控制電路,該下拉控制電路耦接於該下拉電路以及該反或閘的該第一輸入端之間; A pull-down control circuit, which is coupled between the pull-down circuit and the first input terminal of the inverter;
    一拉升電路;以及A pull-up circuit; and
    一拉升控制電路,該拉升控制電路耦接於該拉升電路與該反或閘的一輸出端之間。 A pull-up control circuit, the pull-up control circuit is coupled between the pull-up circuit and an output terminal of the inverter.
  4. 如請求項3所述的驅動電路,其中The driving circuit according to claim 3, wherein
    該反向器包含一第一電晶體和一第二電晶體,其中該第一電晶體的一第一端與該第二電晶體的一第一端耦接,該第一電晶體的一第二端與該第二電晶體的一第二端用以作為該反向器的該輸入端; The inverter includes a first transistor and a second transistor, wherein a first end of the first transistor is coupled to a first end of the second transistor, and a first end of the first transistor is Two ends and a second end of the second transistor are used as the input end of the inverter;
    該反或閘包含一第三電晶體、一第四電晶體、一第五電晶體和一第六電晶體,其中該第三電晶體的一第一端與該第四電晶體的一第一端耦接,該第四電晶體的一第二端與該第五電晶體的一第一端、該第六電晶體的一第一端耦接並作為該反或閘的該輸出端,該第三電晶體的一第二端與該第五電 晶體的一第二端耦接並用以作為該反或閘的該第二輸入端,該第四電晶體的一第三端與該第六電晶體的一第二端用以作為該反或閘的該第一輸入端; The reverse OR gate includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein a first end of the third transistor and a first end of the fourth transistor Terminal is coupled, a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor, and a first terminal of the sixth transistor is coupled to serve as the output terminal of the inverter, the A second end of the third transistor and the fifth transistor A second end of the crystal is coupled and used as the second input end of the NOR gate, a third end of the fourth transistor and a second end of the sixth transistor are used as the NOR gate The first input terminal;
    該下拉控制電路包含一第七電晶體,其中該第七電晶體的一第一端與該第四電晶體的該第二端以及該第六電晶體的該第二端耦接,該第七電晶體的該第一端用以接收該切換訊號; The pull-down control circuit includes a seventh transistor, wherein a first end of the seventh transistor is coupled to the second end of the fourth transistor and the second end of the sixth transistor, and the seventh transistor The first end of the transistor is used for receiving the switching signal;
    該拉升控制電路包含一第八電晶體,其中該第八電晶體的一第一端與該第七電晶體的一第二端耦接,該第八電晶體的一第二端用以接收該第一控制訊號,該第八電晶體的一第三端與該第六電晶體的該第一端耦接; The pull control circuit includes an eighth transistor, wherein a first end of the eighth transistor is coupled to a second end of the seventh transistor, and a second end of the eighth transistor is used for receiving For the first control signal, a third end of the eighth transistor is coupled to the first end of the sixth transistor;
    該拉升電路包含一第九電晶體,其中該第九電晶體的一第一端與該第七電晶體的該第二端、該第八電晶體的該第一端耦接;以及The pull-up circuit includes a ninth transistor, wherein a first end of the ninth transistor is coupled to the second end of the seventh transistor and the first end of the eighth transistor; and
    該下拉電路包含一第十電晶體,其中該第十電晶體的一第一端與該第九電晶體的一第二端耦接在該第一驅動單元的一輸出端。 The pull-down circuit includes a tenth transistor, wherein a first terminal of the tenth transistor and a second terminal of the ninth transistor are coupled to an output terminal of the first driving unit.
  5. 如請求項1所述的驅動電路,其中該至少一第一驅動單元包含: The driving circuit according to claim 1, wherein the at least one first driving unit includes:
    一第一電晶體與一第二電晶體,該第一電晶體的一第一端與該第二電晶體的一第一端耦接,該第一電晶體的一第二端耦接一第一供應電壓端,該第二電晶體的一第二端耦接一第二供應電壓端,該第一電晶體的一第三端與該第二電晶體 的一第三端耦接於用以接收該第一控制訊號的一輸入端; A first transistor and a second transistor, a first end of the first transistor is coupled to a first end of the second transistor, and a second end of the first transistor is coupled to a first end A supply voltage terminal, a second terminal of the second transistor is coupled to a second supply voltage terminal, a third terminal of the first transistor and the second transistor A third terminal of is coupled to an input terminal for receiving the first control signal;
    一第三電晶體、一第四電晶體、一第五電晶體與一第六電晶體,該第三電晶體的一第一端與該第四電晶體的一第一端耦接,該第三電晶體的一第二端耦接該第一供應電壓端,該第四電晶體的一第二端與該第五電晶體的一第一端、該第六電晶體的一第一端耦接,該第五電晶體的一第二端、該第六電晶體的一第二端與該第二供應電壓端耦接,該第五電晶體的一第三端與該第三電晶體的一第三端耦接,該第四電晶體的一第三端與該第六電晶體的一第三端耦接以接收該切換訊號; A third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, a first end of the third transistor is coupled to a first end of the fourth transistor, the first A second terminal of the three transistors is coupled to the first supply voltage terminal, and a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor and a first terminal of the sixth transistor. Connected, a second terminal of the fifth transistor, a second terminal of the sixth transistor are coupled to the second supply voltage terminal, and a third terminal of the fifth transistor is coupled to the second terminal of the third transistor. A third end is coupled, and a third end of the fourth transistor is coupled to a third end of the sixth transistor to receive the switching signal;
    一第七電晶體,該第七電晶體的一第一端耦接該第一供應電壓端,該第七電晶體的一第二端用以接收該切換訊號; A seventh transistor, a first terminal of the seventh transistor is coupled to the first supply voltage terminal, and a second terminal of the seventh transistor is used for receiving the switching signal;
    一第八電晶體,該第八電晶體的一第一端耦接該第七電晶體的一第三端,該第八電晶體的一第二端與該第六電晶體的該第一端耦接,該第八電晶體的一第三端用以接收該第一控制訊號; An eighth transistor, a first end of the eighth transistor is coupled to a third end of the seventh transistor, a second end of the eighth transistor and the first end of the sixth transistor Coupled, a third end of the eighth transistor is used to receive the first control signal;
    一第九電晶體,該第九電晶體的一第一端與該第一供應電壓端耦接,該第九電晶體的一第二端與該第七電晶體的該第三端、該第八電晶體的該第一端耦接;以及 A ninth transistor, a first end of the ninth transistor is coupled to the first supply voltage end, a second end of the ninth transistor is connected to the third end of the seventh transistor, the The first end of the eight transistor is coupled; and
    一第十電晶體,該第十電晶體的一第一端與該第九電晶體的一第三端耦接,該第十電晶體的一第二端與該第二供應電壓端耦接,該第十電晶體的一第三端與該第八電晶體的該第二端耦接。 A tenth transistor, a first terminal of the tenth transistor is coupled to a third terminal of the ninth transistor, and a second terminal of the tenth transistor is coupled to the second supply voltage terminal, A third end of the tenth transistor is coupled to the second end of the eighth transistor.
  6. 如請求項1所述的驅動電路,其中The driving circuit according to claim 1, wherein
    當該第一控制訊號具有一高位準且該第二控制訊號具有一低位準時,該控制電路用以自該至少一第一驅動單元輸出該第一驅動訊號; When the first control signal has a high level and the second control signal has a low level, the control circuit is used for outputting the first driving signal from the at least one first driving unit;
    其中該第一驅動訊號響應於該切換訊號具有一高位準或一低位準。 The first driving signal has a high level or a low level in response to the switching signal.
  7. 如請求項1所述的驅動電路,其中The driving circuit according to claim 1, wherein
    當該第一控制訊號具有一低位準且該第二控制訊號具有一高位準時,該控制電路用以自該至少一第二驅動單元輸出該第二驅動訊號。 When the first control signal has a low level and the second control signal has a high level, the control circuit is used to output the second driving signal from the at least one second driving unit.
  8. 如請求項1所述的驅動電路,其中The driving circuit according to claim 1, wherein
    該至少一第一驅動單元與該至少一第二驅動單元的數量為1比N,N為等於或大於1的一正整數。 The number of the at least one first driving unit and the at least one second driving unit is 1 to N, and N is a positive integer equal to or greater than 1.
  9. 一種驅動電路操作方法,包含: A driving circuit operation method, including:
    藉由響應一第一控制訊號和一第二控制訊號關斷一控制電路,根據自一第一驅動單元輸出的一第一驅動訊號同時驅動一畫素陣列中的每一列畫素;以及By turning off a control circuit in response to a first control signal and a second control signal, simultaneously driving each row of pixels in a pixel array according to a first driving signal output from a first driving unit; and
    藉由導通該控制電路,根據自一第二驅動單元輸出的一第二驅動訊號漸進地驅動該畫素陣列中的每一列畫素。 By turning on the control circuit, each row of pixels in the pixel array is gradually driven according to a second driving signal output from a second driving unit.
  10. 如請求項9所述的驅動電路操作方法,更包含: The driving circuit operation method as described in claim 9, including Include:
    透過該第一驅動單元響應於該第一控制訊號以及一切換訊號產生該第一驅動訊號; Generating the first driving signal in response to the first control signal and a switching signal through the first driving unit;
    其中該第一驅動訊號與該切換訊號具有相同的位準。 The first driving signal and the switching signal have the same level.
  11. 如請求項9所述的驅動電路操作方法,更包含: The operating method of the driving circuit as described in claim 9 further includes:
    當該第一控制訊號具有一低位準且該第二控制訊號具有一高位準時,自該第二驅動單元輸出該第二驅動訊號至該畫素陣列。 When the first control signal has a low level and the second control signal has a high level, the second driving signal is output from the second driving unit to the pixel array.
  12. 如請求項9所述的驅動電路操作方法,更包含: The operating method of the driving circuit as described in claim 9 further includes:
    調整該第一控制訊號與該第二控制訊號以改變該畫素陣列的一同時驅動時間以及一漸進驅動時間。 The first control signal and the second control signal are adjusted to change a simultaneous driving time and a progressive driving time of the pixel array.
TW108140503A 2019-11-07 Driving circuit and the operation method thereof TWI713008B (en)

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TWI552129B (en) 2014-11-26 2016-10-01 群創光電股份有限公司 Scan driver and display using the same
TW201724064A (en) 2015-12-16 2017-07-01 奕力科技股份有限公司 Panel drive circuit comprising a plurality of gate driving units
CN107767827A (en) 2017-09-07 2018-03-06 昆山龙腾光电有限公司 Compensation circuit and display device
CN106652958B (en) 2017-01-16 2019-06-04 昆山龙腾光电有限公司 Gate driving circuit and control method
TWI673704B (en) 2018-06-14 2019-10-01 友達光電股份有限公司 Gate driving apparatus

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI552129B (en) 2014-11-26 2016-10-01 群創光電股份有限公司 Scan driver and display using the same
TW201724064A (en) 2015-12-16 2017-07-01 奕力科技股份有限公司 Panel drive circuit comprising a plurality of gate driving units
CN106652958B (en) 2017-01-16 2019-06-04 昆山龙腾光电有限公司 Gate driving circuit and control method
CN107767827A (en) 2017-09-07 2018-03-06 昆山龙腾光电有限公司 Compensation circuit and display device
TWI673704B (en) 2018-06-14 2019-10-01 友達光電股份有限公司 Gate driving apparatus

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