CN111402777B - Drive circuit and operation method thereof - Google Patents

Abstract

The application relates to a driving circuit and an operation method thereof. The first driving unit is enabled in response to the first control signal and the switching signal and generates a first driving signal. The second driving unit is enabled in response to the second control signal and generates a second driving signal. The control circuit is coupled between the first driving unit and the second driving unit, and selects to output the first driving signal from the first driving unit or output the second driving signal from the second driving unit to the pixel array according to the first control signal and the second control signal. A plurality of columns of pixels in the pixel array are driven simultaneously in response to the first drive signal and sequentially according to the second drive signal.

Description

Drive circuit and operation method thereof

Technical Field

The present disclosure relates to a driving circuit for a pixel circuit, and more particularly, to a driving circuit including a progressive driving circuit and a simultaneous driving circuit.

Background

Progressive scanning mode (progressive scanning mode) and simultaneous mode (simultaneous mode) driving circuits are widely used in circuits for driving pixel arrays, so that the pixel arrays emit light in response to progressive driving signals and simultaneous driving signals, respectively. However, in some known technologies, the size of the short-circuit control circuit (short bar control circuit) for switching the pixel array to receive the above two signals is too large, and the complicated circuit also causes the output signal of the short-circuit control circuit to have too long response time. In other techniques, a voltage different from the supply voltage of the driving circuit is required to control the short-circuit control circuit.

Disclosure of Invention

The present disclosure provides a driving circuit, which includes at least one first driving unit, at least one second driving unit, and a control circuit. The at least one first driving unit is used for responding to the first control signal and the switching signal to be enabled and generating a first driving signal. The at least one second driving unit is used for responding to the second control signal and being enabled and generating a second driving signal. The control circuit is coupled between the at least one first driving unit and the at least one second driving unit, and the control circuit is used for selecting to output the first driving signal from the at least one first driving unit or output the second driving signal from the at least one second driving unit as an output signal to the at least one pixel array according to the first control signal and the second control signal. Each row of pixels in the at least one pixel array is driven in response to the first driving signal at the same time, or each row of pixels in the at least one pixel array is driven sequentially according to the second driving signal.

The present disclosure provides a method for operating a driving circuit, the method comprising: simultaneously driving each row of pixels in the pixel array according to a first driving signal output from the first driving unit by turning off the control circuit in response to the first control signal and the second control signal; and progressively driving each row of pixels in the pixel array according to a second driving signal output from the second driving unit by the conducting control circuit.

The driving circuit and the operation method thereof can output signals from the simultaneous driving unit and the progressive scanning driving unit respectively through the selective conduction of the simplified control circuit, and drive the pixel array in the simultaneous driving mode and the progressive scanning driving mode respectively through the output signals.

Drawings

In order to make the aforementioned and other objects, features, advantages and embodiments of the present disclosure more comprehensible, the following description is provided:

fig. 1 is a block diagram illustrating a driving circuit and a pixel array according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of the simultaneous driving unit shown in FIG. 1 according to an embodiment of the present application;

FIG. 3 is a circuit diagram of the simultaneous driving unit shown in FIG. 2 according to an embodiment of the present application;

FIG. 4 is a waveform diagram illustrating various control signals and node levels according to an embodiment of the present application;

FIGS. 5A-5D are schematic diagrams illustrating the equivalent circuit operation of the simultaneous driving unit shown in FIG. 3 according to an embodiment of the present application;

FIG. 6 is a schematic diagram of the scan driving unit shown in FIG. 1 according to an embodiment of the present application; and

fig. 7 is a block diagram illustrating a driving circuit and a pixel array according to another embodiment of the present application.

[ notation ] to show

100: driving circuit

110: control circuit

120: simultaneous drive unit

130. 1301-130 n: scanning driving unit

111. 112, 112: switch with a switch body

200. 2001-200 n: pixel array

CL1, CL 2: control signal

SC: switching signal

CK: clock signal

OUT, OUT [0] to OUT [ n ]: output signal

IN: scanning signal

DS1, DS 2: drive signal

121: inverter with a capacitor having a capacitor element

122: NOR gate

123: pull-down control circuit

124: pulling-up control circuit

125: pulling-up circuit

126: pull-down circuit

T1, T2, T3, T4, T5, T6, T7, T8, T9, T10: transistor with a high breakdown voltage

Q, N, K: node point

VGH, VGL: supply voltage terminal

Time interval: t1, T2

Sub-interval: t11, T12, T13

Detailed Description

Embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct or indirect physical or electrical contact with each other, and may also refer to two or more elements operating or acting together.

As used herein, the term "circuit" refers broadly to an article connected by one or more transistors and/or one or more active and passive components in a manner to process a signal.

Certain terms are used throughout the description and following claims to refer to particular components. However, it will be understood by those skilled in the art that the same elements may be referred to by different names. The specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to.

Please refer to fig. 1. Fig. 1 is a block diagram illustrating a driving circuit 100 and a pixel array 200 according to an embodiment of the present disclosure. As shown in fig. 1, the driving circuit 100 and the pixel array 200 are coupled to an output terminal of the driving circuit 100. The driving circuit 100 includes a control circuit 110, a simultaneous driving unit 120, and a scan driving unit 130. In connection, the control circuit 110 is coupled between the output terminal of the driving circuit 100 and the scan driving unit 130, and the driving unit 120 is coupled to the output terminal of the driving circuit 100.

As shown in FIG. 1, the control circuit 110 includes switches 111-112. In some embodiments, the switch 111 may be implemented by any suitable type of P-type Transistor, such as a P-type Thin Film Transistor (TFT) or a P-type metal oxide semiconductor (pmos) Transistor, and the switch 112 may be implemented by any suitable type of N-type Transistor. In the embodiment shown in fig. 1, the first terminal of the switch 111 is coupled to the scan driving unit 130, the second terminal of the switch 111 is coupled to the simultaneous driving unit 120, and the control terminal of the switch 111 is configured to receive the control signal CL1, and the first terminal and the second terminal of the switch 112 are coupled to the first terminal and the second terminal of the switch 111, and the control terminal of the switch 112 is configured to receive the control signal CL 2. The above description of the components of the control circuit 110 is provided as an example for understanding the embodiments of the present application, and is not intended to limit the present application. Other embodiments of the present application are also within the scope of the present application.

In some embodiments, the scan driving unit 130 is implemented by Gate driver on array (GOA), and the scan driving unit 130 is configured to drive a row of pixels in the pixel array 200 by the output driving signal, specifically, the output driving signal turns on a row of transistors of the row of pixels, so that data signals for controlling brightness, gray scale, color, and the like are input into the row of pixels, and then the output driving signal turns off the row of pixels and turns on the next row of pixels until data writing of each row of pixels in the pixel array 200 is completed. The detailed operation of the scan driving unit 130 provided in the present application will be described in detail later.

In operational relation, the simultaneous driving unit 120 is configured to generate the driving signal DS1 in response to the control signal CL1 and the switching signal SC being enabled, and the scan driving unit 130 is configured to generate the driving signal DS2 in response to the control signal CL2 being enabled, and then the control circuit 110 is configured to select the driving signal DS1 output from the simultaneous driving unit 120 or the driving signal DS2 output from the scan driving unit 130 as the output signal OUT to the pixel array 200 according to the control signals CL1 and CL2, wherein each pixel in the pixel array 200 is driven simultaneously in response to the driving signal DS1 as the output signal OUT, or sequentially driven to receive a data signal according to the driving signal DS2 as the output signal OUT.

For example, in some embodiments, when the simultaneous driving unit 120 outputs the driving signal DS1 as the output signal OUT to the pixel array 200, each row of pixels in the pixel array 200 is driven to perform reset (reset) and/or compensation, etc. at the same time, in other words, the simultaneous driving unit 120 outputs pulses with the same waveform to each pixel in the pixel array 200 in a time period, so that the pixels are driven to perform operation at the same time; in addition, when the scan driving unit 130 outputs the driving signal DS2 as the output signal OUT to the pixel array 200, each column of pixels in the pixel array 200 is sequentially driven to be written with data, emit light, and the like. The above-mentioned embodiments are provided only for the purpose of easy understanding of the present application, but the embodiments of the present application are not limited thereto. The detailed operation of the control circuit 110, the simultaneous driving unit 120, and the scan driving unit 130 provided herein will be described in detail later.

Please refer to fig. 2. Fig. 2 is a schematic diagram illustrating the simultaneous driving unit 120 shown in fig. 1 according to an embodiment of the present application. As shown in fig. 2, the simultaneous driving unit 120 includes an inverter 121, a nor gate 122, a pull-down control circuit 123, a pull-up control circuit 124, a pull-up circuit 125, and a pull-down circuit 126. The input terminal of the inverter 121 is configured to receive the control signal CL1, the output terminal of the inverter 121 is coupled to the first input terminal of the nor gate 122, the second input terminal of the nor gate 122 is configured to receive the switching signal SC, the pull-down control circuit 123 is coupled between the pull-down circuit 126 and the second output terminal of the nor gate 122, and the pull-up control circuit 124 is coupled between the pull-up circuit 125 and the output terminal of the nor gate 122.

Please refer to fig. 3. Fig. 3 is a circuit diagram illustrating the simultaneous driving unit 120 shown in fig. 2 according to an embodiment of the present application. As shown in fig. 3, the inverter 121 includes transistors T1, T2, the nor gate 122 includes transistors T3, T4, T5, T6, the pull-down control circuit 123 includes transistor T7, the pull-up control circuit 124 includes transistor T8, the pull-up circuit 125 includes transistor T9, and the pull-down circuit 126 includes transistor T10, wherein the transistors T1, T3, T4, T7, T9 are P-type transistors, and the transistors T2, T5, T6, T8, T10 are N-type transistors. It should be noted that the above embodiments of the inverter 121, the nor gate 122, the pull-down control circuit 123 and the pull-up control circuit 124 are only examples for easy understanding of the present application, and other circuit configurations are within the scope of the present application, for example, the transistors T1, T3, T4, T7 and T9 may be implemented by N-type transistors, and the transistors T2, T5, T6, T8 and T10 are P-type transistors, and the control signals applied to these transistors are adjusted accordingly.

Specifically, in some embodiments, as shown in fig. 3, a first terminal of the transistor T1 is coupled to a first terminal of the transistor T2, a second terminal of the transistor T1 is coupled to a second terminal of the transistor T2 and serves as an input terminal of the inverter 121, a third terminal of the transistor T1 is coupled to the supply voltage terminal VGH, and a third terminal of the transistor T2 is coupled to the supply voltage terminal VGL, wherein the supply voltage terminal VGH is higher than the supply voltage terminal VGL.

Continuing with the above embodiment, the first terminal of the transistor T3 in the nor gate 122 is coupled to the first terminal of the transistor T4, the second terminal of the transistor T4 is coupled to the first terminal of the transistor T5 and the first terminal of the transistor T6 and serves as the output terminal (node N) of the nor gate 122, the second terminal of the transistor T3 is coupled to the second terminal of the transistor T5 and serves as the first input terminal (node Q) of the nor gate 122, the third terminal of the transistor T4 is coupled to the second terminal of the transistor T6 and serves as the second input terminal of the nor gate 122, the third terminal of the transistor T3 is coupled to the supply voltage terminal VGH, and the third terminal of the transistor T5 and the third terminal of the transistor T6 are coupled to the supply voltage terminal VGL.

In addition, a first terminal of the transistor T7 of the pull-down control circuit 123 is coupled to the second terminal of the transistor T4 and the second terminal of the transistor T6, a first terminal of the transistor T7 is coupled to the switching signal SC, and a second terminal of the transistor T7 is coupled to the supply voltage terminal VGH. A first terminal of the transistor T8 of the pull-up control circuit 124 is coupled to the third terminal of the transistor T7 at the node K. The transistor T8 is for receiving the control signal CL1, and the third terminal of the transistor T8 is coupled to the second terminal of the transistor T4, the first terminal of the transistor T5 and the first terminal of the transistor T6.

Continuing with the above embodiment, the first terminal of the transistor T9 in the pull-up circuit 125 is coupled to the supply voltage terminal VGH, and the second terminal of the transistor T9 is coupled to the third terminal of the transistor T7 and the first terminal of the transistor T8. The first terminal of the transistor T10 in the pull-down circuit 126 is coupled to the third terminal of the transistor T9 for driving the output terminal of the cell 120, the second terminal of the transistor T10 is coupled to the supply voltage terminal VGL, and the third terminal of the transistor T10 is coupled to the third terminal of the transistor T8.

Please refer to fig. 4. Fig. 4 is a waveform diagram illustrating various control signals and levels of nodes according to an embodiment of the present disclosure. In some embodiments, control signals as shown in fig. 4 may be implemented in the driving circuit 100 as shown in fig. 1, and the manner in which the simultaneous driving unit 120 in the driving circuit 100 operates in response to various signals as shown in fig. 4 will be as shown in the embodiments in fig. 5A to 5D.

As shown in fig. 4, in the time interval T1, the control signal CL1 has a high level and the control signal CL2 has a low level, the driving circuit 100 operates in a simultaneous mode (simultaneous mode) to output the driving signal DS1 as the output signal OUT to the pixel array 200, and in the time interval T2, the control signal CL2 has a low level and the control signal CL2 has a high level, the driving circuit 100 operates in a progressive mode (progressive mode) to output the driving signal DS2 as the output signal OUT to the pixel array 200, in other words, the time for operating the pixel array 200 in each mode, i.e., the simultaneous driving time and the progressive driving time of the pixel array 200, can be changed by adjusting the times at which the control signals CL1 and CL2 respectively have high and low levels. It is noted that the output signals OUT may include output signals OUT [0] OUT [ n ] corresponding to n rows of pixels in the pixel array 200, but for the sake of simplicity, only one row of pixels in the pixel array 200 is shown in FIG. 4.

Please refer to fig. 5A to 5D. Fig. 5A to 5D are schematic equivalent circuit operation diagrams illustrating the operation of the simultaneous driving unit 120 shown in fig. 3 according to an embodiment of the present application. For ease of understanding, the same elements in fig. 5A to 5D as in fig. 3 will be labeled with the same reference numerals. Unless there is a need to explain the cooperative relationship with the elements shown in fig. 5A to 5D, the specific operation of similar elements that have been discussed in detail in the above paragraphs is omitted here for the sake of brevity.

Please refer to fig. 4 and fig. 5A together. Specifically, in the sub-interval T11 of the time interval T1, the control signal CL1 has a high level, accordingly, the transistor T1 is turned off, the transistor T2 is turned on, and the node Q level is a low level (turned on with the supply voltage terminal VGL having a low level), in other words, the control signal CL1 having a high level is outputted as a signal having a low level after passing through the inverter 121. Then, in response to the low level of the node Q, the transistor T3 is turned on, the transistor T5 is turned off, and in response to the switching signal SC having a high level, the transistor T4 is turned off, the transistor T6 is turned on, and accordingly the node N has a low level (turned on with the supply voltage terminal VGL having a low level), in other words, the first input terminal (node Q) of the nor gate 122 receives a low level, the second input terminal (switching signal SC) receives a high level, and the output terminal (node N) outputs a low level. The transistor T7 is turned off in response to the high-level switching signal SC, the transistor T8 is turned on in response to the high-level control signal CL1, so that the node K has a low level, the transistor T9 is turned on in response to the high-level control signal SC, the transistor T10 is turned off, and the output terminal of the driving unit 120 outputs the high-level-removed driving signal DS1 from the supply voltage terminal VGH as the output signal OUT.

Please refer to fig. 4 and fig. 5B together with the above embodiments. In the sub-interval T12 of the time interval T1, the control signal CL1 has a high level, the transistor T1 is turned off, the transistor T2 is turned on, and the level of the node Q is low, in other words, the inverter 121 still outputs a low level signal. Then, in response to the low level of the node Q, the transistor T3 is turned on, the transistor T5 is turned off, and in response to the switching signal SC being switched to the low level, the transistor T4 is turned on, the transistor T6 is turned off, and accordingly the node N is at a high level (turned on with the supply voltage terminal VGH at a high level), in other words, the first input terminal (node Q) of the nor gate 122 receives the low level, the second input terminal (switching signal SC) thereof receives the low level, and the output terminal (node N) thereof outputs the high level. The transistor T7 is turned on according to the low-level switching signal SC, so that the node K has a high level, the transistor T8 is turned off according to the high-level control signal CL1 and the high level of the node K, the transistor T9 is turned off accordingly, the transistor T10 is turned on, and at this time, the output terminal of the driving unit 120 outputs the low-level-removed driving signal DS1 from the supply voltage terminal VGL as the output signal OUT.

Next, please refer to fig. 4 and fig. 5C together. In the sub-interval T13 of the time interval T1, the control signal CL1 has a high level, the transistor T1 is turned off, the transistor T2 is turned on, the level of the node Q is low, and the inverter 121 outputs a signal having a low level. Then, in response to the low potential of the node Q, the transistor T3 is turned on, the transistor T5 is turned off, and in response to the switching signal SC having a high potential, the transistor T4 is turned off, the transistor T6 is turned on, and accordingly the node N has a low potential, in other words, the output terminal (node N) of the nor gate 122 outputs a low potential. The transistor T7 is turned off in response to the high-level switching signal SC, the transistor T8 is turned on in response to the high-level control signal CL1, the node K has a low level, the transistor T9 is turned on in response to the high-level control signal CL 8 being turned off, and the transistor T10 is turned on, at this time, the output terminal of the driving unit 120 outputs the high-level driving signal DS1 from the supply voltage terminal VGH as the output signal OUT.

As described above, the driving circuit 100 operates in the simultaneous mode, and in the time interval T1, the simultaneous driving unit 120 outputs the output signal OUT in response to the high-level control signal CL1, and the control circuit 110 is turned off in response to the control signals CL1 and CL2, so that each column in the pixel array 200 receives the output signal OUT from the simultaneous driving unit 120 and acts simultaneously. For example, in some embodiments, a transistor included in each row of pixels in the pixel array 200 is turned on or off in response to the output signal OUT to perform the pixel circuit Vth compensation. Those skilled in the art will understand the related art of Vth compensation of the pixel circuit, and will not be described herein.

It should be noted that, as shown in fig. 4, in the time interval T1, i.e. in the simultaneous mode, the driving signal DS1 output from the simultaneous driving unit 120 has the same phase level as the switching signal SC, in other words, the simultaneous driving time can be further changed by changing the duty cycle of the switching signal SC to change the duty cycle of the driving signal DS 1.

Please refer to fig. 4 and 5D together with the above embodiments. In the time interval T2, the control signal CL1 has a low level, the transistor T1 is turned on, the transistor T2 is turned off, and the node Q level is high, in other words, the control signal CL1 having a low level is outputted as a signal having a high level after passing through the inverter 121. Then, in response to the high voltage at the node Q, the transistor T3 is turned off, the transistor T5 is turned on, and in response to the switching signal SC being switched to the low voltage, the transistor T4 is turned on, the transistor T6 is turned off, and accordingly the node N is at the low voltage (turned on with the supply voltage terminal VGL at the low voltage), in other words, the first input terminal (node Q) of the nor gate 122 receives the high voltage, the second input terminal (switching signal SC) receives the low voltage, and the output terminal (node N) outputs the low voltage. The transistor T7 is turned on according to the low-level switching signal SC, so that the node K has a high level, the transistor T8 is turned off according to the low-level control signal CL1, the transistor T9 is turned off accordingly, and the transistor T10 is turned off, at this time, the driving unit 120 does not output any signal. In some embodiments, the output of the simultaneous driving unit 120 is in a floating state (floating). However, the present application is not limited thereto.

Please refer to fig. 6. Fig. 6 is a schematic diagram illustrating the scan driving unit 130 shown in fig. 1 according to an embodiment of the present application. As shown in fig. 6, the scan driving unit 130 includes transistors T11, T12, T13, T14, T15, T16, and capacitors C1, C2. The transistor T11 is coupled to the transistors T12, T15, T16, the transistor T12 is coupled to the capacitor C1, the transistor T14 is coupled to the transistors T15, T16, and the transistor T13 is coupled to the capacitors C1, C2. The scan driving unit 130 is operative to output a driving signal DS2 as an output signal OUT to the pixel array 200 IN response to the scan signal IN and the pulse signals CK1 and CK 2. It should be noted that the scan driving unit 130 shown in fig. 6 is only used for example, any circuit for sequentially providing pulse signals to drive a plurality of rows of pixels in different enabling periods, such as any GOA circuit, can be used to implement the present application.

Please refer to fig. 4 again. In the time interval T2, the control signal CL1 has a low voltage level and the control signal CL2 has a high voltage level, such that the scan driving unit 130 is enabled and the control circuit 110 is turned on, such that the driving signal DS2 generated by the scan driving unit 130 is used as the output signal OUT. As shown IN fig. 4, when the scan signal IN is a pulse signal, the elements IN the scan driving unit 130 cooperate to output a corresponding pulse signal as the driving signal DS2, and the control circuit 110 is turned on IN response to the control signals CL1 and CL2, and then the control circuit 110 outputs the output signal OUT from the scan driving unit 130.

Please refer to fig. 7. Fig. 7 is a block diagram illustrating a driving circuit 100 and a pixel array 200 according to another embodiment of the present application. As shown in FIG. 7, the driving circuit 100 includes a plurality of scan driving units 1301-130 n, the control circuit 110 includes a plurality of sets of coupled switches 111-112, the pixel arrays 2001-200 n are coupled to the sets of switches 111-112 in the control circuit 110, and at least one timing driving unit 120 is coupled to the scan driving units 1301-130 n. In some embodiments, the simultaneous driving unit 120 simultaneously drives the pixel arrays 2001-200 n in the simultaneous mode. In some embodiments, the number of the simultaneous driving units 110 and the number of the scanning driving units included in the driving circuit 100 are 1 to N, where N is a positive integer equal to or greater than 1.

In summary, the driving circuit and the operating method thereof of the present application output signals from the simultaneous driving unit and the progressive scanning driving unit respectively by selective conduction of a simplified control circuit, and drive the pixel array in the simultaneous driving mode and the progressive scanning driving mode respectively by the output signals, so that the volume of the driving circuit is greatly reduced by applying the control circuit provided by the present application to the driving circuit.

In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

The above are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made by the claims of the present disclosure should be covered by the present disclosure.

Claims (12)

1. A driving circuit, comprising:

at least one first driving unit, for responding to the first control signal and the switching signal being enabled and generating a first driving signal;

at least one second driving unit, for responding to the second control signal being enabled and generating a second driving signal; and

a control circuit coupled between the at least one first driving unit and the at least one second driving unit, the control circuit being configured to select to output the first driving signal from the at least one first driving unit or output the second driving signal from the at least one second driving unit as an output signal to at least one pixel array according to the first control signal and the second control signal;

each row of pixels in the at least one pixel array is driven simultaneously in response to the first driving signal, or each row of pixels in the at least one pixel array is driven sequentially according to the second driving signal.

2. The driving circuit of claim 1, wherein the control circuit comprises:

a first switch, a first end of which is coupled to the at least one first driving unit, a second end of which is coupled to the at least one second driving unit, and a control end of which is used for receiving the first control signal; and

a second switch, a first end and a second end of which are coupled to the first end and the second end of the first switch, respectively, and a control end of which is used for receiving the second control signal.

3. The driving circuit of claim 1, wherein the at least one first driving unit comprises:

a NOR gate, a first input end of the NOR gate is used for receiving the switching signal;

an input end of the inverter is used for receiving the first control signal, and an output end of the inverter is coupled to the second input end of the NOR gate;

a pull-down circuit;

a pull-down control circuit coupled between the pull-down circuit and the first input terminal of the nor gate;

a pull-up circuit; and

a pull-up control circuit coupled between the pull-up circuit and the output of the NOR gate.

4. A drive circuit as claimed in claim 3, wherein

The inverter comprises a first transistor and a second transistor, wherein a first end of the first transistor is coupled with a first end of the second transistor, and a second end of the first transistor and a second end of the second transistor are used as the input end of the inverter;

the nor gate comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein a first terminal of the third transistor is coupled to a first terminal of the fourth transistor, a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor and a first terminal of the sixth transistor and serves as the output terminal of the nor gate, a second terminal of the third transistor is coupled to a second terminal of the fifth transistor and serves as the second input terminal of the nor gate, and a third terminal of the fourth transistor and a second terminal of the sixth transistor serve as the first input terminal of the nor gate;

the pull-down control circuit comprises a seventh transistor, wherein a first terminal of the seventh transistor is coupled to the second terminal of the fourth transistor and the second terminal of the sixth transistor, and the first terminal of the seventh transistor is configured to receive the switching signal;

the pull-up control circuit comprises an eighth transistor, wherein a first terminal of the eighth transistor is coupled to a second terminal of the seventh transistor, a second terminal of the eighth transistor is configured to receive the first control signal, and a third terminal of the eighth transistor is coupled to the first terminal of the sixth transistor;

the pull-up circuit comprises a ninth transistor, wherein a first terminal of the ninth transistor is coupled to the second terminal of the seventh transistor and the first terminal of the eighth transistor; and

the pull-down circuit comprises a tenth transistor, wherein a first terminal of the tenth transistor and a second terminal of the ninth transistor are coupled to the output terminal of the first driving unit.

5. The driving circuit of claim 1, wherein the at least one first driving unit comprises:

a first transistor and a second transistor, wherein a first terminal of the first transistor is coupled to a first terminal of the second transistor, a second terminal of the first transistor is coupled to a first supply voltage terminal, a second terminal of the second transistor is coupled to a second supply voltage terminal, and a third terminal of the first transistor and a third terminal of the second transistor are coupled to an input terminal for receiving the first control signal;

a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein a first terminal of the third transistor is coupled to a first terminal of the fourth transistor, a second terminal of the third transistor is coupled to the first supply voltage terminal, a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor and a first terminal of the sixth transistor, a second terminal of the fifth transistor and a second terminal of the sixth transistor are coupled to the second supply voltage terminal, a third terminal of the fifth transistor is coupled to a third terminal of the third transistor, and a third terminal of the fourth transistor is coupled to a third terminal of the sixth transistor for receiving the switching signal;

a seventh transistor, a first terminal of which is coupled to the first supply voltage terminal, and a second terminal of which is configured to receive the switching signal;

a first terminal of the eighth transistor is coupled to the third terminal of the seventh transistor, a second terminal of the eighth transistor is coupled to the first terminal of the sixth transistor, and a third terminal of the eighth transistor is configured to receive the first control signal;

a ninth transistor, a first terminal of the ninth transistor being coupled to the first supply voltage terminal, a second terminal of the ninth transistor being coupled to the third terminal of the seventh transistor and the first terminal of the eighth transistor; and

a tenth transistor, a first terminal of the tenth transistor being coupled to the third terminal of the ninth transistor, a second terminal of the tenth transistor being coupled to the second supply voltage terminal, and a third terminal of the tenth transistor being coupled to the second terminal of the eighth transistor.

6. A drive circuit as claimed in claim 1, wherein

When the first control signal has a high level and the second control signal has a low level, the control circuit is used for outputting the first driving signal from the at least one first driving unit;

wherein the first driving signal has a high level or a low level in response to the switching signal.

7. A drive circuit as claimed in claim 1, wherein

When the first control signal has a low level and the second control signal has a high level, the control circuit is used for outputting the second driving signal from the at least one second driving unit.

8. A drive circuit as claimed in claim 1, wherein

The number of the at least one first driving unit and the at least one second driving unit is 1 to N, wherein N is a positive integer equal to or greater than 1.

9. A method of operating a driver circuit for the driver circuit of claim 1, comprising:

simultaneously driving each row of pixels in the pixel array according to a first driving signal output from the first driving unit by turning off the control circuit in response to the first control signal and the second control signal; and

by turning on the control circuit, each row of pixels in the pixel array is driven progressively according to a second driving signal output from the second driving unit.

10. The method of claim 9, further comprising:

generating the first driving signal by the first driving unit in response to the first control signal and a switching signal;

wherein the first driving signal and the switching signal have the same level.

11. The method of claim 9, further comprising:

when the first control signal has a low level and the second control signal has a high level, the second driving signal is output from the second driving unit to the pixel array.

12. The method of claim 9, further comprising:

the first control signal and the second control signal are adjusted to change the simultaneous driving time and the progressive driving time of the pixel array.

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