CN110033730B - Composite driving display panel - Google Patents
Composite driving display panel Download PDFInfo
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- CN110033730B CN110033730B CN201910242078.7A CN201910242078A CN110033730B CN 110033730 B CN110033730 B CN 110033730B CN 201910242078 A CN201910242078 A CN 201910242078A CN 110033730 B CN110033730 B CN 110033730B
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- 239000002131 composite material Substances 0.000 title claims abstract description 45
- 239000003990 capacitor Substances 0.000 claims description 34
- 238000010586 diagram Methods 0.000 description 27
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- 230000001276 controlling effect Effects 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- Computer Hardware Design (AREA)
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
A composite driving display panel includes a multi-tasking circuit and a plurality of columns of pixel circuits. The multiplexing circuit is used for outputting one of the first voltage signal and the common driving signal. The multi-column pixel circuits are coupled to the multiplexing circuit and are used for correspondingly receiving a plurality of first control signals. Each pixel circuit of the multi-row pixel circuit comprises a writing circuit, a first driving transistor, a light-emitting unit and a light-emitting control circuit. The write circuit is coupled to the first node and the multiplexing circuit for transmitting a data signal to the first node. The first driving transistor has a control terminal coupled to a first node, a first terminal for receiving a first voltage signal, and a second terminal coupled to a second node. The light emitting control circuit is coupled between the second node and the light emitting unit and used for receiving a first voltage signal. The light-emitting control circuit provides a first driving current to the light-emitting unit according to the first voltage signal, and the first driving transistor provides a second driving current to the light-emitting unit according to the data signal.
Description
Technical Field
The present invention relates to a display panel, and more particularly, to a composite driving display panel with switchable operation modes.
Background
However, the wavelength of the light generated by the green micro-leds is inversely proportional to the current flowing through the green micro-leds, so that the conventional micro-led display faces the problem of green color shift (color shift) when the green pixel circuit of the conventional micro-led display is intended to display different gray-scale brightness.
Disclosure of Invention
The invention provides a composite driving display panel. The composite driving display panel comprises a multitasking circuit and a plurality of columns of pixel circuits. The multiplexing circuit is used for outputting one of the first voltage signal and the common driving signal. The multi-column pixel circuits are coupled to the multiplexing circuit and are used for correspondingly receiving a plurality of first control signals. Each pixel circuit of the multi-column pixel circuits comprises a writing circuit, a first driving transistor, a light-emitting unit and a light-emitting control circuit. The write circuit is coupled to the first node and the multiplexing circuit for transmitting a data signal to the first node. The first driving transistor comprises a control end, a first end and a second end, wherein the control end of the first driving transistor is coupled to the first node, the first end of the first driving transistor is used for receiving a first voltage signal, and the second end of the first driving transistor is coupled to the second node. The light emitting control circuit is coupled between the second node and the light emitting unit and used for receiving a first voltage signal. The light-emitting control circuit provides a first driving current to the light-emitting unit according to the first voltage signal, and the first driving transistor provides a second driving current to the light-emitting unit according to the data signal.
The composite driving display panel can overcome the color cast problem of a micro-light diode as a light-emitting unit.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
Fig. 1 is a simplified functional block diagram of a composite drive display panel according to an embodiment of the invention.
Fig. 2 is a functional block diagram of the pixel circuit of fig. 1.
Fig. 3 is a circuit diagram of the pixel circuit of fig. 2 in an embodiment.
FIG. 4 is a simplified timing diagram of driving signals of the composite driving display panel in the first mode.
Fig. 5 is an equivalent circuit operation diagram of the pixel circuit of fig. 3 in a reset phase of a first mode.
Fig. 6 is an equivalent circuit operation diagram of the pixel circuit of fig. 3 in the compensation phase of the first mode.
FIG. 7 is an equivalent circuit operation diagram of the pixel circuit of FIG. 3 in a writing phase of a first mode.
FIG. 8 is a simplified timing diagram of the first node voltage, the common driving signal and the first driving current.
Fig. 9 is an equivalent circuit operation diagram of the pixel circuit of fig. 3 in a first sub-phase of a first mode.
Fig. 10 is an equivalent circuit operation diagram of the pixel circuit of fig. 3 in the second sub-stage of the first mode.
FIG. 11 is a simplified timing diagram of driving signals of the composite driving display panel in the second mode.
Fig. 12 is an equivalent circuit operation diagram of the pixel circuit of fig. 3 in a reset phase of a second mode.
Fig. 13 is an equivalent circuit operation diagram of the pixel circuit of fig. 3 in the compensation stage of the second mode.
FIG. 14 is an equivalent circuit operation diagram of the pixel circuit of FIG. 3 in a second mode at a writing phase.
Fig. 15 is an equivalent circuit operation diagram of the pixel circuit of fig. 3 in a light-emitting stage of a second mode.
Fig. 16 is a circuit diagram of the pixel circuit of fig. 2 in another embodiment.
FIG. 17 is a simplified timing diagram of driving signals for a composite-drive display panel using the pixel circuit of FIG. 16 and operating in a first mode.
FIG. 18 is a simplified timing diagram of driving signals for a composite-drive display panel using the pixel circuit of FIG. 16 and operating in a second mode.
Wherein, the reference numbers:
100: composite driving display panel Swe: common control signal
102: source driver Sm 1: a first multitask signal
104: gate driver Sm 2: second multitask signal
110: multitask circuit Sdata: data signal
120: pixel circuits SW1 to SW 7: first to seventh switches
210: first drive transistors M1, M2: first multitask switch and second multitask switch
220: write circuit task switch
230: compensation circuit T1: reset phase
240: light emission control circuit T2: compensation phase
250: light-emitting unit T3: write phase
310: the second drive transistor T4: stage of luminescence
CT1, CT1[1] -CT 1[ n ]: first controls P1, P2: a first sub-stage and a second sub-stage
Signals N1-N5: first to fifth nodes
CT 2: second control signals V1 to V5: first to fifth node voltages
CT 3: third control signal Vref 1: a first reference voltage and a second reference voltage
OVDD: system high voltages Idr1, Idr 2: first drive current, second drive
OVSS: current of light emission control signal
L E1 first Enable potential
L D1 first disable potential
L E2 second enabling potential
L D2 second inhibit potential
L S1 first fixed potential
L S2 second fixed potential
Detailed Description
The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:
embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar components or process flows.
Fig. 1 is a simplified functional block diagram of a composite drive display panel 100 according to an embodiment of the present invention. The composite driving display panel 100 includes a source driver 102, a gate driver 104, a multiplexing circuit 110, and a plurality of pixel circuits 120. The pixel circuits 120 are coupled to the multiplexing circuit 110 and arranged in a plurality of columns. The pixel circuits 120 arranged in a plurality of columns are used for correspondingly receiving a plurality of first control signals CT1[1] CT1[ n ] from the gate driver 104. The multiplexing circuit 110 is used for selectively outputting one of the first voltage signal OVDD and the common driving signal Swe to the multi-column pixel circuit 120. By providing the first control signals CT1[1] -CT 1[ n ], the system high voltage OVDD and the common driving signal Swe to the rows of pixel circuits 120, the composite-driving display panel 100 can be switched between two operation modes to adapt to the light-emitting characteristics of different types of pixel circuits 120. For simplicity and ease of illustration, other components and connections in the composite-driven display panel 100 are not shown in fig. 1.
The numbers of components and the indices [1] to [ n ] in the signal numbers used in the specification and the drawings are only for convenience of referring to individual components and signals, and the number of the above components and signals is not intended to be limited to a specific number. In the present specification and drawings, if a component number or a signal number is used without specifying an index of the component number or the signal number, the component number or the signal number refers to any unspecified component or signal in a component group or a signal group. For example, the signal number CT1[1] designates the object as the first control signal CT1[1], and the signal number CT1 designates the object as any unspecified first control signal CT1 among the first control signals CT1[1] -CT 1[ n ].
Fig. 2 is a functional block diagram of the pixel circuit 120 of fig. 1. The pixel circuit 120 includes a first driving transistor 210, a writing circuit 220, a compensation circuit 230, a light emitting control circuit 240, and a light emitting unit 250. The first driving transistor 210 includes a control terminal, a first terminal and a second terminal, the control terminal of the first driving transistor 210 is coupled to the first node N1, the first terminal of the first driving transistor 210 is configured to receive the first voltage signal OVDD, and the second terminal of the first driving transistor 210 is coupled to the second node N2. The write circuit 220 is coupled to the first node N1 and the multiplexing circuit 110, and is configured to transmit the data signal Sdata to the first node N1 according to the first control signal CT 1. The compensation circuit 230 is coupled to the first node N1 and the second node N2, and is used for setting the voltage at the first node N1 to be an absolute value negatively related to the threshold voltage of the first driving transistor 210, so as to compensate the threshold voltage variation of the first driving transistor 210. The light emitting unit 250 includes a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal), wherein the second terminal of the light emitting unit 250 is used for receiving the second voltage signal OVSS.
In practice, the light emitting unit 240 may be implemented by an organic light-emitting diode (oled) or a micro-led (micro-led).
The light-emitting control circuit 240 is coupled between the first terminal of the light-emitting unit 250 and the second node N2, and is configured to receive the first voltage signal OVDD. When the composite-drive display panel 100 operates in the first mode, the light-emitting control circuit 240 disconnects the conductive path between the second node N2 and the light-emitting unit 250 and provides the first driving current Idr1 with a constant magnitude to the light-emitting unit according to the first voltage signal OVDD. Thus, the composite-driven display panel 100 can be used to light the light-emitting units 250 made of certain materials (e.g., green micro-leds) and driven by a constant current, so as to avoid color shift.
On the other hand, when the composite driving display panel 100 operates in the second mode, the first driving transistor 210 generates the second driving current Idr2 with a variable magnitude according to the data signal Sdata. The light-emitting control circuit 240 turns on the conductive path between the second node N2 and the light-emitting unit 250, so that the light-emitting unit 250 receives the second driving current Idr2 from the first driving transistor 210. As such, the composite-drive display panel 100 can be used to light the light emitting units 250 made of other materials (e.g., organic light emitting diodes) and suitable for controlling the brightness by the amount of current flowing through them.
Fig. 3 is a circuit diagram of the pixel circuit 120 of fig. 2 in an embodiment. As shown in fig. 3, the write circuit 220 includes a first capacitor C1, a second capacitor C2, and a first switch SW 1. The first capacitor C1 includes a first terminal and a second terminal, the first terminal of the first capacitor C1 is coupled to the first node N1, and the second terminal of the first capacitor C1 is coupled to the third node N3. The second capacitor C2 includes a first terminal and a second terminal, the first terminal of the second capacitor C2 is coupled to the first node N1, and the second terminal of the second capacitor C2 is coupled to the multiplexing circuit 110. The first switch SW1 includes a control terminal, a first terminal and a second terminal, the control terminal of the first switch SW1 is configured to receive the first control signal CT1, the first terminal of the first switch SW1 is coupled to the third node N3, and the second terminal of the first switch SW1 is configured to receive the data signal Sdata.
The compensation circuit 230 includes a second switch SW2 and a third switch SW 3. The second switch SW2 includes a control terminal, a first terminal and a second terminal, the control terminal of the second switch SW2 is configured to receive the second control signal CT2, the first terminal of the second switch SW2 is coupled to the second node N2, and the second terminal of the second switch SW2 is coupled to the first node N1. The third switch SW3 includes a control terminal, a first terminal and a second terminal, the control terminal of the third switch SW3 is configured to receive the third control signal CT3, the first terminal of the third switch SW3 is configured to receive the first reference voltage Vref1, and the second terminal of the third switch SW3 is coupled to the second node N2.
The light emission control circuit 240 includes a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, a third capacitor C3, and a second driving transistor 310. The fourth switch SW4 includes a control terminal, a first terminal and a second terminal, the control terminal of the fourth switch SW4 is configured to receive the fourth control signal CT4, the first terminal of the fourth switch SW4 is coupled to the second node N2, and the second terminal of the fourth switch SW4 is coupled to the fourth node N4. The fifth switch SW5 includes a control terminal, a first terminal and a second terminal, the control terminal of the fifth switch SW5 is configured to receive the fifth control signal CT5, the first terminal of the fifth switch SW5 is coupled to the fourth node N4, and the second terminal of the fifth switch SW5 is coupled to the fifth node N5. The sixth switch SW6 includes a control terminal, a first terminal and a second terminal, the control terminal of the sixth switch SW6 is configured to receive the sixth control signal CT6, and the first terminal of the sixth switch SW6 is configured to receive the first voltage signal OVDD. The second driving transistor 310 includes a control terminal, a first terminal and a second terminal, the control terminal of the second driving transistor 310 is coupled to the fourth node N4, the first terminal of the second driving transistor 310 is coupled to the second terminal of the sixth switch SW6, and the second terminal of the second driving transistor 310 is coupled to the fifth node N5. A first terminal of the third capacitor C3 is configured to receive the first voltage signal OVDD, and a second terminal of the third capacitor C3 is coupled to the fourth node N4.
In addition, the multiplexing circuit 110 includes a first multiplexing switch M1 and a second multiplexing switch M2. The first multiplexer M1 includes a control terminal, a first terminal and a second terminal, the control terminal of the first multiplexer M1 is configured to receive a first multiplexing signal Sm1, the first terminal of the first multiplexer M1 is coupled to the second terminal of the second capacitor C2, and the second terminal of the first multiplexer M1 is configured to receive a first voltage signal OVDD. The second multiplexing switch M2 includes a control terminal, a first terminal and a second terminal, the control terminal of the second multiplexing switch M2 is configured to receive the second multiplexing signal Sm2, the first terminal of the second multiplexing switch M2 is coupled to the second terminal of the second capacitor C2, and the second terminal of the second multiplexing switch M2 is configured to receive the common driving signal Swe.
In practice, the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, the first multiplexing switch M1, and the second multiplexing switch M2 may be implemented by various suitable P-type transistors.
Fig. 4 is a simplified timing diagram of the driving signals of the composite driving display panel 100 in the first mode. The operation of the composite driving display panel 100 in the first mode will be further described with reference to fig. 3 and fig. 4. For convenience of description, the voltages of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are represented by the first node voltage V1, the second node voltage V2, the third node voltage V3, the fourth node voltage V4 and the fifth node voltage V5, respectively.
As shown in fig. 4, the first control signal CT1, the second control signal CT2, the third control signal CT3, the fourth control signal CT4, the fifth control signal CT5 and the sixth control signal CT6 are switched between a first enable potential L E1 and a first disable potential L D1, the second voltage signal OVSS is switched between a second enable potential L E2 and a second disable potential L D2, the first voltage signal OVDD and the first reference voltage Vref1 have a fixed voltage level, and when the display panel 100 is driven to operate in the first mode, the first multi-tasking switch M1 is turned off and the second multi-tasking switch M2 is turned on to transmit the common driving signal Swe to the second capacitor C2.
In the reset period T1, the first control signal CT1, the second control signal CT2, the third control signal CT3 and the fourth control signal CT4 have the first enable potential L E1, the fifth control signal CT5 and the sixth control signal CT6 have the first disable potential L D1, the second voltage signal OVSS has the second disable potential L D2., the data signal Sdata has the first reference potential L S1, and the common driving signal Swe has the second reference potential L S2, so that the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 are turned on, and the fifth switch SW5, the sixth switch SW6 and the light emitting unit 250 are turned off.
In this case, the pixel circuit 120 is equivalent to the equivalent circuit shown in fig. 5. As shown in fig. 5, the first node voltage V1 and the fourth node voltage V4 are set close to the first reference voltage Vref 1. The data signal Sdata is delivered to the third node N3, and the common driving signal Swe is delivered to the second terminal of the second capacitor C2. In the reset period T1, the data signal Sdata and the common driving signal Swe are dc signals, so the data signal Sdata and the common driving signal Swe are isolated by the first capacitor C1 and the second capacitor C2, respectively, and are not transmitted to the first node N1.
In the compensation phase T2, the first control signal CT1, the second control signal CT2 and the fifth control signal CT5 have the first enable potential L E1, the third control signal CT3, the fourth control signal CT4 and the sixth control signal CT6 have the first disable potential L D1, the second voltage signal OVSS has the second disable potential L D2., the data signal Sdata is maintained at the first reference potential L S1, and the common driving signal Swe is maintained at the second reference potential L S2, so that the first switch SW1 and the second switch SW2 are turned on, and the third switch SW3, the fourth switch SW4, the fifth switch SW5, the sixth switch SW6 and the light emitting unit 250 are turned off.
In this case, the pixel circuit 120 is equivalent to the equivalent circuit shown in fig. 6. As shown in fig. 6, the first voltage signal OVDD charges the first node N1 through the first driving transistor 210 until the first node voltage V1 has a voltage level as shown in formula 1 below:
v1 ═ OVDD- | Vth1| equation 1
Where Vth1 represents the threshold voltage of the first drive transistor 210.
In the writing period T3, the first control signal CT1 is switched from the first disable potential L D1 to the first enable potential L E1, and is maintained at the first enable potential L E1 for a predetermined time Tp, and then is switched back from the first enable potential L E1 to the first disable potential L D1, the second control signal CT2, the third control signal CT3, the fourth control signal CT4, the fifth control signal CT5 and the sixth control signal CT6 have the first disable potential L D1, and the second voltage signal OVSS has the second disable potential L D2., at this time, the common driving signal SW is maintained at the second reference potential L S2, the data signal Sdata is switched among a plurality of voltage potentials higher than the first reference potential L S1, and thus the first switch SW1 is turned on, and the remaining switches of the pixel circuit 120 and the light emitting unit 250 are turned off.
In this case, the pixel circuit 120 is equivalent to the equivalent circuit shown in FIG. 7. the data signal Sdata is transmitted to the third node N3, such that the third node voltage V3 starts to change from the first reference voltage L S1 stored in the compensation stage T2. the change amount of the third node voltage V3 (i.e., the AC component of the data signal Sdata) is further transmitted to the first node N1. via the first capacitor C1. therefore, the first node voltage V1 has a voltage level shown in equation 2 below:
v1 ═ OVDD- | Vth1| + L G-L S1 equation 2
L G represents a specific voltage level of the data signal Sdata when the pixel circuit 120 enters the writing phase T3 and the first switch SW1 is turned on, the specific voltage level is used for determining the turn-on time of the first driving transistor 210 in the next phase of operation.
In the lighting period T4, the first control signal CT1, the second control signal CT2, the third control signal CT3 and the fifth control signal CT5 have the first disable potential L D1, the fourth control signal CT4 and the sixth control signal CT6 have the first enable potential L e1, the common driving signal Swe has a gradually decreasing ramp pulse, therefore, in this period, the fourth switch SW4 and the sixth switch SW6 are kept on, and the first driving transistor 210 and the second driving transistor 310 are alternately turned on and off, fig. 8 particularly shows a simplified timing diagram of the first node voltage V1, the common driving signal Swe and the first driving current r1, as shown in fig. 8, the lighting period T4 includes a first sub-period P1 and a second sub-period.
In the first sub-phase P1, the common driving signal Swe starts to fall from the second reference voltage L S2, and the ac component of the common driving signal Swe is further transmitted to the first node N1 through the second capacitor C2, so that the first node voltage V1 also starts to fall, in this phase, the first node voltage V1 is greater than the voltage level shown in formula 1, so the first driving transistor 210 is turned off, on the other hand, the second driving transistor 310 is turned on, so that the pixel circuit 120 is equivalent to the equivalent circuit shown in fig. 9.
Since the fourth node voltage V4 is equal to the first reference voltage Vref1, the second driving transistor 310 generates the first driving current Idr1 with a magnitude shown in equation 3 below during the first sub-phase P1:
where Vth2 represents the threshold voltage of the second drive transistor 31O. K2 represents the carrier mobility (carrier mobility) of the second driving transistor 310, the unit capacitance of the gate oxide, and the product of the gate width to length ratio. Since the first voltage signal OVDD and the first reference voltage Vref1 have fixed voltage potentials, the first driving current Idr1 has a fixed magnitude as shown in equation 3.
In the second sub-phase P2, the common driving signal Swe continuously decreases, so that the first node voltage V1 decreases to a voltage level less than that shown in equation 1. Therefore, the first driving transistor 210 is switched from the off state to the on state, such that the first voltage signal OVDD is transmitted to the fourth node N4 through the first driving transistor 210 and the fourth switch SW 4. In this way, the fourth node voltage V4 is equal to the voltage level of the first voltage signal OVDD, such that the second driving transistor 310 is switched from the on state to the off state. In this case, the pixel circuit 120 is equivalent to the equivalent circuit shown in fig. 10.
If the ramp pulse of the common driving signal Swe has a constant falling slope, the time duration of the first sub-phase P1 is positively correlated to the voltage level of the first node voltage V1 during the writing phase T3 (i.e., the voltage level shown in equation 2). On the other hand, the duration of the second sub-phase P2 is negatively related to the voltage level of the first node voltage V1 during the write phase T3.
As can be seen from the above, the higher the voltage potential of the data signal Sdata received by the pixel circuit 120 in the writing period T3, the longer the light-emitting time of the pixel circuit 120 in the light-emitting period T4. That is, when the composite-driving display panel 100 operates in the first mode, the plurality of pixel circuits 120 may emit light asynchronously and have the same light-emitting brightness. By adjusting the light emitting time of the pixel circuit 120 in the light emitting period T4, the user can feel different gray levels of brightness.
Fig. 11 is a simplified timing diagram of the driving signals when the composite driving display panel 100 operates in the second mode. As shown in fig. 10, waveforms of the first control signal CT1, the second control signal CT2, the third control signal CT3, the first voltage signal OVDD, and the second voltage signal OVSS in the second mode are similar to those in the first mode, and for brevity, repeated description is omitted here. In addition, when the display panel 100 is driven to operate in the second mode, the first multiplexing switch M1 is turned on and the second multiplexing switch M2 is turned off to transmit the first voltage signal OVDD to the second capacitor C2.
In the reset period T1, the fourth control signal CT4 and the fifth control signal CT5 have the first enable potential L E1, the sixth control signal CT6 has the first disable potential L d1, and the data signal Sdata has the first reference potential L s1, so that the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4 and the fifth switch SW5 are turned on, and the sixth switch SW6 and the light emitting unit 250 are turned off.
In this case, the pixel circuit 120 is equivalent to the equivalent circuit shown in fig. 12. As shown in fig. 12, the first node voltage V1, the fourth node voltage V4, and the fifth node voltage V5 are set to be close to the first reference voltage Vref 1. The data signal Sdata is transferred to the third node N3, and the first voltage signal OVDD is transferred to the second terminal of the second capacitor C2. Since the data signal Sdata is a dc signal in the reset period T1, the data signal Sdata is isolated by the first capacitor C1 and is not transmitted to the first node N1.
In the compensation phase T2, the fifth control signal CT2 has a first enable potential L E1, the fourth control signal CT4 and the sixth control signal CT6 have a first disable potential L d 1. in addition, the data signal Sdata is maintained at the first reference potential L s 1. therefore, the first switch SW1, the second switch SW2 and the fifth switch SW5 are turned on, and the third switch SW3, the fourth switch SW4, the sixth switch SW6 and the light emitting unit 250 are turned off.
In this case, the pixel circuit 120 is equivalent to the equivalent circuit shown in fig. 13. As shown in fig. 13, the first voltage signal OVDD charges the first node N1 through the first driving transistor 210 until the first node voltage V1 has a voltage level shown in formula 1.
In the write phase T3, the fifth control signal CT5 has a first enable potential L E1, the fourth control signal CT4 and the sixth control signal CT6 have a first disable potential L d1, the data signal Sdata is switched among a plurality of voltage potentials that are lower than the first reference potential L s1, and thus the first switch SW1 and the fifth switch SW5 are turned on, and the remaining switches of the pixel circuit 120 are turned off.
As shown in FIG. 14, the data signal Sdata is transmitted to the third node N3 such that the third node voltage V3 starts to change from the first reference potential L S1 stored in the compensation stage T2. the change of the third node voltage V3 (i.e., the AC component of the data signal Sdata) is further transmitted to the first node N1. via the first capacitor C1. thus, the first node voltage V1 has a voltage level shown in equation 4:
v1 ═ OVDD- | Vth1| + L A-L S1 equation 4
L A represents a specific voltage level of the data signal Sdata when the pixel circuit 120 enters the write phase T3 and the first switch SW1 is turned on, the specific voltage level is used for determining the magnitude of the first driving current Idr1 generated by the first driving transistor 210 in the next operation, and is not used for determining the turn-on time of the first driving transistor 210.
It is noted that, in the reset stage T1 and the compensation stage T2 of fig. 11, the plurality of first control signals CT1[1] -CT 1[ n ] are all at the first enabling potential L E1 in the write stage T3, the plurality of first control signals CT1[1] -CT 1[ n ] are sequentially switched from the first disabling potential L D1 to the first enabling potential L E1 and are maintained at the first enabling potential L E1 for the predetermined time Tp, and then are switched from the first enabling potential L E1 to the first disabling potential L D1. in other words, the plurality of pixel circuits 120 of the composite-driven display panel 100 simultaneously compensate the threshold voltage variation of the respective first driving transistors 210, and then sequentially receive the data signal sdata having the specific voltage potential, so that each pixel circuit 120 can obtain sufficient time to compensate the threshold voltage variation of the first driving transistors 210.
In the lighting period T4, the fourth control signal CT4 and the fifth control signal CT5 have the first enable potential L E1, and the sixth control signal CT6 has the first disable potential L d1, so that the fourth switch SW4 and the fifth switch SW5 are turned on, and the rest of the switches of the pixel circuit 120 are turned off.
In this case, the pixel circuit 120 is equivalent to the equivalent circuit shown in fig. 15. As shown in FIG. 15, the first driving transistor 210 generates the second driving current Idr2 according to the first node voltage V1, and the second driving current Idr2 charges the fourth node N4, such that the second driving transistor 310 is turned off. The magnitude of the second driving current Idr2 can be expressed by the following equation 5:
where k1 represents the carrier mobility (carrier mobility) of the first driving transistor 210, the product of the unit capacitance of the gate oxide layer and the gate width-to-length ratio, and Cp1 and Cp2 represent the capacitance values of the first capacitor C1 and the second capacitor C2, respectively.
From equation 5, the magnitude of the second driving current Idr2 is not changed by the variation of the threshold voltage of the first driving transistor 210. By adjusting the magnitude of the driving current Idr2, the user can feel different gray levels of brightness. That is, when the composite-drive display panel 100 operates in the second mode, the pixel circuits 120 emit light simultaneously and may have different light-emitting luminances.
In one embodiment, one or more of the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, the fifth switch SW5, the sixth switch SW6, the first multiplexing switch M1 and the second multiplexing switch M2 are implemented by N-type transistors. In this case, corresponding one or more of the first control signal CT1, the second control signal CT2, the third control signal CT3, the fourth control signal CT4, the fifth control signal CT5, the sixth control signal CT6, the first multiplexing control signal Sm1, and the second multiplexing control signal Sm2 may take a waveform that is inverted from the corresponding signal of fig. 4.
Fig. 16 is a circuit diagram of the pixel circuit 120 of fig. 2 in another embodiment. The pixel circuit 120 of fig. 16 is similar to the pixel circuit 120 of fig. 3. The difference is that the light-emitting control circuit 240 of the pixel circuit 120 of fig. 16 further includes a seventh switch SW 7. The seventh switch SW7 includes a control terminal, a first terminal and a second terminal, the control terminal of the seventh switch SW7 is configured to receive the seventh control signal CT7, the first terminal of the seventh switch SW7 is coupled to the second terminal of the sixth switch SW6, and the second terminal of the seventh switch SW7 is configured to receive the second reference voltage Vref 2. In the present embodiment, the second reference voltage Vref2 has a fixed voltage potential.
Fig. 17 is a simplified timing diagram of driving signals of the composite-drive display panel 100 using the pixel circuit 120 of fig. 16 and operating in the first mode. As shown in fig. 17, the control signals of the first mode of the present embodiment are similar to the control signals of the first mode shown in fig. 4. The difference is that the seventh control signal CT7 of the present embodiment has the same waveform as the fifth control signal CT 5. Therefore, the seventh switch SW7 is turned off during the reset period T1, the write period T3 and the light-emitting period T4 of the first mode, and is turned on during the compensation period T2.
During the compensation period T2, the second reference voltage Vref2 charges the fourth node N4 through the seventh switch SW7 and the second driving transistor 310 until the fourth node voltage V4 has a voltage level as shown in equation 6 below:
v4 is Vref2- | Vth2| equation 6
Therefore, during the light emitting period T4, the magnitude of the first driving current Idr1 generated by the second driving transistor 310 can be expressed by the following equation 7:
from equation 7, the magnitude of the first driving current Idr1 does not change due to the variation of the threshold voltage of the second driving transistor 310.
Fig. 18 is a simplified timing diagram of driving signals of the composite-drive display panel 100 using the pixel circuit 120 of fig. 16 and operating in the second mode. As shown in fig. 18, the control signals of the second mode of the present embodiment are similar to the control signals of the second mode shown in fig. 11. The difference is that the waveform of the seventh control signal CT7 is the same as that of the sixth control signal CT 6. Therefore, the seventh switch SW7 is turned off during the reset phase T1, the compensation phase T2, the write phase T3 and the light-emitting phase T4 of the second mode.
As can be seen from the above, the pixel circuit 120 of fig. 16 can compensate for the threshold voltage variation of the first driving transistor 210 and the second driving transistor 310. Therefore, the composite-driven display panel 100 using the pixel circuit 120 of fig. 16 can provide a high-quality display in both the first mode and the second mode. The remaining connection manners, components, embodiments and advantages of the pixel circuit 120 shown in fig. 3 are all applicable to the pixel circuit 120 shown in fig. 16, and for brevity, the description is not repeated herein.
In one embodiment, the second terminal of the seventh switch SW7 does not receive the second reference voltage Vref2, but is used for receiving an additional data signal to modulate the magnitude of the first driving current Idr1 in the first mode. Thus, the composite driving display panel 100 can have greater flexibility in controlling the brightness and color of the display image.
To sum up, when the composite driving display panel 100 operates in the first mode, the color shift problem of the micro-leds as the light emitting units can be overcome. On the other hand, when the composite-type driving display panel 100 operates in the second mode, the composite-type driving display panel can drive a pixel circuit using an organic light emitting diode as a light emitting unit, or drive a pixel circuit using a micro light emitting diode which is manufactured by a more advanced process and has no color deviation problem as a light emitting unit. Therefore, the composite driving display panel 100 has high application flexibility.
Certain terms are used throughout the description and following claims to refer to particular components. However, it will be understood by those skilled in the art that the same elements may be referred to by different names. The description and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" as used herein includes any direct or indirect connection. Therefore, if the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection such as wireless transmission, optical transmission, etc., or indirectly connected to the second element through other elements or connection means.
In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A composite driving display panel, comprising:
a multiplexing circuit for outputting one of a first voltage signal and a common driving signal;
a plurality of rows of pixel circuits coupled to the multiplexing circuit and configured to correspondingly receive a plurality of first control signals, each of the plurality of rows of pixel circuits comprising:
a write circuit, coupled to a first node and the multiplexing circuit, for transmitting a data signal to the first node;
a first driving transistor including a control terminal, a first terminal and a second terminal, the control terminal of the first driving transistor being coupled to a first node, the first terminal of the first driving transistor being configured to receive the first voltage signal, the second terminal of the first driving transistor being coupled to a second node;
a light emitting unit; and
a light emitting control circuit coupled between the second node and the light emitting unit for receiving the first voltage signal;
the light-emitting control circuit provides a first driving current to the light-emitting unit according to the first voltage signal, and the first driving transistor provides a second driving current to the light-emitting unit according to the data signal.
2. The composite driving display panel according to claim 1, wherein when the composite driving display panel operates in a first mode, the light-emitting control circuit disconnects the second node from the light-emitting unit and provides the first driving current to the light-emitting unit,
when the composite driving display panel works in a second mode, the light-emitting control circuit conducts the second node and the light-emitting unit so that the light-emitting unit receives the second driving current.
3. The composite driving display panel of claim 1, wherein the write circuit transmits the common driving signal to the first node when the common driving signal received by the write circuit has a ramp pulse.
4. The composite driving display panel of claim 1, further comprising a compensation circuit coupled to the first node and the second node for setting a first node voltage of the first node to an absolute value that is negatively related to a threshold voltage of the first driving transistor.
5. The composite driven display panel of claim 4, wherein the write circuit comprises:
a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to a third node;
a second capacitor having a first end coupled to the first node and a second end coupled to the multiplexing circuit; and
a first switch, including a control terminal, a first terminal and a second terminal, wherein the control terminal of the first switch is configured to receive a first control signal of the plurality of first control signals, the first terminal of the first switch is coupled to the third node, and the second terminal of the first switch is configured to receive the data signal.
6. The composite driven display panel of claim 5, wherein the compensation circuit comprises:
a second switch including a control terminal, a first terminal and a second terminal, the control terminal of the second switch being configured to receive a second control signal, the first terminal of the second switch being coupled to the second node, the second terminal of the second switch being coupled to the first node; and
a third switch having a control terminal, a first terminal and a second terminal, the control terminal of the third switch being configured to receive a third control signal, the first terminal of the third switch being configured to receive a first reference voltage, the second terminal of the third switch being coupled to the second node.
7. The composite driving display panel of claim 6, wherein the first control signal, the second control signal and the third control signal switch between a first enable potential and a first disable potential, a second voltage signal switches between a second enable potential and a second disable potential,
wherein, in a reset phase, the first control signal, the second control signal and the third control signal have the first enable potential, and the second voltage signal has the second disable potential,
in a compensation stage, the first control signal and the second control signal have the first enable potential, the third control signal has the first disable potential, and the second voltage signal has the second disable potential,
in a write-in phase, the first control signal is switched from the first forbidden potential to the first enabled potential, is maintained at the first enabled potential for a preset time, is switched from the first enabled potential to the first forbidden potential, the second control signal and the third control signal have the first forbidden potential, and the second voltage signal has the second forbidden potential,
in a lighting phase, the first control signal, the second control signal and the third control signal have the first disable potential, and the second voltage signal has the second enable potential.
8. The composite driven display panel of claim 5, wherein the multiplexing circuit comprises:
a first multiplexing switch, including a control terminal, a first terminal and a second terminal, wherein the control terminal of the first multiplexing switch is configured to receive a first multiplexing signal, the first terminal of the first multiplexing switch is coupled to the second terminal of the second capacitor, and the second terminal of the first multiplexing switch is configured to receive the first voltage signal; and
a second multi-tasking switch, comprising a control terminal, a first terminal and a second terminal, wherein the control terminal of the second multi-tasking switch is configured to receive a second multi-tasking signal, the first terminal of the second multi-tasking switch is coupled to the second terminal of the second capacitor, and the second terminal of the second multi-tasking switch is configured to receive the common driving signal.
9. The composite driven display panel of claim 4, wherein the light emission control circuit comprises:
a fourth switch including a control terminal, a first terminal and a second terminal, the control terminal of the fourth switch being configured to receive a fourth control signal, the first terminal of the fourth switch being coupled to the second node, the second terminal of the fourth switch being coupled to a fourth node;
a fifth switch having a control terminal, a first terminal and a second terminal, the control terminal of the fifth switch being configured to receive a fifth control signal, the first terminal of the fifth switch being coupled to the fourth node, the second terminal of the fifth switch being coupled to a fifth node;
a sixth switch, including a control terminal, a first terminal and a second terminal, wherein the control terminal of the sixth switch is configured to receive a sixth control signal, and the first terminal of the sixth switch is configured to receive the first voltage signal;
a second driving transistor comprising a control terminal, a first terminal and a second terminal, wherein the control terminal of the second driving transistor is coupled to the fourth node, the first terminal of the second driving transistor is coupled to the second terminal of the sixth switch, and the second terminal of the second driving transistor is coupled to the fifth node; and
a third capacitor having a first end and a second end, the first end of the third capacitor is used for receiving the first voltage signal, and the second end of the third capacitor is coupled to the fourth node.
10. The composite driving display panel according to claim 9, wherein the fourth control signal, the fifth control signal and the sixth control signal switch between a first enable potential and a first disable potential, a second voltage signal switches between a second enable potential and a second disable potential,
wherein, when the composite driving display panel works in a first mode, in a reset stage, the fourth control signal has the first enable potential, the fifth control signal and the sixth control signal have the first disable potential, and the second voltage signal has the second disable potential,
in a compensation stage, the fifth control signal has the first enable potential, the fourth control signal and the sixth control signal have the first disable potential, and the second voltage signal has the second disable potential,
in a write phase, the fourth control signal, the fifth control signal and the sixth control signal have the first disable potential, and the second voltage signal has the second disable potential,
in a lighting phase, the fourth control signal and the sixth control signal have the first enable potential, the fifth control signal has the first disable potential, and the second voltage signal has the second enable potential.
11. The composite driving display panel according to claim 10, wherein when the composite driving display panel is operated in the first mode, the common driving signal has a constant voltage level in the reset phase, the compensation phase and the write phase, and the common driving signal has a ramp pulse in the light-emitting phase.
12. The composite driving display panel according to claim 10, wherein in the reset phase when the composite driving display panel is operated in a second mode, the fourth control signal and the fifth control signal have the first enable potential, the sixth control signal has the first disable potential, and the second voltage signal has the second disable potential,
in the compensation stage, the fifth control signal has the first enable potential, the fourth control signal and the sixth control signal have the first disable potential, and the second voltage signal has the second disable potential,
in the write phase, the fifth control signal has the first enable potential, the fourth control signal and the sixth control signal have the first disable potential, and the second voltage signal has the second disable potential,
in the light-emitting stage, the fourth control signal and the fifth control signal have the first enable potential, the sixth control signal has the first disable potential, and the second voltage signal has the second enable potential.
13. The composite driven display panel of claim 12, wherein the light emission control circuit further comprises:
a seventh switch, including a control terminal, a first terminal and a second terminal, wherein the control terminal of the seventh switch is configured to receive a seventh control signal, the first terminal of the seventh switch is coupled to the second terminal of the sixth switch, and the second terminal of the seventh switch is configured to receive a second reference voltage.
14. The composite driving display panel according to claim 13, wherein the waveforms of the seventh control signal and the fifth control signal are the same when the composite driving display panel operates in the first mode, and the waveforms of the seventh control signal and the sixth control signal are the same when the composite driving display panel operates in the second mode.
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| US201862659662P | 2018-04-18 | 2018-04-18 | |
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| TW107138671A TWI678690B (en) | 2018-04-18 | 2018-10-31 | Hybrid driving display panel |
| TW107138671 | 2018-10-31 |
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| CN110459164B (en) * | 2019-07-26 | 2020-12-08 | 深圳市华星光电半导体显示技术有限公司 | Pixel driving circuit and display device |
| TWI707328B (en) * | 2019-09-17 | 2020-10-11 | 友達光電股份有限公司 | Driving chip and display device having the same |
| CN112750392B (en) * | 2019-10-30 | 2022-04-15 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| TWI713008B (en) * | 2019-11-07 | 2020-12-11 | 友達光電股份有限公司 | Driving circuit and the operation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632850A (en) * | 2005-01-27 | 2005-06-29 | 广辉电子股份有限公司 | Display device and used display panel, pixel circuit and compensating mechanism |
| CN102054436A (en) * | 2010-12-28 | 2011-05-11 | 友达光电股份有限公司 | Pixel circuit of active matrix organic light emitting diode display |
| WO2016175997A1 (en) * | 2015-04-28 | 2016-11-03 | Microsoft Technology Licensing, Llc | Sub-pixel compensation |
| CN106097959A (en) * | 2016-06-02 | 2016-11-09 | 京东方科技集团股份有限公司 | Pixel cell and driving method, pixel-driving circuit and display device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7295192B2 (en) * | 2004-05-04 | 2007-11-13 | Au Optronics Corporation | Compensating color shift of electro-luminescent displays |
| KR100703463B1 (en) * | 2005-08-01 | 2007-04-03 | 삼성에스디아이 주식회사 | Data Driving Circuit and Driving Method of Organic Light Emitting Display Using the same |
| TWI356374B (en) * | 2006-11-21 | 2012-01-11 | Chimei Innolux Corp | Liquid crystal display |
| CN101192382B (en) * | 2006-11-29 | 2010-11-10 | 群康科技(深圳)有限公司 | LCD device |
| WO2008139766A1 (en) * | 2007-05-14 | 2008-11-20 | Sharp Kabushiki Kaisha | Display device and display method thereof |
| CN101127194B (en) * | 2007-09-26 | 2011-05-04 | 友达光电股份有限公司 | Positive type organic light emitting diode display |
| US8754834B2 (en) * | 2009-12-25 | 2014-06-17 | Sony Corporation | Display device and electronic device |
| CN102930840B (en) * | 2012-08-09 | 2015-03-18 | 京东方科技集团股份有限公司 | Liquid crystal display driving circuit as well as driving method and LCD (Liquid Crystal Display) thereof |
| CN105280139B (en) * | 2015-11-11 | 2018-05-01 | 深圳市华星光电技术有限公司 | AMOLED luminance compensation methods and AMOLED drive systems |
| KR102577409B1 (en) * | 2016-08-22 | 2023-09-14 | 엘지디스플레이 주식회사 | Controller, display device, and the method for driving the display device |
| CN106960656B (en) * | 2017-05-11 | 2019-03-19 | 京东方科技集团股份有限公司 | A kind of organic light emitting display panel and its display methods |
-
2019
- 2019-03-28 CN CN201910242078.7A patent/CN110033730B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632850A (en) * | 2005-01-27 | 2005-06-29 | 广辉电子股份有限公司 | Display device and used display panel, pixel circuit and compensating mechanism |
| CN102054436A (en) * | 2010-12-28 | 2011-05-11 | 友达光电股份有限公司 | Pixel circuit of active matrix organic light emitting diode display |
| WO2016175997A1 (en) * | 2015-04-28 | 2016-11-03 | Microsoft Technology Licensing, Llc | Sub-pixel compensation |
| CN106097959A (en) * | 2016-06-02 | 2016-11-09 | 京东方科技集团股份有限公司 | Pixel cell and driving method, pixel-driving circuit and display device |
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