CN110033730A - Combined type drives display panel - Google Patents
Combined type drives display panel Download PDFInfo
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- CN110033730A CN110033730A CN201910242078.7A CN201910242078A CN110033730A CN 110033730 A CN110033730 A CN 110033730A CN 201910242078 A CN201910242078 A CN 201910242078A CN 110033730 A CN110033730 A CN 110033730A
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
A kind of combined type driving display panel includes multiplexing circuitry and multiple row pixel circuit.Multiplexing circuitry is used to export the one of them of first voltage signal and common drive signal.Multiple row pixel circuit is coupled to multiplexing circuitry, for accordingly receiving multiple first control signals.Each pixel circuit of multiple row pixel circuit includes write circuit, the first driving transistor, luminescence unit and emission control circuit.Write circuit is coupled to first node and multiplexing circuitry, for a data-signal to be sent to first node.The control terminal of first driving transistor is coupled to first node, and for first end for receiving first voltage signal, second end is coupled to second node.Emission control circuit is coupled between second node and luminescence unit, for receiving first voltage signal.Emission control circuit provides the first driving current to luminescence unit according to first voltage signal, and the first driving transistor provides the second driving current to luminescence unit according to data-signal.
Description
Technical field
The present invention drives display panel in relation to a kind of display panel, the combined type of espespecially a kind of changeable operating mode.
Background technique
Compared to liquid crystal display, micro- light emitting diode (micro LED) display has low power consumption, high color full
The advantages that with degree and high reaction speed, so that micro- light emitting diode indicator is considered as the hot topic of next-generation main flow display product
One of technology.Traditional micro- light emitting diode indicator is supplied to the electric current of pixel circuit by adjustment, to control pixel circuit
In micro- light emitting diode generate light brightness.However, being limited to current process technique, the micro- light emitting diode of green is produced
The wavelength of raw light can be inversely proportional to the electric current for flowing through the micro- light emitting diode of green.Therefore, when traditional micro- light emitting diode is aobvious
When showing that the green pixel circuit in device is intended to show different gray-scale intensities, the problem of green colour cast (color shift) can be faced.
Summary of the invention
The present invention provides a kind of combined type driving display panel.It includes multiplexing circuitry and more that combined type, which drives display panel,
Column pixel circuit.Multiplexing circuitry is used to export the one of them of first voltage signal and common drive signal.Multiple row pixel electricity
Road is coupled to multiplexing circuitry, for accordingly receiving multiple first control signals.Each pixel electricity of multiple row pixel circuit
Road includes write circuit, the first driving transistor, luminescence unit and emission control circuit.Write circuit is coupled to first node
And multiplexing circuitry, for a data-signal to be sent to first node.First driving transistor include control terminal, first end and
The control terminal of second end, the first driving transistor is coupled to first node, and the first end of the first driving transistor is for receiving the
The second end of one voltage signal, the first driving transistor is coupled to second node.Emission control circuit be coupled to second node and
Between luminescence unit, for receiving first voltage signal.Wherein emission control circuit provides first according to first voltage signal and drives
Streaming current to luminescence unit, the first driving transistor provides the second driving current to luminescence unit according to data-signal.
Above-mentioned combined type driving display panel can overcome the problems, such as colour cast of the low-light diode as luminescence unit.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Detailed description of the invention
Fig. 1 is to drive the simplified functional block diagram of display panel according to the combined type of one embodiment of the invention.
Fig. 2 is the functional block diagram of the pixel circuit of Fig. 1.
Fig. 3 is circuit diagram of the pixel circuit of Fig. 2 in an embodiment.
Fig. 4 is the simplified timing diagram of driving signal when combined type drives display panel to work in first mode.
The pixel circuit that Fig. 5 is Fig. 3 is in the equivalent circuit operation chart of the reset phase of first mode.
The pixel circuit that Fig. 6 is Fig. 3 is in the equivalent circuit operation chart of the compensated stage of first mode.
The pixel circuit that Fig. 7 is Fig. 3 is in the equivalent circuit operation chart of the write phase of first mode.
Fig. 8 is first node voltage, common drive signal and the simplified timing diagram of the first driving current.
The pixel circuit that Fig. 9 is Fig. 3 is in the equivalent circuit operation chart of the first sub-stage of first mode.
The pixel circuit that Figure 10 is Fig. 3 is in the equivalent circuit operation chart of the second sub-stage of first mode.
Figure 11 is the simplified timing diagram of driving signal when combined type drives display panel to work in second mode.
The pixel circuit that Figure 12 is Fig. 3 is in the equivalent circuit operation chart of the reset phase of second mode.
The pixel circuit that Figure 13 is Fig. 3 is in the equivalent circuit operation chart of the compensated stage of second mode.
The pixel circuit that Figure 14 is Fig. 3 is in the equivalent circuit operation chart of the write phase of second mode.
The pixel circuit that Figure 15 is Fig. 3 is in the equivalent circuit operation chart of the light emitting phase of second mode.
Figure 16 is circuit diagram of the pixel circuit of Fig. 2 in another embodiment.
Figure 17 is that combined type drives driving of the display panel using the pixel circuit of Figure 16 and when working in first mode to believe
Number simplified timing diagram.
Figure 18 is that combined type drives driving of the display panel using the pixel circuit of Figure 16 and when working in second mode to believe
Number simplified timing diagram.
Wherein, appended drawing reference:
100: combined type drives display panel Swe: common control signal
102: the Sm1: the first multi-task signal of source electrode driver
104: the Sm2: the second multi-task signal of gate drivers
110: multiplexing circuitry Sdata: data-signal
120: pixel circuit SW1~SW7: first switch~the 7th switch
210: the first driving transistor M1, M2: the first multitask switch, more than second
220: write circuit task switch
230: compensation circuit T1: reset phase
240: emission control circuit T2: compensated stage
250: luminescence unit T3: write phase
310: the second driving transistor T4: light emitting phase
CT1, CT1 [1]~CT1 [n]: first control P1, P2: the first sub-stage, the second sub-stage
Signal N1~N5: first node~the 5th node
CT2: second control signal V1~V5: first node voltage~the 5th node voltage
CT3: third controls the Vref1: the first reference voltage of signal, the second reference voltage
OVDD: system high voltage Idr1, Idr2: the first driving current, the second driving
OVSS: LED control signal electric current
LE1: the first enable current potential
LD1: the first forbidden energy current potential
LE2: the second enable current potential
LD2: the second forbidden energy current potential
LS1: the first fixed current potential
LS2: the second fixed current potential
Specific embodiment
Structural principle and working principle of the invention are described in detail with reference to the accompanying drawing:
Illustrate the embodiment of the present invention below in conjunction with relevant drawings.In the accompanying drawings, identical label indicate it is identical or
Similar component or method flow.
Fig. 1 is to drive the simplified functional block diagram of display panel 100 according to the combined type of one embodiment of the invention.It is compound
It includes source electrode driver 102, gate drivers 104, multiplexing circuitry 110 and multiple pixels electricity that formula, which drives display panel 100,
Road 120.Multiple pixel circuits 120 are coupled to multiplexing circuitry 110, and are arranged in multiple row.It is arranged in the pixel circuit 120 of multiple row
For accordingly receiving multiple first control signal CT1 [1]~CT1 [n] from gate drivers 104.Multiplexing circuitry 110 is used for
Selectively the one of them of output first voltage signal OVDD and common drive signal Swe is to multiple row pixel circuit 120.By
It is electric to multiple row pixel to provide first control signal CT1 [1]~CT1 [n], system high voltage OVDD and common drive signal Swe
Road 120, combined type driving display panel 100 can switch between two kinds of operating modes, to adapt to different types of pixel electricity
The characteristics of luminescence on road 120.To make simplified form and ease of explanation, combined type drives other assemblies and company in display panel 100
Relationship is connect not to be illustrated in Fig. 1.
Index [1]~[n] in component numerals used in this case the description and the appended drawings and signal number, the side of being intended merely to
Just an other component and signal are censured, is not intended that the quantity by aforementioned components and signal is confined to given number.It is said in this case
In bright book and attached drawing, if not indicating the rope of the component numerals or signal number when using a certain component numerals or signal number
Draw, then represent the component numerals or signal number be censure belonging in component group or signal group not specific any component or
Signal.For example, the object that signal number CT1 [1] is censured is [1] first control signal CT1, and pair that signal number CT1 is censured
As being then not specific any first control signal CT1 in first control signal CT1 [1]~CT1 [n].
Fig. 2 is the functional block diagram of the pixel circuit 120 of Fig. 1.Pixel circuit 120 includes the first driving transistor 210, writes
Enter circuit 220, compensation circuit 230, emission control circuit 240 and luminescence unit 250.First driving transistor 210 includes control
End processed, first end and second end, the control terminal of the first driving transistor 210 are coupled to first node N1, the first driving transistor
210 first end is coupled to second node for receiving first voltage signal OVDD, the second end of the first driving transistor 210
N2.Write circuit 220 is coupled to first node N1 and multiplexing circuitry 110, for believing data according to first control signal CT1
Number Sdata is sent to first node N1.Compensation circuit 230 is coupled to first node N1 and second node N2, is used for first segment
The voltage of point N1 is set as absolute value of the negative about the critical voltage of the first driving transistor 210, brilliant with the first driving of compensation
The critical voltage variation of body pipe 210.Luminescence unit 250 includes first end (for example, anode tap) and second end (for example, cathode
End), wherein the second end of luminescence unit 250 is for receiving second voltage signal OVSS.
In implementation, luminescence unit 240 can use Organic Light Emitting Diode (organic light-emitting diode)
Or micro- light emitting diode (micro light-emitting diode) Lai Shixian.
Emission control circuit 240 is coupled between the first end of luminescence unit 250 and second node N2, and for receiving the
One voltage signal OVDD.When combined type driving display panel 100 works in first mode, emission control circuit 240 be will disconnect
Conductive path between second node N2 and luminescence unit 250, and provide according to first voltage signal OVDD with fixed size
The first driving current Idr1 to luminescence unit.In this way, which combined type driving display panel 100 can be used to light with certain
Material (for example, the micro- light emitting diode of green) is made, and is suitble to the luminescence unit 250 driven with the electric current of fixed size, to keep away
Exempt to generate colour cast.
On the other hand, when combined type driving display panel 100 works in second mode, the first driving 210 meeting of transistor
The the second driving current Idr2 that can vary in size is generated according to data-signal Sdata.The second section can be connected in emission control circuit 240
Conductive path between point N2 and luminescence unit 250 drives so that luminescence unit 250 receives second from the first driving transistor 210
Streaming current Idr2.In this way, which combined type driving display panel 100 can be used to light with other materials (for example, organic hair
Optical diode) it is made, and be suitble to control the luminescence unit 250 of brightness with the size of current flowed through.
Fig. 3 is circuit diagram of the pixel circuit 120 of Fig. 2 in an embodiment.As shown in figure 3, write circuit 220 is wrapped
C1 containing first capacitor, the second capacitor C2 and first switch SW1.First capacitor C1 includes first end and second end, first capacitor
The first end of C1 is coupled to first node N1, and the second end of first capacitor C1 is coupled to third node N3.Second capacitor C2 includes
First end and second end, the first end of the second capacitor C2 are coupled to first node N1, and the second end of the second capacitor C2 is coupled to more
Task circuit 110.First switch SW1 includes control terminal, first end and second end, and the control terminal of first switch SW1 is for receiving
First control signal CT1, the first end of first switch SW1 are coupled to third node N3, and the second end of first switch SW1 is for connecing
Receive data-signal Sdata.
Compensation circuit 230 includes second switch SW2 and third switch SW3.Second switch SW2 includes control terminal, first end
And second end, for receiving second control signal CT2, the first end of second switch SW2 is coupled to the control terminal of second switch SW2
Second node N2, the second end of second switch SW2 are coupled to first node N1.Third switch SW3 include control terminal, first end and
Second end, the control terminal of third switch SW3 is for receiving the first end of third control signal CT3, third switch SW3 for receiving
The second end of first reference voltage Vref 1, third switch SW3 is coupled to second node N2.
Emission control circuit 240 include the 4th switch SW4, the 5th switch SW5, the 6th switch SW6, third capacitor C3 and
Second driving transistor 310.4th switch SW4 includes control terminal, first end and second end, and the control terminal of the 4th switch SW4 is used
In receiving the 4th control signal CT4, the first end of the 4th switch SW4 is coupled to second node N2, the second end of the 4th switch SW4
It is coupled to fourth node N4.5th switch SW5 includes control terminal, first end and second end, and the control terminal of the 5th switch SW5 is used for
The 5th control signal CT5 is received, the first end of the 5th switch SW5 is coupled to fourth node N4, the second end coupling of the 5th switch SW5
It is connected to the 5th node N5.6th switch SW6 includes control terminal, first end and second end, and the control terminal of the 6th switch SW6 is for connecing
The first end of the 6th control signal CT6, the 6th switch SW6 is received for receiving first voltage signal OVDD.Second driving transistor
310 include control terminal, first end and second end, and the control terminal of the second driving transistor 310 is coupled to fourth node N4, and second drives
The first end of dynamic transistor 310 is coupled to the second end of the 6th switch SW6, and the second end of the second driving transistor 310 is coupled to
5th node N5.The first end of third capacitor C3 is for receiving first voltage signal OVDD, the second end of third capacitor C3 then coupling
It is connected to fourth node N4.
In addition, multiplexing circuitry 110 includes the first multitask switch M1 and the second multitask switch M2.First multitask
Switch M1 includes control terminal, first end and second end, and the control terminal of the first multitask switch M1 is for receiving the first multitask letter
Number Sm1, the first end of the first multitask switch M1 are coupled to the second end of the second capacitor C2, and the second of the first multitask switch M1
End is for receiving first voltage signal OVDD.Second multitask switch M2 include control terminal, first end and second end, more than second
The control terminal of business switch M2 is coupled to second for receiving the second multi-task signal Sm2, the first end of the second multitask switch M2
The second end of capacitor C2, the second end of the second multitask switch M2 is for receiving common drive signal Swe.
In implementation, first switch SW1, second switch SW2, third switch SW3, the 4th switch SW4, the 5th switch SW5,
Six switch SW6, the first multitask switch M1 and the second multitask switch M2 can be with various suitable P-type transistors come real
It is existing.
Fig. 4 is the simplified timing diagram of driving signal when combined type drives display panel 100 to work in first mode.With
It is lower to further illustrate running of the combined type driving display panel 100 in first mode for Fig. 4 is arranged in pairs or groups with Fig. 3.In order to illustrate
On convenience, below will be with first node voltage V1, second node voltage V2, third node voltage V3, fourth node voltage V4
And the 5th node voltage V5 respectively represent first node N1, second node N2, third node N3, fourth node N4 and
The voltage of five node N5.
As shown in figure 4, first control signal CT1, second control signal CT2, third control signal CT3, the 4th control letter
Number CT4, the 5th control signal CT5 and the 6th control signal CT6 in the first enable current potential LE1 and the first forbidden energy current potential LD1 it
Between switch, second voltage signal OVSS switches between the second enable current potential LE2 and the second forbidden energy current potential LD2, first voltage letter
Number OVDD and the first reference voltage Vref 1 then have fixed voltage potential.In addition, when driving display panel 100 works in the
When one mode, the first multitask switch M1 can be turned off and the second multitask switch M2 can be connected, and common drive signal Swe is passed
It is handed to the second capacitor C2.
In reset phase T1, first control signal CT1, second control signal CT2, third control signal CT3 and the 4th
Controlling signal CT4, there is the first enable current potential LE1, the 5th control signal CT5 and the 6th control signal CT6 to have the first forbidden energy electricity
Position LD1, and second voltage signal OVSS has the second forbidden energy current potential LD2.In addition, data-signal Sdata has the first reference electricity
LS1, common drive signal Swe then have the second reference potential LS2 for position.Therefore, first switch SW1, second switch SW2, third
Switch SW3 and the 4th switch SW4 can be connected, and the 5th switch SW5, the 6th switch SW6 and luminescence unit 250 can turn off.
In the case, pixel circuit 120 can be equivalent to equivalent circuit shown in fig. 5.As shown in figure 5, first node is electric
Pressure V1 and fourth node voltage V4 can be configured to close to the first reference voltage Vref 1.Data-signal Sdata can be passed to
Third node N3, and common drive signal Swe can be passed to the second end of the second capacitor C2.In reset phase T1, data
Signal Sdata and common drive signal Swe is direct current signal, so data-signal Sdata and common drive signal Swe can distinguish
It is isolated by first capacitor C1 and the second capacitor C2, without being transferred to first node N1.
In compensated stage T2, first control signal CT1, second control signal CT2 and the 5th control signal CT5 have the
One enable current potential LE1, third, which controls signal CT3, the 4th control signal CT4 and the 6th control signal CT6, has the first forbidden energy
Current potential LD1, and second voltage signal OVSS has the second forbidden energy current potential LD2.In addition, data-signal Sdata is maintained at the first ginseng
Current potential LS1 is examined, common drive signal Swe is maintained at the second reference potential LS2.Therefore, first switch SW1 and second switch SW2
It can be connected, and third switch SW3, the 4th switch SW4,250 meeting of the 5th switch SW5 and the 6th switch SW6 and luminescence unit
Shutdown.
In the case, pixel circuit 120 can be equivalent to equivalent circuit shown in fig. 6.As shown in fig. 6, first voltage is believed
Number OVDD can charge to first node N1 through the first driving transistor 210, until first node voltage V1 has as following " public
Formula 1 " shown in voltage potential:
V1=OVDD- | Vth1 | " formula 1 "
Wherein, Vth1 indicates the critical voltage of the first driving transistor 210.
In write phase T3, first control signal CT1 the first enable current potential first can be switched to from the first forbidden energy current potential LD1
LE1, and the first enable current potential LE1 is maintained in a preset time T p, then first is switched back into from the first enable current potential LE1 again
Forbidden energy current potential LD1.Second control signal CT2, third control signal CT3, the 4th control signal CT4, the 5th control signal CT5 with
And the 6th control signal CT6 have the first forbidden energy current potential LD1, and second voltage signal OVSS have the second forbidden energy current potential LD2.This
When, common drive signal Swe is maintained at the second reference potential LS2, and data-signal Sdata is then cut between multiple voltage potentials
It changes, and multiple voltage potential is higher than the first reference potential LS1.Therefore, first switch SW1 can be connected, and pixel circuit 120
Rest switch and luminescence unit 250 can then turn off.
In the case, pixel circuit 120 can be equivalent to equivalent circuit shown in Fig. 7.Data-signal Sdata can be transferred to
Third node N3, so that the first reference potential LS1 stored by third node voltage V3 self compensation stage T2 starts to change.Third
The variable quantity (also that is, alternating component of data-signal Sdata) of node voltage V3 can be further transferred to via first capacitor C1
First node N1.Therefore, first node voltage V1 can have the voltage potential as shown in following " formula 2 ":
V1=OVDD- | Vth1 |+LG-LS1 " formula 2 "
Wherein, LG is indicated when pixel circuit 120 enters write phase T3 and first switch SW1 is connected, data-signal
Specific voltage current potential possessed by Sdata.This specific voltage current potential is for determining the first driving transistor 210 in next stage
Turn-on time in running.
In light emitting phase T4, first control signal CT1, second control signal CT2, third control signal CT3 and the
There is five control signal CT5 the first forbidden energy current potential LD1, the 4th control signal CT4 and the 6th control signal CT6 to have the first enable
Current potential LE1.Common drive signal Swe then has the ramp pulse being gradually reduced.Therefore, in this stage, the 4th switch SW4 and
6th switch SW6 can maintain to be connected, and the first driving transistor 210 and the second driving transistor 310 then can alternate conduction and passes
It is disconnected.When Fig. 8 especially depicts first node voltage V1, common drive signal Swe and the first driving current Idr1 simplified
Sequence figure.As shown in figure 8, light emitting phase T4 includes the first sub-stage P1 and the second sub-stage.
It is begun to decline in the first sub-stage P1, common drive signal Swe from the second reference potential LS2, and common driving letter
The alternating component of number Swe can be further transferred to first node N1 through the second capacitor C2, so that first node voltage V1 is also opened
Begin to decline.In this stage, first node voltage V1 is greater than voltage potential shown in above-mentioned " formula 1 ", so the first driving is brilliant
Body pipe 210 can turn off.On the other hand, second driving transistor 310 can be connected so that pixel circuit 120 be equivalent to it is shown in Fig. 9
Equivalent circuit.
Since fourth node voltage V4 is equal to the first reference voltage Vref 1, the second driving transistor 310 is in the first sub-stage
The first driving current Idr1 of the size as shown in following " formula 3 " can be generated in P1:
Wherein, Vth2 indicates the critical voltage of the second driving transistor 31O.K2 represents the load of the second driving transistor 310
Transport factor (carrier mobility), grid oxic horizon specific capacitance size with the product with gate pole breadth length ratio three.
Since first voltage signal OVDD and the first reference voltage Vref 1 have fixed voltage potential, so by " formula 3 " it is found that the
One driving current Idr1 has fixed size.
It is continued to decline in the second sub-stage P2, common drive signal Swe, deteriorates to less than first node voltage V1 " public
Formula 1 " shown in voltage potential.Therefore, the first driving meeting switching-on state of automatic shutoff state of transistor 210, so that first
Voltage signal OVDD is transferred to fourth node N4 via the first driving transistor 210 and the 4th switch SW4.In this way, the 4th
Node voltage V4 can be equal to the voltage potential of first voltage signal OVDD, so that the second driving transistor 310 is cut from state
Shift to off state.In the case, pixel circuit 120 can be equivalent to equivalent circuit shown in Fig. 10.
If the ramp pulse of common drive signal Swe has fixed descending slope, the time of the first sub-stage P1 is long
Degree, can be positively correlated with first node voltage V1 in the voltage potential of write phase T3 (also that is, voltage shown in " formula 2 " is electric
Position).On the other hand, the time span of the second sub-stage P2, then can negative about first node voltage V1 in write phase T3
Voltage potential.
It can be seen from the above, pixel circuit 120 is got in the voltage potential of the write phase T3 data-signal Sdata received
Height, then pixel circuit 120 can be longer in the fluorescent lifetime of light emitting phase T4.Also that is, when combined type driving display panel 100 works
When first mode, multiple pixel circuits 120 can be shone with asynchronous, and light emission luminance having the same.By adjustment pixel
Circuit 120 can allow user to experience the brightness of different grayscale in the fluorescent lifetime of light emitting phase T4.
Figure 11 is the simplified timing diagram of driving signal when combined type drives display panel 100 to work in second mode.
As shown in Figure 10, first control signal CT1, second control signal CT2, third control signal CT3, first voltage signal OVDD with
And waveform of the second voltage signal OVSS in second mode, it is similar to its waveform in the first mode, for brevity,
This does not repeat to repeat.In addition, when drive display panel 100 work in second mode when, the first multitask switch M1 can be connected and
Second multitask switch M2 can be turned off, and first voltage signal OVDD is transferred to the second capacitor C2.
In reset phase T1, the 4th control signal CT4 and the 5th control signal CT5 is with the first enable current potential LE1, and the 6th
Controlling signal CT6 has the first forbidden energy current potential LD1.In addition, data-signal Sdata has the first reference potential LS1.Therefore,
One switch SW1, second switch SW2, third switch SW3, the 4th switch SW4 and the 5th switch SW5 can be connected, and the 6th switch
SW6 and luminescence unit 250 can turn off.
In the case, pixel circuit 120 can be equivalent to equivalent circuit shown in Figure 12.As shown in figure 12, first node
Voltage V1, fourth node voltage V4 and the 5th node voltage V5 can be configured to close to the first reference voltage Vref 1.Data letter
Number Sdata can be passed to third node N3, and first voltage signal OVDD can be passed to the second end of the second capacitor C2.By
In data-signal Sdata in reset phase T1 be direct current signal, so data-signal Sdata can be isolated by first capacitor C1,
Without being transferred to first node N1.
There is the first enable current potential LE1, the 4th control signal CT4 and the 6th in compensated stage T2, the 5th control signal CT2
Controlling signal CT6 has the first forbidden energy current potential LD1.In addition, data-signal Sdata is maintained at the first reference potential LS1.Therefore,
First switch SW1, second switch SW2 and the 5th switch SW5 can be connected, and third switch SW3, the 4th switch SW4, the 6th open
Closing SW6 and luminescence unit 250 can turn off.
In the case, pixel circuit 120 can be equivalent to equivalent circuit shown in Figure 13.As shown in figure 13, first voltage
Signal OVDD can charge to first node N1 through the first driving transistor 210, until first node voltage V1 has " formula 1 "
Shown in voltage potential.
There is the first enable current potential LE1, the 4th control signal CT4 and the 6th in write phase T3, the 5th control signal CT5
Controlling signal CT6 has the first forbidden energy current potential LD1.Data-signal Sdata can switch between multiple voltage potentials, and multiple
Voltage potential is lower than the first reference potential LS1.Therefore, first switch SW1 and the 5th switch SW5 can be connected, and pixel circuit 120
Rest switch can turn off.
In this case, pixel circuit 120 can be equivalent to equivalent circuit shown in Figure 14.As shown in figure 14, data-signal
Sdata can be transferred to third node N3, so that the first reference potential LS1 stored by third node voltage V3 self compensation stage T2
Start to change.The variable quantity (also that is, alternating component of data-signal Sdata) of third node voltage V3 can be via first capacitor C1
It is further transferred to first node N1.Therefore, first node voltage V1 can have the voltage potential as shown in following " formula 4 ":
V1=OVDD- | Vth1 |+LA-LS1 " formula 4 "
Wherein, LA is indicated when pixel circuit 120 enters write phase T3 and first switch SW1 is connected, data-signal
Specific voltage current potential possessed by Sdata.This specific voltage current potential is for determining the first driving transistor 210 in next fortune
In work, the size of generated first driving current Idr1, and when being not used in the conducting for determining the first driving transistor 210
Between.
It is worth noting that, in the reset phase T1 and compensated stage T2 of Figure 11, multiple first control signal CT1 [1]~
CT1 [n] is all in the first enable current potential LE1.In write phase T3, multiple first control signal CT1 [1]~CT1 [n] then can be according to
Sequence switches to the first enable current potential LE1 by the first forbidden energy current potential LD1, and the first enable current potential is maintained in preset time T p
Then LE1 just switches to the first forbidden energy current potential LD1 by the first enable current potential LE1.In other words, combined type drives display panel 100
Multiple pixel circuits 120 can first compensate the critical voltage variation of respective first driving transistor 210, then received in sequence simultaneously
Data-signal Sdata with specific voltage current potential.Come in this way, which each pixel circuit 120 can obtain the sufficient time
The critical voltage variation of compensation the first driving transistor 210.
In light emitting phase T4, the 4th control signal CT4 and the 5th control signal CT5 is with the first enable current potential LE1, and the 6th
Controlling signal CT6 has the first forbidden energy current potential LD1.Therefore, the 4th switch SW4 and the 5th switch SW5 can be connected, pixel circuit
120 rest switch can turn off.
In this case, pixel circuit 120 can be equivalent to equivalent circuit shown in figure 15.As shown in figure 15, the first driving is brilliant
Body pipe 210 can generate the second driving current Idr2 according to first node voltage V1, and the second driving current Idr2 can be to Section four
Point N4 charging, so that the second driving transistor 310 turns off.The size of second driving current Idr2 can be by " formula 5 " table below
Show:
Wherein, k1 represents carrier transport factor (carrier mobility), the grid oxic horizon of the first driving transistor 210
Specific capacitance size first capacitor C1 and the second capacitor C2 are respectively represented with the product with gate pole breadth length ratio three, Cp1 and Cp2
Capacitance.
By " formula 5 " it is found that the size of the second driving current Idr2 will not be because of the critical electricity of the first driving transistor 210
Buckling is different and changes.By the size of adjustment driving current Idr2, user can be allowed to experience the brightness of different grayscale.Also
That is, when combined type driving display panel 100 works in second mode, the multiple meeting of pixel circuits 120 synchronous light-emittings, and can have
There is different light emission luminance.
In a certain embodiment, first switch SW1 above-mentioned, second switch SW2, third switch SW3, the 4th switch SW4,
One or more of 5th switch SW5, the 6th switch SW6, the first multitask switch M1 and second multitask switch M2 are to use N
Transistor npn npn is realized.In the case, first control signal CT1, second control signal CT2, third control signal CT3, the
Four control signal CT4, the 5th control signal CT5, the 6th control signal CT6, the first multitask control more than signal Sm1 and second
Corresponding one or more can use and the waveform of the corresponding signal inversion of Fig. 4 in task control signal Sm2.
Figure 16 is circuit diagram of the pixel circuit 120 of Fig. 2 in another embodiment.120 phase of pixel circuit of Figure 16
It is similar to the pixel circuit 120 of Fig. 3.Difference is that the emission control circuit 240 of the pixel circuit 120 of Figure 16 additionally comprises the 7th and opens
Close SW7.7th switch SW7 includes control terminal, first end and second end, and the control terminal of the 7th switch SW7 is for receiving the 7th control
The first end of signal CT7 processed, the 7th switch SW7 are coupled to the second end of the 6th switch SW6, and the second end of the 7th switch SW7 is used
In the second reference voltage Vref 2 of reception.In the present embodiment, the second reference voltage Vref 2 has fixed voltage potential.
Figure 17 is that combined type drives display panel 100 using the pixel circuit 120 of Figure 16 and when working in first mode
The simplified timing diagram of driving signal.As shown in figure 17, the control signal of the first mode of the present embodiment, is similar to earlier figures 4
The control signal of depicted first mode.Difference is that the 7th control signal CT7 of the present embodiment and the 5th controls signal
The waveform of CT5 is identical.Therefore, the 7th switch SW7 can be in the reset phase T1, write phase T3 and light emitting phase T4 of first mode
Shutdown, and can be connected in compensated stage T2.
In compensated stage T2, the second reference voltage Vref 2 can be right through the driving transistor 310 of the 7th switch SW7 and second
Fourth node N4 charging, until fourth node voltage V4 has the voltage potential as shown in " formula 6 " below:
V4=Vref2- | Vth2 | " formula 6 "
Therefore, in light emitting phase T4, the size of the first driving current Idr1 that the second driving transistor 310 generates can be by
" formula 7 " below indicates:
By " formula 7 " it is found that the size of the first driving current Idr1 will not be because of the critical electricity of the second driving transistor 310
Buckling is different and changes.
Figure 18 is that combined type drives display panel 100 using the pixel circuit 120 of Figure 16 and when working in second mode
The simplified timing diagram of driving signal.As shown in figure 18, the control signal of the second mode of the present embodiment, is similar to earlier figures 11
The control signal of depicted second mode.Difference is that the 7th control signal CT7 of the present embodiment and the 6th controls signal
The waveform of CT6 is identical.Therefore, the 7th switch SW7 in second mode reset phase T1, compensated stage T2, write phase T3 with
And light emitting phase T4 can be turned off.
It can be seen from the above, the pixel circuit 120 of Figure 16 can compensate for the first driving transistor 210 and the second driving transistor
310 critical voltage variation.Therefore, display panel 100 is driven using the combined type of the pixel circuit of Figure 16 120, in the first mould
The display picture of high quality can be all provided in formula and second mode.Remaining connection type, the group of the pixel circuit 120 of earlier figures 3
Part, embodiment and advantage all do not repeat to repeat herein for brevity suitable for the pixel circuit 120 of Figure 16.
In a certain embodiment, the second end of the 7th switch SW7 does not receive the second reference voltage Vref 2, but is used for
Additional data-signal is received, with the size of the first driving current of modulation Idr1 in first mode.In this way, which combined type is driven
Dynamic display panel 100 can have bigger elasticity when controlling the brightness and color that it shows picture.
In conclusion low-light diode can be overcome as hair when combined type driving display panel 100 works in first mode
The colour cast problem of light unit.On the other hand, it when combined type driving display panel 100 works in second mode, can drive with organic
Pixel circuit of the light emitting diode as luminescence unit, or driving are made of more advanced processing procedure without there is colour cast problem
Pixel circuit of micro- light emitting diode as luminescence unit.Therefore, combined type driving display panel 100 has high using bullet
Property.
Some vocabulary is used in specification and claims to censure specific component.However, affiliated technology neck
Has usually intellectual in domain, it is to be appreciated that same component may be called with different nouns.Specification and right are wanted
It asks book not in such a way that the difference of title is as component is distinguished, but carrys out the base as differentiation with the difference of component functionally
It is quasi-."comprising" mentioned by specification and claims is open term, therefore should be construed to " include but do not limit
In ".In addition, " coupling " is herein comprising any direct and indirect connection means.Therefore, if it is described herein that first assembly is coupled to
Second component, then represent first assembly can by being electrically connected or being wirelessly transferred, it is direct and the signals connection type such as optical delivery
Ground is connected to the second component, or electrical property or signal are connected to second component indirectly by other assemblies or connection means.
In addition, unless specified in the instructions, otherwise the term of any singular lattice all includes the connotation of multiple grid simultaneously.
Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention, ripe
It knows those skilled in the art and makes various corresponding changes and modifications, but these corresponding changes and change in accordance with the present invention
Shape all should fall within the scope of protection of the appended claims of the present invention.
Claims (14)
1. a kind of combined type driving display panel, characterized by comprising:
One multiplexing circuitry, for exporting the one of them of a first voltage signal and a common drive signal；
Multiple row pixel circuit is coupled to the multiplexing circuitry, and for accordingly receiving multiple first control signals, the multiple row picture
Each pixel circuit of plain circuit includes:
One write circuit is coupled to a first node and the multiplexing circuitry, for a data-signal to be sent to the first segment
Point；
One first driving transistor includes a control terminal, a first end and a second end, the control of the first driving transistor
End is coupled to a first node, and the first end of the first driving transistor is for receiving the first voltage signal, first drive
The second end of dynamic transistor is coupled to a second node；
One luminescence unit；And
One emission control circuit is coupled between the second node and the luminescence unit, for receiving the first voltage signal；
Wherein, which provides one first driving current to the luminescence unit according to the first voltage signal, this
One driving transistor provides one second driving current to the luminescence unit according to the data-signal.
2. the combined type as claimed in claim 1 drives display panel, which is characterized in that wherein, shown when the combined type drives
When panel works in a first mode, which disconnects the second node and the luminescence unit, and provide this first
Driving current to the luminescence unit,
Wherein, when combined type driving display panel works in a second mode, which is connected second section
Point and the luminescence unit, so that the luminescence unit receives second driving current.
3. combined type as described in claim 1 drives display panel, which is characterized in that wherein, when the write circuit receives
The common drive signal have a ramp pulse when, which is sent to the first node for the common drive signal.
4. combined type as described in claim 1 drives display panel, which is characterized in that additionally comprise a compensation circuit, be coupled to
The first node and the second node, for setting negative about first drive for a first node voltage of the first node
The absolute value of one critical voltage of dynamic transistor.
5. combined type as claimed in claim 4 drives display panel, which is characterized in that wherein, which includes:
One first capacitor includes a first end and a second end, and the first end of the first capacitor is coupled to the first node, should
The second end of first capacitor is coupled to a third node；
One second capacitor includes a first end and a second end, and the first end of second capacitor is coupled to the first node, should
The second end of second capacitor is coupled to the multiplexing circuitry；And
One first switch includes a control terminal, a first end and a second end, and the control terminal of the first switch is for receiving this
A first control signal in multiple first control signals, the first end of the first switch are coupled to the third node, this
The second end of one switch is for receiving the data-signal.
6. combined type as claimed in claim 5 drives display panel, which is characterized in that wherein, which includes:
One second switch includes a control terminal, a first end and a second end, and the control terminal of the second switch is for receiving one
Second control signal, the first end of the second switch are coupled to the second node, and the second end of the second switch is coupled to
The first node；And
One third switch includes a control terminal, a first end and a second end, and the control terminal of third switch is for receiving one
Third controls signal, and the first end of third switch is for receiving one first reference voltage, the second end of third switch
It is coupled to the second node.
7. combined type as claimed in claim 6 drives display panel, which is characterized in that wherein, the first control signal, this
Two control signals and third control signal switch between one first enable current potential and one first forbidden energy current potential, second electricity
Pressure signal switches between one second enable current potential and one second forbidden energy current potential,
Wherein, in a reset phase, the first control signal, the second control signal and third control signal have should
First enable current potential, and the second voltage signal has the second forbidden energy current potential,
In a compensated stage, the first control signal, the second control signal have the first enable current potential, third control
Signal has the first forbidden energy current potential, and the second voltage signal has the second forbidden energy current potential,
In a write phase, which switches to the first enable current potential from the first forbidden energy current potential, and in one
It is maintained at the first enable current potential in preset time, then switches to the first forbidden energy current potential from the first enable current potential again, it should
Second control signal and third control signal have the first forbidden energy current potential, and the second voltage signal has second forbidden energy
Current potential,
In a light emitting phase, the first control signal, the second control signal and the third control signal have this first
Forbidden energy current potential, and the second voltage signal has the second enable current potential.
8. combined type as claimed in claim 5 drives display panel, which is characterized in that wherein, which includes:
One first multitask switch includes a control terminal, a first end and a second end, the control of first multitask switch
End for receiving first multi-task signal, first multitask switch the first end be coupled to second capacitor this second
End, the second end of first multitask switch is for receiving the first voltage signal；And
One second multitask switch includes a control terminal, a first end and a second end, the control of second multitask switch
End for receiving second multi-task signal, second multitask switch the first end be coupled to second capacitor this second
End, the second end of second multitask switch is for receiving the first voltage signal.
9. combined type as claimed in claim 4 drives display panel, which is characterized in that wherein, which includes:
One the 4th switch includes a control terminal, a first end and a second end, and the control terminal of the 4th switch is for receiving one
4th control signal, the first end of the 4th switch are coupled to the second node, and the second end of the 4th switch is coupled to
One fourth node；
One the 5th switch includes a control terminal, a first end and a second end, and the control terminal of the 5th switch is for receiving one
5th control signal, the first end of the 5th switch are coupled to the fourth node, and the second end of the 5th switch is coupled to
One the 5th node；
One the 6th switch includes a control terminal, a first end and a second end, and the control terminal of the 6th switch is for receiving one
6th control signal, the first end of the 6th switch is for receiving the first voltage signal；
One second driving transistor includes a control terminal, a first end and a second end, the control of the second driving transistor
End is coupled to the fourth node, and the first end of the second driving transistor is coupled to the second end of the 6th switch, this
The second end of two driving transistors is coupled to the 5th node；And
One third capacitor includes a first end and a second end, and the first end of the third capacitor is for receiving the first voltage
The second end of signal, the third capacitor is coupled to the fourth node.
10. combined type as claimed in claim 9 drives display panel, which is characterized in that wherein, the 4th control signal is somebody's turn to do
5th control signal and the 6th control signal switch between one first enable current potential and one first forbidden energy current potential, this second
Voltage signal switches between one second enable current potential and one second forbidden energy current potential,
Wherein, when combined type driving display panel works in a first mode, in a reset phase, the 4th control letter
Number there is the first enable current potential, the 5th control signal and the 6th control signal have the first forbidden energy current potential, and this
Two voltage signals have the second forbidden energy current potential,
In a compensated stage, the 5th control signal has the first enable current potential, the 4th control signal and the 6th control
Signal processed has the first forbidden energy current potential, and the second voltage signal has the second forbidden energy current potential,
In a write phase, the 4th control signal, the 5th control signal and the 6th control signal have this first
Forbidden energy current potential, and the second voltage signal has the second forbidden energy current potential,
In a light emitting phase, the 4th control signal has the first enable current potential, the 5th control with the 6th control signal
Signal processed has the first forbidden energy current potential, and the second voltage signal has the second enable current potential.
11. combined type as claimed in claim 10 drives display panel, which is characterized in that wherein, when combined type driving is aobvious
When showing that panel works in the first mode, in the reset phase, the compensated stage and the write phase, the common driving letter
Number there is a fixed voltage potential, and in the light emitting phase, which has a ramp pulse.
12. combined type as claimed in claim 10 drives display panel, which is characterized in that wherein, when combined type driving is aobvious
When showing that panel works in a second mode, in the reset phase, the 4th control signal has with the 5th control signal should
First enable current potential, the 6th control signal has the first forbidden energy current potential, and the second voltage signal has second forbidden energy
Current potential,
In the compensated stage, the 5th control signal has the first enable current potential, the 4th control signal and the 6th control
Signal processed has the first forbidden energy current potential, and the second voltage signal has the second forbidden energy current potential,
In the write phase, the 5th control signal has the first enable current potential, the 4th control signal and the 6th control
Signal processed has the first forbidden energy current potential, and the second voltage signal has the second forbidden energy current potential,
In the light emitting phase, the 4th control signal has the first enable current potential, the 6th control with the 5th control signal
Signal processed has the first forbidden energy current potential, and the second voltage signal has the second enable current potential.
13. combined type as claimed in claim 12 drives display panel, which is characterized in that wherein, the emission control circuit is another
Include:
One the 7th switch includes a control terminal, a first end and a second end, and the control terminal of the 7th switch is for receiving one
7th control signal, the first end of the 7th switch are coupled to the second end of the 6th switch, the 7th switch this
Two ends are for receiving one second reference voltage.
14. combined type as claimed in claim 13 drives display panel, which is characterized in that wherein, when combined type driving is aobvious
When showing that panel works in the first mode, the 7th control signal is identical as the 5th control waveform of signal, when the combined type
When driving display panel works in the second mode, the 7th control signal is identical as the 6th control waveform of signal.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| US201862659662P | 2018-04-18 | 2018-04-18 | |
| US62/659,662 | 2018-04-18 | ||
| TW107138671A TWI678690B (en) | 2018-04-18 | 2018-10-31 | Hybrid driving display panel |
| TW107138671 | 2018-10-31 |
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| CN110033730A true CN110033730A (en) | 2019-07-19 |
| CN110033730B CN110033730B (en) | 2020-08-04 |
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