CN110033731A - Combined type drives display panel - Google Patents
Combined type drives display panel Download PDFInfo
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- CN110033731A CN110033731A CN201910242136.6A CN201910242136A CN110033731A CN 110033731 A CN110033731 A CN 110033731A CN 201910242136 A CN201910242136 A CN 201910242136A CN 110033731 A CN110033731 A CN 110033731A
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- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- 230000003287 optical effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
Abstract
A kind of combined type driving display panel includes multiplexing circuitry and multiple row pixel circuit.Multiplexing circuitry is used for the one of them of output system high voltage and common drive signal.Multiple row pixel circuit is coupled to multiplexing circuitry, and for receiving multiple first control signals.A wherein pixel circuit for multiple row pixel circuit includes driving transistor, write circuit and luminescence unit.The control terminal of driving transistor is coupled to first node, and for first end for receiving system high voltage, second end is coupled to second node.Write circuit is coupled to first node and multiplexing circuitry, and data-signal is sent to first node by the wherein first control signal for according to multiple first control signals.The first end of luminescence unit is coupled to second node, and second end is for receiving LED control signal.When the common drive signal that write circuit receives has triangular pulse or ramp pulse, common drive signal is sent to first node by write circuit.
Description
Technical field
The present invention drives display panel in relation to a kind of display panel, the combined type of espespecially a kind of changeable operating mode.
Background technique
Compared to liquid crystal display, micro- light emitting diode (micro LED) display has low power consumption, high color full
The advantages that with degree and high reaction speed, so that micro- light emitting diode indicator is considered as the hot topic of next-generation main flow display product
One of technology.Traditional micro- light emitting diode indicator is supplied to the electric current of pixel circuit by adjustment, to control pixel circuit
In micro- light emitting diode generate light brightness.However, being limited to current process technique, the micro- light emitting diode of green is produced
The wavelength of raw light can be inversely proportional to the electric current for flowing through the micro- light emitting diode of green.Therefore, when traditional micro- light emitting diode is aobvious
When showing that the green pixel circuit in device is intended to show different gray-scale intensities, the problem of green colour cast (color shift) can be faced.
Summary of the invention
The present invention provides a kind of combined type driving display panel.It includes multiplexing circuitry and more that combined type, which drives display panel,
Column pixel circuit.Multiplexing circuitry is used for according to the first multi-task signal and the second multi-task signal, output system high voltage and
The one of them of common drive signal.Multiple row pixel circuit is coupled to multiplexing circuitry, and for accordingly receiving multiple first
Control signal.A wherein pixel circuit for multiple row pixel circuit includes driving transistor, write circuit and luminescence unit.Driving is brilliant
Body pipe includes control terminal, first end and second end, and the control terminal of transistor is driven to be coupled to first node, drives the of transistor
One end drives the second end of transistor to be coupled to second node for receiving system high voltage.Write circuit is coupled to first segment
Point and multiplexing circuitry, and data-signal is sent to by the wherein first control signal for according to multiple first control signals
First node.Luminescence unit includes first end and second end, and the first end of luminescence unit is coupled to second node, luminescence unit
Second end is for receiving LED control signal.When the common drive signal that write circuit receives has triangular pulse or slope
When pulse, common drive signal is sent to first node by write circuit.
Above-mentioned combined type driving display panel can overcome the problems, such as colour cast of micro- light emitting diode as luminescence unit.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Detailed description of the invention
Fig. 1 is to drive the simplified functional block diagram of display panel according to the combined type of one embodiment of the invention.
Fig. 2 is the schematic diagram according to the pixel circuit of first embodiment of the invention.
Fig. 3 is that combined type drives display panel to simplify when working in first mode according to multiple driving signals of an embodiment
Timing diagram afterwards.
The pixel circuit that Fig. 4 is Fig. 2 is in the equivalent circuit operation chart of the reset phase of first mode.
The pixel circuit that Fig. 5 is Fig. 2 is in the equivalent circuit operation chart of the compensated stage of first mode.
The pixel circuit that Fig. 6 is Fig. 2 is in the equivalent circuit operation chart of the write phase of first mode.
The pixel circuit that Fig. 7 is Fig. 2 is in the equivalent circuit operation chart of the light emitting phase of first mode.
Fig. 8 is simplified for first node voltage in the first mode of an embodiment according to the present invention and common drive signal
Timing diagram.
After Fig. 9 simplifies for first node voltage in the first mode of another embodiment according to the present invention with common drive signal
Timing diagram.
Figure 10 is that combined type drives display panel when working in second mode according to multiple driving signals letter of an embodiment
Timing diagram after change.
The pixel circuit that Figure 11 is Fig. 2 is in the equivalent circuit operation chart of the light emitting phase of second mode.
Figure 12 is the schematic diagram according to the pixel circuit of second embodiment of the invention.
Figure 13 is the schematic diagram according to the pixel circuit of third embodiment of the invention.
Figure 14 is the schematic diagram according to the pixel circuit of fourth embodiment of the invention.
Figure 15 is the schematic diagram according to the pixel circuit of fifth embodiment of the invention.
Wherein, appended drawing reference:
100: combined type drives the LD2: the second forbidden energy of display panel current potential
102: the fixed current potential of source electrode driver LS1: the first
104: the fixed current potential of gate drivers LS2: the second
110: multiplexing circuitry Swe: common control signal
120: the Sm1: the first multi-task signal of pixel circuit
120a~120d: the Sm2: the second multi-task signal of pixel circuit
210: driving transistor Sdata: data-signal
220,220b: write circuit SW1~SW4: first switch~4th
230,230c: compensation circuit switch
240: luminescence unit T1: reset phase
CT1, CT1 [1]~CT1 [n]: first control T2: compensated stage
Signal T3: write phase
CT2: second control signal T4: light emitting phase
CT3: third controls the P1~P5: the first sub-stage of signal~the 5th son
OVDD: system high voltage stage
OVSS: LED control signal Vref: reference voltage
LE1: the first enable current potential V1: first node voltage
LD1: the first forbidden energy current potential V2: second node voltage
LE2: the second enable current potential V3: third node voltage
Specific embodiment
Structural principle and working principle of the invention are described in detail with reference to the accompanying drawing:
Illustrate the embodiment of the present invention below in conjunction with relevant drawings.In the accompanying drawings, identical label indicate it is identical or
Similar component or method flow.
Fig. 1 is to drive the simplified functional block diagram of display panel 100 according to the combined type of one embodiment of the invention.It is compound
It includes source electrode driver 102, gate drivers 104, multiplexing circuitry 110 and multiple pixels electricity that formula, which drives display panel 100,
Road 120.Multiple pixel circuits 120 are coupled to multiplexing circuitry 110, and are arranged in multiple row.It is arranged in the pixel circuit 120 of multiple row
For accordingly receiving multiple first control signal CT1 [1]~CT1 [n] from gate drivers 104.Multiplexing circuitry 110 is used for
Selectively the one of them of output system high voltage OVDD and common drive signal Swe are to multiple row pixel circuit 120.By making
With first control signal CT1 [1]~CT1 [n], system high voltage OVDD and common drive signal Swe, combined type driving display
Panel 100 can operate at first mode and second mode, to adapt to the characteristics of luminescence of different types of pixel circuit 120.
To make simplified form and ease of explanation, the other assemblies in combined type driving display panel 100 are not illustrated in connection relationship
In Fig. 1.
Index [1]~[n] in component numerals used in this case the description and the appended drawings and signal number, the side of being intended merely to
Just an other component and signal are censured, is not intended that the quantity by aforementioned components and signal is confined to given number.It is said in this case
In bright book and attached drawing, if not indicating the rope of the component numerals or signal number when using a certain component numerals or signal number
Draw, then represent the component numerals or signal number be censure belonging in component group or signal group not specific any component or
Signal.For example, the object that signal number CT1 [1] is censured is [1] first control signal CT1, and pair that signal number CT1 is censured
As being then not specific any first control signal CT1 in first control signal CT1 [1]~CT1 [n].
Fig. 2 is the schematic diagram according to the pixel circuit 120 of first embodiment of the invention.As shown in Fig. 2, pixel circuit 120
Include driving transistor 210, write circuit 220, compensation circuit 230 and luminescence unit 240.Driving transistor 210 includes control
End processed, first end and second end, the control terminal of driving transistor 210 are coupled to first node N1, and the first of driving transistor 210
End is coupled to second node N2 for receiving system high voltage OVDD, the second end of driving transistor 210.
Write circuit 220 is coupled to first node N1 and multiplexing circuitry 110, and for according to first control signal CT1
Data-signal Sdata is sent to first node N1.Compensation circuit 230 is coupled to first node N1 and second node N2, uses
In by the voltage of first node N1 be set as negative about driving transistor 210 critical voltage absolute value.Luminescence unit 240
Comprising first end (for example, anode tap) and second end (for example, cathode terminal), the first end of luminescence unit 240 is coupled to the second section
Point N2, the second end of luminescence unit 240 is for receiving LED control signal OVSS.
Multiplexing circuitry 120 is for receiving the first multi-task signal Sm1 and the second multi-task signal Sm2, and foundation first
Multi-task signal Sm1 and the second multi-task signal Sm2 switching output system high voltage OVDD and common drive signal Swe is wherein
One is to write circuit 220.It is worth noting that, common drive signal Swe in certain periods have fixed voltage,
Then there is triangular pulse in the other period.When the common drive signal Swe that write circuit 220 receives has triangle
When pulse, common drive signal Swe can be sent to first node N1 by write circuit 220, to control shining for luminescence unit 240
Time.
Specifically, write circuit 220 includes first capacitor C1, the second capacitor C2 and first switch SW1.First capacitor C1
Comprising first end and second end, the first end of first capacitor C1 is coupled to first node N1, the second end coupling of first capacitor C1
In third node N3.Second capacitor C2 includes first end and second end, and the first end of the second capacitor C2 is coupled to first node N1,
The second end of second capacitor C2 is coupled to multiplexing circuitry 110.First switch SW1 includes control terminal, first end and second end, the
For the control terminal of one switch SW1 for receiving first control signal CT1, the first end of first switch SW1 is coupled to third node N3,
The second end of first switch SW1 is used to receive data-signal Sdata from source electrode driver 102.
Compensation circuit 230 includes second switch SW2 and third switch SW3.Second switch SW2 includes control terminal, first end
And second end, the control terminal of second switch SW2 are used to receive second control signal CT2, second switch from gate drivers 104
The first end of SW2 is coupled to second node N2, and the second end of second switch SW2 is coupled to first node N1.Third switch SW3 packet
Containing control terminal, first end and second end, the control terminal of third switch SW3 is used to receive third control letter from gate drivers 104
For the first end of number CT3, third switch SW3 for receiving reference voltage Vref, the second end of third switch SW3 is coupled to the second section
Point N2.
In addition, multiplexing circuitry 110 includes the first multitask switch M1 and the second multitask switch M2.First multitask
Switch M1 includes control terminal, first end and second end, and the control terminal of the first multitask switch M1 is for receiving the first multitask letter
Number Sm1, the first end of the first multitask switch M1 are coupled to the second end of the second capacitor C2, and the second of the first multitask switch M1
End is for receiving system high voltage OVDD.Second multitask switch M2 includes control terminal, first end and second end, the second multitask
The control terminal of switch M2 is coupled to the second electricity for receiving the second multi-task signal Sm2, the first end of the second multitask switch M2
Hold the second end of C2, the second end of the second multitask switch M2 is for receiving common drive signal Swe.
In implementation, first switch SW1, second switch SW2, third switch SW3, the first multitask switch M1, more than second
Business switch M2 and driving transistor 210 can be realized with various suitable P-type transistors.
In addition, luminescence unit 240 can with Organic Light Emitting Diode (organic light-emitting diode) or
It is micro- light emitting diode (micro light-emitting diode) Lai Shixian.In one embodiment, luminescence unit 240 be with
Micro- light emitting diode is realized, and combined type driving display panel 100 works in first mode.In another embodiment, it shines single
Member 240 is to be realized with Organic Light Emitting Diode, and combined type driving display panel 100 works in second mode.In order to illustrate upper
Convenience, will be come below with first node voltage V1, second node voltage V2 and third node voltage V3 respectively generation claim first
The voltage of the voltage of node N1, the voltage of second node N2 and third node N3.
Fig. 3 is the simplified timing diagram of driving signal when combined type drives display panel 100 to work in first mode.With
The lower running that combined type driving display panel 100 is further illustrated Fig. 2 is arranged in pairs or groups with Fig. 3.As shown in figure 3, the first control letter
Number CT1, second control signal CT2 and third control signal CT3 can be in the first enable current potential LE1 (for example, low voltage potential)
Switch between the first forbidden energy current potential LD1 (for example, high voltage potential).LED control signal OVSS then can be in the second enable current potential
Switch between LE2 (for example, low voltage potential) and the second forbidden energy current potential LD2 (for example, high voltage potential).In addition, working as combined type
When driving display panel 100 works in first mode, the first multitask switch M1 can be turned off, and the second multitask switch M2 can be led
It is logical, so that common drive signal Swe is transferred to pixel circuit 120.
In reset phase T1, first control signal CT1, second control signal CT2 and third control signal CT3 have the
One enable current potential LE1.LED control signal OVSS has the second forbidden energy current potential LD2.Data-signal Sdata has the first fixed electricity
Position LS1, and common drive signal Swe has the second fixed current potential LS2.
Therefore, first switch SW1, second switch SW2 and third switch SW3 can be connected, and luminescence unit 240 can close
It is disconnected.Multiplexing circuitry 110 and pixel circuit 120 can be equivalent to equivalent circuit shown in Fig. 4.Data-signal Sdata can be via
First switch SW1 is transferred to third node N3.Reference voltage Vref can be transferred to via second switch SW2 and third switch SW3
First node N1.Therefore, first node voltage V1 and second node voltage V2 can be similar to reference voltage Vref, so that driving is brilliant
Body pipe 210 is connected, and third node voltage V3 can have the first fixed current potential LS1.
There is the first enable current potential LE1, third in compensated stage T2, first control signal CT1, second control signal CT2
Controlling signal CT3 has the first forbidden energy current potential LD1 (for example, high voltage potential), and LED control signal OVSS has second to prohibit
It can current potential LD2.Data-signal Sdata has been maintained at the first fixed current potential LS1, and it is solid that common drive signal Swe is then maintained at second
Determine current potential LS2.
Therefore, first switch SW1 and second switch SW2 can be connected, and third switch SW3 and luminescence unit 240 can close
It is disconnected.Multiplexing circuitry 110 and pixel circuit 120 can be equivalent to equivalent circuit shown in fig. 5.Data-signal Sdata can be via
First switch SW1 is transferred to third node N3, and third node voltage V3 is made to be maintained at the first fixed current potential LS1.System high voltage
OVDD can then be transferred to first node N1 via driving transistor 210 and second switch SW2, and charge to first node N1,
Until first node voltage V1 has the voltage potential as shown in following " formula 1 ":
V1=OVDD- | Vth | " formula 1 "
Wherein, Vth indicates the critical voltage of driving transistor 210.
The first enable current potential LE1 can be switched to from the first forbidden energy current potential LD1 in write phase T3, first control signal CT1,
And the first enable current potential LE1 is maintained in a preset time T p, then the first forbidden energy is switched back into from the first enable current potential LE1 again
Current potential LD1.Second control signal CT2 and third control signal CT3 then have the first forbidden energy current potential LD1, and LED control signal
OVSS has the second forbidden energy current potential LD2.Common drive signal Swe is maintained at the second fixed current potential LS2, and data-signal Sdata is then
Start from switching between multiple voltage potentials, and multiple voltage potential is higher than the first fixed current potential LS1.
Therefore, first switch SW1 can be connected, and second switch SW2, third switch SW3 and luminescence unit 240 can close
It is disconnected.Multiplexing circuitry 110 and pixel circuit 120 can be equivalent to equivalent circuit shown in fig. 6.Data-signal Sdata can be via
First switch SW1 is transferred to third node N3, so that third node voltage V3 changes since the first fixed current potential LS1.Third
The variable quantity (also that is, alternating component of data-signal Sdata) of node voltage V3 can be further transferred to via first capacitor C1
First node N1.In this way, which first node voltage V1 can have the voltage potential as shown in following " formula 2 ":
V1=OVDD- | Vth |+LG-LS1 " formula 2 "
Wherein, LG is indicated when pixel circuit 120 enters write phase T3 and first switch SW1 is connected, data-signal
Specific voltage current potential possessed by Sdata.This specific voltage current potential can determine driving transistor 210 in next running
Turn-on time length.
Then, signal CT3 is controlled in light emitting phase T4, first control signal CT1, second control signal CT2 and third
With the first forbidden energy current potential LD1, and LED control signal OVSS has the second enable current potential LE2.Therefore, first switch SW1,
Two switch SW2 and third switch SW3 can be turned off, and luminescence unit 240 can be connected.Multiplexing circuitry 110 and pixel circuit
120 can be equivalent to equivalent circuit shown in Fig. 7.
It is worth noting that, common drive signal Swe can have the triangle arteries and veins for falling before and rising again in light emitting phase T4
Punching.Therefore, the voltage change (also that is, alternating component of common drive signal Swe) of the second end of the second capacitor C2 can be through the
Two capacitor C2 are transferred to first node N1, so that driving transistor 210 is sequentially off, is connected and closes in light emitting phase T4
Disconnected state.
Fig. 8 is in the first mode of an embodiment according to the present invention, first node voltage V1 and common drive signal Swe is simple
Timing diagram after change.Further illustrate pixel circuit 120 in the running of light emitting phase T4 by Fig. 8 is cooperated with Fig. 7 below.Such as figure
Shown in 8, light emitting phase T4 includes the first sub-stage P1, the second sub-stage P2 and third sub-stage P3.
As previously mentioned, first node voltage V1 can have the voltage as shown in above-mentioned " formula 2 " electric in write phase T3
Position, and it is higher than voltage potential shown in " formula 1 ".Therefore, driving transistor 210 can be turned off in write phase T3.In the first son
The voltage potential of stage P1, common drive signal Swe can be gradually reduced from the second fixed current potential LS2, so that first node voltage
Voltage potential shown in V1 oneself " formula 2 " is gradually reduced, but first node voltage V1 is still higher than the electricity of voltage shown in " formula 1 "
Position.Therefore, driving transistor 210 can be in an off state in the first sub-stage P1.
In the second sub-stage P2, the voltage potential of common drive signal Swe can first continue to decline, then be gradually increasing.?
It is begun to decline in this case, first node voltage V1 understands voltage potential shown in " formula 1 " certainly, then rises to " formula 1 " again
Shown in voltage potential.Therefore, driving transistor 210 can be in the conductive state in the second sub-stage P2, and common drive signal
The voltage potential of Swe can be low enough so that driving transistor 210 works in linear zone.Therefore, in the second sub-stage P2, system is high
Voltage OVDD can be transferred to the first end of luminescence unit 240 through driving transistor 210, so that luminescence unit 240 flows through fixation
Electric current and there is fixed brightness.
In third sub-stage P3, the voltage potential of common drive signal Swe will continue to rise, so that first node voltage V1
The voltage potential shown in " formula 1 " rises to voltage potential shown in " formula 2 ".Therefore, driving transistor 210 is in third
Stage P3 can be in an off state.
It is noted that if the triangular pulse of common drive signal Swe has fixed rise and fall slope,
The time span of first sub-stage P1 and third sub-stage P3 can be positively correlated with first node voltage V1 in the electricity of write phase T3
Piezoelectric position (also that is, voltage potential shown in " formula 2 ").On the other hand, the time span of the second sub-stage P2, then can be negatively correlated
In first node voltage V1 in the voltage potential of write phase T3.
In other words, pixel circuit 120 is lower in the voltage potential of the write phase T3 data-signal Sdata received, then
Pixel circuit 120 can be longer in the fluorescent lifetime of light emitting phase T4.By adjustment pixel circuit 120 shining in light emitting phase T4
Time can allow user to experience the brightness of different grayscale.Also that is, when combined type driving display panel 100 works in first
When mode, multiple pixel circuits 120 can have the fluorescent lifetime of different length, and light emission luminance having the same.
Please refer to Fig. 9, in another embodiment that pixel circuit 120 works in first mode, common drive signal Swe in
Light emitting phase T4 has ramp pulse.Therefore, the voltage change of the second end of the second capacitor C2 is (also that is, common drive signal Swe
Alternating component), first node N1 can be transferred to through the second capacitor C2 so that driving transistor 210 in light emitting phase T4 according to
Sequence is off and on state.In the case, light emitting phase T4 includes the 4th sub-stage P4 and the 5th sub-stage P5.
It can be gradually reduced from the second fixed current potential LS2 in the voltage potential of the 4th sub-stage P4, common drive signal Swe,
So that voltage potential shown in first node voltage V1 oneself " formula 2 " is gradually reduced, but first node voltage V1 is still higher than " formula
1 " voltage potential shown in.Therefore, driving transistor 210 can be in an off state in the 4th sub-stage P4.
In the 5th sub-stage P5, the voltage potential of common drive signal Swe continues to decline, so that under first node voltage V1
It is brought down below voltage potential shown in " formula 1 ".Therefore, driving transistor 210 can be in the conductive state in the 5th sub-stage P5.
In addition, the voltage potential of common drive signal Swe can switch to the second fixed current potential LS2 at the end of the 5th sub-stage P5, make
It obtains first node voltage V1 and switches to voltage potential shown in " formula 2 ", transistor 210 is driven with shutdown.
In the present embodiment, if the ramp pulse of common drive signal Swe has fixed descending slope, the 4th sub- rank
The time span of section P1, can be positively correlated with first node voltage V1 in the voltage potential of write phase T3 (also that is, " formula 2 " institute
The voltage potential shown).On the other hand, the time span of the 5th sub-stage P5, then can negative about first node voltage V1 in writing
Enter the voltage potential of stage T3.
Figure 10 is the simplified timing diagram of driving signal when combined type drives display panel 100 to work in second mode.
When combined type driving display panel 100 works in second mode, the first multitask switch M1 can be connected, and the second multitask is opened
Closing M2 can turn off, so that system high voltage OVDD is transferred to pixel circuit 120.In the case, combined type drives display panel
The running of the 100 reset phase T1 and compensated stage T2 in second mode, the resetting that can be similar to respectively in first mode
The running of stage T1 and compensated stage T2 do not repeat to repeat herein for brevity.
As shown in Figure 10, the write phase T3 of second mode is also similar to the write phase T3 of first mode, and difference is
Data-signal Sdata starts from switching between multiple voltage potentials, and multiple voltage potential current potential LS1 fixed lower than first.
Therefore, first node voltage V1 can have the voltage potential as shown in following " formula 3 ":
V1=OVDD- | Vth |+LA-LS1 " formula 3 "
Wherein, LA is indicated when pixel circuit 120 enters write phase T3 and first switch SW1 is connected, data-signal
Specific voltage current potential possessed by Sdata.This specific voltage current potential can determine driving transistor 210 in next running,
The size of generated driving current Idri, and will not influence the turn-on time of driving transistor 210.
It is worth noting that, in the reset phase T1 and compensated stage T2 of Figure 10, multiple first control signal CT1 [1]~
CT1 [n] is all in the first enable current potential LE1.In write phase T3, multiple first control signal CT1 [1]~CT1 [n] then can be according to
Sequence switches to the first enable current potential LE1 by the first forbidden energy current potential LD1, and the first enable current potential is maintained in preset time T p
Then LE1 just switches to the first forbidden energy current potential LD1 by the first enable current potential LE1.In other words, combined type drives display panel 100
Multiple pixel circuits 120 can compensate simultaneously driving transistor 210 critical voltage variation, then received in sequence have specific voltage
The data-signal Sdata of current potential.In this way, which each pixel circuit 120 can obtain the sufficient time to compensate driving crystal
The critical voltage variation of pipe 210.
In the light emitting phase T4 of the present embodiment, first switch SW1, second switch SW2 and third switch SW3 are off
State, and the second end of the second capacitor C2 receives the system high voltage OVDD with fixed current potential.In the case, multitask
Circuit 110 and pixel circuit 120 can be equivalent to equivalent circuit shown in Figure 11.First node voltage V1 can be maintained at above-mentioned
Voltage potential shown in " formula 3 " so that driving transistor 210 works in saturation region, and generates big as shown in following " formula 4 "
Small driving current Idri:
Wherein, k represents the list of the carrier transport factor (carrier mobility) of driving transistor 210, grid oxic horizon
For position capacitance size with the product with gate pole breadth length ratio three, Cp1 and Cp2 respectively represent the electricity of first capacitor C1 and the second capacitor C2
Capacitance.
By " formula 4 " it is found that the size of driving current Idri will not because of driving transistor 210 critical voltage variation and
Change.By the size of adjustment driving current Idri, user can be allowed to experience the brightness of different grayscale.Also that is, when compound
When formula driving display panel 100 works in second mode, the multiple meeting of pixel circuits 120 synchronous light-emittings, and can have different
Light emission luminance.
Figure 12 is the schematic diagram according to the pixel circuit 120a of second embodiment of the invention.Before pixel circuit 120a is suitable for
The combined type driving display panel 100 stated, and it is similar to the pixel circuit 120 of Fig. 2.Difference is that pixel circuit 120a is also wrapped
Containing the 4th switch SW4.4th switch SW4 includes control terminal, first end and second end.The control terminal of 4th switch SW4 is for connecing
The 4th control signal CT4 is received, the first end of the 4th switch SW4 is coupled to second node N2, the second end coupling of the 4th switch SW4
In the first end of luminescence unit 240.
In the present embodiment, the 4th control signal CT4 in reset phase T1, compensated stage T2 and write phase T3 all
With the first forbidden energy current potential LD1, and there is the first enable current potential LE1 in light emitting phase T4.Therefore, the 4th switch SW4 is in weight
Setting stage T1, compensated stage T2 and write phase T3 can turn off, and can be connected in light emitting phase T4.
Therefore, in the present embodiment, LED control signal OVSS is maintained at the second enable current potential LE2, without changing it
Voltage potential is to turn off luminescence unit 240.It is likely to occur inside combined type driving display panel 100 in this way, can reduce
Noise.Remaining connection type, component, embodiment and the advantage of aforementioned pixel circuit 120 are all suitable for pixel circuit
120a does not repeat to repeat herein for brevity.
Figure 13 is the schematic diagram according to the pixel circuit 120b of third embodiment of the invention.Before pixel circuit 120b is suitable for
The combined type driving display panel 100 stated, and it is similar to the pixel circuit 120 of Fig. 2.Difference is that pixel circuit 120b includes
Write circuit 220b, and write circuit 220b includes first capacitor C1, the second capacitor C2 and first switch SW1.First capacitor C1
Comprising first end and second end, the first end of first capacitor C1 is coupled to first node N1, the second end coupling of first capacitor C1
In third node N3.Second capacitor C2 includes first end and second end, and the first end of the second capacitor C2 is coupled to third node N3,
The second end of second capacitor C2 is coupled to multiplexing circuitry 110.First switch SW1 includes control terminal, first end and second end, the
For the control terminal of one switch SW1 for receiving first control signal CT1, the first end of first switch SW1 is coupled to third node N3,
The second end of first switch SW1 signal Sdata for receiving data.
Since the first capacitor C1 and the second capacitor C2 of pixel circuit 120b are coupled in parallel in third node N3.Therefore,
It can be indicated by " formula 5 " below in the size of the light emitting phase T4 of the present embodiment, driving current Idri:
By " formula 5 " it is found that in write phase T3, the data-signal Sdata of the present embodiment can have lesser amplitude with
Reduce power consumption.Remaining connection type, component, embodiment and the advantage of aforementioned pixel circuit 120 are all suitable for pixel circuit
120b does not repeat to repeat herein for brevity.
Figure 14 is the schematic diagram according to the pixel circuit 120c of fourth embodiment of the invention.Before pixel circuit 120c is suitable for
The combined type driving display panel 100 stated, and it is similar to the pixel circuit 120 of Fig. 2.Difference is that pixel circuit 120c includes
Compensation circuit 230c, and compensation circuit 230c includes second switch SW2 and third switch SW3.Second switch SW2 includes control
End, first end and second end, the control terminal of second switch SW2 is for receiving second control signal CT2, and the of second switch SW2
One end is coupled to second node N2, and the second end of second switch SW2 is coupled to first node N1.Third switch SW3 includes control
End, first end and second end, the control terminal of third switch SW3 control signal CT3 for receiving third, and the of third switch SW3
One end is coupled to first node N1, and the second end of third switch SW3 is for receiving reference voltage Vref.
It can subtract in the reset phase T1 of the present embodiment by the equivalent impedance of second switch SW2 and third switch SW3
Few first end from driving transistor 210 flow to the size of current of the second end of third switch SW3.Therefore, pixel circuit 120c
Has the advantages that low-power consumption.Remaining connection type, component, embodiment and the advantage of aforementioned pixel circuit 120, are all suitable for
Pixel circuit 120c does not repeat to repeat herein for brevity.
Figure 15 is the schematic diagram according to the pixel circuit 120d of fifth embodiment of the invention.Before pixel circuit 120d is suitable for
The combined type driving display panel 100 stated, and include write circuit 220b and compensation circuit 230c above-mentioned.Therefore, aforementioned picture
Remaining connection type, component, embodiment and the advantage of plain circuit 120,120b and 120c are all suitable for pixel circuit
120d does not repeat to repeat herein for brevity.
In conclusion low-light diode conduct can be overcome when combined type driving display panel 100 works in first mode
The colour cast problem of luminescence unit.Also, combined type driving display panel 100 can also work in second mode, have to drive
Pixel circuit of the machine light emitting diode as luminescence unit, or driving are made with more advanced processing procedure, without there is colour cast to ask
Pixel circuit of the micro- light emitting diode of topic as luminescence unit.Therefore, combined type driving display panel 100 has high using bullet
Property.
Some vocabulary is used in specification and claims to censure specific component.However, affiliated technology neck
Has usually intellectual in domain, it is to be appreciated that same component may be called with different nouns.Specification and right are wanted
It asks book not in such a way that the difference of title is as component is distinguished, but carrys out the base as differentiation with the difference of component functionally
It is quasi-."comprising" mentioned by specification and claims is open term, therefore should be construed to " include but do not limit
In ".In addition, " coupling " is herein comprising any direct and indirect connection means.Therefore, if it is described herein that first assembly is coupled to
Second component, then represent first assembly can by being electrically connected or being wirelessly transferred, it is direct and the signals connection type such as optical delivery
Ground is connected to the second component, or electrical property or signal are connected to second component indirectly by other assemblies or connection means.
In addition, unless specified in the instructions, otherwise the term of any singular lattice all includes the connotation of multiple grid simultaneously.
Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention, ripe
It knows those skilled in the art and makes various corresponding changes and modifications, but these corresponding changes and change in accordance with the present invention
Shape all should fall within the scope of protection of the appended claims of the present invention.
Claims (13)
1. a kind of combined type driving display panel, characterized by comprising:
One multiplexing circuitry, for exporting a system high voltage according to one first multi-task signal and one second multi-task signal
With the one of them of a common drive signal；
Multiple row pixel circuit is coupled to the multiplexing circuitry, and for accordingly receiving multiple first control signals, the multiple row picture
A wherein pixel circuit for plain circuit includes:
One driving transistor, includes a control terminal, a first end and a second end, the control terminal of the driving transistor is coupled to
One first node, the first end of the driving transistor is for receiving the system high voltage, the second end of the driving transistor
It is coupled to a second node；
One write circuit is coupled to the first node and the multiplexing circuitry, and for according to multiple first control signal
Wherein a data-signal is sent to the first node by a first control signal；And
One luminescence unit includes a first end and a second end, and the first end of the luminescence unit is coupled to the second node, should
The second end of luminescence unit is for receiving a LED control signal；
Wherein when the common drive signal that the write circuit receives has a triangular pulse or a ramp pulse, this is write
Enter circuit and the common drive signal is sent to the first node.
2. combined type as described in claim 1 drives display panel, which is characterized in that wherein, which includes:
One first capacitor includes a first end and a second end, and the first end of the first capacitor is coupled to the first node, should
The second end of first capacitor is coupled to a third node；
One second capacitor includes a first end and a second end, and the first end of second capacitor is coupled to the first node, should
The second end of second capacitor is coupled to the multiplexing circuitry；And
One first switch includes a control terminal, a first end and a second end, and the control terminal of the first switch is for receiving this
First control signal, the first end of the first switch are coupled to the third node, and the second end of the first switch is for connecing
Receive the data-signal.
3. combined type as described in claim 1 drives display panel, which is characterized in that wherein, which includes:
One first capacitor includes a first end and a second end, and the first end of the first capacitor is coupled to the first node, should
The second end of first capacitor is coupled to a third node；
One second capacitor includes a first end and a second end, and the first end of second capacitor is coupled to the third node, should
The second end of second capacitor is coupled to the multiplexing circuitry；And
One first switch includes a control terminal, a first end and a second end, and the control terminal of the first switch is for receiving this
First control signal, the first end of the first switch are coupled to the third node, and the second end of the first switch is for connecing
Receive the data-signal.
4. combined type as claimed in claim 2 or claim 3 drives display panel, which is characterized in that additionally comprise a compensation circuit, be used for
Absolute value of the negative about a critical voltage of the driving transistor is set by a first node voltage of the first node, it should
Compensation circuit includes:
One second switch includes a control terminal, a first end and a second end, and the control terminal of the second switch is for receiving one
Second control signal, the first end of the second switch are coupled to the second node, and the second end of the second switch is coupled to
The first node；And
One third switch includes a control terminal, a first end and a second end, and the control terminal of third switch is for receiving one
Third controls signal, and the first end of third switch is for receiving a reference voltage, the second end coupling of third switch
In the second node.
5. combined type as claimed in claim 4 drives display panel, which is characterized in that wherein, the first control signal, this
Two control signals and third control signal switch between one first enable current potential and one first forbidden energy current potential, the control that shines
Signal processed switches between one second enable current potential and one second forbidden energy current potential,
Wherein, in a reset phase, the first control signal, the second control signal and third control signal have should
First enable current potential, and the LED control signal has the second forbidden energy current potential.
6. combined type as claimed in claim 5 drives display panel, which is characterized in that wherein, in a compensated stage, this
One control signal, the second control signal have the first enable current potential, which, which controls signal, has the first forbidden energy current potential,
And the LED control signal has the second forbidden energy current potential.
7. combined type as claimed in claim 6 drives display panel, which is characterized in that wherein, in a write phase, this
One control signal has the first enable current potential, and the second control signal and third control signal have first forbidden energy electricity
Position, and the LED control signal has the second forbidden energy current potential.
8. combined type as claimed in claim 7 drives display panel, which is characterized in that wherein, in a light emitting phase, this
One control signal, the second control signal and third control signal have the first forbidden energy current potential, and the light emitting control is believed
Number have the second enable current potential.
9. combined type as claimed in claim 2 or claim 3 drives display panel, which is characterized in that wherein, additionally comprise compensation electricity
Road, for by a first node voltage of the first node be set as negative about the driving transistor a critical voltage it is exhausted
To value, which includes:
One second switch includes a control terminal, a first end and a second end, and the control terminal of the second switch is for receiving one
Second control signal, the first end of the second switch are coupled to the second node, and the second end of the second switch is coupled to
The first node；And
One third switch includes a control terminal, a first end and a second end, and the control terminal of third switch is for receiving one
Third controls signal, and the first end of third switch is coupled to the first node, and the second end of third switch is for connecing
Receive a reference voltage.
10. combined type as claimed in claim 2 or claim 3 drives display panel, which is characterized in that wherein, the multiplexing circuitry packet
Contain:
One first multitask switch includes a control terminal, a first end and a second end, the control of first multitask switch
End for receiving first multi-task signal, first multitask switch the first end be coupled to second capacitor this second
End, the second end of first multitask switch is for receiving the system high voltage；And
One second multitask switch includes a control terminal, a first end and a second end, the control of second multitask switch
End for receiving second multi-task signal, second multitask switch the first end be coupled to second capacitor this second
End, the second end of second multitask switch is for receiving the common drive signal.
11. combined type as claimed in claim 10 drives display panel, which is characterized in that wherein, when first multitask is opened
When shutdown and the second multitask switch conduction, the multiple row pixel circuit light emission luminance having the same,
Wherein when the first multitask switch conduction and the second multitask switch OFF, the synchronous hair of the multiple row pixel circuit
Light.
12. combined type as described in claim 1 drives display panel, which is characterized in that wherein, should in a compensated stage
Multiple first control signal that multiple row pixel circuit receives has the first enable current potential, and in the write phase, this is more
Multiple first control signal that column pixel receives sequentially switches to the first enable current potential by the first forbidden energy current potential, and in
It is maintained at the first enable current potential in one preset time, the first forbidden energy current potential is just then switched to by the first enable current potential.
13. combined type as described in claim 1 drives display panel, which is characterized in that additionally comprise:
One the 4th switch includes a control terminal, a first end and a second end, and wherein the control terminal of the 4th switch is for connecing
One the 4th control signal is received, the first end of the 4th switch is coupled to the second node, the second end coupling of the 4th switch
It is connected to the first end of the luminescence unit.
Applications Claiming Priority (4)
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| US201862659662P | 2018-04-18 | 2018-04-18 | |
| US62/659,662 | 2018-04-18 | ||
| TW107138058A TWI684969B (en) | 2018-04-18 | 2018-10-26 | Hybrid driving display panel |
| TW107138058 | 2018-10-26 |
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| CN110033731B CN110033731B (en) | 2020-09-25 |
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| CN111402794A (en) * | 2019-09-17 | 2020-07-10 | 友达光电股份有限公司 | Driving chip and related display |
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