CN101887676A - Source driver - Google Patents
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- CN101887676A CN101887676A CN2009101412402A CN200910141240A CN101887676A CN 101887676 A CN101887676 A CN 101887676A CN 2009101412402 A CN2009101412402 A CN 2009101412402A CN 200910141240 A CN200910141240 A CN 200910141240A CN 101887676 A CN101887676 A CN 101887676A
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Abstract
The invention discloses a source driver, which is used for driving a display panel. The source driver comprises a plurality of channels and an output switch, wherein the channels generate a plurality of drive voltages; the output switch is coupled with the channels and selectively connects the channels to a plurality of data wires of the display panel; the data wires comprise a plurality of odd data wires and a plurality of even data wires; the output switch comprises a plurality of output multiplexers; each output multiplexer is coupled with the corresponding channels, and connects at least one corresponding channel to one of the plurality of data wires when enabled; and the output multiplexers are sequentially enabled in a frame period.
Description
Technical field
The present invention relates to a kind of source electrode driver, particularly a kind ofly be used to reduce electromagnetic interference (EMI) (electromagnetic interference, source electrode driver EMI).
Background technology
(liquid crystal display LCD) has in light weight, advantages such as volume is little, low power consumption and radiationless line scattering, is therefore used in a large number in recent years because LCD.
Fig. 1 is the synoptic diagram of conventional liquid crystal.As shown in Figure 1, LCD 100 comprises display panel 102, gate drivers 104 and source electrode driver 106.Display panel 102 comprises the pel array of being made up of a plurality of pixels 111.Gate drivers 104 is activation sweep trace S1 to SM successively.Then, source electrode driver 106 is converted to a plurality of driving voltages with digital of digital video data, and a plurality of driving voltages is sent to pixel 111 on the sweep trace that is enabled with display frame by data line D1～DN.Source electrode driver 106 mainly comprise digital analog converter (digital-to-analog converter, DAC), output buffer (output buffer) and output multiplexer (output multiplexer).Digital analog converter is used for digital image signal is converted to driving voltage, and transmit driving voltage to output buffer promoting the driving force of driving voltage, and transmit the pixel 111 of driving voltage to the display panel 102 with show image.
Generally speaking, for fear of the liquid crystal polarization phenomena that pixel 111 interior residual charges are caused, pixel 111 must adopt the mode of reversal of poles (polarity inversion) to drive to promote display quality.With a counter-rotating (dot inversion) is example, the pixel 111 of same position can drive with the driving voltage of opposed polarity in two continuous pictures, for example be the driving voltage of positive polarity or negative polarity, and neighbor 111 also can drive in same picture with the driving voltage of opposed polarity.In source electrode driver 106,, therefore can cause higher power consumption owing to can swing (swing) between positive polarity voltage and reverse voltage from the driving voltage of output buffer output.
In order to reduce power consumption, output buffer can be designed to promote the output buffer of driving force of the driving voltage of the output buffer of driving voltage of positive polarity and negative polarity respectively.And the operation by output multiplexer, the driving voltage of positive polarity and the driving voltage of negative polarity can together be exported to pixel 111 by data line D1～DN.Do not considering that linear load (line loading) can influence under the situation of signal transmission at present, because the output multiplexer that control signal is controlled is to be enabled simultaneously with outputting drive voltage, therefore can produce the big electric current of moment, and then cause the electromagnetic interference (EMI) in the source electrode driver 106.Electromagnetic interference (EMI) can reduce the usefulness of source electrode driver 106, and then causes operation of LCD not normal, so source electrode driver must solve the problems referred to above by circuit design.
Summary of the invention
In view of this, the invention provides a kind of source electrode driver, be used to reduce the electromagnetic interference (EMI) that source electrode driver produces.Therefore, a kind of display panel of above-mentioned source electrode driver that comprises can meet the safety criterion of electromagnetic interference (EMI) (safe criterion).
An one exemplary embodiment of the present invention provides a kind of source electrode driver, is used to drive display panel, and wherein source electrode driver comprises a plurality of passages and an output switch.Described passage produces a plurality of driving voltages to drive display panel.The output switch comprises a plurality of output multiplexers, optionally to connect the data line of described passage to the display panel.When each output multiplexer was enabled, each output multiplexer was connected in the data line one with passage, and wherein these output multiplexers are enabled in a frame period successively.
The source electrode driver utilization output switch of an one exemplary embodiment of the present invention optionally connects the data line of described passage to display panel, is enabled successively in a frame period with the control output multiplexer.Therefore, when source electrode driver is driving pixel on the display panel, can not produce the big electric current of moment in the source electrode driver, and then reduce electromagnetic interference (EMI).
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.What this must understand be, following generality is described and detailed description is all exemplary illustrated, and is in order to be further explained for claims of the present invention.
Description of drawings
Fig. 1 is the synoptic diagram of conventional liquid crystal.
Fig. 2 is the block scheme according to the source electrode driver of one embodiment of the invention.
Fig. 3 is the sequential chart of inner control signal and delayed control signal during the picture frame of Fig. 2.
Fig. 4 is the circuit diagram of output multiplexer of the source electrode driver of Fig. 2.
Fig. 5 is the block scheme according to the source electrode driver of another embodiment of the present invention.
Fig. 6 is the block scheme according to the source electrode driver of another embodiment of the present invention.
Fig. 7 is the block scheme according to the source electrode driver of another embodiment of the present invention.
Embodiment
Generally speaking, source electrode driver comprises a plurality of driving passages, to drive the pixel on each data line respectively in different scan periods.Each of source electrode driver drive passage can comprise shift registor (shift register, SR), digital analog converter (digital-to-analog converter, DAC), output buffer (output buffer) etc.(data latch is DL) with receiving video data (video data) according to timing control signal control data latch for shift registor.Digital analog converter is converted to aanalogvoltage with video data, and output buffer is used to promote this aanalogvoltage.In addition, the back-end circuit of source electrode driver more comprises a plurality of output multiplexers, it transmits the aanalogvoltage that the drives passage pixel to the display panel simultaneously according to control signal, wherein control signal is produced by time schedule controller (timing controller).In order to solve the electromagnetic interference (EMI) of exporting aanalogvoltage simultaneously and being produced because of moment, example embodiment of the present invention provides a kind of circuit design with the control output multiplexer.Because any those skilled in the art all can understand the operation of said elements in the source electrode driver, therefore relevant with said elements operation is not partly just described in detail at this.
Fig. 2 is the block scheme according to the source electrode driver of one embodiment of the present of invention.Please refer to Fig. 2, source electrode driver 200 is suitable for driving many data line D1～DN on the display panel 230, and source electrode driver 200 comprises a plurality of driving channel C H and output switch 202.Wherein, data line D1～DN comprises many odd data lines and many even data lines.Output switch 202 comprises a plurality of delay cell 210_1～210_N, and a plurality of output multiplexer group 220_1～220_N.Output switch 202 couples described passage, and optionally connects driving channel C H to data line D1～DN.Drive N pixel 231 on channel C H difference driven sweep line S 1～SM.Each drives passage and comprises shift registor (SR) 242, data latches (DL) 243, digital analog converter (DAC) 244 and output buffer (OP) 246 respectively.Drive channel C H and receive pixel data DP1～DPN (not illustrating) respectively.Digital-to-analogue conversion 244 comprises a plurality of driving channel C H, respectively pixel data DP 1～DPN is converted to picture element signal VP1～VPN.Then, drive channel C H and pass through a plurality of output buffers 246 difference output pixel signal VP1～VPN to output multiplexer MUX.Because any those skilled in the art know that each drives the detail operations of passage, so just do not described in detail at this part.
Each output multiplexer group 220_1～220_N comprises output multiplexer MUX.Each output multiplexer MUX is coupled to corresponding passage, and connects corresponding passage one in the bar data line at the most when being enabled at least, and wherein output multiplexer MUX is enabled in a frame period successively.For instance, when the first output multiplexer MUX was enabled, it was coupled to first and second channel C H, and first passage and second channel are connected to data line D1 and D2.
The first input end of each output multiplexer MUX and second input end receive respectively from the picture element signal VP1 of the output buffer 246 of source electrode driver and picture element signal VP2.In the present embodiment, picture element signal VP1 and picture element signal VP2 can have complementary polarity to carry out reversal of poles, and wherein complementary polarity for example is positive polarity and negative polarity.First output terminal of each output multiplexer and second output terminal couple (for example data line D1) and (for example data line D2) in the even data line in the odd data line respectively.When display panel carries out reversal of poles (for example being row counter-rotatings (column inversion) or some counter-rotating (dot inversion)), each output multiplexer MUX controlled signal CON activation, and transmit picture element signal VP1 and picture element signal VP2 respectively, or transmit picture element signal VP1 and picture element signal VP2 respectively to even data line D2 and odd data line D1 to odd data line D1 and even data line D2.
Delay cell 210_1～210_N couples with series system, with continuous delayed control signal CON, and then produces a plurality of delayed control signal D_1～D_N respectively to output multiplexer group 220_1～220_N.Output multiplexer group 220_1～220_N is driven successively according to delayed control signal D_1～D_N respectively.In the present embodiment, each delay cell is implemented by two reversers that are one another in series 211,214.Certainly, any those skilled in the art also can use logic gate (logic gate), layout cabling (routing wire) to wait other elements to implement, so the present invention is not limited to this.
Fig. 3 is the sequential chart of inner control signal CON and delayed control signal D_1～D_N during the picture frame of Fig. 2.In the present embodiment, but suppose control signal CON activation output multiplexer MUX when the logic high levle, with output pixel signal VP1 and the picture element signal VP2 data line to the display panel 230.Yet any those skilled in the art also can comply with its required logic state that designs control signal CON voluntarily.Please be simultaneously with reference to Fig. 2 and Fig. 3, delay cell 210_1 delayed control signal CON is to produce delayed control signal D_1 in time t1.Simultaneously, the output multiplexer MUX of the output multiplexer group 220_1 pixel 231 of synchronous driving picture element signal to the display panel in fact.Wherein, picture element signal is from the pairing output buffer of output multiplexer MUX.Similarly, other delay cells also have similar operation with the output multiplexer group.Since output multiplexer group 220_1～220_N in different time by different delayed control signal activations, therefore during a picture frame in, output multiplexer MUX is enabled successively.Thus, the moment induction current of source electrode driver just can reduce, and then reduces electromagnetic interference (EMI).
Fig. 4 is the circuit diagram of output multiplexer MUX of the source electrode driver 200 of Fig. 2.Please be simultaneously with reference to Fig. 2 and Fig. 4, output multiplexer comprises switch T1 to T4.The first input end I1 of switch T1 and the T3 foundation first control signal F1 conducting output multiplexer MUX and the second input end I2 are to the first output terminal O1 and the second output terminal O2 of output multiplexer MUX.The first input end I1 of switch T2 and the T4 foundation second control signal F2 conducting output multiplexer MUX and the second input end I2 are to the second output terminal O2 and the first output terminal O1 of output multiplexer MUX.In the present embodiment, delayed control signal D_1～D_N is the first control signal F1 or the first control signal F2, and the first control signal F1 and first control signal F2 reverse signal each other.Therefore, when output multiplexer MUX is delayed control signal D_1～D_N activation, output multiplexer MUX transmits picture element signal VP1 and picture element signal VP2 respectively to odd data line D1 and even data line D2, perhaps transmits picture element signal VP1 and picture element signal VP2 respectively to even data line D2 and odd data line D1.
In another embodiment of the present invention, switch T1～T4 can implement by transistor.For instance, if the first picture element signal VP1 has positive polarity, and the second picture element signal VP2 has negative polarity, then switch T1 and T2 can utilize N type metal oxide semiconductor (N-typemetal-oxide-semiconductor, NMOS) transistor is implemented, (P-type MOS, PMOS) transistor is implemented, to avoid transistorized body effect (body effect) and switch T3 and T4 can utilize P-type mos.Therefore, the conducting state of necessary gauge tap T1 of the first control signal F1 and T4, and the conducting state of necessary gauge tap T2 of the second control signal F2 and T3.Wherein, the first control signal F1 and second control signal F2 reverse signal each other.
Fig. 5 is the block scheme according to the source electrode driver of another embodiment of the present invention.Please refer to Fig. 5, each delay cell 510_1～510_N can implement by reverser 512, with delayed control signal CON successively.The class of operation of the embodiment of Fig. 5 is like the embodiment of Fig. 3, so do not give unnecessary details with regard to not adding at this.As mentioned above, output multiplexer is by control signal CON activation, and therefore the control method of output multiplexer MUX must be suitably revised in the design that utilizes reverser 512 to implement delay cell.That is to say that output multiplexer group 520_1 is by delayed control signal D_1 activation, and output multiplexer group 520_2 is by delayed control signal D_2 activation, and delayed control signal D_2 is the reverse signal of delayed control signal D_1, by that analogy.
Fig. 6 is the block scheme according to the source electrode driver of one embodiment of the invention.Please refer to Fig. 2 and Fig. 6, both are the difference part: the output switch 602 of source electrode driver 600 also comprises a plurality of reverser 630_1～630_N, and it couples delay cell 610_1～610_N respectively.Reverser 630_1～630_N can avoid the decay of delayed control signal when signal transmits.
Fig. 7 is the block scheme according to the source electrode driver of one embodiment of the invention.Please refer to Fig. 7, the output switch 702 of source electrode driver 700 comprises a plurality of reverser 730_1～730_N, a plurality of delay cell 710_1～710_N, and a plurality of output multiplexer group 720_1～720_N.Reverser 730_1～730_N couples with series system, produces a plurality of reverse control signal I_1～I_N with foundation control signal CON.Delay cell 710_1～710_N delayed backward control signal I_1～I_N is to produce delayed control signal D_1～D_N respectively.The class of operation of present embodiment is like the embodiment of above-mentioned Fig. 2, Fig. 5 and Fig. 6, promptly at different time activation output multiplexer group 720_1～720_N successively with the minimizing electromagnetic interference (EMI).In the present embodiment, each reverser directly transmits reverse control signal to next reverser, and is not that embodiment as Fig. 6 is with the delay cell by correspondence and is coupled to output multiplexer MUX layout cabling and transmits reverse signal.Therefore, present embodiment can reduce the load effect (loading effect) of the change that influences reverse signal.
In sum, the source electrode driver of the foregoing description utilizes delay cell delayed control signal successively, so the output multiplexer group can be driven in different time.Thus, can avoid producing the big electric current of moment induction, and then reduce electromagnetic interference (EMI).In addition, by using the reverser that is connected with each delay cell, the intensity of control signal also can obtain to strengthen in the signal transmission.
Though the present invention discloses as above with embodiment; but it is not to be used for limiting the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; should make a little variation and modification, so protection scope of the present invention should be looked being as the criterion that the accompanying Claim book defined.
Claims (19)
1. a source electrode driver is used to drive display panel, and this source electrode driver comprises:
A plurality of passages are in order to produce a plurality of driving voltages; And
The output switch couples described passage and optionally connects many data lines of described passage to this display panel, and wherein said data line comprises many odd data lines and many even data lines, and this output switch comprises:
A plurality of output multiplexers, each described output multiplexer couples corresponding described passage, when each described output multiplexer is enabled, the described passage that each described output multiplexer connects at least one correspondence to the described data line, wherein said output multiplexer is enabled in a frame period successively.
2. source electrode driver according to claim 1, wherein this output switch also comprises:
A plurality of delay cells are used for continuous delayed control signal, and produce a plurality of delayed control signals respectively, and wherein said delay cell couples with series system.
3. source electrode driver according to claim 2, wherein said output multiplexer form a plurality of output multiplexer groups, and described output multiplexer group receives described delayed control signal respectively.
4. source electrode driver according to claim 3, wherein each described output multiplexer has first input end, second input end, first output terminal and second output terminal, wherein this first input end and this second input end receive first picture element signal and second picture element signal respectively, and this first output terminal and this second output terminal couple respectively in the described odd data line one with described even data line in one, optionally transmit in this first picture element signal and this second picture element signal to the described odd data line one and the described even data line one respectively with this delayed control signal that is received according to each described output multiplexer group, or transmit extremely in the described even data line and the described odd data line of this first picture element signal and this second picture element signal respectively.
5. source electrode driver according to claim 2, wherein this output switch also comprises:
A plurality of reversers, each described reverser has input end and output terminal, the input end of first reverser receives this control signal, the output terminal of first reverser couples first delay cell, the input end of i reverser receives (i-1) this delayed control signal that individual delay cell produced, and the output terminal of i reverser couples i delay cell, 2≤i≤N wherein, and N is the number of delay cell.
6. source electrode driver according to claim 3, wherein this output multiplexer comprises:
First switch has first end this first input end as each described output multiplexer, and second end is coupled to one in the described odd data line, with according to its first end of the first control signal conducting with and second end;
Second switch has first end that first end is coupled to this first switch, and second end couples one in the described even data line, with according to its first end of the first control signal conducting with and second end;
The 3rd switch has first end this second input end as each described output multiplexer, and second end couples one in this even data line, with according to its first end of the second control signal conducting with and second end;
The 4th switch has first end that first end couples the 3rd switch, and second end couples one in the described odd data line, with according to its first end of the second control signal conducting with and second end;
This first control signal and this second control signal reverse signal each other each other wherein, and this delayed control signal that this output multiplexer received is this first control signal or this second control signal.
7. source electrode driver according to claim 6, wherein the reverse signal of this first control signal is that this first control signal is oppositely got, and the reverse signal of this second control signal is that this second control signal is oppositely got.
8. source electrode driver according to claim 6, wherein this first switch to the 4th switch is a transistor.
9. source electrode driver according to claim 3, wherein this delay cell comprises first reverser, this first reverser has input end and output terminal, the input end of first reverser in first delay cell receives this control signal, the output terminal of first reverser in first delay cell produces first delayed control signal, and the input end of first reverser in i delay cell receives (i-1) individual delayed control signal, 2≤i≤N wherein, N is the number of output multiplexer group.
10. source electrode driver according to claim 2, wherein this delay cell comprises:
First reverser, have input end and output terminal, the input end of first reverser in first delay cell receives this control signal, and the input end of first reverser in i delay cell receives (i-1) individual delayed control signal, 2≤i≤N wherein, N is the number of delay cell; And
Second reverser, have input end and be coupled to the output terminal of this first reverser, the output terminal of this second reverser in first delay cell produces first delayed control signal, and the output terminal of this second reverser in i delay cell produces i delayed control signal.
11. source electrode driver according to claim 1, wherein this output switch also comprises:
A plurality of reversers produce a plurality of reverse control signals according to control signal, and wherein this reverser couples with series system; And
A plurality of delay cells postpone this reverse control signal respectively and produce a plurality of delayed control signals.
12. source electrode driver according to claim 11, wherein this output multiplexer forms a plurality of output multiplexer groups, and this output multiplexer group receives this delayed control signal respectively.
13. source electrode driver according to claim 12, wherein each described output multiplexer has first input end, second input end, first output terminal and second output terminal, wherein this first input end and this second input end receive first picture element signal and second picture element signal respectively, and this first output terminal and this second output terminal couple one in the described odd data line one and the described even data line respectively, optionally transmit in this first picture element signal and this second picture element signal to the described odd data line one and the described even data line one respectively with this delayed control signal that is received according to each described output multiplexer group, or transmit extremely in the described even data line and the described odd data line of this first picture element signal and this second picture element signal respectively.
14. source electrode driver according to claim 11, wherein each described output multiplexer comprises:
First switch has first end this first input end as this output multiplexer, and second end is coupled to one in the described odd data line, with according to its first end of the first control signal conducting with and second end;
Second switch has first end that first end is coupled to this first switch, and second end couples one in the described even data line, with according to its first end of the first control signal conducting with and second end;
The 3rd switch has first end this second input end as described output multiplexer, and second end couples one in the described even data line, with according to its first end of the second control signal conducting with and second end;
The 4th switch has first end that first end couples the 3rd switch, and second end couples described odd data line one of them, with according to its first end of the second control signal conducting with and second end;
This first control signal and this second control signal reverse signal each other each other wherein, and this delayed control signal that each described output multiplexer received is this first control signal or this second control signal.
15. source electrode driver according to claim 14, wherein the reverse signal of this first control signal is that this first control signal is reverse, and the reverse signal of this second control signal is that this second control signal is reverse.
16. source electrode driver according to claim 14, wherein this first switch to the 4th switch is a transistor.
17. source electrode driver according to claim 11, wherein this delay cell comprises:
First reverser, have input end and output terminal, the input end of first reverser in first delay cell receives this control signal, and the input end of first reverser in i delay cell receives (i-1) individual delayed control signal, 2≤i≤N wherein, N is the number of delay cell; And
Second reverser, have input end and be coupled to the output terminal of this first reverser, the output terminal of this second reverser in first delay cell produces first delayed control signal, and the output terminal of this second reverser in i delay cell produces i delayed control signal.
18. source electrode driver according to claim 4, wherein this first picture element signal and this second picture element signal have complementary polarity.
19. source electrode driver according to claim 4, wherein this first picture element signal and this second picture element signal have different colours.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101412402A CN101887676A (en) | 2009-05-14 | 2009-05-14 | Source driver |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101412402A CN101887676A (en) | 2009-05-14 | 2009-05-14 | Source driver |
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| CN102087825A (en) * | 2010-12-31 | 2011-06-08 | 友达光电股份有限公司 | Source driver |
| CN103632640A (en) * | 2012-08-21 | 2014-03-12 | 联咏科技股份有限公司 | Driving apparatus for liquid crystal display |
| CN104036735A (en) * | 2013-03-05 | 2014-09-10 | 联咏科技股份有限公司 | Display driving apparatus, and driving method of display panel |
| CN104485063A (en) * | 2014-12-31 | 2015-04-01 | 深圳市华星光电技术有限公司 | Display panel and drive circuit thereof |
| CN104575355A (en) * | 2014-12-31 | 2015-04-29 | 深圳市华星光电技术有限公司 | Display panel and drive circuit thereof |
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| US9576518B2 (en) | 2014-12-31 | 2017-02-21 | Shenzhen China Optoelectronics Technology Co., Ltd | Display panel and driving circuit thereof |
| US9607539B2 (en) | 2014-12-31 | 2017-03-28 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Display panel capable of reducing a voltage level changing frequency of a select signal and drive circuit thereof |
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| CN116798337A (en) * | 2023-08-28 | 2023-09-22 | 深圳通锐微电子技术有限公司 | Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment |
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| CN102087825A (en) * | 2010-12-31 | 2011-06-08 | 友达光电股份有限公司 | Source driver |
| CN102087825B (en) * | 2010-12-31 | 2013-01-02 | 友达光电股份有限公司 | source driver |
| CN103632640A (en) * | 2012-08-21 | 2014-03-12 | 联咏科技股份有限公司 | Driving apparatus for liquid crystal display |
| CN104036735A (en) * | 2013-03-05 | 2014-09-10 | 联咏科技股份有限公司 | Display driving apparatus, and driving method of display panel |
| US9607539B2 (en) | 2014-12-31 | 2017-03-28 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Display panel capable of reducing a voltage level changing frequency of a select signal and drive circuit thereof |
| JP2018506065A (en) * | 2014-12-31 | 2018-03-01 | 深▲せん▼市華星光電技術有限公司Ｓｈｅｎｚｈｅｎ Ｃｈｉｎａ Ｓｔａｒ Ｏｐｔｏｅｌｅｃｔｒｏｎｉｃｓ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．， Ｌｔｄ． | Display panel and driving circuit thereof |
| GB2550728B (en) * | 2014-12-31 | 2021-06-23 | Shenzhen China Star Optoelect | Display panel and drive circuit thereof |
| WO2016106843A1 (en) * | 2014-12-31 | 2016-07-07 | 深圳市华星光电技术有限公司 | Display panel and drive circuit therefor |
| CN104575355B (en) * | 2014-12-31 | 2017-02-01 | 深圳市华星光电技术有限公司 | Display panel and drive circuit thereof |
| US9576518B2 (en) | 2014-12-31 | 2017-02-21 | Shenzhen China Optoelectronics Technology Co., Ltd | Display panel and driving circuit thereof |
| CN104485063A (en) * | 2014-12-31 | 2015-04-01 | 深圳市华星光电技术有限公司 | Display panel and drive circuit thereof |
| EA033985B1 (en) * | 2014-12-31 | 2019-12-17 | Шэньчжэнь Чайна Стар Оптоэлектроникс Текнолоджи Ко., Лтд. | Display panel and drive circuit therefor |
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| CN105575333B (en) * | 2015-12-22 | 2018-03-30 | 深圳市华星光电技术有限公司 | OLED display and source electrode driver |
| WO2017107290A1 (en) * | 2015-12-22 | 2017-06-29 | 深圳市华星光电技术有限公司 | Oled display device and source driver |
| CN105575333A (en) * | 2015-12-22 | 2016-05-11 | 深圳市华星光电技术有限公司 | OLED device and source driver |
| CN108109576A (en) * | 2017-11-21 | 2018-06-01 | 友达光电股份有限公司 | Multiplexer circuit and display panel thereof |
| CN108109576B (en) * | 2017-11-21 | 2021-03-12 | 友达光电股份有限公司 | Multiplexer circuit and display panel thereof |
| CN110033731A (en) * | 2018-04-18 | 2019-07-19 | 友达光电股份有限公司 | Combined type drives display panel |
| CN116798337A (en) * | 2023-08-28 | 2023-09-22 | 深圳通锐微电子技术有限公司 | Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment |
| CN116798337B (en) * | 2023-08-28 | 2023-11-24 | 深圳通锐微电子技术有限公司 | Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment |
| CN116825025A (en) * | 2023-08-30 | 2023-09-29 | 深圳通锐微电子技术有限公司 | Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment |
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Application publication date: 20101117 |