CN116825025A - Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment - Google Patents
Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment Download PDFInfo
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- CN116825025A CN116825025A CN202311102448.XA CN202311102448A CN116825025A CN 116825025 A CN116825025 A CN 116825025A CN 202311102448 A CN202311102448 A CN 202311102448A CN 116825025 A CN116825025 A CN 116825025A
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- 230000001629 suppression Effects 0.000 title claims abstract description 28
- 230000003321 amplification Effects 0.000 claims abstract description 14
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 14
- 230000003111 delayed effect Effects 0.000 claims description 19
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 7
- 230000033228 biological regulation Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 3
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
Abstract
The application relates to an electromagnetic interference suppression circuit, a source driver, a display panel and electronic equipment, wherein the suppression circuit comprises an input voltage generation unit, a channel operational amplification unit, a multiplexing output multiplexer and a time delay control unit, and the time delay control unit and the multiplexing output multiplexer are matched with each other to enable the integral output of the channel operational amplification unit to keep the electromagnetic interference specification and the driving capability corresponding to a specific temperature at different temperatures by generating a time delay clock signal with the time delay which does not change along with the temperature and sending the time delay signal to the multiplexing output multiplexer.
Description
Technical Field
The present application relates to the field of display, and in particular, to an electromagnetic interference suppression circuit, a source driver, a display panel, and an electronic device.
Background
The source driver generally includes a channel operational amplifier circuit, and when the source driver operates to drive a TFT (Thin Film Transistor ) display panel, the channel operational amplifier circuit has a significant difference in electromagnetic interference at low temperature and high temperature (relative to normal operating temperature), for example, the channel operational amplifier circuit has an enhanced driving capability at low temperature, a larger electromagnetic radiation interference, a reduced driving capability at high temperature, and a smaller electromagnetic radiation interference, i.e., it is difficult to make the channel operational amplifier circuit maintain a consistent electromagnetic interference specification and the same driving capability when the source driver operates.
Disclosure of Invention
In view of the above, the present application provides an electromagnetic interference suppression circuit, a source driver, a display panel, and an electronic device, which are applied to the source driver, and can enable a channel operational amplifier unit in the source driver to maintain the electromagnetic interference and driving capability of the same specification.
The source driver includes a digital selection circuit, and the suppression circuit includes:
the input voltage generating unit is electrically connected with the digital selecting circuit and is used for receiving the digital selecting signal output by the digital selecting circuit to generate a reference voltage input signal.
The channel operational amplification unit is electrically connected with the input voltage generation unit and is used for receiving the reference voltage input signal output by the input voltage generation unit and amplifying the reference voltage input signal to generate an amplified signal.
The multiplexing output multiplexer is electrically connected with the channel operational amplification unit and is used for receiving the amplified signals output by the channel operational amplification unit and selecting and outputting the amplified signals.
The delay control unit is electrically connected with the multiplexing output multiplexer and is used for outputting a delay clock signal to the multiplexing output multiplexer, and the delay of the delay clock signal does not change along with temperature.
The multiplexing output multiplexer is further used for carrying out delay processing on the amplified signal according to the delay clock signal so as to generate a delayed amplified signal.
In one embodiment, the delay control unit includes a control signal generation unit and a delay clock generation unit electrically connected.
The control signal generating unit is used for outputting a current control signal to the delay clock generating unit, wherein the current control signal is irrelevant to temperature change.
The delay clock generation unit is electrically connected with the multiplexing output multiplexer and is used for generating a delay clock signal according to the current control signal and outputting the delay clock signal to the multiplexing output multiplexer.
In one embodiment, the control signal generation unit includes a bandgap reference circuit.
In one embodiment, the multiplexing output multiplexer includes a first output terminal and a second output terminal, and the level signals of the first output terminal and the second output terminal are different in height.
In one embodiment, the bandgap reference circuit includes a positive temperature coefficient cell, a PTAT current cell, and a current output cell that are electrically interconnected.
The positive temperature coefficient unit is used for generating a current regulating signal and outputting the current regulating signal to the PTAT current unit, wherein the current regulating signal changes inversely with the temperature.
The PTAT current unit is used for generating a node current signal according to the current regulation signal, wherein the node current signal does not change with temperature.
The current output unit is used for acquiring the node current signal and outputting the node current signal to generate a current control signal.
In one embodiment, the PTAT current unit includes a first PMOS transistor, a second PMOS transistor, an operational amplifier, a first triode and a second triode, gates of the first PMOS transistor and the second PMOS transistor are connected to each other, sources of the first PMOS transistor and the second PMOS transistor are connected to a power supply, a drain of the first PMOS transistor is electrically connected to a first end of the first triode and a positive input end of the operational amplifier, a drain of the second PMOS transistor is electrically connected to a first end of the second triode and a negative input end of the operational amplifier, an output end of the operational amplifier is electrically connected to gates of the first PMOS transistor and the second PMOS transistor, and respective second ends and third ends of the first triode and the second triode are grounded.
The positive temperature coefficient unit comprises a first positive temperature coefficient unit and a second positive temperature coefficient unit, one end of the first positive temperature coefficient unit is electrically connected with the first end of the first triode, the other end of the first positive temperature coefficient unit is grounded, and one end of the second positive temperature coefficient unit is electrically connected with the first end of the second triode, and the other end of the second positive temperature coefficient unit is grounded.
The output end of the operational amplifier is used for outputting a node current signal.
In one embodiment, the current output unit includes a third PMOS transistor, a gate of the third PMOS transistor is electrically connected to a gate of the first PMOS transistor, a source of the third PMOS transistor is electrically connected to the power supply, and a drain of the third PMOS transistor is used for outputting the current control signal.
In addition, a source driver is provided, and the source driver comprises the suppression circuit.
In addition, a display panel is also provided, and the display panel comprises the source driver.
In addition, an electronic device is provided, and the electronic device comprises the display panel.
The suppression circuit comprises an input voltage generating unit, a channel operational amplifying unit, a multiplexing output multiplexer and a time delay control unit, wherein the input voltage generating unit is electrically connected with the digital selection circuit, receives a digital selection signal output by the digital selection circuit to generate a reference voltage input signal, the channel operational amplifying unit is electrically connected with the input voltage generating unit, is used for receiving the reference voltage input signal output by the input voltage generating unit and amplifying the reference voltage input signal to generate an amplified signal, the multiplexing output multiplexer is electrically connected with the channel operational amplifying unit, is used for receiving the amplified signal output by the channel operational amplifying unit and selectively outputting the amplified signal, the time delay control unit is electrically connected with the multiplexing output multiplexer, is used for outputting a delayed clock signal to the multiplexing output multiplexer, the time delay of the delayed clock signal does not change along with temperature, the multiplexing output multiplexer is also used for delaying the amplified signal according to the delayed clock signal to generate a delayed amplified signal, and the delayed clock signal is sent to the multiplexing output multiplexer, namely, through the cooperation of the time delay control unit and the multiplexing output multiplexer, the whole output of the channel operational amplifying unit can keep a specific temperature (for example, the working temperature) at different temperatures, the time delay control unit can correspondingly operate at a certain temperature, the time delay can be adjusted relatively to the normal driving capability of the multiplexing output unit, and the electromagnetic driving capability can be adjusted relatively to the normal driving capability of the multiplexing output unit through the multiplexing output unit is relatively high in comparison with the normal performance, and the performance of the normal operation performance can be controlled by the operation performance of the multiplexing unit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a suppression circuit for electromagnetic interference according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a conventional delayed clock signal according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a delayed clock signal using the suppression circuit according to an embodiment of the present application;
fig. 4 is a block diagram of a delay control unit according to an embodiment of the present application;
fig. 5 is a schematic circuit diagram of a delay control unit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. Based on the embodiments in the present application. The various embodiments described below and their technical features can be combined with each other without conflict.
As shown in fig. 1, the present application provides an electromagnetic interference suppression circuit 100, which is applied to a source driver, wherein the source driver includes a digital selection circuit 20, and the suppression circuit 100 includes:
the input voltage generating unit 110 is electrically connected to the digital selecting circuit 20, and receives the digital selecting signal outputted from the digital selecting circuit 20 to generate a reference voltage input signal.
The channel operational amplification unit 120 is electrically connected to the input voltage generation unit 110, and is configured to receive and amplify the reference voltage input signal output by the input voltage generation unit 110 to generate an amplified signal.
The multiplexing output multiplexer 130 is electrically connected to the channel operational amplification unit 120, and is configured to receive the amplified signal output by the channel operational amplification unit 120 and perform selective output.
The delay control unit 140 is electrically connected to the multiplexing output multiplexer 130, and is configured to output a delayed clock signal to the multiplexing output multiplexer 130, where the delay of the delayed clock signal does not change with temperature.
The multiplexing output multiplexer 130 is further configured to delay the amplified signal according to the delayed clock signal to generate a delayed amplified signal.
The output end of the source driver is usually used for being connected with the TFT display panel, and when the source driver works, a driving voltage signal is output to the TFT display panel so as to charge the TFT display panel, and further the torsion degree of liquid crystal molecules is controlled so as to display a display picture corresponding to the color.
In this embodiment, the suppression circuit 100 includes the input voltage generating unit 110, the channel operational amplifying unit 120, the multiplexing output multiplexer 130 and the delay control unit 140, that is, the overall output of the channel operational amplifying unit 120 can keep the electromagnetic interference specification and the driving capability corresponding to a specific temperature (for example, a normal operating temperature) at different temperatures through the cooperation of the delay control unit 140 and the multiplexing output multiplexer 130, so that the technical disadvantage that the driving capability is strong at a low temperature (relative to the normal operating temperature) and the electromagnetic interference is large is overcome, and the overall driving capability of the channel operational amplifying unit 120 can also be adjusted through the cooperation of the delay control unit 140 and the multiplexing output multiplexer 130.
In one embodiment, the input voltage generating unit 110 generates two reference voltage input signals, wherein one reference voltage input signal is a first preset level signal, and the other reference voltage input signal is a second preset level signal, and the first preset level signal is higher than the second preset level signal.
The input voltage generating unit 110 is further connected to an external power supply voltage, and is configured to generate a corresponding reference voltage input signal according to the digital selection signal.
In one embodiment, as shown in fig. 1, the channel operational amplifier unit 120 includes a first channel operational amplifier A1 and a second channel operational amplifier A2, wherein a first preset level signal is input to a positive input terminal of the first channel operational amplifier A1, a negative input terminal of the first channel operational amplifier A1 is electrically connected to a corresponding output terminal, a second preset level signal is input to a positive input terminal of the second channel operational amplifier A2, and a negative input terminal of the second channel operational amplifier A2 is electrically connected to a corresponding output terminal.
In one embodiment, as shown in fig. 1, the mux 130 includes a first input terminal and a second input terminal, the first input terminal is electrically connected to the output terminal of the first channel operational amplifier A1, and the second input terminal is electrically connected to the output terminal of the second channel operational amplifier A2.
The mux 130 is generally electrically connected to the TFT display panel, and is configured to output the corresponding delayed amplified signal as a driving voltage signal to drive the TFT display panel.
In the suppression circuit 100, the generated delayed clock signals are shown in fig. 3, the time delays of-40 ℃, 85 ℃ and 125 ℃ are the same and are 20ns (in fig. 3, the clock signals corresponding to-40 ℃, 85 ℃ and 125 ℃ respectively are shown as a period for simplicity), if the delay control unit 140 in the suppression circuit 100 is omitted, the generated delayed clock signals are shown in fig. 2 (in fig. 2, the clock signals corresponding to-40 ℃, 85 ℃ and 125 ℃ respectively are shown as top-down), and obviously, compared with the two, in the suppression circuit 100, by arranging the delay control unit 140, the delayed clock signals irrelevant to temperature change can be generated, so that the time delay of the delayed clock signals is a fixed time delay at a normal working specific temperature.
In one embodiment, as shown in fig. 4, the delay control unit 140 includes a control signal generating unit 142 and a delay clock generating unit 144 electrically connected.
The control signal generation unit 142 is configured to output a current control signal to the delay clock generation unit 144, the current control signal being independent of temperature variation.
The delay clock generating unit 144 is electrically connected to the multiplexing output multiplexer 130, and is configured to generate a delay clock signal according to the current control signal, and output the delay clock signal to the multiplexing output multiplexer 130.
In the present embodiment, the current control signal generated by the control signal generating unit 142 is a physical quantity that is independent of temperature change, and thus the delay clock generating unit 144 can generate a delay clock signal that is independent of temperature change from the current control signal.
In an embodiment, the control signal generation unit 142 comprises, i.e. is implemented by, a bandgap reference circuit.
In one embodiment, the multiplexing output multiplexer 130 includes a first output terminal and a second output terminal, where the level signals of the first output terminal and the second output terminal are different.
When the first output end outputs a high-level signal, the second output end outputs a low-level signal.
In one embodiment, as shown in fig. 5, the control signal generation unit 142 includes a positive temperature coefficient unit 142a, a PTAT current unit 142b, and a current output unit 142c electrically interconnected.
The ptc unit 142a is configured to generate a current adjustment signal and output the current adjustment signal to the PTAT current unit 142b, wherein the current adjustment signal varies inversely with temperature.
The PTAT current unit 142b is configured to generate a node current signal according to the current adjustment signal, the node current signal not varying with temperature.
The current output unit 142c is configured to obtain and output the node current signal to generate a current control signal.
Where AVDD represents the supply voltage and PTAT (proportional to absolute temperature) represents proportional to absolute temperature.
In one embodiment, as shown in fig. 4, the PTAT current unit 142b includes a first PMOS transistor P1, a second PMOS transistor P2, an operational amplifier A3, a first resistor R1, a first triode S1 and a second triode S2, gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to each other, sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to a power supply, a drain of the first PMOS transistor P1 is electrically connected to a first end of the first triode S1 and a positive input end of the operational amplifier A3, a drain of the second PMOS transistor P2 is electrically connected to a first end of the second triode S2 through the first resistor R1, and an output end of the operational amplifier A3 is electrically connected to gates of the first PMOS transistor P1 and the second PMOS transistor P2, and a second end and a third end of the first triode S1 and the second triode S2 are grounded, respectively.
The ptc unit 142a includes a first ptc unit 142a1 and a second ptc unit 142a2, wherein one end of the first ptc unit 142a1 is electrically connected to the first end of the first transistor S1 and the other end is grounded, and one end of the second ptc unit 142a2 is electrically connected to the first end of the second transistor S2 and the other end is grounded.
Wherein the output terminal (node Vref) of the operational amplifier A3 is used for outputting a node current signal.
As shown in fig. 4, the first ptc unit 142a1 is set to the second resistor R2, and the second ptc unit 142a2 is set to the third resistor R3.
In this embodiment, the first transistor S1 and the second transistor S2 are both negative temperature coefficient units, and the second resistor R2 and the third resistor R3 are positive temperature coefficient units, so that the current of the node Vref is independent of the temperature change.
In one embodiment, as shown in fig. 4, the current output unit 142c includes a third PMOS transistor P3, a gate of the third PMOS transistor P3 is electrically connected to a gate of the first PMOS transistor P1, a source of the third PMOS transistor P3 is electrically connected to a power supply, and a drain of the third PMOS transistor P3 is used for outputting a current control signal.
In this embodiment, the third PMOS transistor P3 and the first PMOS transistor P1 form a current mirror, and at this time, the current control signal output by the drain of the third PMOS transistor P3 is the same as the current of the node Vref, i.e. the current control signal is independent of temperature change.
In addition, a source driver is provided, and the source driver includes the suppression circuit 100.
The source driver may be provided with a plurality of suppression circuits 100, where the source driver includes a plurality of channel operational amplification units 120, a driving time of each channel operational amplification unit 120, and a delay time between each channel operational amplification unit 120, which are all kept at the same time at different temperatures, so as to achieve the same electromagnetic interference resistance, so that the source driver can maintain an electromagnetic interference specification and a driving capability corresponding to a specific temperature (e.g., a normal operating temperature) as a whole.
In addition, a display panel is also provided, and the display panel comprises the source driver.
In addition, an electronic device is provided, and the electronic device comprises the display panel.
That is, the foregoing embodiments of the present application are merely examples, and are not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, such as the combination of technical features of the embodiments, or direct or indirect application in other related technical fields, are included in the scope of the present application.
In addition, the present application may be identified by the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, the word "e.g." is used to mean "serving as an example, instance, or illustration". Any embodiment described as "for example" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (10)
1. An electromagnetic interference suppression circuit for a source driver, the source driver including a digital selection circuit, the suppression circuit comprising:
an input voltage generating unit, configured to be electrically connected to the digital selection circuit, and receive a digital selection signal output by the digital selection circuit to generate a reference voltage input signal;
the channel operational amplification unit is electrically connected with the input voltage generation unit and is used for receiving the reference voltage input signal output by the input voltage generation unit and amplifying the reference voltage input signal to generate an amplified signal;
the multiplexing output multiplexer is electrically connected with the channel operational amplification unit and is used for receiving the amplified signals output by the channel operational amplification unit and selecting and outputting the amplified signals;
the delay control unit is electrically connected with the multiplexing output multiplexer and is used for outputting a delay clock signal to the multiplexing output multiplexer, and the delay of the delay clock signal does not change along with temperature;
the multiplexing output multiplexer is further configured to delay the amplified signal according to the delayed clock signal, so as to generate a delayed amplified signal.
2. The suppression circuit according to claim 1, wherein the delay control unit comprises a control signal generation unit and a delay clock generation unit electrically connected;
the control signal generating unit is used for outputting a current control signal to the delay clock generating unit, and the current control signal is irrelevant to temperature change;
the delay clock generation unit is electrically connected with the multiplexing output multiplexer and is used for generating the delay clock signal according to the current control signal and outputting the delay clock signal to the multiplexing output multiplexer.
3. The suppression circuit according to claim 2, wherein the control signal generation unit includes a band difference reference circuit.
4. The suppression circuit of claim 1, wherein the multiplexed output multiplexer includes a first output terminal and a second output terminal, the first output terminal and the second output terminal being different in level signal level.
5. A suppression circuit according to claim 3, wherein the bandgap reference circuit comprises a positive temperature coefficient unit, a PTAT current unit and a current output unit electrically interconnected;
the positive temperature coefficient unit is used for generating a current regulation signal and outputting the current regulation signal to the PTAT current unit, and the current regulation signal changes inversely with temperature;
the PTAT current unit is used for generating a node current signal according to the current regulation signal, and the node current signal does not change with temperature;
the current output unit is used for acquiring the node current signal and outputting the node current signal so as to generate the current control signal.
6. The suppression circuit according to claim 5, wherein the PTAT current unit comprises a first PMOS transistor, a second PMOS transistor, an operational amplifier, a first triode and a second triode, gates of the first PMOS transistor and the second PMOS transistor are connected to each other, sources of the first PMOS transistor and the second PMOS transistor are connected to a power supply, drains of the first PMOS transistor are electrically connected to a first end of the first triode and a positive input end of the operational amplifier, drains of the second PMOS transistor are electrically connected to a first end of the second triode and a negative input end of the operational amplifier, an output end of the operational amplifier is electrically connected to gates of the first PMOS transistor and the second PMOS transistor, and respective second ends and third ends of the first triode and the second triode are grounded;
the positive temperature coefficient unit comprises a first positive temperature coefficient unit and a second positive temperature coefficient unit, one end of the first positive temperature coefficient unit is electrically connected with the first end of the first triode, the other end of the first positive temperature coefficient unit is grounded, and one end of the second positive temperature coefficient unit is electrically connected with the first end of the second triode, and the other end of the second positive temperature coefficient unit is grounded;
and the output end of the operational amplifier is used for outputting the node current signal.
7. The suppression circuit of claim 6, wherein the current output unit comprises a third PMOS transistor, a gate of the third PMOS transistor is electrically connected to a gate of the first PMOS transistor, a source of the third PMOS transistor is electrically connected to a power supply, and a drain of the third PMOS transistor is configured to output the current control signal.
8. A source driver, comprising the method of claim 1
A suppression circuit as recited in any one of claims 7.
9. A display panel comprising the source driver of claim 8.
10. An electronic device comprising the display panel of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311102448.XA CN116825025A (en) | 2023-08-30 | 2023-08-30 | Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311102448.XA CN116825025A (en) | 2023-08-30 | 2023-08-30 | Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment |
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| CN116825025A true CN116825025A (en) | 2023-09-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311102448.XA Pending CN116825025A (en) | 2023-08-30 | 2023-08-30 | Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment |
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