JPH1124766A - Reference voltage generator - Google Patents
Reference voltage generatorInfo
- Publication number
- JPH1124766A JPH1124766A JP9172055A JP17205597A JPH1124766A JP H1124766 A JPH1124766 A JP H1124766A JP 9172055 A JP9172055 A JP 9172055A JP 17205597 A JP17205597 A JP 17205597A JP H1124766 A JPH1124766 A JP H1124766A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- reference voltage
- differential amplifier
- output
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の属する技術分野】基準電圧発生装置に関し、特
に複数の基準電圧を効率的に発生する基準電圧発生装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generator, and more particularly to a reference voltage generator for efficiently generating a plurality of reference voltages.
【０００１】[0001]
【従来の技術】基準電圧発生装置は、基準となる電圧を
安定的に発生させるもので、半導体装置内部などで基準
電圧を必要とする回路に基準電圧を供給するものであ
る。基準電圧を発生させる回路は電圧、温度等の条件が
変わっても一定の電圧を発生させなければならないた
め、通常任意の電圧を発生させることはできない。つま
り、この回路は一定の電圧を発生させるだけのため、そ
の出力電圧を使って所望の電圧を生成するためには更に
差動増幅器と抵抗を使っている。2. Description of the Related Art A reference voltage generating device stably generates a reference voltage, and supplies a reference voltage to a circuit that requires the reference voltage inside a semiconductor device or the like. A circuit for generating a reference voltage must generate a constant voltage even when conditions such as voltage and temperature change, and thus cannot normally generate an arbitrary voltage. That is, since this circuit only generates a constant voltage, a differential amplifier and a resistor are further used to generate a desired voltage using the output voltage.
【０００２】例えば、特開昭６２−２７４９０９に見ら
れるような回路構成になる（図３に示す）。この公知例
では、基準電圧発生源１が一定の電圧を電圧、温度等の
条件が変化しても供給するもので、２が差動増幅器、Ｑ
１０１〜Ｑ３６４で選択されるＲ１〜Ｒ６４が抵抗であ
る。この例では、トランジスタＱ１０１〜Ｑ３６４で任
意の抵抗比を選択できるようにしているが一定の電圧だ
けを生成する場合はなくてもよく、この公知例を簡略化
したものが、図４である。この図では、Ｖ０が公知例の
Ｖｒｅｆ，ＶＲＥＦが公知例のＶｒｅｆ２に対応し、１
が公知例の２の作動増幅器に対応する。この簡略化した
図で説明すると、ある特定の基準電圧Ｖ０は作動増幅器
の一方に入力され、差動増幅器のもう一方には、出力で
あるＶＲＥＦを抵抗分割したＶ１が入力される。この
時、 Ｖ１＝ＶＲＥＦ・Ｒ２／（Ｒ１＋Ｒ２） ・・・・・・・・・・・（１） の関係があり、差動増幅器は、２つの入力が一致するよ
うに動作するので、最終的には、 Ｖ０＝Ｖ１ ・・・・・・・・・・・・・・・・・・・・・・・・（２） となり、所望の基準電圧ＶＲＥＦは、 ＶＲＥＦ＝Ｖ０・（Ｒ１＋Ｒ２）／Ｒ２ ・・・・・・・・・・・（３） で求められる値になるので、Ｒ１，Ｒ２を調整すること
により、所望の電圧を得られることになる。For example, a circuit configuration as shown in Japanese Patent Application Laid-Open No. 62-274909 is shown (shown in FIG. 3). In this known example, the reference voltage generator 1 supplies a constant voltage even when conditions such as voltage and temperature change.
R1 to R64 selected by 101 to Q364 are resistors. In this example, an arbitrary resistance ratio can be selected by the transistors Q101 to Q364, but it is not necessary to generate only a constant voltage. FIG. 4 is a simplified version of this known example. In this figure, V0 corresponds to Vref of a known example, VREF corresponds to Vref2 of a known example, and 1
Corresponds to the two operational amplifiers of the known example. In this simplified diagram, a specific reference voltage V0 is input to one of the operational amplifiers, and V1 which is a resistance-divided output of VREF is input to the other of the differential amplifiers. At this time, there is a relationship of V1 = VREF.R2 / (R1 + R2) (1), and the differential amplifier operates so that the two inputs coincide with each other. V0 = V1 (2), and the desired reference voltage VREF is VREF = V0 · (R1 + R2) / R2... (3) Since the value is obtained, the desired voltage can be obtained by adjusting R1 and R2.
【０００３】Ｃは容量で、ＶＲＥＦを安定させるための
補償容量として入れてある。[0003] C is a capacity, which is included as a compensation capacity for stabilizing VREF.
【０００４】[0004]
【発明が解決しようとする課題】従来の基準電圧発生装
置では、複数の異る基準電圧が必要な場合は、図５に示
したように、図４の６０に相当する回路を６１〜６３の
ように複数個半導体装置内に設け、それぞれのブロック
内のＲ１とＲ２の比率を変えて、それぞれ異る電圧を生
成する必要があった。このため、必要な基準電圧が複数
ある場合、その必要数分だけ発生回路が必要であり、抵
抗を除き同一の回路を複数設ける必要があり、コストと
密接に結び付いているチップサイズが大きくなってしま
うという問題点があった。In a conventional reference voltage generator, when a plurality of different reference voltages are required, as shown in FIG. 5, a circuit corresponding to 60 in FIG. As described above, it is necessary to provide a plurality of semiconductor devices and generate different voltages by changing the ratio of R1 and R2 in each block. For this reason, when there are a plurality of necessary reference voltages, a necessary number of generation circuits are necessary, and a plurality of the same circuits except for the resistors need to be provided, and a chip size closely connected to cost increases. There was a problem that it would.
【０００５】差動増幅器の回路規模はそれほど大きくな
いが、特に抵抗は、大きな面積を必要とするためであ
る。それは、消費電流を抑えるため抵抗値を大きくする
必要があるためである。例えば、図５のＲ１＋Ｒ２が１
０００ＫΩの時、これらの抵抗を通って流れる電流は、
１μＡとなる。通常、低消費電流のためＲ１＋Ｒ２は１
００Ｋ〜１０ＭΩ程度の範囲で抵抗値を設定する。例え
ば１０００ＫΩの抵抗をシリサイドで形成するとする
と、シリサイドの単位矩形面積当り抵抗値が約１０Ωと
し、２μｍの幅で２００ｍｍの長さが必要になることか
らも大きな面積が必要になることが理解できる。Although the circuit scale of the differential amplifier is not so large, the resistor particularly requires a large area. This is because it is necessary to increase the resistance value in order to suppress current consumption. For example, R1 + R2 in FIG.
At 000 KΩ, the current flowing through these resistors is
1 μA. Usually, R1 + R2 is 1 due to low current consumption.
The resistance value is set in the range of about 00K to 10 MΩ. For example, if a resistance of 1000 KΩ is formed of silicide, the resistance per unit rectangular area of silicide is about 10Ω, and a width of 2 μm and a length of 200 mm are required.
【０００６】図６に示したように図４のＲ１を細分化
し、ＶＲＥＦ２を生成したらよいのではないかとも考え
られるが、ＶＲＥＦ２の電圧の安定化のために入れてあ
る補償容量Ｃ２のため、差動増幅器にフィードバックす
る電圧Ｖ１が時定数Ｒ１１・Ｃ２分遅れるため、差動増
幅器に対する制御に遅れを生じさせ、発振現象を起こ
し、基準電圧として使えないものとなってしまうことが
ある。As shown in FIG. 6, it is conceivable that R1 in FIG. 4 may be subdivided to generate VREF2. However, due to the compensation capacitance C2 inserted for stabilizing the voltage of VREF2, Since the voltage V1 fed back to the differential amplifier is delayed by the time constant R11 · C2, the control of the differential amplifier is delayed, causing an oscillation phenomenon, which may not be used as a reference voltage.
【０００７】[0007]
【課題を解決するための手段】本発明の基準電圧発生装
置は、差動増幅器の一方の入力端子には第１の基準電圧
発生手段の出力が印加され、他方には前記差動増幅器の
出力電圧に比例する電圧を発生する電圧帰還手段の出力
が印加され、かつ前記差動増幅器の出力に前記電圧帰還
手段とは別の電圧経路を有する複数の基準電圧を発生さ
せる第２の基準電圧発生手段を備えている。A reference voltage generator according to the present invention has an output terminal of a first reference voltage generator applied to one input terminal of a differential amplifier and an output terminal of the differential amplifier connected to the other input terminal. A second reference voltage generator to which an output of a voltage feedback means for generating a voltage proportional to the voltage is applied, and a plurality of reference voltages having different voltage paths from the voltage feedback means are generated at the output of the differential amplifier; Means.
【０００８】[0008]
【発明の実施の形態】次に本発明について図面を参照し
て説明する。図１は、本発明の一実施例の回路図であ
る。前述した従来例と同じ構成部分は、同一の番号を付
けている。この実施例では、３つの異る基準電圧を発生
させる場合を示してある。Ｒ１とＲ２はＶＲＥＦ１を生
成するための分割抵抗で、Ｒ３，Ｒ４，Ｒ５はＶＲＥＦ
１からＶＲＥＦ１より電位の低いＶＲＥＦ２，ＶＲＥＦ
３を生成するための分割抵抗である。また、Ｃ１，Ｃ
２，Ｃ３は安定性のために入れてある補償容量である。
この図において、従来と異るところは、ＶＲＥＦ１から
Ｒ３，Ｒ４，Ｒ５を使って抵抗分割で所望の電圧を取り
出すようにしている点である。また、 ＶＲＥＦ１＞ＶＲＥＦ２＞ＶＲＥＦ３ ・・・・・・・・・・・・（４） の関係になるように必要としている基準電圧を並び替え
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of one embodiment of the present invention. The same components as those in the conventional example described above are denoted by the same reference numerals. In this embodiment, a case where three different reference voltages are generated is shown. R1 and R2 are divided resistors for generating VREF1, and R3, R4, and R5 are VREF.
1 to VREF2, VREF lower in potential than VREF1
3 is a divisional resistor for generating 3. Also, C1, C
2 and C3 are compensation capacitors provided for stability.
This figure differs from the conventional one in that a desired voltage is extracted from VREF1 by resistance division using R3, R4 and R5. Also, the necessary reference voltages are rearranged so as to satisfy the relationship of VREF1>VREF2> VREF3 (4).
【０００９】この例では、ＶＲＥＦ１は従来例と同じよ
うに ＶＲＥＦ１＝Ｖ０・（Ｒ１＋Ｒ２）／Ｒ２ ・・・・・・・・・・（５） で計算される値となり、ＶＲＥＦ２，ＶＲＥＦ３をそれ
ぞれ ＶＲＥＦ２＝ＶＲＥＦ１・（Ｒ４＋Ｒ５）／（Ｒ３＋Ｒ４＋Ｒ５） ・（６） ＶＲＥＦ３＝ＶＲＥＦ１・Ｒ５／（Ｒ３＋Ｒ４＋Ｒ５） ・・・・（７） で計算される値となる。ここで、Ｒ３，Ｒ４，Ｒ５を任
意に選択することにより任意の電圧を取り出すことがで
きる。この場合、差動増幅器のフィードバックループ
内、即ち、ＶＲＥＦ１からＲ１を通って差動アンプの−
（マイナス）入力に至る経路には、ＶＲＥＦ１のみに容
量が付いており、経路にある抵抗の手前に付いているた
めフィードバックに遅延を生ずることはない。In this example, VREF1 is a value calculated by the following equation: VREF1 = V0 ＋ (R1 + R2) / R2 (5), as in the conventional example, and VREF2 is VREF2 = VREF1 · (R4 + R5) / (R3 + R4 + R5) (6) VREF3 = VREF1 · R5 / (R3 + R4 + R5) (7) Here, an arbitrary voltage can be extracted by arbitrarily selecting R3, R4, and R5. In this case, in the feedback loop of the differential amplifier, that is, from VREF1 through R1, −
In the path leading to the (minus) input, only VREF1 has a capacitance, and the path is in front of the resistor in the path, so that there is no delay in feedback.
【００１０】次に本発明の第２の実施例について、図２
を基に説明する。実施例１では、常に一定の基準電圧を
出力する場合は問題ないが、半導体装置の初期不良を取
り除く試験であるスクリーニングのため、通常、高電圧
をかけて加速試験を行う場合に問題が生じる場合があ
る。Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described based on FIG. In the first embodiment, there is no problem in the case where a constant reference voltage is always output. However, in the case of a screening which is a test for removing an initial failure of a semiconductor device, a problem usually occurs when an accelerated test is performed by applying a high voltage. There is.
【００１１】例えば、半導体記憶装置において、ＶＲＥ
Ｆ１が周辺回路用の電源電圧の基準電圧、ＶＲＥＦ２が
メモリセル用電源電圧の基準電圧といった場合、通常メ
モリセル容量の絶縁酸化膜は周辺回路のトランジスタの
ゲート酸化膜の厚さより薄いため、加速係数が周辺回路
とメモリセル部と異る。従って、ＶＲＥＦ１とＶＲＥＦ
２の比率が通常時と加速試験時に変えないとならない場
合に対応できないという問題がある。これは、ＶＲＥＦ
２が上記式（６）で決定され、ＶＲＥＦ１に対して常に
一定の比率を持つことから明確である。For example, in a semiconductor memory device, VRE
When F1 is the reference voltage of the power supply voltage for the peripheral circuit and VREF2 is the reference voltage of the power supply voltage for the memory cell, the insulating oxide film of the memory cell capacitor is usually thinner than the thickness of the gate oxide film of the transistor of the peripheral circuit. Are different from the peripheral circuit and the memory cell portion. Therefore, VREF1 and VREF
There is a problem that it is not possible to cope with the case where the ratio of 2 must be changed between the normal time and the acceleration test. This is VREF
2 is determined by the above equation (6), and is clear from the fact that it always has a constant ratio with respect to VREF1.
【００１２】そこで、実施例２では、抵抗Ｒ３とＲ４の
間にスイッチとして動作するＰｃｈトランジスタＰ１を
挿入し、加速試験時にハイレベルになるＴＥＳＴという
信号を入力することにより、ＶＲＥＦ１とＶＲＥＦ２が
電気的に切り離れた状態にできるようにしている。この
時、テスト用電源発生回路８を設け、ＶＲＥＦ２に供給
することによりＶＲＥＦ１とＶＲＥＦ２が通常時と異る
比率を持つ電位になるようにした。図示はしていない
が、Ｖ０も通常時とは異る電圧を発生させることによ
り、ＶＲＥＦ１を通常時とは異る電圧にすることも可能
である。この例では、ＶＲＥＦ３は ＶＲＥＦ３＝ＶＲＥＦ２・Ｒ５／（Ｒ４＋Ｒ５） ・・・・・・・（８） という式で求められる電圧になるが、式（５）とは関係
なく独立した電圧を生成させることもＶＲＥＦ２と同様
な回路を用いることにより可能である。ＴＥＳＴ信号が
ロウレベルの時は、テスト用電圧発生回路の出力はハイ
インピーダンス状態になるようにすることにより、実施
例１と同一の動作になる。Therefore, in the second embodiment, a Pch transistor P1 which operates as a switch is inserted between the resistors R3 and R4, and a signal TEST which becomes a high level during an acceleration test is inputted, so that VREF1 and VREF2 are electrically connected. So that they can be separated from each other. At this time, a test power supply generating circuit 8 is provided and supplied to VREF2 so that VREF1 and VREF2 have a potential different from that in the normal state. Although not shown, it is also possible to make VREF1 a voltage different from the normal state by generating a voltage different from the normal state also for V0. In this example, VREF3 is VREF3 = VREF2 · R5 / (R4 + R5)... (8), but a voltage independent of equation (5) is generated. Is also possible by using a circuit similar to VREF2. When the TEST signal is at a low level, the output of the test voltage generating circuit is set to a high impedance state, thereby performing the same operation as in the first embodiment.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、差動増幅
器の一方の入力端子には第１の基準電圧発生手段の出力
が印加され、他方には前記差動増幅器の出力電圧に比例
する電圧を発生する電圧帰還手段の出力が印加され、か
つ前記差動増幅器の出力に前記電圧帰還手段とは別に複
数の基準電圧を発生させる第２の基準電圧発生手段を備
えることにより、回路を複数設けることなく効率的な基
準電圧を発生させることが可能となっている。As described above, according to the present invention, the output of the first reference voltage generating means is applied to one input terminal of the differential amplifier, and the other is proportional to the output voltage of the differential amplifier. The output of the voltage feedback means for generating a voltage is applied, and the output of the differential amplifier is provided with a second reference voltage generation means for generating a plurality of reference voltages separately from the voltage feedback means. It is possible to generate an efficient reference voltage without providing.
【００１４】このような構成にすることにより、複数の
基準電圧が必要な場合、その必要数の基準電圧発生回路
が必要だったのが、従来の回路に加え第２の基準電圧発
生回路という簡単な構成で複数の基準電圧が発生でき
る。With such a configuration, when a plurality of reference voltages are required, the required number of reference voltage generation circuits are required. A plurality of reference voltages can be generated with a simple configuration.
【図１】本発明の第１の実施例の回路図。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
【図２】本発明の第２の実施例の回路図。FIG. 2 is a circuit diagram of a second embodiment of the present invention.
【図３】従来例を示す回路図。FIG. 3 is a circuit diagram showing a conventional example.
【図４】従来例を簡単化した回路図。FIG. 4 is a simplified circuit diagram of a conventional example.
【図５】従来技術による複数の基準電圧発生回路の例。FIG. 5 is an example of a plurality of reference voltage generation circuits according to the related art.
【図６】従来技術による他の複数の基準電圧発生回路の
例。FIG. 6 is an example of another plurality of reference voltage generation circuits according to the related art.
１ 差動増幅器 ２ 第１の基準電圧 ３１〜３５，３１１，３１２ 抵抗 ４０〜４３ 電圧補償用容量 ５０〜５３ 生成した基準電圧 ６０〜６３ 基準電圧発生回路 ７ テスト信号 ８ テスト用電圧発生回路 ９ Ｐ−チャネルトランジスタ REFERENCE SIGNS LIST 1 differential amplifier 2 first reference voltage 31 to 35, 311, 312 resistance 40 to 43 voltage compensation capacitance 50 to 53 generated reference voltage 60 to 63 reference voltage generation circuit 7 test signal 8 test voltage generation circuit 9 P -Channel transistor
Claims (3)
基準電圧発生手段の出力が印加され、他方には前記差動
増幅器の出力電圧に比例する電圧を発生する電圧帰還手
段の出力が印加され、かつ前記差動増幅器の出力に前記
電圧帰還手段とは別の電圧経路を有する複数の基準電圧
を発生させる第２の基準電圧発生手段を備えたことを特
徴とする基準電圧発生回路。An output of a first reference voltage generating means is applied to one input terminal of a differential amplifier, and an output of a voltage feedback means for generating a voltage proportional to an output voltage of the differential amplifier is applied to the other input terminal. And a second reference voltage generating means for generating a plurality of reference voltages having a voltage path different from that of the voltage feedback means at the output of the differential amplifier. .
１の入力端に接続した基準電圧入力端子と、前記差動増
幅回路の第２の入力端に接続した節点と、前記増幅回路
の出力端に接続した第１の出力電圧端子と、前記節点と
前記第１の出力電圧端子間に設けられた第１の抵抗と、
前記節点と電源端子間に設けられた第２の抵抗と、前記
第１の出力電圧端子と第２の出力電圧端子間に設けられ
た第３の抵抗と、前記第２の出力電圧端子と第３の出力
電圧端子間に設けられた第４の抵抗と、前記第３の出力
電圧端子と前記電源端子間に設けられた第５の抵抗とを
有することを特徴とする基準電圧発生装置。2. A differential amplifier circuit; a reference voltage input terminal connected to a first input terminal of the differential amplifier circuit; a node connected to a second input terminal of the differential amplifier circuit; A first output voltage terminal connected to an output terminal of the circuit, a first resistor provided between the node and the first output voltage terminal,
A second resistor provided between the node and a power supply terminal, a third resistor provided between the first output voltage terminal and the second output voltage terminal, and a second resistor connected to the second output voltage terminal. A reference voltage generator comprising: a fourth resistor provided between the third output voltage terminals; and a fifth resistor provided between the third output voltage terminal and the power supply terminal.
抗の一端との間に設けられテスト信号に応答して導通す
るスイッチ手段と、前記テスト信号に応答して前記第２
の出力電圧端子にテスト用電圧を供給する電圧供給回路
を更に有することを特徴とする請求項２記載の基準電圧
発生装置。3. A switch means provided between the second output voltage terminal and one end of the third resistor, the switch means being turned on in response to a test signal, and the second means being turned on in response to the test signal.
3. The reference voltage generator according to claim 2, further comprising a voltage supply circuit for supplying a test voltage to an output voltage terminal of the reference voltage generator.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17205597A JP3223844B2 (en) | 1997-06-27 | 1997-06-27 | Reference voltage generator |
| KR10-1998-0024628A KR100422031B1 (en) | 1997-06-27 | 1998-06-27 | Reference voltage generation circuit for generating a plurality of reference voltages |
| CNB981025609A CN1140050C (en) | 1997-06-27 | 1998-06-29 | Reference voltage generating circuit of generating plurality of reference voltages |
| US09/106,266 US6147549A (en) | 1997-06-27 | 1998-06-29 | Reference voltage generating circuit of generating a plurality of reference voltages |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17205597A JP3223844B2 (en) | 1997-06-27 | 1997-06-27 | Reference voltage generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1124766A true JPH1124766A (en) | 1999-01-29 |
| JP3223844B2 JP3223844B2 (en) | 2001-10-29 |
Family
ID=15934706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17205597A Expired - Fee Related JP3223844B2 (en) | 1997-06-27 | 1997-06-27 | Reference voltage generator |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6147549A (en) |
| JP (1) | JP3223844B2 (en) |
| KR (1) | KR100422031B1 (en) |
| CN (1) | CN1140050C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001052012A1 (en) * | 2000-01-12 | 2001-07-19 | Advantest Corporation | Constant voltage supply circuit, substrate of constant voltage supply circuit, and method of applying constant voltage |
| JP2018180576A (en) * | 2017-04-03 | 2018-11-15 | 富士通セミコンダクター株式会社 | Voltage dropping circuit and semiconductor integrated circuit |
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| EP1014547A3 (en) * | 1998-12-21 | 2000-11-15 | Fairchild Semiconductor Corporation | Low-current charge pump system |
| JP2001332696A (en) * | 2000-05-24 | 2001-11-30 | Nec Corp | Board electric potential detecting circuit and board electric potential generating circuit |
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| US7180211B2 (en) * | 2003-09-22 | 2007-02-20 | Micro Technology, Inc. | Temperature sensor |
| US6970009B1 (en) * | 2004-01-16 | 2005-11-29 | Unisys Corporation | Single-transistor two resistor circuit which translate test signals to selectable voltage levels |
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| JP5295706B2 (en) * | 2008-10-03 | 2013-09-18 | 株式会社東芝 | Voltage generation circuit and semiconductor memory device including the same |
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| JP5493916B2 (en) | 2010-01-28 | 2014-05-14 | ミツミ電機株式会社 | Buck-boost DC-DC converter and switching control circuit |
| JP5625369B2 (en) * | 2010-01-28 | 2014-11-19 | ミツミ電機株式会社 | Buck-boost DC-DC converter and switching control circuit |
| KR101095515B1 (en) * | 2011-09-09 | 2011-12-16 | 주식회사 마이크로텍 | Low drop trm control circuit of active phased array antenna |
| CN104731144B (en) * | 2013-12-23 | 2017-07-04 | 比亚迪股份有限公司 | A kind of generating circuit from reference voltage |
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| WO2016201596A1 (en) * | 2015-06-15 | 2016-12-22 | Micron Technology, Inc. | Apparatuses and methods for providing reference voltages |
| CN116743124A (en) * | 2023-06-28 | 2023-09-12 | 上海极海盈芯科技有限公司 | Threshold value generation circuit, chip and device |
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| GB1599406A (en) * | 1977-08-11 | 1981-09-30 | Horstmann Gear Group Ltd | Gas detector with a failure sensor |
| JPS5665190A (en) * | 1979-11-01 | 1981-06-02 | Nippon Electric Co | Voltage devider circuit |
| JPS56132815A (en) * | 1980-03-21 | 1981-10-17 | Nec Corp | Reference step voltage generating circuit |
| JPS62274909A (en) * | 1986-05-23 | 1987-11-28 | Hitachi Micro Comput Eng Ltd | Selecting circuit |
| JPS6355530A (en) * | 1986-08-27 | 1988-03-10 | Hitachi Ltd | Liquid crystal display device |
| US5105102A (en) * | 1990-02-28 | 1992-04-14 | Nec Corporation | Output buffer circuit |
| JPH04157909A (en) * | 1990-10-22 | 1992-05-29 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| KR920010633A (en) * | 1990-11-30 | 1992-06-26 | 김광호 | Reference voltage generation circuit of semiconductor memory device |
| JPH05100756A (en) * | 1991-10-07 | 1993-04-23 | Nec Ic Microcomput Syst Ltd | Voltage divider circuit |
| US5381034A (en) * | 1992-04-27 | 1995-01-10 | Dallas Semiconductor Corporation | SCSI terminator |
| JP3321246B2 (en) * | 1993-06-08 | 2002-09-03 | 株式会社東芝 | Current control voltage generation circuit |
| JP3326949B2 (en) * | 1994-01-28 | 2002-09-24 | 富士通株式会社 | Semiconductor integrated circuit |
| US5559424A (en) * | 1994-10-20 | 1996-09-24 | Siliconix Incorporated | Voltage regulator having improved stability |
-
1997
- 1997-06-27 JP JP17205597A patent/JP3223844B2/en not_active Expired - Fee Related
-
1998
- 1998-06-27 KR KR10-1998-0024628A patent/KR100422031B1/en not_active IP Right Cessation
- 1998-06-29 CN CNB981025609A patent/CN1140050C/en not_active Expired - Fee Related
- 1998-06-29 US US09/106,266 patent/US6147549A/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001052012A1 (en) * | 2000-01-12 | 2001-07-19 | Advantest Corporation | Constant voltage supply circuit, substrate of constant voltage supply circuit, and method of applying constant voltage |
| US6756774B2 (en) | 2000-01-12 | 2004-06-29 | Advantest Corporation | Constant voltage source, a constant voltage source circuit board and a method for applying a constant voltage |
| DE10190481B4 (en) * | 2000-01-12 | 2008-01-17 | Advantest Corp. | Constant voltage source, constant voltage source circuit board and method for supplying a predetermined voltage |
| JP2018180576A (en) * | 2017-04-03 | 2018-11-15 | 富士通セミコンダクター株式会社 | Voltage dropping circuit and semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3223844B2 (en) | 2001-10-29 |
| CN1208991A (en) | 1999-02-24 |
| KR100422031B1 (en) | 2004-06-04 |
| CN1140050C (en) | 2004-02-25 |
| US6147549A (en) | 2000-11-14 |
| KR19990007415A (en) | 1999-01-25 |
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