JP2018180576A - Voltage dropping circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an increase of a circuit area.SOLUTION: A gate potential generating circuit 11 includes a diode-connected nMOS 11 b, receives input potential VCC and reference potential Vref, generates potential Va 1 based on reference potential Vref, a gate potential Vg 1 obtained by adding a threshold voltage Vthn of a nMOS 11 b to the potential Va 1 is outputted, from a drain terminal of the nMOS 11 b. A gate potential generating circuit 12 is connected to a drain terminal of the nMOS 11 b via resistor elements 12 b to 12 d connected in series, and has a diode-connected nMOS 12a, and outputs gate potentials Vg 2 and Vg 3 obtained by dividing the gate potential Vg 1 by resistors from the node 12 e between the resistance elements 12 c and 12 d or the node 12 f between the resistance elements 12 b and 12 c. nMOS 13a to 13c outputs output potentials Vout1 to Vout3 lower than the input potential VCC, based on the gate potentials Vg1 to Vg3.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a step-down circuit and a semiconductor integrated circuit.

  There is a step-down circuit using an n-channel MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) as a circuit to step down an input potential supplied from the outside of a semiconductor integrated circuit to an internal potential used as a power supply voltage in an internal circuit. . This step-down circuit is also called an nMOS regulator.

  A conventional step-down circuit using an n-channel MOSFET (hereinafter abbreviated as nMOS) includes an nMOS which is an output transistor for outputting an internal potential, and a gate potential generation circuit for supplying a gate potential to the nMOS. The output transistor outputs an internal potential based on the gate potential.

  The gate potential generation circuit includes a comparison circuit (for example, implemented using an operational amplifier) that controls the gate potential based on the reference potential. The gate potential generation circuit includes a MOS diode having the same threshold voltage as the output transistor, and outputs a gate potential obtained by adding the threshold voltage to the potential controlled by the comparison circuit. In the step-down circuit including such a gate potential generation circuit, the threshold voltage of the MOS diode and the threshold voltage of the output transistor are offset. Therefore, the threshold voltage of the output transistor is suppressed from fluctuating due to conditions such as the manufacturing process or temperature to affect the output potential.

Japanese Patent Application Laid-Open No. 11-24766 JP, 2011-238103, A Japanese Patent Application Publication No. 2007-14176

  By the way, in recent years, semiconductor integrated circuits have multiple power supplies, and a plurality of different power supply voltages may be used in semiconductor integrated circuits. In order to simultaneously generate a plurality of different internal potentials as a power supply voltage from a certain input potential, a plurality of step-down circuits including the above-described comparison circuit and the like may be provided. However, in that case, there is a problem that the circuit area is increased.

  In one aspect, the present invention aims to suppress an increase in circuit area of a step-down circuit.

  One embodiment includes a first n-channel MOSFET diode-connected, receives an input potential and a reference potential, and generates a first potential based on the reference potential, the first n-channel type It is connected in series with a first gate potential generation circuit that outputs a first gate potential obtained by adding the threshold voltage of the first n-channel MOSFET to the first potential from a first drain terminal of the MOSFET. A second n-channel type MOSFET connected and diode-connected to the first drain terminal via a plurality of resistive elements, the first resistive element and the second resistive element included in the plurality of resistive elements A second gate potential generation circuit that outputs a second gate potential obtained by subjecting the first gate potential to resistance division from a first node between resistance elements, and each of the first gate potential generating circuits Position or based on the second gate potential, the step-down circuit having a plurality of third n-channel MOSFET for outputting a lower output voltage than the input voltage is provided.

  Also, in one embodiment, a semiconductor integrated circuit is provided.

  In one aspect, the present invention can suppress an increase in circuit area of a step-down circuit.

It is a figure which shows an example of the pressure | voltage fall circuit of 1st Embodiment. It is a figure which shows the pressure | voltage fall circuit of a comparative example. It is a figure which shows an example of the pressure | voltage fall circuit which outputs each output electric potential using several nMOS. It is a figure which shows an example of the pressure | voltage fall circuit of 2nd Embodiment. It is a figure which shows an example of the semiconductor integrated circuit provided with the pressure | voltage fall circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First Embodiment
FIG. 1 is a diagram illustrating an example of the step-down circuit according to the first embodiment.

The step-down circuit 10 includes gate potential generation circuits 11, 12 and nMOSs 13a, 13b, 13c.
The gate potential generation circuit 11 has a p-channel MOSFET (hereinafter abbreviated as pMOS) 11a, an nMOS 11b, a comparison circuit 11c, and resistance elements 11d and 11e.

  The output terminal of the comparison circuit 11c is connected to the gate terminal of the pMOS 11a, and the input potential VCC is supplied to the source terminal and the substrate terminal of the pMOS 11a. The drain terminal of the pMOS 11a is connected to the drain terminal and the gate terminal of the nMOS 11b.

  The nMOS 11 b is diode-connected. That is, the gate terminal and the drain terminal are connected. Therefore, the nMOS 11 b functions as a MOS diode. The reference potential VSS is supplied to the substrate terminal and the source terminal of the nMOS 11 b through the resistance elements 11 d and 11 e. The reference potential VSS is, for example, 0 V (ground potential). The resistance value of the resistance element 11d is R1, and the resistance value of the resistance element 11e is R2.

  Comparison circuit 11 c is realized, for example, by an operational amplifier (differential amplifier circuit), and operates based on input potential VCC and reference potential VSS. The reference potential Vref is supplied to the inverting input terminal (denoted as "-" in FIG. 1) of the comparison circuit 11c. The non-inversion input terminal (denoted as "+" in FIG. 1) of the comparison circuit 11c is connected to the node 11f between the resistance element 11d and the resistance element 11e which are connected in series. The output terminal of the comparison circuit 11c is connected to the gate terminal of the pMOS 11a. Thereby, the comparison circuit 11c controls the drain current I1 of the pMOS 11a such that the potential Vmoni of the node 11f becomes equal to the reference potential Vref.

The reference potential Vref is supplied from the outside of the step-down circuit 10.
Although the details will be described later, the gate potential generation circuit 11 generates the potential Va1 of the source terminal and the substrate terminal of the nMOS 11b based on the reference potential Vref. Then, the gate potential generation circuit 11 outputs a gate potential Vg1 obtained by adding the threshold voltage Vthn of the nMOS 11b to the potential Va1 from the drain terminal of the nMOS 11b.

The gate potential generation circuit 12 has an nMOS 12a and resistance elements 12b, 12c and 12d.
The nMOS 12a is diode-connected. That is, the gate terminal and the drain terminal are connected. Therefore, the nMOS 12a functions as a MOS diode. The drain terminal and the gate terminal of the nMOS 12a are connected to the drain terminal of the nMOS 11b (and the drain terminal of the pMOS 11a) through the resistance elements 12b, 12c and 12d. The reference potential VSS is supplied to the source terminal of the nMOS 12a, and the substrate terminal of the nMOS 12a is connected to the source terminal. The resistance value of the resistance element 12b is R3, the resistance value of the resistance element 12c is R4, and the resistance value of the resistance element 12d is R5.

  Gate potential generation circuit 12 outputs gate potential Vg2 obtained by dividing gate potential Vg1 by resistance division from node 12e between resistance elements 12c and 12d, and gate potential Vg1 is divided by resistance potential from node 12f between resistance elements 12b and 12c. The gate potential Vg3 is output.

The nMOSs 13a to 13c output the output potentials Vout1, Vout2, and Vout3 lower than the input potential VCC based on the gate potentials Vg1 to Vg3.
The gate terminal of the nMOS 13a is connected to the drain terminal of the pMOS 11a (and the gate terminal and drain terminal of the nMOS 11b), and the input potential VCC is supplied to the drain terminal of the nMOS 13a. The source terminal and the substrate terminal of the nMOS 13a have an output potential Vout1 lower than the input potential VCC.

  The gate terminal of the nMOS 13 b is connected to a node 12 e between the resistive element 12 c and the resistive element 12 d, and the input potential VCC is supplied to the drain terminal of the nMOS 13 b. The source terminal and the substrate terminal of the nMOS 13 b have an output potential Vout2 lower than the input potential VCC.

  The gate terminal of the nMOS 13c is connected to the node 12f between the resistive element 12b and the resistive element 12c, and the input potential VCC is supplied to the drain terminal of the nMOS 13c. The source terminal and the substrate terminal of the nMOS 13c have an output potential Vout3 lower than the input potential VCC.

  The nMOSs 11b, 12a, 13a to 13c preferably have the same threshold voltage Vthn. As will be described later, it is possible to offset each other's threshold voltage Vthn and to suppress the influence of fluctuations in the threshold voltage Vthn due to conditions such as a manufacturing process or temperature on the output potentials Vout1 to Vout3. In order to have the same threshold voltage Vthn, the nMOSs 11b, 12a, 13a to 13c are designed to have the same characteristics. That is, the nMOSs 11b, 12a, 13a to 13c have the same shape, size, and the like.

Hereinafter, the operation of the step-down circuit 10 will be described.
In the following, it is assumed that the nMOSs 11b, 12a, 13a to 13c have the same threshold voltage Vthn, and R1 + R2 = R3 + R4 + R5. The reason for setting R1 + R2 = R3 + R4 + R5 will be described later.

  In the gate potential generation circuit 11, when the drain current I1 of the pMOS 11a is controlled by the comparison circuit 11c to make the reference potential Vref equal to the potential Vmoni of the node 11f, VrefVrefVmoni = I1 × R1.

  At this time, the potential Va1 of the source terminal and the substrate terminal of the nMOS 11b is Va1 = I1 × (R1 + R2). Further, since the voltage for energizing the nMOS 11b is the threshold voltage Vthn, the gate potential Vg1 (the drain potential of the pMOS 11a) output from the gate potential generation circuit 11 is Vg1 = Va1 + Vthn.

  The nMOS 13a receiving the gate potential Vg1 is energized when the gate-source voltage Vgs becomes Vgs = Vg1−Vout1 ≧ Vthn. The gate terminal of the nMOS 13a is connected to the gate terminal of the nMOS 11b. Therefore, when the drain current I1 flows in the gate potential generation circuit 11, the same current also flows between the drain terminal and the source terminal of the nMOS 13a. At this time, Vg1−Vout1 = Vthn. As described above, since Vg1 = Va1 + Vthn, the output potential Vout1 is Vout1 = Va1.

  Since the potential Va1 is determined by the drain current I1 controlled based on the reference potential Vref and the resistance values R1 and R2 as described above, the desired output potential Vout1 can be obtained by adjusting these values.

  On the other hand, in gate potential generation circuit 12, gate potential Vg2, which is the potential of node 12e between resistance elements 12c and 12d, is Vg2 = Vg1−I2 × R5. Further, gate potential Vg3, which is the potential of node 12f between resistance elements 12b and 12c, is Vg3 = Vg1−I2 × (R4 + R5). The current I2 is a current flowing in a series circuit including the nMOS 12a and the resistance elements 12b, 12c and 12d.

  The voltage for energizing the nMOS 12a is the threshold voltage Vthn, and since R1 + R2 = R3 + R4 + R5, I2 = I1. Therefore, gate potentials Vg2 and Vg3 become Vg2 = Vg1-I1 * R5, and Vg3 = Vg1-I1 * (R4 + R5). Further, since Vg1 = Vout1 + Vthn, the gate potentials Vg2 and Vg3 can be expressed as Vg2 = Vout1 + Vthn−I1 × R5 and Vg3 = Vout1 + Vthn−I1 × (R4 + R5).

  Therefore, the output potential Vout2 is Vout2 = Vg2−Vthn = Vout1 + Vthn−I1 × R5−Vthn = Vout1−I1 × R5. Further, the output potential Vout3 is Vout3 = Vg3-Vthn = Vout1 + Vthn-I1 * (R4 + R5) -Vthn = Vout1-I1 * (R4 + R5).

  As described above, according to the step-down circuit 10, a plurality of step-down potentials can be simultaneously output with a simple circuit, and, for example, an increase in circuit area can be suppressed as compared with the step-down circuit of the comparative example shown below.

(Comparative example)
FIG. 2 is a diagram showing a step-down circuit of a comparative example. In FIG. 2, the same elements as in FIG. 1 are denoted by the same reference numerals.

  The step-down circuit 10a of the comparative example includes a step-down unit 10a1 having a gate potential generation circuit 11 and an nMOS 13a, and a step-down unit 10a2 having a gate potential generation circuit 14 and an nMOS 13b. The step-down unit 10a1 outputs an output potential Vout1, and the step-down unit 10a2 outputs an output potential Vout2.

  The gate potential generation circuit 14 generates a gate potential Vg2 of the gate terminal of the nMOS 13b. The gate potential generation circuit 14 has a pMOS 14 a, an nMOS 14 b, a comparison circuit 14 c, and resistance elements 14 d and 14 e, and has the same circuit configuration as the gate potential generation circuit 11.

In such a step-down circuit 10a, the output potential Vout1 is Vout1 = Va1 as in the step-down circuit 10 shown in FIG.
On the other hand, the output potential Vout2 is generated as follows.

  In the gate potential generation circuit 14, when the drain current I1a of the pMOS 14a is controlled by the comparison circuit 14c to make the reference potential Vref equal to the potential Vmonia of the node 14f, Vref ≒ Vmonia = I1a × R1a. R1a is a resistance value of the resistance element 14d.

  At this time, the potential Va2 of the source terminal and the substrate terminal of the nMOS 14b is Va2 = I1a × (R1a + R2a). R2a is a resistance value of the resistance element 14e. Further, assuming that the threshold voltage of the nMOS 14b is Vthn, the gate potential Vg2 (the drain potential of the pMOS 14a) output from the gate potential generation circuit 14 is Vg2 = Va2 + Vthn.

  The nMOS 13b receiving the gate potential Vg2 is energized when the gate-source voltage Vgs becomes Vgs = Vg2−Vout2 ≧ Vthn. Since the gate terminal of the nMOS 13b is connected to the gate terminal of the nMOS 14b, when the drain current I1a flows in the gate potential generation circuit 14, the same current also flows between the drain terminal and the source terminal of the nMOS 13b. At this time, Vg2−Vout2 = Vthn. As described above, since Vg2 = Va2 + Vthn, the output potential Vout2 is Vout2 = Va2.

  Similar to the step-down circuit 10 shown in FIG. 1, the step-down circuit 10a can simultaneously output a plurality of output potentials Vout1 and Vout2 which are not affected by the fluctuation of the threshold voltage Vthn. However, since a plurality of gate potential generation circuits 11 and 14 each including a comparison circuit are used, the circuit scale becomes large and power consumption also increases. Although the step-down circuit 10a which outputs two output potentials Vout1 and Vout2 is shown in the example of FIG. 2, the circuit area further increases as the number of output potentials to be output simultaneously increases.

  On the other hand, according to the step-down circuit 10 shown in FIG. 1, the output potential (gate potential Vg1 is divided by the series circuit including the nMOS 12a and the resistance elements 12b to 12d) based on the gate potentials Vg2 and Vg3. Step-down potentials Vout2 and Vout3 are obtained. As a result, a step-down circuit 10 that simultaneously outputs a plurality of step-down potentials can be realized with a simple circuit, and an increase in circuit area can be suppressed as compared with the step-down circuit 10a of the comparative example. Further, the increase in current consumption due to the increase in circuit area can be suppressed.

  Further, the step-down circuit 10 can suppress that the fluctuation of the threshold voltage Vthn of the nMOSs 13a to 13c affects the output potentials Vout1 to Vout3 by having the nMOSs 11b and 12a. This effect is more remarkable because the term of the threshold voltage Vthn can be eliminated from the expression of the output potentials Vout1 to Vout3 by setting the nMOSs 11b, 12a, 13a to 13c to have the same threshold voltage Vthn as described above. It becomes. However, even if the threshold voltages of the nMOSs 11b, 12a, 13a to 13c do not match, the difference in the threshold voltages affects the values of the output potentials Vout1 to Vout3, but the influence of the fluctuation of the threshold voltage is small.

  Further, I2 = I1 can be obtained by setting R1 + R2 = R3 + R4 + R5 after the nMOSs 11b, 12a, 13a to 13c have the same threshold voltage Vthn. Therefore, as described above, the output potentials Vout2 and Vout3 can be expressed by the equation using the drain current I1. Since the drain current I1 is obtained from the relationship of Vref ≒ Vmoni = I1 × R1, it becomes easy to determine the resistance values R3 to R5 for obtaining the desired output potentials Vout2 and Vout3.

  Although FIG. 1 shows the step-down circuit 10 that outputs three output potentials Vout1 to Vout3, the present invention is not limited to this. Two output potentials Vout2 and Vout3 may be output without providing the nMOS 13a (without outputting the output potential Vout1). In addition, the number of resistance elements included in the gate potential generation circuit 12 is increased, three or more gate potentials are generated by resistance division, and four or more gate potentials are supplied, thereby providing four or more nMOS. A step-down circuit that outputs an output potential can be realized by adding a small number of circuit elements.

  Further, the number of resistance elements included in the gate potential generation circuit 12 is two, and one gate potential Vg2 is generated by resistance division, and two output potentials are generated based on the gate potential Vg1 and the gate potential Vg2. May be output.

  By the way, in the example of FIG. 1, although the nMOSs 13a to 13c are one in number, one or a plurality of the nMOSs 13a to 13c are connected in parallel to each other in order to correspond to a larger current load. May be connected.

FIG. 3 is a diagram showing an example of a step-down circuit that outputs each output potential using a plurality of nMOS. In FIG. 3, the same elements as in FIG. 1 are denoted by the same reference numerals.
The step-down circuit 20 shown in FIG. 3 includes n1 pieces of nMOSs 13a1 to 13an1 connected in parallel. For example, the nMOS 13a1 corresponds to the nMOS 13a of the step-down circuit 10 shown in FIG. The step-down circuit 20 also includes n2 nMOSs 13b1 to 13bn2 connected in parallel. For example, the nMOS 13 b 1 corresponds to the nMOS 13 b of the step-down circuit 10 shown in FIG. Furthermore, the step-down circuit 20 includes n3 nMOSs 13c1 to 13cn3 connected in parallel. For example, the nMOS 13c1 corresponds to the nMOS 13c of the step-down circuit 10 shown in FIG.

  The gate potential Vg1 is supplied to the gate terminals of the nMOSs 13a1 to 13an1, and the input potential VCC is supplied to the drain terminals of the nMOSs 13a1 to 13an1. The source terminals and the substrate terminals of the nMOSs 13a1 to 13an1 have an output potential Vout1 lower than the input potential VCC.

  The gate potential Vg2 is supplied to the gate terminals of the nMOSs 13b1 to 13bn2, and the input potential VCC is supplied to the drain terminals of the nMOSs 13b1 to 13bn2. The source terminals and the substrate terminals of the nMOSs 13b1 to 13bn2 have an output potential Vout2 lower than the input potential VCC.

  The gate potential Vg3 is supplied to the gate terminals of the nMOSs 13c1 to 13cn3 and the input potential VCC is supplied to the drain terminals of the nMOSs 13c1 to 13cn3. The source terminals and the substrate terminals of the nMOSs 13c1 to 13cn3 have an output potential Vout3 lower than the input potential VCC.

  Even if the gate width of one nMOS is expanded, it is possible to cope with a larger current load, but the characteristics change. The step-down circuit 20 uses nMOSs 13a1 to 13cn3 each having the same characteristics as the nMOSs 11b and 12a. As a result, it is possible to cope with a larger current load while maintaining the effect of suppressing the influence of the fluctuation of the threshold voltage Vthn on the output potentials Vout1 to Vout3. In the example of the step-down circuit 20 of FIG. 3, the parallel circuit of the nMOSs 13a1 to 13an1 has a current supply capability capable of corresponding to the current load of n1 × I1, and the parallel circuit of the nMOSs 13b1 to 13bn corresponds to the current load of n2 × I1. With possible current supply capability. Further, the parallel circuit of the nMOSs 13c1 to 13cn3 has a current supply capability that can cope with the n3 × I1 current load.

Second Embodiment
FIG. 4 is a diagram showing an example of the step-down circuit according to the second embodiment. In FIG. 4, the same elements as in FIG. 1 are denoted by the same reference numerals.

In the step-down circuit 30 of the second embodiment, the output potential Vout1 is supplied to the drain terminals of the nMOSs 13b and 13c instead of the input potential VCC.
The elements used for the semiconductor integrated circuit are miniaturized and there is a possibility that the short channel effect may occur when the gate length of the nMOSs 13a to 13c becomes short. The short channel effect is a phenomenon in which the drain current increases as the drain voltage rises in the saturation region of the drain current-drain voltage characteristics.

  In the step-down circuit 10 shown in FIG. 1, when the input potential VCC which is the drain voltage of the nMOSs 13a to 13c changes, the drain current may change due to the short channel effect. At this time, the output potentials Vout1 to Vout3 also change (although they are reduced to about several percent of the change of the input potential VCC).

  On the other hand, in the step-down circuit 30 of the second embodiment, since the output potential Vout1 is used as the drain voltage of the nMOSs 13b and 13c, changes in the output potentials Vout2 and Vout3 due to changes in the input potential VCC are reduced. can do.

  In the step-down circuit 30 according to the second embodiment, the drain terminals of the nMOSs 13b and 13c are connected to the source terminal of the nMOS 13a. Therefore, as shown in FIG. 3, when using the nMOS 13 b 1 to the nMOS 13 b n 2, n 2 nMOSs connected in parallel are used instead of the nMOS 13 a so as to correspond to the same current load. Similarly, as shown in FIG. 3, when the nMOS 13c1 to the nMOS 13cn3 are used, n3 nMOSs connected in parallel are used instead of the nMOS 13a so as to correspond to the same current load.

  Further, in the example of the step-down circuit 30 described above, the output potential Vout1 is used as the drain voltage of the nMOSs 13b and 13c, but is not limited thereto. For example, the output potential Vout2 is used as the drain voltage of the nMOS 13c May be

(An example of a semiconductor integrated circuit)
FIG. 5 is a diagram showing an example of a semiconductor integrated circuit provided with a step-down circuit.
The semiconductor integrated circuit 40 has an internal circuit 41 in addition to the step-down circuit 10 as shown in FIG. 1, for example.

  The internal circuit 41 includes a circuit 41a operating using the output potential Vout1 as a power supply potential, a circuit 41b operating using the output potential Vout2 as a power supply potential, and a circuit 41c operating using the output potential Vout3 as a power supply potential.

The circuits 41a to 41c are, for example, digital logic circuits, analog circuits, memory circuits, and the like, and are not particularly limited.
By using the step-down circuit 10 as shown in FIG. 1 as a step-down circuit that simultaneously outputs a plurality of output potentials Vout1 to Vout3 from the input potential VCC, an increase in the circuit area of the semiconductor integrated circuit 40 can be suppressed.

The step-down circuit 20 shown in FIG. 3 or the step-down circuit 30 shown in FIG. 4 may be used instead of the step-down circuit 10 shown in FIG.
As described above, one aspect of the step-down circuit and the semiconductor integrated circuit of the present invention has been described based on the embodiments, but these are merely examples, and the present invention is not limited to the above description.

10 Step-down circuit 11, 12 Gate potential generation circuit 11a pMOS
11b, 12a, 13a to 13c nMOS
11c Comparison circuit 11d, 11e, 12b to 12d Resistance element 11f, 12e, 12f Node R1 to R5 Resistance value I1 Drain current I2 Current Va1, Vmoni potential VCC input potential Vg1 to Vg3 Gate potential Vout1 to Vout3 Output potential Vref Reference potential VSS Reference Potential Vthn threshold voltage

Claims (8)

A first n-channel MOSFET diode-connected, receives an input potential and a reference potential, generates a first potential based on the reference potential, and generates a first drain of the first n-channel MOSFET A first gate potential generation circuit that outputs a first gate potential obtained by adding a threshold voltage of the first n-channel MOSFET to the first potential from a terminal;
A second n-channel type MOSFET connected and diode-connected to the first drain terminal via a plurality of resistance elements connected in series, the first resistance included in the plurality of resistance elements A second gate potential generation circuit that outputs a second gate potential obtained by subjecting the first gate potential to resistance division from a first node between the element and the second resistive element;
A plurality of third n-channel type MOSFETs each outputting an output potential lower than the input potential based on the first gate potential or the second gate potential;
Step-down circuit having The first n-channel MOSFET is supplied with a reference potential via a first gate terminal connected to the first drain terminal, and a third resistance element and a fourth resistance element connected in series. A first source terminal, and a first substrate terminal connected to the first source terminal;
The first gate potential generation circuit further includes:
A first p having a second gate terminal, a second drain terminal connected to the first drain terminal, and a second source terminal and a second substrate terminal to which the input potential is supplied A channel type MOSFET,
A first input terminal connected to a second node between the third resistance element and the fourth resistance element, a second input terminal to which the reference potential is supplied, and the second And a comparison circuit having an output terminal connected to the gate terminal, and controlling the drain current of the first p-channel MOSFET such that the potential of the second node is equal to the reference potential. ,
The second n-channel MOSFET includes a third drain terminal connected to the first drain terminal via the plurality of resistive elements, and a third gate terminal connected to the third drain terminal. And a third source terminal supplied with the reference potential, and a third substrate terminal connected to the third source terminal.
The step-down circuit according to claim 1.   The step-down circuit according to claim 1, wherein the first n-channel MOSFET, the second n-channel MOSFET, and the plurality of third n-channel MOSFETs have the same threshold voltage, respectively. .   4. The device according to claim 1, wherein the first n-channel MOSFET, the second n-channel MOSFET, and the plurality of third n-channel MOSFETs have the same characteristics. Step-down circuit.   The step-down circuit according to claim 2, wherein a first combined resistance value of the third resistance element and the fourth resistance element is equal to a second combined resistance value of the plurality of resistance elements. A fourth n-channel MOSFET that is one of the plurality of third n-channel MOSFETs and has a fourth drain terminal to which the input potential is supplied;
A fifth n-channel MOSFET that is one of the plurality of third n-channel MOSFETs and has a fifth drain terminal to which the output potential of the fourth n-channel MOSFET is supplied;
The step-down circuit according to any one of claims 1 to 5, comprising:   One or more sixth ones connected in parallel to each of the plurality of third n-channel MOSFETs and outputting the output potential based on the first gate potential or the second gate potential The step-down circuit according to any one of claims 1 to 6, comprising an n-channel MOSFET. A first n-channel MOSFET diode-connected, receives an input potential and a reference potential, generates a first potential based on the reference potential, and generates a first drain of the first n-channel MOSFET A first gate potential generation circuit that outputs a first gate potential obtained by adding a threshold voltage of the first n-channel MOSFET to the first potential from a terminal;
A second n-channel type MOSFET connected and diode-connected to the first drain terminal via a plurality of resistance elements connected in series, the first resistance included in the plurality of resistance elements A second gate potential generation circuit that outputs a second gate potential obtained by subjecting the first gate potential to resistance division from a first node between the element and the second resistive element;
A plurality of third n-channel type MOSFETs each outputting an output potential lower than the input potential based on the first gate potential or the second gate potential;
A step-down circuit with
An internal circuit that operates using the output potential;
A semiconductor integrated circuit having

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