JPS62274909A - Selecting circuit - Google Patents

Abstract

PURPOSE:To improve the resistance to noise by connecting plural switch elements to coupling nodes of plural resistances, which constitute a resistance voltage dividing circuit and are connected in series, in a reference voltage generating circuit so that they constitute a hierarchical circuit network having a binary tree structure. CONSTITUTION:A selecting circuit has 64 resistance elements R1-R64 connected in series between the output terminal of a differential amplifying circuit 2 and a ground terminal Gnd, and one of coupling nodes N1-N64 of respective resistance elements including terminals is selectively connected to the inverted input terminal of the differential amplifying circuit 2 on a basis of the combination of levels of 6-bit external control signals T1-T6 to selectively form a feedback path. The feedback path has a two-branched three-hierarchy dendritic circuit network as the fundamental constitution. One of nodes N1-N64 is electively connected to the inverted input terminal of the differential amplifying circuit 2 in accordance with the combination of levels of external control signals T1-T6 to selectively form a prescribed feedback path.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a selection circuit for selecting passive elements connected in series, and is applicable to, for example, a gain adjustment circuit in a reference voltage generation circuit. It concerns techniques that can be effectively utilized.

[Prior art]

A reference voltage source such as a bandgap reference type can be used to obtain a stable voltage against power supply voltage fluctuations and temperature changes, but the resulting voltage may be affected by process variations. . In such a case, the voltage output from the reference voltage source is supplied to the non-inverting input terminal of the differential amplifier circuit, and the output voltage of the differential amplifier circuit is supplied to the differential amplifier via the resistive voltage divider circuit. By feeding back the reference voltage to the inverting input terminal of the circuit and adjusting and setting the voltage dividing ratio of the resistive voltage dividing circuit, a reference voltage whose gain is adjusted to a desired level can be obtained from the differential amplifier circuit.

At this time, such a resistor voltage divider circuit is
It is possible to use a selection circuit to which a dendritic circuit network described in "Electronic Communication Handbook" P2O3 published by 1-Omu Co., Ltd. is applied. That is, a hierarchical selection circuit network with a binary tree structure is constructed by connecting switching elements made up of a plurality of MOSFETs to a connection node of resistive elements connected in series, and the switching elements are switched for each layer by a selection signal. It is possible to obtain a predetermined partial pressure ratio.

[Problem that the invention seeks to solve]

By the way, in the resistor voltage divider circuit applied to the gain adjustment circuit in the reference voltage generation circuit mentioned above, highly accurate fine adjustment of the output voltage is required due to its nature, so the resulting voltage division ratio is fine. Therefore, the number of resistance elements, that is, the number of layers of switch elements increases significantly. Then,
Since the number of switch elements such as MOSFETs that contribute to the selective formation of conductive paths to obtain a predetermined voltage division ratio in such a resistive voltage divider circuit increases, undesirable parasitic effects on the MOSFETs as such switch elements increase. The capacitance and on-resistance increase as a whole, making it more susceptible to noise and making it impossible to obtain a stable reference voltage by adjusting and setting it with high precision.

An object of the present invention is to provide a selection circuit that can improve noise resistance.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a plurality of switch elements are connected to a joint node of a plurality of series-connected resistance elements constituting a resistance voltage divider circuit.
The devices are connected to form a hierarchical circuit network having a tree structure, and each of the switch devices at the highest level among the switch devices is controlled by a selection signal outputted from a decoder circuit.

[For production]

According to the above-mentioned means, each of the highest switching elements among the switching elements is switch-controlled by the selection signal output from the decoder circuit, so that the hierarchy level is determined according to the number of bits of the control signal supplied to the decoder circuit. The number of layers of switch elements forming the physical network is reduced, thereby achieving improved noise resistance.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of a selection circuit according to the present invention. The circuit shown in the figure is applied to a reference voltage generation circuit, and is formed by a known semiconductor integrated circuit manufacturing technique.

In the figure, 1 is a reference voltage generation source such as a bandgap reference type, and although its details are not shown, for example, the mutual threshold voltage of MO8FE1' with a P-type gate and a MOSFET with an N-type gate is A configuration can be adopted in which the reference voltage Vref1 is generated based on the difference.

Reference voltage Vref output from such reference voltage generation source 1
, in order to be able to adjust the level of the reference voltage V
A differential amplifier circuit 2 is provided which receives ref at its non-inverting input terminal, and the output voltage of the differential amplifier circuit 2 is sent to the inverting input terminal of the differential amplifier circuit via a selection circuit 3 serving as a resistive voltage divider circuit. By feeding back and adjusting and setting the voltage dividing ratio to be selected by the selection circuit 3, the reference voltage Vref whose gain has been adjusted to a desired level is applied to the differential amplifier circuit 2.
It can be obtained from the output terminal.

The selection circuit 3 has, for example, 64 resistance elements R1 to R64 connected in series between the output terminal of the differential amplifier circuit 2 and the ground terminal Gnd, and a coupling node of each resistance element including the termination. One of N1 to N64 is selectively connected to the inverting input terminal of the differential amplifier circuit 2 based on a combination of levels of 6-bit external control signals Tl to T6 to selectively form a feedback path. It is.

The above-mentioned return route is not particularly limited, but the return route may be divided into two
1i! The basic configuration is a J-layer morning branch network.

That is, such a dendritic circuit includes 16 N-channel type MOSFETs Q1, Q1, 6, and the MO8FETs Q, o+ to Q, each having its drain coupled to the inverting input terminal of the differential amplifier circuit 2. , 32 N-channel type MOS FET Q20 each having a drain coupled to each source so as to be branched into two from 16 sources.
+ to Q237, and the above MOS FET Q
2 o 1 to Q7, 64 N with drains connected to the sources so as to be branched into two from the sources of Q7, 7.
Channel type MO8FETQ3. , to Q364, and the sources of the lowest MO8FETs Q3o to Q364 are coupled to the nodes N ] to NN6, respectively.

The switching operations of MO8FETQ, . This is performed by a decoder circuit DEC that selectively turns on one of Q1 to Ql and 6. That is, the external control signals T1 to T4 are converted into complementary level signals through the inverter circuit IVI, the inverter circuit IV], and the inverter circuit IV2, respectively, and the converted 4-bit complementary level signal is 16 A four-person Noah gate circuit G. 1 to G J G in different combinations. Such Noagu 1~Circuit G.

, to G, 6 are the corresponding M O
S FETQ,. , to Q, 16 gates 1 to 16, thereby providing 4-bit external control signals T1 to T4.
One of the MO8FETQ, . . . , Q1, 6 is selectively turned on depending on the combination of levels of

The above intermediate MOS FFT Q2ns to Q23. The gates of the circuits receive, at alternate positions, signals of complementary levels formed by the external control signal T5 being supplied to the inverter circuit IV3 and the inverter circuits IV3 and IV4, and the gates of Both of the two branched MOSFETs are switched in a complementary manner. The gates of the lowest MOSFETQ 30□ to Q364 are also connected to the external control signal T6 as in the above case.
The MOSFETs on one side of the two branched double-sevens are switched in a complementary manner depending on the level of the external control signal T6, and one of the two MOSFETs is switched in a complementary manner according to the level of the external control signal T6. .

Therefore, depending on the combination of levels of the external control signals T1 to T4, the highest MO8FET Q1°1 to Q,1
When one of 6 is turned on, the middle MO8
FETQ,. Among □ to Q23□, a pair of M branches from the first MOSFET in the on state to an intermediate position.
One of the OSFETs is turned on depending on the level of the external control signal T5. Furthermore, the lowest M O
Among S F E T Q a o 1 to Q364,
One of the pair of MOSFETs branching downward from the intermediate MOSFET in the on state is turned on in accordance with the level of the external control signal T6. In this way, one of the nodes N1 to N64 is selectively connected to the inverting input terminal of the differential amplifier circuit 2 according to the combination of levels of the external control signals T1 to T6, thereby providing a predetermined signal. A return path is selectively formed. When such a feedback path is selectively formed, a predetermined resistance voltage division ratio is set according to the resistance value of the resistance element included in the feedback path and the resistance value of the resistance element not included in the feedback path. Thereby, the differential amplifier circuit 2 performs an amplification operation according to the voltage negatively fed back via the feedback path, and outputs a predetermined reference voltage vref2 whose gain has been adjusted.

Here, the levels of the external control signals T1 to T6 are selectively set in combination according to the error in the reference voltage Vref1 due to process variations in the reference voltage source 1 and the level of the finally required reference voltage Vrefz. For example, it is supplied from a fuse cutting circuit (not shown).

Next, the effects of the above embodiment will be explained.

(1) Depending on the combination of levels of external control signals T] to T6 output from a fuse cutting circuit (not shown), etc.
When a feedback path from any one of the nodes N1- to N64 to the inverting input terminal of the operational amplifier circuit 2 is selectively formed, the ON-state MOSFETs connected in series included in the feedback path are There will be 3 pieces. This inputs 4-bit external control signals T1- to T4 and changes the level of any one of 16 types of selection signals formed according to the combination of the signal levels to a selection such as high level. This is because the decoder circuit DEC that makes the selection circuit 3 is renumbered. As a result, the dendritic network configured with two branches is
16 MO8F ET Q, which are switched based on the output signal from the decoder circuit DEC. , to Q
With 4 and 6 at the top, it is possible to select 6 IU return routes in a total of 3 hierarchies. If the code decoder circuit D E
If C is not adopted, a 6-layer dendritic circuit with two branches will be required to select 64 feedback paths based on the external sg signal of 6 bits.

(2) J-, based on the above effect, MOS FT! included in the selected return path! : Since the number of T decreases, such M
Undesired capacitance parasitic to OSFET and the MO8
Since the on-resistance of FJ': ']' is reduced as a whole, noise resistance can be improved.

(3) The above effects enable highly accurate gain adjustment in the reference voltage generation circuit which is supposed to output a stable voltage in the first place.

(71) In particular, in the embodiment described in section 1, the number of components required for the 1 selection circuit 3 is reduced by employing a decoder circuit I)EC that decodes a part of the 6-bit external control signals T1 to T6. In other words, the area occupied by the selection circuit 3 can be reduced. For example, 4 above
When a circuit is constructed from a CMO8 circuit, the number of elements required for it is usually 8, so
The number of MOSFETs required to configure the NOAG 1~circuit and the bifurcated three-layer dendritic network of the above embodiment is 2/1.0. On the other hand, if a decoder circuit that decodes all of the 6-bit external control signals] to T6 is employed, such a decoder circuit includes 64 circuits, and one
~When a circuit is configured with CM and OS circuits, the number of MOSFETs required for it is normally 12, so in such a configuration, a total of 824 MOSFETs are required.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, 64 return paths can be selected based on a 6-bit external control signal, but the present invention is not limited to this, and the scale can be changed as appropriate. In that case, all switching elements may be operated by the output signal of the decoder circuit, if the viewpoint of reducing the number of constituent elements of the selection circuit and the area occupied by them is ignored. Further, the decoder circuit is not limited to being configured by a NOR gate circuit, but may be configured by a gate circuit.

In the above explanation, the invention made by the present inventor is mainly applied to a gain adjustment circuit in a reference voltage generation circuit, which is the background field of application. The present invention can be applied to various selection circuits for selecting passive elements. The present invention can be applied to conditions where passive elements are selected based on at least the output from the decoder circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, a plurality of switch elements are connected to a joint node of a plurality of series-connected resistance elements constituting a resistance voltage divider circuit.
The configuration of the selection circuit is such that the switches are connected to form a hierarchical circuit network with a branch tree structure, and each of the switch elements at the highest level among the switch elements is controlled by a selection signal output from the decoder circuit. The number of layers of switch elements forming a hierarchical network is reduced without significantly increasing the number of elements and the occupied area, thereby achieving improved noise resistance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a selection circuit according to the present invention. ]... Reference voltage generation source, 2... Differential amplifier circuit, 3...
... Selection circuit, R1 to R64... Resistance element, N1 to N64... Node, T1 to T6... External control signal ', Q +o, to Q, 7.・= MOS F
E T , Q2o1 to Q232-MOS F E
T, Q, ... to Q364-MOS FET, D
E C...Decoder circuit, Go to G I G.
...Noah gate circuit.

Claims (1)

[Claims] 1. A selection signal is formed based on a plurality of passive elements connected in series, a plurality of switch elements connected to a coupling node of the passive elements, and a control signal of a predetermined number of bits, and the selection signal is A selection circuit comprising: a decoder circuit that supplies a signal to the gate of the switching element to switch a predetermined one of the switching elements. 2. The plurality of switch elements form a hierarchical circuit network having a binary tree structure, and each switch element at the top level thereof is switch-controlled by a selection signal output from the decoder circuit. A selection circuit according to claim 1. 3. Claim 1 or 2, wherein the passive element is a resistance element included in a resistance voltage divider circuit.
Selection circuit described in section.