CN116798337B - Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment - Google Patents
Electromagnetic interference suppression circuit, source driver, display panel and electronic equipment Download PDFInfo
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- CN116798337B CN116798337B CN202311086319.6A CN202311086319A CN116798337B CN 116798337 B CN116798337 B CN 116798337B CN 202311086319 A CN202311086319 A CN 202311086319A CN 116798337 B CN116798337 B CN 116798337B
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- 230000001629 suppression Effects 0.000 title claims abstract description 36
- 230000003139 buffering effect Effects 0.000 claims abstract description 41
- 230000007704 transition Effects 0.000 claims abstract description 13
- 239000000872 buffer Substances 0.000 claims description 120
- 238000000034 method Methods 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
Abstract
The application relates to an electromagnetic interference suppression circuit, a source driver, a display panel and an electronic device, wherein the electromagnetic interference suppression circuit is applied to the source driver, the source driver comprises a vertical scanning counter and a digital latch, the circuit comprises a buffering and frequency dividing unit, a first multiplexer and a second multiplexer, the electromagnetic interference suppression circuit can output two paths of main frequency clock signals through the cooperation of the buffering and frequency dividing unit, the first multiplexer and the second multiplexer, when the scanning counting signal is even or odd by utilizing the vertical scanning characteristic in the working process of the source driver, the first multiplexer and the second multiplexer simultaneously output two paths of main frequency clock signals to drive the digital latch, and as the frequencies of the first main frequency clock signal and the second main frequency clock signal are the same and the transition time is different, the electromagnetic interference caused by the circuit output current of the digital latch at the same time is greatly reduced, and the corresponding data output is not interfered.
Description
Technical Field
The present application relates to the field of display, and in particular, to an electromagnetic interference suppression circuit, a source driver, a display panel, and an electronic device.
Background
In conventional display panel driving, a source driver receives timing control data (Timing Controller, TCON) sent from a timing controller, parses the timing control data through an internal clock recovery circuit and a digital circuit, and outputs driving voltages to the display panel.
The timing control data generally includes clock signals and RGB data, and when the source driver is turned on, an internal digital circuit receives the timing control data, and the clock signals in the timing control data are used as a main clock of the digital circuit in the source driver after passing through the frequency divider. The digital circuit uses the main frequency clock as a design core, so that a remarkable electromagnetic interference effect of the frequency band of the main frequency clock can be generated.
Disclosure of Invention
In view of the above, the present application provides an electromagnetic interference suppression circuit, a source driver, a display panel and an electronic device, which can reduce electromagnetic interference radiation caused by a main clock of a digital circuit in the source driver.
An electromagnetic interference suppression circuit for a source driver including a vertical scan counter and a digital latch, the electromagnetic interference suppression circuit comprising:
the buffer and frequency-dividing unit is used for receiving an initial clock signal sent by an external device, respectively buffering and outputting a first clock signal and a second clock signal according to the initial clock signal, and respectively performing frequency-dividing and re-buffering processing on the first clock signal and the second clock signal so as to output a first main frequency clock signal and a second main frequency clock signal, wherein the transition time of each of the first main frequency clock signal and the second main frequency clock signal is different.
The first multiplexer is electrically connected with the buffering and frequency-dividing unit and is used for being electrically connected with the vertical scanning counter and the digital latch respectively.
The first multiplexer is used for receiving the scanning counting signal output by the vertical scanning counter, receiving the second main frequency clock signal output by the buffering and frequency dividing unit and outputting the second main frequency clock signal to the digital latch when the scanning counting signal is even, and receiving the first main frequency clock signal output by the buffering and frequency dividing unit and outputting the first main frequency clock signal to the digital latch when the scanning counting signal is odd.
The second multiplexer is electrically connected with the buffering and frequency dividing unit and is electrically connected with the vertical scanning counter and the digital latch.
The second multiplexer is used for receiving the scanning counting signal output by the vertical scanning counter, receiving the first main frequency clock signal output by the buffering and frequency dividing unit and outputting the first main frequency clock signal to the digital latch when the scanning counting signal is even, and receiving the second main frequency clock signal output by the buffering and frequency dividing unit and outputting the second main frequency clock signal to the digital latch when the scanning counting signal is odd.
In one embodiment, the buffering and frequency dividing unit includes:
the first buffer unit is electrically connected with the external device, receives the initial clock signal and respectively buffers and outputs a first clock signal and a second clock signal.
The frequency dividing unit is electrically connected with the first buffer unit, receives the first clock signal and the second clock signal output by the first buffer unit, and respectively divides frequencies to obtain a first initial main frequency clock signal and a second initial main frequency clock signal.
The second buffer unit is electrically connected with the frequency removing unit, the first multiplexer and the second multiplexer respectively, and is used for receiving the first initial main frequency clock signal and the second initial main frequency clock signal output by the frequency removing unit, respectively carrying out buffer processing to obtain a first main frequency clock signal and a second main frequency clock signal, and outputting the first main frequency clock signal and the second main frequency clock signal to the first multiplexer and the second multiplexer.
In one embodiment, the frequency removing unit includes:
the first frequency dividing unit is electrically connected with the first buffer unit and the second buffer unit and is used for receiving the first clock signal output by the first buffer unit and dividing the frequency so as to obtain a first initial main frequency clock signal and outputting the first initial main frequency clock signal to the second buffer unit.
The second frequency dividing unit is electrically connected with the first buffer unit and the second buffer unit and is used for receiving the second clock signal output by the first buffer unit and dividing the frequency so as to obtain a second initial main frequency clock signal and outputting the second initial main frequency clock signal to the second buffer unit.
In one embodiment, the second buffer unit includes:
the first buffer subunit is electrically connected with the first frequency-dividing unit and the first multiplexer and is used for receiving the first initial main frequency clock signal output by the first frequency-dividing unit and performing buffer processing so as to obtain the first main frequency clock signal and output the first main frequency clock signal to the first multiplexer and the second multiplexer.
The second buffer subunit is electrically connected with the second frequency-dividing unit and the second multiplexer and is used for receiving the second initial main frequency clock signal output by the second frequency-dividing unit and performing buffer processing so as to obtain a second main frequency clock signal and outputting the second main frequency clock signal to the first multiplexer and the second multiplexer.
In an embodiment, the electromagnetic interference suppression circuit further includes a third buffer unit, an input end of the third buffer unit is electrically connected to the first multiplexer and the second multiplexer, and an output end of the third buffer unit is electrically connected to the digital latch.
The third buffer unit is used for receiving the first main frequency clock signal or the second main frequency clock signal output by the first multiplexer and the second multiplexer respectively, and performing buffer processing to output the corresponding buffer main frequency clock signal to the digital latch.
In one embodiment, the third buffer unit includes a third buffer subunit and a fourth buffer subunit, an input end of the third buffer subunit is electrically connected with the first multiplexer, an output end of the third buffer subunit is electrically connected with the digital latch, an input end of the fourth buffer subunit is electrically connected with the second multiplexer, and an output end of the fourth buffer subunit is electrically connected with the digital latch.
The third buffer subunit is configured to receive the first main frequency clock signal or the second main frequency clock signal output by the first multiplexer, and perform buffering processing to output a corresponding buffered main frequency clock signal to the digital latch;
the fourth buffer subunit is configured to receive the first main frequency clock signal or the second main frequency clock signal output by the second multiplexer, and perform buffering processing to output a corresponding buffered main frequency clock signal to the digital latch.
In one embodiment, the digital latch includes a first latch unit and a second latch unit, the first multiplexer is electrically connected to the first latch unit, and the second multiplexer is electrically connected to the second latch unit.
The first multiplexer is used for outputting the second main frequency clock signal to the first latch unit when the scanning counting signal is even, and outputting the first main frequency clock signal to the second latch unit when the scanning counting signal is odd.
The second multiplexer is used for outputting the first main frequency clock signal to the first latch unit when the scanning counting signal is even, and outputting the second main frequency clock signal to the second latch unit when the scanning counting signal is odd.
In addition, a source driver is provided, and the source driver comprises the electromagnetic interference suppression circuit.
In addition, a display panel is also provided, and the display panel comprises the source driver.
In addition, an electronic device is provided, and the electronic device comprises the display panel.
The electromagnetic interference suppression circuit is applied to a source driver, the source driver comprises a vertical scanning counter and a digital latch, the vertical scanning counter and the digital latch are electrically connected, the first multiplexer is used for receiving a scanning count signal output by the vertical scanning counter, when the scanning count signal is even, the second main clock signal output by the receiving buffer and the frequency dividing unit is output to the digital latch, when the scanning count signal is odd, the first main clock signal output by the receiving and frequency dividing unit is output to the digital latch, the first main clock signal and the second main clock signal are output to the digital latch, the first multiplexer is electrically connected with the vertical scanning counter and the digital latch, and is used for receiving the scanning count signal output by the vertical scanning counter, when the scanning count signal is even, the second main clock signal output by the receiving buffer and the frequency dividing unit is output to the digital latch, when the scanning count signal is odd, the first main clock signal output by the receiving buffer and the frequency dividing unit is output to the digital latch, the first main clock signal and the second main clock signal is output to the digital latch, and the first multiplexer is electrically connected with the vertical scanning counter and the digital latch, and the first multiplexer is used for receiving the scanning count signal output by the vertical scanning counter, when the scanning count signal is even, the second main clock signal output by the receiving buffer and the digital clock signal is output by the digital latch, and the digital latch is output by the digital clock The electromagnetic interference suppression circuit can output two paths of main frequency clock signals by matching the first multiplexer and the second multiplexer, when the scanning counting signal is even or odd, the first multiplexer and the second multiplexer simultaneously output two paths of main frequency clock signals to drive the digital latch, and because the first main frequency clock signal and the second main frequency clock signal have the same frequency and different transition time, the electromagnetic interference caused by the circuit output current corresponding to the digital latch at the same time is greatly reduced, and the data output corresponding to the digital latch is not interfered.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit block diagram of an electromagnetic interference suppression circuit according to an embodiment of the present application;
fig. 2 is a circuit block diagram of another electromagnetic interference suppression circuit according to an embodiment of the present application;
fig. 3 is a circuit block diagram of a frequency removing unit according to an embodiment of the present application;
FIG. 4 is a block diagram of a circuit configuration of another electromagnetic interference suppression circuit according to an embodiment of the present application;
fig. 5 is a circuit block diagram of still another electromagnetic interference suppression circuit according to an embodiment of the present application;
fig. 6 is a circuit block diagram of another electromagnetic interference suppression circuit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. Based on the embodiments in the present application. The various embodiments described below and their technical features can be combined with each other without conflict.
As shown in fig. 1, an electromagnetic interference suppression circuit 100 is provided for a source driver 10, the source driver 10 including a vertical scan counter 20 and a digital latch 30, the electromagnetic interference suppression circuit 100 comprising:
the buffering and frequency-dividing unit 110 is configured to receive an initial clock signal sent by an external device, respectively buffer and output a first clock signal and a second clock signal according to the initial clock signal, and respectively perform frequency-dividing and re-buffering processing on the first clock signal and the second clock signal to output a first main frequency clock signal and a second main frequency clock signal, where frequencies of the first main frequency clock signal and the second main frequency clock signal are the same and transition times are different.
The first main frequency clock signal and the second main frequency clock signal have the same frequency and different transition time, which indicate that the frequency removing process is the same and the transition time is different, and indicate that the buffer processing process is different.
In one embodiment, the transition times of the first clock signal and the second clock signal are different, i.e. the buffering processes corresponding to the first clock signal and the second clock signal are different.
The first multiplexer 120 is electrically connected to the buffering and frequency dividing unit 110, and is electrically connected to the vertical scan counter 20 and the digital latch 30, respectively.
The first multiplexer 120 is configured to receive the scan count signal output by the vertical scan counter 20, receive the second main frequency clock signal output by the buffering and frequency dividing unit 110 and output the second main frequency clock signal to the digital latch 30 when the scan count signal is even, and receive the first main frequency clock signal output by the buffering and frequency dividing unit 110 and output the first main frequency clock signal to the digital latch 30 when the scan count signal is odd.
The second multiplexer 130 is electrically connected to the buffer and frequency divider 110, and is electrically connected to the vertical scan counter 20 and the digital latch 30.
The second multiplexer 130 is configured to receive the scan count signal output by the vertical scan counter 20, receive the first main frequency clock signal output by the buffering and frequency dividing unit 110 and output the first main frequency clock signal to the digital latch 30 when the scan count signal is even, and receive the second main frequency clock signal output by the buffering and frequency dividing unit 110 and output the second main frequency clock signal to the digital latch 30 when the scan count signal is odd.
The electromagnetic interference suppression circuit 100 is configured to output two main frequency clock signals by the buffer and frequency divider 110, the first multiplexer 120 and the second multiplexer 130, and the electromagnetic interference suppression circuit 100 is configured to output two main frequency clock signals by the first multiplexer 120 and the second multiplexer 130 to drive the digital latch 30 when the scanning count signal is even or odd by utilizing the vertical scanning characteristic of the source driver 10 during operation, and the electromagnetic interference caused by the circuit output current corresponding to the digital latch 30 at the same time is greatly reduced due to the same frequency and different transition time of the first main frequency clock signal and the second main frequency clock signal, while the data output corresponding to the digital latch 30 is not interfered.
In one embodiment, as shown in fig. 2, the buffering and frequency dividing unit 110 includes:
the first buffer unit 112 is electrically connected to an external device, receives an initial clock signal, and buffers and outputs a first clock signal and a second clock signal, respectively.
The frequency dividing unit 114 is electrically connected to the first buffer unit 112, and receives the first clock signal and the second clock signal output by the first buffer unit 112 and divides the frequency respectively to obtain a first initial main frequency clock signal and a second initial main frequency clock signal.
The second buffer unit 116 is electrically connected to the frequency divider 114, the first multiplexer 120, and the second multiplexer 130, and is configured to receive the first initial main frequency clock signal and the second initial main frequency clock signal output by the frequency divider 114, and perform buffering processing to obtain a first main frequency clock signal and a second main frequency clock signal, and output the first main frequency clock signal and the second main frequency clock signal to the first multiplexer 120 and the second multiplexer 130.
In this embodiment, by the cooperation of the first buffer unit 112, the frequency dividing unit 114 and the second buffer unit 116, the first main frequency clock signal and the second main frequency clock signal can be output to the first multiplexer 120 and the first main frequency clock signal and the second main frequency clock signal can be output to the second multiplexer 130, and the frequencies of the first main frequency clock signal and the second main frequency clock signal are the same and the transition times are different.
In one embodiment, as shown in fig. 3, the frequency dividing unit 114 includes:
the first frequency dividing unit 114a is electrically connected to the first buffer unit 112 and the second buffer unit 116, and is configured to receive the first clock signal output by the first buffer unit 112 and perform frequency division to obtain a first initial main frequency clock signal and output the first initial main frequency clock signal to the second buffer unit 116.
The second frequency dividing unit 114b is electrically connected to the first buffer unit 112 and the second buffer unit 116, and is configured to receive the second clock signal output by the first buffer unit 112 and perform frequency division to obtain a second initial main frequency clock signal and output the second initial main frequency clock signal to the second buffer unit 116.
In this embodiment, the frequency dividing unit is one of frequency dividing circuits, and by performing frequency division on the first frequency dividing unit 114a and the second frequency dividing unit 114b, a first initial main frequency clock signal can be obtained and output to the second buffer unit 116, and a second initial main frequency clock signal can be obtained and output to the second buffer unit 116.
In one embodiment, as shown in fig. 4, the second buffer unit 116 includes:
the first buffer subunit 116a is electrically connected to the first frequency divider unit 114a and the first multiplexer 120, and is configured to receive the first initial primary frequency clock signal output by the first frequency divider unit 114a, perform buffering processing, and obtain a first primary frequency clock signal, and output the first primary frequency clock signal to the first multiplexer 120 and the second multiplexer 130.
The second buffer subunit 116b is electrically connected to the second frequency divider unit 114b and the second multiplexer 130, and is configured to receive the second initial primary frequency clock signal output by the second frequency divider unit 114b, and perform buffering processing to obtain a second primary frequency clock signal, and output the second primary frequency clock signal to the first multiplexer 120 and the second multiplexer 130.
In this embodiment, the buffering processes of the first buffering subunit 116a and the second buffering subunit 116b are different, so that the transition times of the first main clock signal and the second main clock signal are different.
In one embodiment, the number of buffers included in each of the first buffer subunit 116a and the second buffer subunit 116b is different.
In one embodiment, as shown in fig. 5, the electromagnetic interference suppression circuit 100 further includes a third buffer unit 118, wherein an input end of the third buffer unit 118 is electrically connected to the first multiplexer 120 and the second multiplexer 130, respectively, and an output end of the third buffer unit 118 is electrically connected to the digital latch 30.
The third buffer unit 118 is configured to receive the first main frequency clock signal or the second main frequency clock signal output by the first multiplexer 120 and the second multiplexer 130, and perform buffering processing to output the corresponding buffered main frequency clock signals to the digital latch 30.
In this embodiment, the output of each of the first multiplexer 120 and the second multiplexer 130 is buffered by the third buffer unit 118, which is beneficial to the stability of the output signal.
In one embodiment, as shown in fig. 5, the third buffer unit 118 includes a third buffer subunit 118a and a fourth buffer subunit 118b, the input end of the third buffer subunit 118a is electrically connected to the first multiplexer 120, the output end of the third buffer subunit 118a is electrically connected to the digital latch 30, the input end of the fourth buffer subunit 118b is electrically connected to the second multiplexer 130, and the output end of the fourth buffer subunit 118b is electrically connected to the digital latch 30.
The third buffer subunit 118a is configured to receive the first main frequency clock signal or the second main frequency clock signal output by the first multiplexer 120, and perform buffering processing to output a corresponding buffered main frequency clock signal to the digital latch 30.
The fourth buffer subunit 118b is configured to receive the first main frequency clock signal or the second main frequency clock signal output by the second multiplexer 130, and perform buffering processing to output a corresponding buffered main frequency clock signal to the digital latch 30.
In this embodiment, by the cooperation of the third buffer subunit 118a and the fourth buffer subunit 118b, the output signal corresponding to the first multiplexer 120 and the output signal corresponding to the second multiplexer 130 can be respectively sent to the digital latch 30, and the digital latch 30 latches and outputs the input data after receiving the corresponding output signals as clock driving signals.
In one embodiment, as shown in fig. 5, the digital latch 30 includes a first latch unit 31 and a second latch unit 32, a third buffer subunit 118a is electrically connected to the first latch unit 31, and a fourth buffer subunit 118b is electrically connected to the second latch unit 32.
In this embodiment, the first multiplexer 120 is configured to output the second main frequency clock signal to the first latch unit 31 through the third buffer subunit 118a when the scan count signal is even, and output the first main frequency clock signal to the second latch unit 32 through the third buffer subunit 118a when the scan count signal is odd.
The second multiplexer 130 is configured to output the first main frequency clock signal to the first latch unit 31 through the fourth buffer subunit 118b when the scan count signal is even, and output the second main frequency clock signal to the second latch unit 32 through the fourth buffer subunit 118b when the scan count signal is odd.
In this embodiment, through the cooperation of the first multiplexer 120, the third buffer subunit 118a, the second multiplexer 130 and the fourth buffer subunit 118b, two main frequency clock signals can be output to the digital latch unit 30, that is, by utilizing the vertical scanning characteristic of the source driver 10 in the operation process, when the scanning count signal is even or odd, two main frequency clock signals are output by the first multiplexer 120 and the second multiplexer 130 to drive the digital latch, and because the frequencies of the first main frequency clock signal and the second main frequency clock signal are the same and the transition times are different, the electromagnetic interference caused by the circuit output currents corresponding to the digital latch at the same time is greatly reduced, and the data output corresponding to the digital latch 30 is not interfered.
In another embodiment, as shown in fig. 6, the digital latch 30 includes a first latch unit 31 and a second latch unit 32, the first multiplexer 120 is electrically connected to the first latch unit 31, and the second multiplexer 130 is electrically connected to the second latch unit 32.
In one embodiment, the first latch unit 31 and the second latch unit 32 may be understood as dividing each output port in the digital latch 30 into two parts according to port positions, for example, the first latch unit 31 may be a left part port of the digital latch 30 and the second latch unit 32 may be understood as a right part port of the digital latch 30.
The first multiplexer 120 is configured to output the second main frequency clock signal to the first latch unit 31 when the scan count signal is even, and output the first main frequency clock signal to the second latch unit 32 when the scan count signal is odd.
The second multiplexer 130 is configured to output the first main frequency clock signal to the first latch unit 31 when the scan count signal is even, and output the second main frequency clock signal to the second latch unit 32 when the scan count signal is odd.
In this embodiment, by the cooperation of the first multiplexer 120 and the second multiplexer 130, two main frequency clock signals can be output to the digital latch unit 30, that is, by utilizing the vertical scanning characteristic in the operation process of the source driver 10, when the scanning count signal is even or odd, the two main frequency clock signals are simultaneously output by the first multiplexer 120 and the second multiplexer 130 to drive the digital latch 30, and because the frequencies of the first main frequency clock signal and the second main frequency clock signal are the same and the transition times are different, the electromagnetic interference caused by the circuit output currents corresponding to the digital latch 30 at the same time is greatly reduced, and the data output corresponding to the digital latch 30 is not interfered.
In addition, as shown in fig. 1, a source driver 10 is provided, and the source driver 10 includes the electromagnetic interference suppression circuit 100.
In addition, a display panel is provided, and the display panel comprises the source driver 10.
In addition, an electronic device is provided, and the electronic device comprises the display panel.
The division of the units in the electromagnetic interference suppression circuit 100 is only for illustration, and in other embodiments, the electromagnetic interference suppression circuit 100 may be divided into different units as needed to perform all or part of the functions of the electromagnetic interference suppression circuit 100.
That is, the foregoing embodiments of the present application are merely examples, and are not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, such as the combination of technical features of the embodiments, or direct or indirect application in other related technical fields, are included in the scope of the present application.
In addition, the present application may be identified by the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, the word "e.g." is used to mean "serving as an example, instance, or illustration". Any embodiment described as "for example" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (10)
1. An electromagnetic interference suppression circuit for use in a source driver, the source driver including a vertical scan counter and a digital latch, the electromagnetic interference suppression circuit comprising:
the buffer and frequency-dividing unit is used for receiving an initial clock signal sent by an external device, respectively buffering and outputting a first clock signal and a second clock signal according to the initial clock signal, and respectively performing frequency-dividing and re-buffering processing on the first clock signal and the second clock signal so as to output a first main frequency clock signal and a second main frequency clock signal, wherein the frequencies of the first main frequency clock signal and the second main frequency clock signal are the same and the transition times are different;
the first multiplexer is electrically connected with the buffering and frequency-dividing unit and is used for being electrically connected with the vertical scanning counter and the digital latch respectively;
the first multiplexer is configured to receive a scan count signal output by the vertical scan counter, receive the second main frequency clock signal output by the buffering and frequency dividing unit and output the second main frequency clock signal to the digital latch when the scan count signal is even, and receive the first main frequency clock signal output by the buffering and frequency dividing unit and output the first main frequency clock signal to the digital latch when the scan count signal is odd;
the second multiplexer is electrically connected with the buffering and frequency-dividing unit and is electrically connected with the vertical scanning counter and the digital latch;
the second multiplexer is configured to receive a scan count signal output by the vertical scan counter, receive the first main frequency clock signal output by the buffering and frequency dividing unit and output the first main frequency clock signal to the digital latch when the scan count signal is even, and receive the second main frequency clock signal output by the buffering and frequency dividing unit and output the second main frequency clock signal to the digital latch when the scan count signal is odd.
2. The electromagnetic interference suppression circuit according to claim 1, wherein the buffering and frequency dividing unit includes:
the first buffer unit is electrically connected with the external device, and is used for receiving the initial clock signal and buffering and outputting the first clock signal and the second clock signal;
the frequency dividing unit is electrically connected with the first buffer unit, receives the first clock signal and the second clock signal output by the first buffer unit, and respectively divides frequencies to obtain a first initial main frequency clock signal and a second initial main frequency clock signal;
the second buffer unit is electrically connected with the frequency removing unit, the first multiplexer and the second multiplexer respectively, and is used for receiving the first initial main frequency clock signal and the second initial main frequency clock signal output by the frequency removing unit, respectively performing buffer processing to obtain a first main frequency clock signal and a second main frequency clock signal, and outputting the first main frequency clock signal and the second main frequency clock signal to the first multiplexer and the second multiplexer.
3. The electromagnetic interference suppression circuit according to claim 2, wherein the frequency dividing unit includes:
the first frequency dividing unit is electrically connected with the first buffer unit and the second buffer unit and is used for receiving the first clock signal output by the first buffer unit and dividing the frequency to obtain a first initial main frequency clock signal and outputting the first initial main frequency clock signal to the second buffer unit;
the second frequency dividing unit is electrically connected with the first buffer unit and the second buffer unit and is used for receiving the second clock signal output by the first buffer unit and dividing the frequency so as to obtain a second initial main frequency clock signal and outputting the second initial main frequency clock signal to the second buffer unit.
4. The electromagnetic interference suppression circuit according to claim 3, wherein the second buffer unit includes:
the first buffer subunit is electrically connected with the first frequency dividing unit and the first multiplexer and is used for receiving a first initial main frequency clock signal output by the first frequency dividing unit and performing buffer processing so as to obtain a first main frequency clock signal and outputting the first main frequency clock signal to the first multiplexer and the second multiplexer;
the second buffer subunit is electrically connected with the second frequency-dividing unit and the second multiplexer and is used for receiving the second initial main frequency clock signal output by the second frequency-dividing unit and performing buffer processing so as to obtain a second main frequency clock signal and output the second main frequency clock signal to the first multiplexer and the second multiplexer.
5. The emi suppression circuit of claim 2, further comprising a third buffer unit having an input electrically connected to the first multiplexer and the second multiplexer, respectively, and an output electrically connected to the digital latch;
the third buffer unit is configured to receive the first main frequency clock signal or the second main frequency clock signal output by each of the first multiplexer and the second multiplexer, and perform buffering processing to output a corresponding buffered main frequency clock signal to the digital latch.
6. The emi suppression circuit of claim 5, wherein the third buffer unit includes a third buffer subunit and a fourth buffer subunit, the input of the third buffer subunit is electrically connected to the first multiplexer, the output of the third buffer subunit is electrically connected to the digital latch, the input of the fourth buffer subunit is electrically connected to the second multiplexer, and the output of the fourth buffer subunit is electrically connected to the digital latch;
the third buffer subunit is configured to receive the first main frequency clock signal or the second main frequency clock signal output by the first multiplexer, and perform buffering processing to output a corresponding buffered main frequency clock signal to the digital latch;
the fourth buffer subunit is configured to receive the first main frequency clock signal or the second main frequency clock signal output by the second multiplexer, and perform buffering processing to output a corresponding buffered main frequency clock signal to the digital latch.
7. The emi suppression circuit of claim 1, wherein the digital latch includes a first latch unit and a second latch unit, the first multiplexer being configured to be electrically connected to the first latch unit, the second multiplexer being configured to be electrically connected to the second latch unit;
the first multiplexer is configured to output the second main frequency clock signal to the first latch unit when the scan count signal is even, and output the first main frequency clock signal to the second latch unit when the scan count signal is odd;
the second multiplexer is configured to output the first main frequency clock signal to the first latch unit when the scan count signal is even, and output the second main frequency clock signal to the second latch unit when the scan count signal is odd.
8. A source driver comprising the electromagnetic interference suppression circuit of any one of claims 1 to 7.
9. A display panel comprising the source driver of claim 8.
10. An electronic device comprising the display panel of claim 9.
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| CN110675791A (en) * | 2018-07-03 | 2020-01-10 | 瑞鼎科技股份有限公司 | Source driver |
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| JP2005301029A (en) * | 2004-04-14 | 2005-10-27 | Matsushita Electric Ind Co Ltd | Circuit and method for driving data of plasma display device |
| KR20090013481A (en) * | 2007-08-02 | 2009-02-05 | 삼성전자주식회사 | Source driver circuit and liquid crystal display device having the same |
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| CN116798337A (en) | 2023-09-22 |
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