CN107767827B - Compensation circuit and display device - Google Patents

Compensation circuit and display device Download PDF

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Publication number
CN107767827B
CN107767827B CN201710801439.8A CN201710801439A CN107767827B CN 107767827 B CN107767827 B CN 107767827B CN 201710801439 A CN201710801439 A CN 201710801439A CN 107767827 B CN107767827 B CN 107767827B
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switching tube
signal
tube
switch tube
control
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CN107767827A (en
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张军
李森龙
吕晶
张好好
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InfoVision Optoelectronics Kunshan Co Ltd
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InfoVision Optoelectronics Kunshan Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a compensation circuit and a display device, wherein the compensation circuit comprises: the charge pump comprises a first switching tube for receiving a first reference voltage, a second switching tube for receiving a second reference voltage, a pre-charging unit, a charging unit and a pull-down unit, wherein a second path end of the first switching tube is connected with a second path end of the second switching tube to provide an output signal, the first switching tube and the second switching tube are alternately conducted along with frame switching, and the phase of the first reference voltage is opposite to that of the second reference voltage; the pre-charging unit enables one of the first switch tube and the second switch tube to be conducted according to a preceding stage grid driving signal, the charging unit maintains the conducting or the cutting-off state of the first switch tube and the second switch tube according to a present stage grid driving signal, and the pull-down unit controls the first switch tube and the second switch tube according to a subsequent stage grid driving signal. By making the transistors in the compensation circuit work alternately, the threshold voltage drift of the transistors can be reduced and the recovery of the threshold voltage drift of the transistors can be realized.

Description

Compensation circuit and display device
Technical Field
The invention relates to the technical field of display, in particular to a compensation circuit and a display device.
Background
The liquid crystal display device is a display device in which the light transmittance of a light source is changed by utilizing a phenomenon that the alignment direction of liquid crystal molecules is changed by an electric field. Liquid crystal display devices have been widely used in mobile terminals such as mobile phones and large-sized display panels such as flat panel televisions due to advantages of good display quality, small volume, and low power consumption. Most of the liquid crystal displays in the market are projection type liquid crystal displays (lcds), which include a liquid crystal panel and a backlight module (backlight module). The liquid crystal panel has the working principle that liquid crystal molecules are placed between two parallel glass substrates, and a driving voltage is applied to the two glass substrates to control the rotation direction of the liquid crystal molecules, so that the light emission of the backlight module is modulated to generate a picture.
In recent years, the development of liquid crystal displays has shown a trend of high integration and low cost, and integrated display driving is becoming a research hotspot of flat panel display technology. The integrated display driving circuit is realized by using a switching transistor (TFT) as a peripheral circuit such as a gate driving circuit and a source driving circuit, and is formed on a TFT substrate together with a pixel switching transistor. Compared with the traditional circuit (IC) driving mode, the method adopting integrated gate driving can not only reduce the number of peripheral driving chips and the press sealing procedure thereof and reduce the cost, but also make the periphery of the display thinner, make the display module more compact and enhance the mechanical and electrical reliability. Among them, an integrated gate driving circuit based on an amorphous silicon switching tube technology has been widely studied. On one hand, the amorphous silicon TFT technology has the advantages of low process temperature, good device uniformity, low cost and the like, and is the mainstream TFT technology at present. On the other hand, the mobility of the amorphous silicon TFT can meet the requirement of the working frequency of the gate drive circuit. However, the stability of the amorphous silicon TFT is relatively poor, and a serious threshold voltage shift phenomenon occurs under a long-term voltage stress bias, thereby affecting the life of the circuit.
In the design of the integrated gate driving circuit in the prior art, the threshold voltage drift of the pull-down switching tube is reduced by adopting a low-voltage direct current bias, a double pull-down structure, a high-frequency pulse bias or a mode of reducing the duty ratio of a voltage signal. The methods can achieve the purpose of prolonging the service life of the integrated gate drive circuit to a certain extent, but because the pull-down switch tube is often under unipolar (voltage is positive) bias and can be subjected to direct-current voltage stress or pulse voltage stress with positive polarity for a long time, the threshold voltage drift of the pull-down switch tube is still very large after long-time work, and the reduction of the conductive capability can occur, so that the service life of the integrated gate drive circuit is seriously influenced. Therefore, how to more effectively suppress the threshold voltage drift of the key switch tube in the circuit and prolong the lifetime of the integrated Gate driving circuit is a key problem in the design of the television panel GIA (integrated Gate driving in Array).
Disclosure of Invention
In order to solve the problems of the prior art, the invention provides a compensation circuit and a display device.
According to an aspect of the present invention, a compensation circuit applied to a display device is provided, including a first switch tube, a second switch tube, a pre-charging unit, a charging unit, and a pull-down unit, where a first path end of the first switch tube receives a first reference voltage, a first path end of the second switch tube receives a second reference voltage, and a second path end of the first switch tube and a second path end of the second switch tube are connected to provide an output signal; the pre-charging unit is enabled by a preceding stage grid driving signal, and when the preceding stage grid driving signal is effective, the pre-charging unit respectively provides a first control signal and a second control signal to the control end of the first switch tube and the control end of the second switch tube so as to enable one of the first switch tube and the second switch tube to be conducted; the charging unit is enabled by a current-stage grid driving signal, and when the current-stage grid driving signal is effective, the charging unit maintains the on or off state of the first switching tube and the second switching tube; and the pull-down unit is enabled by a post-stage gate driving signal, and when the post-stage gate driving signal is valid, the pull-down unit respectively provides the first control signal and the second control signal to the control end of the first switching tube and the control end of the second switching tube, the first switching tube and the second switching tube are alternately switched on along with frame switching, and the phase of the first reference voltage is opposite to that of the second reference voltage.
Preferably, the compensation circuit further comprises a first low-frequency signal input terminal and a second low-frequency signal input terminal, wherein the first low-frequency signal input terminal inputs a first low-frequency voltage signal, and the second low-frequency signal input terminal inputs a second low-frequency voltage signal.
Preferably, the first low frequency voltage signal and the second low frequency voltage signal are complementary voltage signals.
Preferably, when the first low-frequency voltage signal is at a high level, the first control signal is active; when the first low-frequency signal is at a low level, the second control signal is active.
Preferably, the pre-charging unit comprises a third switching tube and a fourth switching tube; the control end of the third switching tube is connected with the control end of the fourth switching tube to input the preceding stage grid electrode driving signal; the first low-frequency voltage signal is input into a first pass end of the third switching tube, and a second pass end of the third switching tube is connected with a control end of the first switching tube so as to output the first control signal to the first switching tube; and the first path end of the fourth switching tube inputs the second low-frequency voltage signal, and the second path end of the fourth switching tube is connected with the control end of the second switching tube to output the second control signal to the second switching tube.
Preferably, the charging unit includes a first capacitor and a second capacitor; the first end of the first capacitor is connected with the first end of the second capacitor so as to input the current-stage grid driving signal; the second end of the first capacitor is connected with the control end of the first switch tube so as to output the first control signal to the first switch tube; and the second end of the second capacitor is connected with the control end of the second switch tube so as to output the second control signal to the second switch tube.
Preferably, the pull-down unit comprises a fifth switching tube and a sixth switching tube; the control end of the fifth switching tube is connected with the control end of the sixth switching tube so as to input the lower-level gate drive signal; the first low-frequency voltage signal is input to the first path end of the fifth switching tube, and the second low-frequency voltage signal is input to the first path end of the sixth switching tube; the second path end of the fifth switching tube is connected with the control end of the first switching tube so as to output the first control signal to the control end of the first switching tube; and the second path end of the sixth switching tube is connected with the control end of the second switching tube so as to output the second control signal to the control end of the second switching tube.
Preferably, when the preceding stage gate driving signal is valid, the third switching tube and the fourth switching tube are turned on; and when the lower-stage grid driving signal is effective, the fifth switching tube is conducted with the sixth switching tube.
According to another aspect of the present invention, there is provided a display device comprising cascaded multi-stage gate driving circuits and a compensation circuit of any one of the above, each stage of the gate driving circuits being connected to a corresponding compensation circuit.
Compared with the gate driving circuit in the prior art, the embodiment of the invention adds a compensation circuit after the gate driving circuit, wherein the compensation circuit uses two stages of gate driving signals before and after as starting signals of the pre-charging unit and the pull-down unit, and uses a group of low-frequency complementary signals to alternately start the output unit, so that the required reference voltage is output when the gate driving signal of the stage is started and is kept till the end of a frame. By making the transistors in the compensation circuit work alternately, not only the threshold voltage drift of the transistors can be reduced, but also the recovery of the threshold voltage drift of the transistors can be realized.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a prior art integrated gate driven display panel.
Fig. 2 shows a schematic diagram of a gate driving circuit of each stage in the prior art.
Fig. 3 shows a timing diagram of a gate driving circuit of each stage in the prior art.
Fig. 4 shows a schematic diagram of an integrated gate driving display panel according to a first embodiment of the present invention.
Fig. 5 shows a schematic diagram of a compensation circuit according to a second embodiment of the invention.
FIG. 6 is a diagram illustrating the Nth frame timing of the compensation circuit according to the second embodiment of the present invention.
FIG. 7 is a timing diagram of the N +1 th frame of the compensation circuit according to the second embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, lead-out lines other than the corresponding driving electrodes and sensing electrodes are not drawn in the drawings, and some well-known portions may not be shown.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 1 shows a schematic diagram of a prior art integrated gate driven display panel.
As shown in fig. 1, the integrated Gate driving circuit of the prior art includes n Gate Driver in array (GIA) units connected in cascade. The ith stage gate driving unit has an i-2 th stage gate driving signal input terminal 13, an i +2 th stage gate driving signal input terminal 14, a first high frequency clock signal CLKA input terminal 12, a second high frequency clock signal CLKB input terminal 16, a low level VGL input terminal 15, and a present stage gate driving signal output terminal 17, wherein the present stage gate driving signal output terminal 17 is used for driving the pixel array 1100 of the display panel.
When the ith gate driving unit is any one of the third to the last gate driving units, the i-2 gate driving signal input terminal 13 of the ith gate driving unit is electrically connected to the present gate driving signal output terminal 17 of the i-2 gate driving unit. The i +2 th gate driving signal input terminal 14 of the i-th gate driving unit is electrically connected to the present gate driving signal output terminal 17 of the i +2 th gate driving unit.
When the ith stage gate driving unit is the first stage gate driving unit, the i-2 stage gate driving signal input terminal 13 of the ith stage gate driving unit is used for inputting a pulse activating signal STV 1. When the ith stage gate driving unit is the second stage gate driving unit, the i-2 stage gate driving signal input terminal 13 of the ith stage gate driving unit is used for inputting a pulse activating signal STV 2.
When the ith gate driving unit is a gate driving unit of a penultimate stage, the i +2 th gate driving signal input terminal 14 of the ith gate driving unit is used for inputting a pulse activating signal STV 3. When the ith gate driving unit is the gate driving unit of the last but one stage, the i +2 th gate driving signal input terminal 14 of the ith gate driving unit is used for inputting a pulse activating signal STV 4.
Fig. 2 shows a schematic diagram of a gate driving circuit of each stage in the prior art.
As shown in fig. 2, each stage of the gate driving circuit of the related art includes a precharge part, a bootstrap pull-up part, a pull-down part, and a low level sustain part. The pre-charging part comprises a first switch tube T1, the bootstrap pull-up part comprises a second switch tube T2 and a first capacitor C1, the pull-down part comprises a third switch tube T3, a sixth switch tube T6 and a seventh switch tube T7, and the low-level maintaining part comprises a second capacitor C2, a fourth switch tube T4 and a fifth switch tube T5.
Fig. 3 shows a timing diagram of a gate driving circuit of each stage in the prior art.
The operation principle of the integrated gate driving circuit of the prior art will be described in detail with reference to fig. 2 and 3.
Let us take the ith gate driving unit as any one of the third to last gate driving units as an example. For the ith gate driving unit, when G [ i-2] input from the i-2 th gate driving signal input terminal 13 is at a high level, the first switching transistor T1 is turned on to charge the first node Q1 with a high level; when the voltage of the first node Q1 is greater than the threshold voltage of the second switch transistor T2, the second switch transistor T2 is turned on, and in the pull-up stage, the second switch transistor T2 is fully turned on due to the bootstrap effect of the first capacitor C1, and the present stage gate driving signal output terminal 17 outputs the present stage gate driving voltage gi; when G [ i +2] input by the i +2 th stage gate driving signal input end 14 is at a high level, the pull-down unit pulls down the potential of an output point; in the low-level maintaining period, when the first high-frequency clock signal CLKA changes from low to high, the noise potential of the second node Q2 is higher than that of the first node Q1 due to the coupling effect of the first capacitor C1, and the potential of the first node Q1 is stabilized at the low level VGL due to the mutual restriction effect of the fourth capacitor T4 and the fifth capacitor T5.
In the gate driving circuit in the prior art, because the pull-down switch tube is often under unipolar (voltage is positive) bias, the pull-down switch tube is subjected to a long-time positive dc voltage stress or a pulse voltage stress, after long-time operation, the threshold voltage drift of the pull-down switch tube is very large, and the reduction of the conductive capability occurs, thereby seriously affecting the working life of the integrated gate driving circuit.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 4 shows a schematic diagram of an integrated gate driving display panel according to a first embodiment of the present invention.
A first embodiment of the present invention provides a display device using an integrated gate driving circuit. As shown in fig. 4, the display device 2000 includes a plurality of gate driving units and a pixel array 2100 which are cascade-connected. The gate driving unit of each stage includes a gate driving circuit and a compensation circuit 2200 electrically connected to the gate driving circuit.
Fig. 5 shows a schematic diagram of a compensation circuit according to a second embodiment of the invention.
As shown in fig. 5, the compensation circuit 2200 of the second embodiment of the present invention includes a first switch transistor T1 and a second switch transistor T2, wherein a first path terminal of the first switch transistor T1 and a first path terminal of the second switch transistor T2 receive the first reference voltage VGH and the second reference voltage VGL, respectively. The second path ends of the first switch tube T1 and the second switch tube T2 are connected to output a signal Vout[i]The first switch transistor T1 and the second switch transistor T2 are turned on alternately during frame switching to output the first reference voltage VGH and the second reference voltage VGL, respectively.
The compensation circuit 2200 of the second embodiment of the present invention further includes a precharge unit, a charge unit, and a pull-down unit. The pre-charging unit comprises a pre-stage gate driving signal input end 25, a third switching tube T3 and a fourth switching tube T4, the charging unit comprises a present-stage gate driving signal input end 26, a first capacitor C1 and a second capacitor C2, and the pull-down unit comprises a lower-stage gate driving signal input end 27, a fifth switching tube T5 and a sixth switching tube T6.
The control end of the third switching tube T3 is connected to the control end of the fourth switching tube T4, and the preceding stage gate driving signal G [ i-2] is input through the preceding stage gate driving signal input terminal 25. The first path end of the third switch tube inputs a first low-frequency voltage signal ECK1, the second path end of the third switch tube is connected with the control end of the first switch tube T1 to output a first control signal to the first switch tube T1, the first path end of the fourth switch tube T4 inputs a second low-frequency voltage signal ECK2, and the second path end of the fourth switch tube T4 is connected with the control end of the second switch tube T2 to output a second control signal to the second switch tube T2.
A first end of the first capacitor C1 is connected with a first end of the second capacitor C2 to input the present-stage gate driving signal G [ i ]; a second terminal of the first capacitor C1 is connected to the control terminal of the first switch transistor T1 for outputting a first control signal to the first switch transistor T1, and a second terminal of the second capacitor C2 is connected to the control terminal of the second switch transistor T2 for outputting a second control signal to the control terminal of the second switch transistor T2.
A control terminal of the fifth switch transistor T5 is connected to a control terminal of the sixth switch transistor T6 for inputting the lower-level gate driving signal G [ i +2], a first path terminal of the fifth switch transistor T5 inputs the first low-frequency voltage signal ECK1, and a first path terminal of the sixth switch transistor T6 inputs the second low-frequency voltage signal ECK 2.
The second pass terminal of the fifth switch transistor T5 is connected to the control terminal of the first switch transistor T1 for outputting the first control signal to the control terminal of the first switch transistor T1, and the second pass terminal of the sixth switch transistor T6 is connected to the control terminal of the second switch transistor T2 for outputting the second control signal to the control terminal of the second switch transistor T2.
FIG. 6 is a timing diagram of the Nth frame of the compensation circuit according to the first embodiment of the present invention.
In the embodiment of the present invention, the first low frequency clock signal ECK1 and the second low frequency clock signal ECK2 are complementary voltage signals, and the low level voltages of the first low frequency clock signal ECK1 and the second low frequency clock signal ECK2 are much smaller than the threshold voltages of the first switch transistor T1 and the second switch transistor T2. The high level voltages of the first low frequency clock signal ECK1 and the second low frequency clock signal ECK2 are slightly larger than the threshold voltages of the first switch transistor T1 and the second switch transistor T2. The high level voltage of the input upper stage gate driving signal G [ i-2] is greater than the threshold voltages of the third switch transistor T3 and the fourth switch transistor T4, the high level voltage of the input present stage gate driving signal G [ i ] is much less than the threshold voltages of the first switch transistor T1 and the second switch transistor T2, and the high level voltage of the input lower stage gate driving signal G [ i +2] is greater than the threshold voltages of the fifth switch transistor T5 and the sixth switch transistor T6.
As shown in fig. 6, the first low frequency clock signal ECK1 is at a high level and the second low frequency clock signal ECK2 is at a low level in this frame. When the input upper stage grid drive signal G [ i-2]]When the voltage level is high, the third switch tube T3 and the fourth switch tube T4 are turned on, because the first low-frequency clock signal ECK1 is high and the second low-frequency clock signal ECK2 is low, the first low-frequency clock signal ECK1 precharges the first node Q, the potential of the first node Q is raised, the potential of the second node P is lowered, the precharge unit sends a first control signal to the control terminal of the first switch tube T1, the first control signal controls the first switch tube T1 to be turned on, and the output signal V is outputout[i]The first reference voltage VGH is output. When the input upper stage grid drive signal G [ i-2]]When the voltage is low, the third transistor T3 and the fourth transistor T4 are turned off, and the first node Q and the second node P float.
When the current stage gate drive signal G [ i ] is input]When the voltage level is high, the first capacitor C1 is bootstrapped to continue to raise the voltage level of the node Q, the charging unit sends a first control signal to the first switch transistor T1, and the first switch transistor T1 is fully turned on. At this time, because of the bootstrap effect of the second capacitor C2, the potential of the second node P also slightly rises, but is still not enough to turn on the second switch tube T2, so the output signal V is outputtedout[i]The first reference voltage VGH is continuously output.
When the lower gate drive signal G [ i +2] is input]When the voltage level is high, the fifth switch transistor T5 and the sixth switch transistor T6 of the pull-down unit are turned on, the voltage level of the first node Q is pulled down to be equal to the voltage level of the first low-frequency clock signal ECK1, and the pull-down unit sends a first control signal to the first switch transistor T1, at this time, the first switch transistor T1 is kept turned on. The potential of the second node P is pulled down, so the second switch tube T2 is kept closed, and the output signal Vout[i]The first reference voltage VGH is continuously output until the end of this frame.
FIG. 7 is a timing diagram of the N +1 th frame of the compensation circuit according to the first embodiment of the present invention.
As shown in fig. 7, following the frameIn this frame, the first low frequency clock signal ECK1 is switched to low level and the second low frequency clock signal ECK2 is switched to high level. When the input upper stage grid drive signal G [ i-2]]When the voltage level is high, the third switch tube T3 and the fourth switch tube T4 are turned on, the first low frequency clock signal ECK1 is low, and the second low frequency clock signal ECK2 is high, so the second low frequency clock signal ECK2 precharges the second node P, the potential of the second node P is raised, the potential of the first node Q is lowered, so the precharging unit sends the second control signal to the control terminal of the second switch tube T2, the second control signal controls the second switch tube T2 to be turned on, and the output signal V is outputout[i]And outputs the second reference voltage VGL. When the input upper stage grid drive signal G [ i-2]]When the voltage is low, the third transistor T3 and the fourth transistor T4 are turned off, and the first node Q and the second node P float.
When the current stage gate drive signal G [ i ] is input]When the voltage level is high, the second capacitor C2 is bootstrapped to continuously raise the voltage level of the second node P, the charging unit sends a second control signal to the second switch transistor T2, and the second switch transistor T2 is fully turned on. At this time, because of the bootstrap effect of the first capacitor C1, the potential of the first node Q also slightly rises, but is still not enough to turn on the first switch tube T1, so the output signal V1out[i]The second reference voltage VGL is continuously output.
When the lower gate drive signal G [ i +2] is input]When the voltage level is high, the fifth switch transistor T5 and the sixth switch transistor T6 of the pull-down unit are turned on, the voltage level of the second node P is pulled down to be equal to the voltage level of the second low-frequency clock signal ECK2, and the pull-down unit sends a second control signal to the second switch transistor T2, and at this time, the second switch transistor T2 is turned on. The potential of the first node Q is pulled down, so the first switch tube T1 is kept closed, and the output signal Vout[i]The second reference voltage VGL is continuously output until the end of this frame.
The first reference voltage VGH and the second reference voltage VGL of the present invention are opposite in phase, and the switching transistor of the present invention can be implemented in various ways, for example, including a triode, a field effect transistor, or the like.
Compared with the gate driving circuit in the prior art, the embodiment of the invention adds a compensation circuit after the gate driving circuit, wherein the compensation circuit uses two stages of gate driving signals before and after as starting signals of the pre-charging unit and the pull-down unit, and uses a group of low-frequency complementary signals to alternately start the output unit, so that the required reference voltage is output when the gate driving signal of the stage is started and is kept till the end of a frame. By making the transistors in the compensation circuit work alternately, not only the threshold voltage drift of the transistors can be reduced, but also the recovery of the threshold voltage drift of the transistors can be realized.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (9)

1. A compensation circuit applied to a display device comprises a first switch tube, a second switch tube, a pre-charge unit, a charge unit and a pull-down unit,
a first path end of the first switch tube receives a first reference voltage;
the first pass end of the second switch tube receives a second reference voltage;
the second path end of the first switching tube is connected with the second path end of the second switching tube to provide an output signal;
the pre-charging unit, the charging unit and the pull-down unit are respectively connected with the control ends of the first switch tube and the second switch tube,
the pre-charging unit is enabled by a preceding stage grid driving signal, and when the preceding stage grid driving signal is effective, the pre-charging unit respectively provides a first control signal and a second control signal to the control end of the first switch tube and the control end of the second switch tube so as to enable one of the first switch tube and the second switch tube to be conducted;
the charging unit is enabled by a current-stage grid electrode driving signal, and when the current-stage grid electrode driving signal is effective, the charging unit maintains the on or off state of the first switch tube and the second switch tube;
the pull-down unit is enabled by a rear-stage grid electrode driving signal, and when the rear-stage grid electrode driving signal is effective, the pull-down unit respectively provides the first control signal and the second control signal to the control end of the first switch tube and the control end of the second switch tube;
the first switch tube and the second switch tube are alternately conducted along with frame switching, and the phase of the first reference voltage is opposite to that of the second reference voltage.
2. The compensation circuit of claim 1, further comprising a first low frequency signal input to which a first low frequency voltage signal is input and a second low frequency signal input to which a second low frequency voltage signal is input.
3. The compensation circuit of claim 2, wherein the first low frequency voltage signal and the second low frequency voltage signal are complementary voltage signals.
4. The compensation circuit of claim 3, wherein the first control signal is asserted when the first low frequency voltage signal is high;
when the first low-frequency signal is at a low level, the second control signal is active.
5. The compensation circuit of claim 4, wherein the pre-charge unit comprises a third switch tube and a fourth switch tube;
the control end of the third switching tube is connected with the control end of the fourth switching tube to input the preceding stage grid electrode driving signal;
the first low-frequency voltage signal is input into a first pass end of the third switching tube, and a second pass end of the third switching tube is connected with a control end of the first switching tube so as to output the first control signal to the first switching tube;
and the first path end of the fourth switching tube inputs the second low-frequency voltage signal, and the second path end of the fourth switching tube is connected with the control end of the second switching tube to output the second control signal to the second switching tube.
6. The compensation circuit of claim 5, wherein the charging unit comprises a first capacitor and a second capacitor;
the first end of the first capacitor is connected with the first end of the second capacitor so as to input the current-stage grid driving signal;
the second end of the first capacitor is connected with the control end of the first switch tube so as to output the first control signal to the first switch tube;
and the second end of the second capacitor is connected with the control end of the second switch tube so as to output the second control signal to the second switch tube.
7. The compensation circuit of claim 6, wherein the pull-down unit comprises a fifth switching tube and a sixth switching tube;
the control end of the fifth switching tube is connected with the control end of the sixth switching tube so as to input a lower-level gate drive signal;
the first low-frequency voltage signal is input to the first path end of the fifth switching tube, and the second low-frequency voltage signal is input to the first path end of the sixth switching tube;
the second path end of the fifth switching tube is connected with the control end of the first switching tube so as to output the first control signal to the control end of the first switching tube;
and the second path end of the sixth switching tube is connected with the control end of the second switching tube so as to output the second control signal to the control end of the second switching tube.
8. The compensation circuit of claim 7, wherein when the preceding stage gate driving signal is active, the third switching tube and the fourth switching tube are turned on;
and when the lower-stage grid driving signal is effective, the fifth switching tube is conducted with the sixth switching tube.
9. A display device comprising a cascade of a plurality of stages of gate driver circuits and a plurality of stages of compensation circuits as claimed in any one of claims 1 to 8, each stage of the gate driver circuits being connected to a corresponding one of the compensation circuits.
CN201710801439.8A 2017-09-07 2017-09-07 Compensation circuit and display device Active CN107767827B (en)

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CN108428431B (en) * 2018-03-19 2020-03-24 联想(北京)有限公司 Screen and display compensation method
TWI713008B (en) * 2019-11-07 2020-12-11 友達光電股份有限公司 Driving circuit and the operation method thereof

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