CN107767827A - Compensation circuit and display device - Google Patents
Compensation circuit and display device Download PDFInfo
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- CN107767827A CN107767827A CN201710801439.8A CN201710801439A CN107767827A CN 107767827 A CN107767827 A CN 107767827A CN 201710801439 A CN201710801439 A CN 201710801439A CN 107767827 A CN107767827 A CN 107767827A
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- 238000010586 diagram Methods 0.000 description 14
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000004913 activation Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
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- 230000007423 decrease Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
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- 238000007667 floating Methods 0.000 description 2
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- 101000805729 Homo sapiens V-type proton ATPase 116 kDa subunit a 1 Proteins 0.000 description 1
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- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- 239000007788 liquid Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Crystallography & Structural Chemistry (AREA)
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of compensation circuit and display device, wherein, compensation circuit includes：Receive the first switch pipe of the first reference voltage, receive second switch pipe, precharge unit, charhing unit and the drop-down unit of the second reference voltage, wherein, the alternate path end of first switch pipe is connected to provide output signal with the alternate path end of second switch pipe, first switch pipe and second switch pipe switch and alternate conduction, the first reference voltage and the second reference voltage opposite in phase with frame；Precharge unit turns on one of first switch pipe and second switch pipe according to prime gate drive signal, charhing unit maintains the on or off state of first switch pipe and second switch pipe according to this grade of gate drive signal, and drop-down unit controls first switch pipe and second switch pipe according to rear class gate drive signal.By allowing transistor alternation in compensation circuit, the threshold voltage shift of transistor can be reduced and realize the recovery of transistor threshold voltage drift.
Description
Technical field
The present invention relates to display technology field, in particular it relates to a kind of compensation circuit and display device.
Background technology
Liquid crystal display device is that the phenomenon to be changed using the orientation of liquid crystal molecule in the presence of electric field is changed
The display device of light source light transmittance.Due to display quality is good, small volume and it is low in energy consumption the advantages of, liquid crystal display device is
It is widely used in the mobile terminal of such as mobile phone and the large scale display panel of such as flat panel TV.Liquid on existing market
It is projection-type liquid crystal display that crystal display is most of, and it includes liquid crystal panel and backlight module (backlight module).
The operation principle of liquid crystal panel is that liquid crystal molecule is placed among the parallel glass substrate of two panels, and is applied on two panels glass substrate
Add driving voltage to control the direction of rotation of liquid crystal molecule, generation picture is modulated to the luminous of backlight module.
The development of liquid crystal display in the last few years presents high integration, the development trend of low cost, and integrative display drives
The dynamic study hotspot for being increasingly becoming flat panel display.So-called integrative display drive circuit refers to gate driving circuit and source electrode
The peripheral circuits such as drive circuit are realized using switching tube (TFT) and are made in together with pixel switch pipe in TFT substrate.And tradition
Circuit (IC) type of drive compare, using the method for integrated raster data model can not only reduce peripheral driver chip quantity and
Its press seal program, reduce cost, and make it that display periphery is more slim so that display module is compacter, machinery and
Electrical reliability is enhanced.Wherein, the integrated gate drive circuitry based on amorphous silicon switching tube technology has obtained widely grinding
Study carefully.On the one hand it is current because non-crystalline silicon tft technology has the advantages such as technological temperature is low, device uniformity is good, cost is cheap
The TFT technology of main flow.On the other hand, the mobility of non-crystalline silicon tft can meet the requirement of gate driving circuit working frequency.But
It is that the stability of non-crystalline silicon tft is poor, serious threshold voltage shift, which can occur, under the biasing of prolonged voltage stress shows
As so as to influence the life-span of circuit.
The biasing of generally use low-voltage direct, double pull-down structures, height in the integrated gate drive circuitry design of prior art
Frequency pulsed bias reduces the mode of voltage signal dutycycle and reduces the threshold voltage shift for the pipe that pulls down switch.These modes exist
The purpose for extending the integrated gate drive circuitry life-span can be reached to a certain extent, but because the pipe that pulls down switch is often in single
Under the biasing of polarity (voltage for just), can by the DC voltage stress or pulse voltage stress of long period positive polarity,
Pull down switch after working long hours pipe threshold voltage shift it is still very big, and the decline of conductive capability can occur, so as to
Have a strong impact on the working life of integrated gate drive circuitry.Therefore, how key switch pipe in significantly more efficient suppression circuit
Threshold voltage shift, extend the life-span of integrated gate drive circuitry, be television panels GIA (Gate Driver in Array, collection
Into gate driving circuit) design key issue.
The content of the invention
In order to solve the above-mentioned problems of the prior art, the present invention provides a kind of compensation circuit and display device.
According to an aspect of the present invention, there is provided a kind of compensation circuit applied to display device, including first switch pipe,
Two switching tubes, precharge unit, charhing unit and drop-down unit, the first path terminal of the first switch pipe receive the first reference
Voltage, the first path terminal of the second switch pipe receive the second reference voltage, the alternate path end of the first switch pipe and
The alternate path end of the second switch pipe is connected to provide output signal；The precharge unit, it is by prime raster data model
Signal enables, and when the prime gate drive signal is effective, the precharge unit is respectively by the first control signal and second
Control signal provides the control terminal to the control terminal of the first switch pipe and the second switch pipe, so that the first switch
The conducting of one of pipe and the second switch pipe；The charhing unit, it is enabled by this grade of gate drive signal, when described level grid
When pole drive signal is effective, the charhing unit maintains the on or off shape of the first switch pipe and the second switch pipe
State；Drop-down unit, it is enabled by rear class gate drive signal, and when the rear class gate drive signal is effective, the drop-down is single
Member respectively provides first control signal and second control signal to the control terminal of the first switch pipe and described
The control terminal of second switch pipe, the first switch pipe and the second switch pipe switch and alternate conduction with frame, and described the
One reference voltage and the second reference voltage opposite in phase.
Preferably, the compensation circuit also includes the first low frequency signal input and the second low frequency signal input, described
First low frequency signal input inputs the first low-frequency voltage signal, and the second low frequency signal input inputs the second low-frequency voltage
Signal.
Preferably, first low-frequency voltage signal and second low-frequency voltage signal are complementary voltage signal.
Preferably, when first low-frequency voltage signal is high level, first control signal is effective；Described first is low
When frequency signal is low level, second control signal is effective.
Preferably, the precharge unit includes the 3rd switching tube and the 4th switching tube；The control of 3rd switching tube
End is connected with the control terminal of the 4th switching tube inputs the prime gate drive signal；The first of 3rd switching tube is logical
Terminal inputs first low-frequency voltage signal, the alternate path end of the 3rd switching tube and the control of the first switch pipe
End is connected to export first control signal to the first switch pipe；The first path terminal input institute of 4th switching tube
State the second low-frequency voltage signal, the alternate path end of the 4th switching tube be connected with the control terminal of the second switch pipe with to
The second switch pipe exports second control signal.
Preferably, the charhing unit includes the first electric capacity and the second electric capacity；The first end of first electric capacity with it is described
The first end of second electric capacity is connected to input described level gate drive signal；Second end of the first electric capacity and the first switch
The control terminal of pipe is connected to export first control signal to the first switch pipe；Second end of second electric capacity and institute
The control terminal for stating second switch pipe is connected to export second control signal to the second switch pipe.
Preferably, the drop-down unit includes the 5th switching tube and the 6th switching tube；The control terminal of 5th switching tube
It is connected with the control terminal of the 6th switching tube to input subordinate's gate drive signal；The first of 5th switching tube is logical
Terminal inputs first low-frequency voltage signal, and the first path terminal of the 6th switching tube inputs the second low-frequency voltage letter
Number；The alternate path end of 5th switching tube is connected with the control terminal of the first switch pipe with to the first switch pipe
Control terminal exports first control signal；The alternate path end of 6th switching tube and the control terminal of the second switch pipe
It is connected to export second control signal to the control terminal of the second switch pipe.
Preferably, when the prime gate drive signal is effective, the 3rd switching tube and the 4th the switching tube conducting；It is described
When subordinate's gate drive signal is effective, the 5th switching tube and the 6th switching tube conducting.
According to another aspect of the present invention, there is provided a kind of display device, including the multistage gate driving circuit of cascade and upper
Any compensation circuit is stated, every grade of gate driving circuit is connected with the corresponding compensation circuit.
Compared with the gate driving circuit of prior art, the embodiment of the present invention is after gate driving circuit plus a compensation is electric
Road, the compensation circuit by using front and back stages gate drive signal as pull-up unit and the open signal of drop-down unit,
Output unit is alternately opened using one group of low frequency complementary signal, so that when this grade of gate drive signal is opened required for output
Reference voltage simultaneously remains to a frame end.By allowing transistor alternation in compensation circuit, transistor can be not only reduced
Threshold voltage shift, and can also realize transistor threshold voltage drift recovery.
Brief description of the drawings
By the description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 shows the integrated raster data model display panel schematic diagram of prior art.
Fig. 2 shows prior art per one-level gate driving circuit schematic diagram.
Fig. 3 shows prior art per one-level gate driving circuit time diagram.
Fig. 4 shows integrated raster data model display panel schematic diagram according to a first embodiment of the present invention.
Fig. 5 shows compensation circuit schematic diagram according to a second embodiment of the present invention.
Fig. 6 shows second embodiment of the invention compensation circuit nth frame time diagram.
Fig. 7 shows second embodiment of the invention compensation circuit N+1 frame timing schematic diagrames.
Embodiment
The present invention is more fully described hereinafter with reference to accompanying drawing.In various figures, identical element is using similar attached
Icon is remembered to represent.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.In addition, do not drawn in figure
Lead-out wire in addition to corresponding driving electrodes are with sensing electrode, and some known parts may be not shown.
It describe hereinafter many specific details of the present invention, such as the structure of device, material, size, processing work
Skill and technology, to be more clearly understood that the present invention.But just as the skilled person will understand, it can not press
The present invention is realized according to these specific details.
Fig. 1 shows the integrated raster data model display panel schematic diagram of prior art.
As shown in figure 1, the integrated gate drive circuitry of prior art includes n GIA (the Gate Driver in of cascade
Array, integrated gate drive circuitry) unit.I-stage drive element of the grid have the i-th -2 grades gate drive signal inputs 13,
The i-th+2 grades gate drive signal inputs 14, the first high frequency clock signal CLKA inputs 12, the second high frequency clock signal CLKB
Input 16, low level VGL inputs 15 and this grade of gate drive signal output end 17, wherein, this grade of gate drive signal is defeated
Go out the pel array 1100 that end 17 is used to drive display panel.
When the i-stage drive element of the grid is the third level any raster data model into level drive element of the grid third from the bottom
During unit, the i-th -2 grades gate drive signal inputs 13 of the i-stage drive element of the grid are electrically connected to the i-th -2 grades grid
This grade of gate drive signal output end 17 of pole driver element.The i-th+2 grades raster data models letter of the i-stage drive element of the grid
Number input 14 is electrically connected to this grade of gate drive signal output end 17 of the i-th+2 grades drive element of the grid.
When the i-stage drive element of the grid is first order drive element of the grid, the i-stage drive element of the grid
The i-th -2 grades gate drive signal inputs 13 are used to input a pulsed activation signal STV1.When the i-stage drive element of the grid
For the second level drive element of the grid when, the i-th -2 grades gate drive signal inputs 13 of the i-stage drive element of the grid are used for
Input a pulsed activation signal STV2.
When the i-stage drive element of the grid is penultimate stage drive element of the grid, the i-stage raster data model list
The i-th+2 grades gate drive signal inputs 14 of member are used to input a pulsed activation signal STV3.When the i-stage raster data model
When unit is level drive element of the grid last, the i-th+2 grades gate drive signals input of the i-stage drive element of the grid
End 14 is used to input a pulsed activation signal STV4.
Fig. 2 shows prior art per one-level gate driving circuit schematic diagram.
As shown in Fig. 2 the every one-level gate driving circuit of prior art includes pull portion, drop-down in precharge section, bootstrapping
Part and low level maintain part.Wherein, precharge section includes first switch pipe T1, and pull portion includes second switch in bootstrapping
Pipe T2 and the first electric capacity C1, pull-down section point include the 3rd switch transistor T 3, the 6th switch transistor T 6 and the 7th switch transistor T 7, low level dimension
Holding part includes the second electric capacity C2, the 4th switch transistor T 4 and the 5th switch transistor T 5.
Fig. 3 shows prior art per one-level gate driving circuit time diagram.
The integrated gate drive circuitry operation principle of prior art is described in detail with reference to Fig. 2 and Fig. 3.
We are using i-stage drive element of the grid as the third level to any raster data model list of level drive element of the grid third from the bottom
Exemplified by member.For i-stage drive element of the grid, when the G [i-2] that the i-th -2 grades gate drive signal inputs 13 input is
During high level, first switch pipe T1 is opened, and high level is filled with to first node Q1；When first node Q1 voltage is opened more than second
Second switch pipe T2 is opened when closing pipe T2 threshold voltage, in the pull-up stage, because the first electric capacity C1 boot strap, makes second
Switch transistor T 2 is fully opened, and this grade of gate drive signal output end 17 exports this grade of gate drive voltage G [i]；When the i-th+2 grades grid
When the G [i+2] that pole driving signal input 14 inputs is high level, drop-down unit drags down the current potential of output point；Low level is tieed up
It is when the first high frequency clock signal CLKA is by low uprise to hold the stage, makes section point Q2 under the first electric capacity C1 coupling
Noise current potential be higher than first node Q1, because the 4th electric capacity T4 and the 5th electric capacity T5 effect of checking and balance makes first node Q1
Current potential it is stable in low level VGL.
In the gate driving circuit of prior art, because the pipe that pulls down switch is often in the inclined of unipolarity (voltage is just)
Put down, can be pulled down after a long-term service by the DC voltage stress or pulse voltage stress of long period positive polarity
The threshold voltage shift of switching tube can be very big, the decline of conductive capability occurs, so as to have a strong impact on integrated gate drive circuitry
Working life.
The embodiment of the present invention is described in detail with reference to the accompanying drawings.
Fig. 4 shows integrated raster data model display panel schematic diagram according to a first embodiment of the present invention.
First embodiment of the invention provides a kind of display device using integrated gate drive circuitry.As shown in figure 4, display
Device 2000 includes the multiple drive element of the grid and pel array 2100 of cascade.Wherein, the drive element of the grid bag per one-level
The compensation circuit 2200 for including gate driving circuit and being electrically connected with therewith.
Fig. 5 shows compensation circuit schematic diagram according to a second embodiment of the present invention.
As shown in figure 5, the compensation circuit 2200 of second embodiment of the invention includes first switch pipe T1 and second switch pipe
T2, wherein, first switch pipe T1 the first path terminal and second switch pipe T2 alternate path end receive first with reference to electricity respectively
Press VGH and the second reference voltage VGL.First switch pipe T1 is connected with output signal with second switch pipe T2 alternate path end
Vout[i], when frame switches, first switch pipe T1 and second switch pipe T2 are alternately opened, export respectively the first reference voltage VGH and
Second reference voltage VGL.
The compensation circuit 2200 of second embodiment of the invention also includes precharge unit, charhing unit and drop-down unit.Its
In, precharge unit includes prime gate drive signal input 25, the 3rd switch transistor T 3 and the 4th switch transistor T 4, charhing unit
Including this grade of gate drive signal input 26, the first electric capacity C1 and the second electric capacity C2, drop-down unit includes subordinate's raster data model
Signal input part 27, the 5th switch transistor T 5 and the 6th switch transistor T 6.
Wherein, the control terminal of the 3rd switch transistor T 3 is connected with the control terminal of the 4th switch transistor T 4, passes through prime raster data model
Signal input part 25 inputs prime gate drive signal G [i-2].First path terminal of the 3rd switching tube inputs the first low-frequency voltage
Signal ECK1, the alternate path end of the 3rd switching tube are connected with first switch pipe T1 control terminal with to the first switch pipe T1
The first control signal is exported, the first path terminal of the 4th switch transistor T 4 inputs the second low-frequency voltage signal ECK2, the 4th switching tube
T4 alternate path end is connected with second switch pipe T2 control terminal to export the second control signal to the second switch pipe T2.
First electric capacity C1 first end is connected with the second electric capacity C2 first end to input described level gate drive signal G
[i]；First electric capacity C1 the second end is connected with first switch pipe T1 control terminal to be controlled to first switch pipe T1 outputs first
Signal, the second electric capacity C2 the second end are connected with second switch pipe T2 control terminal to be exported to second switch pipe T2 control terminal
Second control signal.
The control terminal of 5th switch transistor T 5 is connected with the control terminal of the 6th switch transistor T 6 to input subordinate gate drive signal G
[i+2], the first path terminal of the 5th switch transistor T 5 input the first low-frequency voltage signal ECK1, the first path of the 6th switch transistor T 6
The second low-frequency voltage signal ECK2 of end input.The alternate path end of 5th switch transistor T 5 is connected with first switch pipe T1 control terminal
To export the first control signal, alternate path end and the second switch pipe of the 6th switch transistor T 6 to first switch pipe T1 control terminal
T2 control terminal is connected to export the second control signal to second switch pipe T2 control terminal.
Fig. 6 shows first embodiment of the invention compensation circuit nth frame time diagram.
In an embodiment of the present invention, the first low-frequency clock signal ECK1 and the second low-frequency clock signal ECK2 is complementary
Voltage signal, and the first low-frequency clock signal ECK1 and the second low-frequency clock signal ECK2 low level voltage are much smaller than first
The threshold voltage of switch transistor T 1 and second switch pipe T2.First low-frequency clock signal ECK1's and the second low-frequency clock signal ECK2
High level voltage is slightly larger than first switch pipe T1 and second switch pipe T2 threshold voltage.And the higher level's raster data model letter inputted
Number G [i-2] high level voltage is more than the threshold voltage of the 3rd switch transistor T 3 and the 4th switch transistor T 4, and this grade of grid of input drives
Dynamic signal G [i] high level voltage is much smaller than first switch pipe T1 and second switch pipe T2 threshold voltage, subordinate's grid of input
Pole drive signal G [i+2] high level voltage is more than the threshold voltage of the 5th switch transistor T 5 and the 6th switch transistor T 6.
As shown in fig. 6, the first low-frequency clock signal ECK1 is high level in this frame, the second low-frequency clock signal ECK2
For low level.When higher level's gate drive signal G [i-2] of input is high level, the 3rd switch transistor T 3 and the 4th switch transistor T 4
Conducting, because the first low-frequency clock signal ECK1 is high level, the second low-frequency clock signal ECK2 is low level, so first is low
Frequency clock signal ECK1 enters line precharge to first node Q, and first node Q current potential is elevated, section point P potential drop
Low, precharge unit sends the first control signal, the first control signal control first switch to first switch pipe T1 control terminal
Pipe T1 is turned on, output signal Vout[i] exports the first reference voltage VGH.When higher level's gate drive signal G [i-2] of input is low
During level, the 3rd switch transistor T 3 and the 4th switch transistor T 4 are closed, and first node Q and section point P are floating.
When this grade of gate drive signal G [i] of input is high level, continue to raise node by the first electric capacity C1 bootstrappings
Q current potential, charhing unit send the first control signal to first switch pipe T1, and first switch pipe T1 is fully opened.Now because
Second electric capacity C2 boot strap, section point P current potential also have it is small size raise, but be still not enough to open second switch
Pipe T2, so output signal Vout[i] continues to output the first reference voltage VGH.
When the subordinate gate drive signal G [i+2] of input is high level, the 5th switch transistor T 5 and the 6th of drop-down unit
Switch transistor T 6 is opened, first node Q current potential be pulled down to it is equal with the first low-frequency clock signal ECK1 current potential, drop-down unit to
First switch pipe T1 sends the first control signal, and now first switch pipe T1 is kept it turned on.Section point P current potential drop-down, institute
Remained turned-off with second switch pipe T2, output signal Vout[i] persistently exports the first reference voltage VGH to this frame end.
Fig. 7 shows first embodiment of the invention compensation circuit N+1 frame timing schematic diagrames.
As shown in fig. 7, as frame switches, the first low-frequency clock signal ECK1 is low level in this frame, the second low frequency
Clock signal ECK2 is high level.When higher level's gate drive signal G [i-2] of input is high level, the He of the 3rd switch transistor T 3
4th switch transistor T 4 is opened, because the first low-frequency clock signal ECK1 is low level, the second low-frequency clock signal ECK2 is high electricity
Flat, so the second low-frequency clock signal ECK2 enters line precharge to section point P, section point P current potential is raised, first node
Q current potential declines, therefore precharge unit sends the second control signal, the second control signal to second switch pipe T2 control terminal
Control second switch pipe T2 conductings, output signal Vout[i] exports the second reference voltage VGL.When higher level's raster data model of input is believed
When number G [i-2] is low level, the 3rd switch transistor T 3 and the 4th switch transistor T 4 are closed, and first node Q and section point P are floating.
When this grade of gate drive signal G [i] of input is high level, continue to raise second by the second electric capacity C2 bootstrappings
Node P current potential, charhing unit send the second control signal to second switch pipe T2, and second switch pipe T2 is fully opened.Now
Because the first electric capacity C1 boot strap, first node Q current potential also have it is small size raise, but be still not enough to unlatching first
Switch transistor T 1, so output signal Vout[i] continues to output the second reference voltage VGL.
When the subordinate gate drive signal G [i+2] of input is high level, the 5th switch transistor T 5 and the 6th of drop-down unit
Switch transistor T 6 is opened, section point P current potential be pulled down to it is equal with the second low-frequency clock signal ECK2 current potential, drop-down unit to
Second switch pipe T2 sends the second control signal, and now second switch pipe T2 is kept it turned on.First node Q current potential drop-down, institute
Remained turned-off with first switch pipe T1, output signal Vout[i] persistently exports the second reference voltage VGL to this frame end.
The the first reference voltage VGH and the second reference voltage VGL opposite in phase of the present invention, and the switching tube of the present invention can
To be realized by various ways, such as including triode or FET etc..
Compared with the gate driving circuit of prior art, the embodiment of the present invention is after gate driving circuit plus a compensation is electric
Road, the compensation circuit by using front and back stages gate drive signal as pull-up unit and the open signal of drop-down unit,
Output unit is alternately opened using one group of low frequency complementary signal, so that when this grade of gate drive signal is opened required for output
Reference voltage simultaneously remains to a frame end.By allowing transistor alternation in compensation circuit, transistor can be not only reduced
Threshold voltage shift, and can also realize transistor threshold voltage drift recovery.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation make a distinction with another entity or operation, and not necessarily require or imply and deposited between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Nonexcludability includes, so that process, method, article or equipment including a series of elements not only will including those
Element, but also the other element including being not expressly set out, or it is this process, method, article or equipment also to include
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Other identical element also be present in process, method, article or equipment including the key element.
According to embodiments of the invention as described above, these embodiments do not have all details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain the principle and practical application of the present invention, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its four corner and equivalent.
Claims (9)
1. a kind of compensation circuit applied to display device, including first switch pipe, second switch pipe, precharge unit, charging
Unit and drop-down unit, it is characterised in that
First path terminal of the first switch pipe receives the first reference voltage；
First path terminal of the second switch pipe receives the second reference voltage；
The alternate path end of the first switch pipe is connected to provide output signal with the alternate path end of the second switch pipe；
The precharge unit, it is enabled by prime gate drive signal, described when the prime gate drive signal is effective
Precharge unit respectively provides the first control signal and the second control signal to the control terminal of the first switch pipe and described
The control terminal of second switch pipe, so that one of the first switch pipe and the second switch pipe turn on；
The charhing unit, it is enabled by this grade of gate drive signal, described to fill when described level gate drive signal is effective
Electric unit maintains the on or off state of the first switch pipe and the second switch pipe；
The drop-down unit, it is enabled by rear class gate drive signal, when the rear class gate drive signal is effective, under described
Draw unit respectively by first control signal and second control signal provide to the first switch pipe control terminal and
The control terminal of the second switch pipe；
The first switch pipe and the second switch pipe switch and alternate conduction with frame, first reference voltage with it is described
Second reference voltage opposite in phase.
2. compensation circuit according to claim 1, it is characterised in that also low including the first low frequency signal input and second
Frequency signal input part, the first low frequency signal input input the first low-frequency voltage signal, the second low frequency signal input
The second low-frequency voltage signal of end input.
3. compensation circuit according to claim 2, it is characterised in that first low-frequency voltage signal and described second low
Frequency voltage signal is complementary voltage signal.
4. compensation circuit according to claim 3, it is characterised in that when first low-frequency voltage signal is high level,
First control signal is effective；
When first low frequency signal is low level, second control signal is effective.
5. compensation circuit according to claim 4, it is characterised in that the precharge unit includes the 3rd switching tube and the
Four switching tubes；
The control terminal of 3rd switching tube is connected with the control terminal of the 4th switching tube inputs the prime raster data model letter
Number；
First path terminal of the 3rd switching tube inputs first low-frequency voltage signal, and the second of the 3rd switching tube is logical
Terminal is connected with the control terminal of the first switch pipe to export first control signal to the first switch pipe；
First path terminal of the 4th switching tube inputs second low-frequency voltage signal, and the second of the 4th switching tube is logical
Terminal is connected with the control terminal of the second switch pipe to export second control signal to the second switch pipe.
6. compensation circuit according to claim 5, it is characterised in that the charhing unit includes the first electric capacity and the second electricity
Hold；
The first end of first electric capacity is connected with the first end of second electric capacity to input described level gate drive signal；
Second end of first electric capacity is connected with the control terminal of the first switch pipe to export institute to the first switch pipe
State the first control signal；
Second end of second electric capacity is connected with the control terminal of the second switch pipe to export institute to the second switch pipe
State the second control signal.
7. compensation circuit according to claim 6, it is characterised in that the drop-down unit includes the 5th switching tube and the 6th
Switching tube；
The control terminal of 5th switching tube is connected with the control terminal of the 6th switching tube to input subordinate's raster data model
Signal；
First path terminal of the 5th switching tube inputs first low-frequency voltage signal, and the first of the 6th switching tube is logical
Terminal inputs second low-frequency voltage signal；
The alternate path end of 5th switching tube is connected with the control terminal of the first switch pipe with to the first switch pipe
Control terminal export first control signal；
The alternate path end of 6th switching tube is connected with the control terminal of the second switch pipe with to the second switch pipe
Control terminal export second control signal.
8. compensation circuit according to claim 7, it is characterised in that described when the prime gate drive signal is effective
3rd switching tube and the 4th switching tube conducting；
When subordinate's gate drive signal is effective, the 5th switching tube and the 6th switching tube conducting.
9. a kind of display device, it is characterised in that multistage gate driving circuit and multistage claim 1 to 8 times including cascade
Compensation circuit described in one, every grade of gate driving circuit are connected with the corresponding compensation circuit.
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| CN201710801439.8A CN107767827B (en) | 2017-09-07 | 2017-09-07 | Compensation circuit and display device |
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| CN201710801439.8A CN107767827B (en) | 2017-09-07 | 2017-09-07 | Compensation circuit and display device |
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| CN108428431A (en) * | 2018-03-19 | 2018-08-21 | 联想(北京)有限公司 | A kind of screen and display compensation method |
| TWI713008B (en) * | 2019-11-07 | 2020-12-11 | 友達光電股份有限公司 | Driving circuit and the operation method thereof |
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Also Published As
| Publication number | Publication date |
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| CN107767827B (en) | 2020-09-04 |
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