CN102654984B - Shifting register unit and grid driving circuit - Google Patents
Shifting register unit and grid driving circuit Download PDFInfo
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- CN102654984B CN102654984B CN201110324771.2A CN201110324771A CN102654984B CN 102654984 B CN102654984 B CN 102654984B CN 201110324771 A CN201110324771 A CN 201110324771A CN 102654984 B CN102654984 B CN 102654984B
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Abstract
The invention discloses a shifting register unit and a grid driving circuit, and is designed for solving the problem of poor reliability and stability in the traditional grid driving circuit. The shifting register unit comprises a precharging unit, a first pull-up unit, a second pull-up unit, a third pull-up unit, a pull-down unit, a first double pull-down unit, a second double pull-down unit and a reset unit. The shifting register unit disclosed by the invention has the advantages that by arrangement of the double pull-down units, the direct-current voltage of a pull-down electronic switch is changed into alternating-current voltage, the problem of threshold voltage drift of the pull-down electronic switch is solved, the suspension of output and pull-up nodes in the grid driving circuit is also reduced, the output noise of the circuit is reduced, and the problems of reliability and stability of the grid driving circuit are solved.
Description
Technical field
The present invention relates to a kind of shift register cell and gate driver circuit, relate in particular to shift register cell and gate driver circuit in a kind of technical field of liquid crystal display.
Background technology
In liquid crystal display, the ultimate principle that realizes a frame picture disply is by source drive, the required data-signal of every one-row pixels to be exported successively from top to bottom, and grid drives successively and from top to bottom the square wave of every a line pixel gates input certain width carried out to gating.Fig. 1 and Fig. 2 are respectively panel integrated gate drive circuitry GOA module fundamental diagram and output waveform figure thereof, and Fig. 3 is existing shift register cell circuit theory diagrams.
The manufacture method of basic gate driver circuit is first to make grid-driving integrated circuit (grid drive IC) and source electrode driven integrated circuit (source drive IC), then by IC attachment process COG (COG:chip on glass), IC is bundled on face glass.When resolution is higher, grid driver output is more, and the limited space inner grid drive wire in glass both sides is arranged more and more closeer, when resolution further increases, considers the requirement of the narrow frame of small-medium size panel, and grid drive wire will be difficult to arrange.Allow to hold so many grid drive wire, also can increase IC and use a number, increase COG processing step, reduce the yield of product and increased cost.The solution of this problem of reply is by the design of panel integrated gate drive circuitry (GOA:Gate driver On Array) at present, in the situation that not increasing any technique and cost, grid-driving integrated circuit is produced on face glass by array processes.The integrated of gate driver circuit not only can be saved cost, reduced the step of small-size liquid crystal displays integrated circuit " binding technique ", also increased the reliability of panel simultaneously.
But, existing gate driver circuit exists that pull-down thin film threshold voltage drifts about under direct current (DC) bias and clock saltus step brings the integrity problem of the circuit such as noise, these circuit reliability problems can affect the display effect of liquid crystal display, and this problem mainly comes from the shift register cell that forms gate driver circuit.
Summary of the invention
In order to overcome above-mentioned defect, the invention provides the shift register cell that a kind of output signal is more reliable and stable.
For achieving the above object, shift register cell of the present invention comprises,
Input end, comprising: start signal input end, the first clock signal input terminal, second clock signal input part, useful signal input end, invalid signals input end and reset signal input end;
Pre-charge circuit, the useful signal of response the first clock signal and start signal, output useful signal; The useful signal of exporting continues to the beginning in next the first clock signal useful signal cycle;
The first circuit, responds the useful signal of described pre-charge circuit, the useful signal of the invalid signals of the first clock signal and second clock signal, this first circuit output useful signal; After the useful signal cut-off of described pre-charge circuit, this first circuit output invalid signals; Respond this first circuit output invalid signals of useful signal of the first clock signal;
Second circuit, responds the useful signal of described pre-charge circuit, this second circuit output invalid signals; After the useful signal cut-off of described pre-charge circuit, this second circuit output invalid signals of the useful signal of response the first clock signal; After the useful signal cut-off of described pre-charge circuit, the response invalid signals of the first clock signal and the useful signal of second clock signal, this second circuit output useful signal;
Tertiary circuit, connects the output terminal of described the first circuit and described second circuit, the invalid signals of the useful signal of response the first circuit output, second clock useful signal, the first clock invalid signals and second circuit output, this tertiary circuit output useful signal; Respond this tertiary circuit output invalid signals of invalid signals of the first clock useful signal or the output of the first circuit;
Output terminal, connects the output terminal of described tertiary circuit, output signal;
Reset circuit, connects described output terminal, and the useful signal of response reset signal resets described output terminal output.
Particularly, described the first circuit comprises:
Rock circuit on first: in response to the useful signal of described pre-charge circuit output and the useful signal of second clock signal, output useful signal; And,
Drop-down electronic circuit: in response to the useful signal of the first clock signal, the signal of described the first pull-up unit output is pulled low to invalid signals.
Particularly, described second circuit comprises:
Rock circuit on the 3rd: in response to the useful signal of second clock signal, output useful signal; In response to the invalid signals of second clock signal, output invalid signals; And,
First pair of drop-down electronic circuit: be connected in the output terminal of described pre-charge circuit, in response to the useful signal of described pre-charge circuit output, the signal of rock circuit output on described second be pulled low to invalid signals; After the signal cut-off of pre-charge circuit output, in response to the useful signal of the first clock signal, the signal of rock circuit output on described second is pulled low to invalid signals.
Particularly, described tertiary circuit comprises:
Rock circuit on second: be connected in the output terminal of described the first circuit, in response to the useful signal of described the first circuit output, output useful signal; In response to the invalid signals of described the first circuit output, output invalid signals; And,
Second pair of drop-down electronic circuit: be connected in the output terminal of described second circuit, in response to the useful signal of described second circuit output or the useful signal of the first clock signal, the signal of rock circuit output on described second be pulled low to invalid signals.
Further, rock circuit on described first, comprising: the second electronic switch and the 3rd electronic switch;
The second electronic switch, it controls the output terminal of pre-charge circuit described in termination, and two controlled ends connect respectively the control end of described second clock signal input part and described the 3rd electronic switch;
The 3rd electronic switch, two controlled end connects respectively described useful signal input end and described the first circuit output end.
Further, described drop-down electronic circuit comprises quadrielectron switch, and it controls termination the first clock signal input terminal, and two controlled ends connect respectively described invalid signals input end and described the first circuit output end.
Further, rock circuit comprises the 5th electronic switch on the described the 3rd, and it controls termination second clock signal input part, and one of them controlled end is connected to effect signal input part or connects second clock signal, another controlled termination tertiary circuit output terminal.
Further, described first pair of drop-down electronic circuit, comprising: the 6th electronic switch and the 7th electronic switch; Wherein,
The 6th electronic switch, it controls termination pre-charge circuit output terminal, and two controlled ends connect respectively second circuit output terminal and invalid signals input end;
The 7th electronic switch, it controls termination the first clock signal input terminal, and two controlled ends connect respectively second circuit output terminal and invalid signals input end.
Further, rock circuit comprises the 8th electronic switch on described second, and it controls termination first circuit output end, controlled termination second clock signal input part or a useful signal output terminal wherein, the output terminal of tertiary circuit described in another controlled termination.
Further, described second pair of pull-down circuit: comprise the 9th electronic switch and the tenth electronic switch; Wherein,
The 9th electronic switch, it controls termination second circuit output terminal, and two controlled ends connect respectively invalid signals input end and tertiary circuit output terminal;
The tenth electronic switch, it controls termination the first clock signal input terminal, and two controlled ends connect respectively invalid signals input end and tertiary circuit output terminal.
Particularly, described reset unit comprises the 11 electronic switch, and it controls termination reset signal input end, and two controlled ends connect respectively the output terminal of invalid signals input end and this shift register cell.
A gate driver circuit, is characterized in that: comprise two above by claim 1 to the shift register cell described in arbitrary claim in claim 11; Every grade of shift register cell is usingd the output of upper level as the start signal of shift register cell at the corresponding levels, and the output of subordinate is as reset signal; The external start signal of shift register cell of the first order, the output signal that the reset signal of most end one-level shift register cell is self.
Shift register cell of the present invention makes the grid voltage of the drop-down electronic switch of current potential become alternating voltage from DC voltage by the setting of two drop-down unit, reduced the grid bias ratio as the thin film transistor (TFT) of electronic switch, improve the problem of drop-down electronic switch threshold voltage shift, but also reduced the unsettled of electronic switch output and each node in shift register cell, reduced the noise of circuit.Shift register cell of the present invention has solved the reliability and stability problem of gate driver circuit effectively by the setting of two drop-down unit, improved the display effect of the liquid crystal display of application gate driver circuit of the present invention.
Accompanying drawing explanation
Fig. 1 is panel integrated gate drive circuitry GOA module fundamental diagram.
Fig. 2 is module output waveform figure shown in Fig. 1.
Fig. 3 is existing shift register cell circuit theory diagrams.
Fig. 4 is shift register cell structural representation in the present invention.
Fig. 5 is shift register cell the first example structure schematic diagram in the present invention.
Fig. 6 is shift register cell the second example structure schematic diagram in the present invention.
Fig. 7 is the timing waveform of shift register cell shown in corresponding diagram 4 and Fig. 5.
Embodiment
Below in conjunction with Figure of description and embodiment, the present invention is described in detail.
Shift register cell of the present invention is the component units of panel integrated gate drive circuitry, and response start signal STV useful signal, the first clock signal clk useful signal, second clock signal CLKB useful signal, useful signal VDD, invalid signals VSS and this shift register cell of reset signal RESET useful signal are exported a useful signal within a predetermined period of time.Useful signal is to make each circuit in this shift register cell or element circuit produce the signal of response, and invalid signals is to make in this shift register cell each circuit or element circuit not produce the signal of response.The useful signal of this shift register cell output is that order connects the circuit of this shift register cell or the signal of element generation response, and invalid signals connects this shift register cell each circuit or element for making do not produce the signal of response.
As shown in Figure 4 and Figure 6, the concrete structure of shift register cell of the present invention comprises,
Input end: comprise start signal input end STV, the first clock signal clk input end, second clock signal CLKB input end, high level VDD input end, low level VSS input end and reset signal RESET input end.
Pre-charge circuit Pre-charging: within the first clock signal useful signal cycle, start signal is pulled to useful signal by the node A in pre-charge circuit; In the useful signal cycle of next the first clock signal, interior nodes A is pulled to invalid signals.Node A be in pre-charge circuit appointment a bit, for the pre-charge circuit structure that comprises electronic switch and electric capacity, node A is positioned at one end of electric capacity, another termination low level of electric capacity.
The first circuit, the useful signal of responsive node A, the useful signal of the invalid signals of the first clock signal clk and second clock signal CLKB, this first circuit output useful signal; After the useful signal cut-off of node A, this first circuit output invalid signals; Respond this first circuit output invalid signals of useful signal of the first clock signal clk.This first circuit comprises: the first pull-up unit PU1 and drop-down unit PD.The first pull-up unit PU1 is at node A useful signal in the cycle, and response second clock signal CLKB exports high level, and the output terminal of this first pull-up unit PU1 is provided with node Q.Drop-down unit PD, within the first clock signal clk useful signal cycle to node Q output low level.
Second circuit, the useful signal of responsive node A, this second circuit output invalid signals; After the useful signal cut-off of node A, this second circuit output invalid signals of the useful signal of response the first clock signal clk; After the useful signal cut-off of node A, the response invalid signals of the first clock signal clk and the useful signal of second clock signal CLKB, this second circuit output useful signal.This second circuit comprises: the first couple of drop-down cells D ual PD1 and the 3rd pull-up unit PU3.The first couple of drop-down cells D ual PD1 be output low level in the signal period or in the first clock signal clk useful signal cycle at node A useful signal, and this first pair drop-down cells D ual PD1 output terminal is provided with node QB.The 3rd pull-up unit PU3, exports high level to node QB at the useful signal of second clock signal CLKB in the cycle.
Tertiary circuit, the output terminal that connects described the first circuit and described second circuit, respond the invalid signals of useful signal, second clock CLKB useful signal, the first clock CLK invalid signals and the second circuit output of the first circuit output, this tertiary circuit output useful signal; Respond this tertiary circuit output invalid signals of invalid signals of the first clock CLK useful signal or the output of the first circuit.This tertiary circuit comprises the second pull-up unit PU2 and second couple of drop-down cells D ual PD2.The second pull-up unit PU2 is at node Q useful signal in the cycle, and response second clock signal CLKB is to the output terminal output high level of this shift register cell.Second couple of drop-down cells D ual PD2, within the first clock signal clk useful signal cycle or node QB useful signal in the cycle to the output terminal output low level of this shift register cell.
Output terminal, connects the output terminal of described tertiary circuit, output signal;
Reset circuit, connects described output terminal, and the useful signal of response reset signal makes described output terminal output invalid signals.
The concrete preferred implementation of each element circuit is as follows.
Preferred embodiment one: use as shown in Figure 4 N-type thin film transistor (TFT) as electronic switch, realize the function of unit in this shift register cell, because thin film transistor (TFT) has good performance and high integration.In the present embodiment, useful signal is high level, and invalid signals is low level.The first clock signal clk is contrary with second clock signal CLKB sequential.The first circuit comprises the first pull-up unit PU1 and drop-down unit PD; Second circuit comprises first couple of drop-down cells D ual PD1 and the 3rd pull-up unit PU3; Tertiary circuit comprises the second pull-up unit PU2 and second couple of drop-down cells D ual PD2.
Precharge unit Pre-charging: comprise capacitor C 1 and the first film transistor T 1; The grid of the first film transistor T 1 connects the first clock signal clk, and drain electrode and source electrode meet respectively start signal STV and node A, and node A connects one end of capacitor C 1, another termination low level VSS of capacitor C 1.
The first pull-up unit PU1: comprise the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3.The grid of the second thin film transistor (TFT) T2 meets node A, and drain electrode meets second clock signal CLKB, and source electrode connects the grid of the 3rd thin film transistor (TFT) T3.The drain electrode of the 3rd thin film transistor (TFT) T3 meets high level VDD, and source electrode meets node Q.
The second pull-up unit PU2: comprise the 8th thin film transistor (TFT) T8, its grid meets node Q, drain electrode meets second clock signal CLKB, and source electrode meets the output terminal OUT of this shift register cell.
The 3rd pull-up unit PU3: comprise the 5th thin film transistor (TFT) T5, its grid meets second clock signal CLKB, drain electrode meets high level VDD, and source electrode meets node QB.
Drop-down unit PD: comprise the 4th thin film transistor (TFT) T4, its grid connects the first clock signal clk, and source electrode meets low level VSS, drain electrode meets node Q.
First couple of drop-down cells D ual PD1: comprise the 6th thin film transistor (TFT) T6 and the 7th thin film transistor (TFT) T7.The grid of the 6th thin film transistor (TFT) T6 meets node A, and drain electrode meets node QB, and source electrode meets low level VSS.The grid of the 7th thin film transistor (TFT) T7 connects the first clock signal clk, and drain electrode meets node QB, and source electrode meets low level VSS.
Second couple of drop-down cells D ual PD2: comprise the 9th thin film transistor (TFT) T9 and the tenth thin film transistor (TFT) T10.The grid of the 9th thin film transistor (TFT) T9 meets node QB, and drain electrode meets the output terminal OUT of this shift register cell, and source electrode meets low level VSS.The grid of the tenth thin film transistor (TFT) T10 connects the first clock signal, and drain electrode meets the output terminal OUT of this shift register cell, and source electrode meets low level VSS.
Reset unit RESET: comprise the 11 thin film transistor (TFT) T11, its grid meets reset signal RESET, drain electrode meets the output terminal OUT of this shift register cell, and source electrode meets low level VSS.
Preferred embodiment two: as shown in Figure 5, use N-type thin film transistor (TFT) to realize the function of unit in this shift register cell, in the present embodiment, useful signal is high level, and invalid signals is low level.The first clock signal clk is contrary with second clock signal CLKB sequential.The first circuit comprises the first pull-up unit PU1 and drop-down unit PD; Second circuit comprises first couple of drop-down cells D ual PD1 and the 3rd pull-up unit PU3; Tertiary circuit comprises the second pull-up unit PU2 and second couple of drop-down cells D ual PD2.The difference of the present embodiment and preferred embodiment one is:
The second pull-up unit PU2: comprise the 8th thin film transistor (TFT) M8, its grid meets node Q, drain electrode meets high level VDD, and source electrode meets the output terminal OUT of this shift register cell.
The 3rd pull-up unit PU3: comprise the 5th thin film transistor (TFT) M5, its grid meets second clock signal CLKB, drain electrode meets second clock signal CLKB, and source electrode meets node QB.
As shown in Fig. 4～Fig. 6, in embodiment mono-and embodiment bis-, the effect of precharge unit Pre-charging is in half clock period that is high level at the first clock signal clk, open the first film transistor T 1, utilize start signal STV to charge to capacitor C 1.So node A keeps high level when start signal STV and the first clock signal clk are all high level.The second thin film transistor (TFT) T2 in the first pull-up unit PU1 opens, but because now second clock signal CLKB is low level, so Node B is still low level.Drop-down unit PD now responds the first clock signal clk and opens, and node Q is low level.The high level of the 6th thin film transistor (TFT) T6 responsive node A in first couple of drop-down cells D ual PD1 makes node QB in low level.The tenth thin film transistor (TFT) T10 of second couple of drop-down cells D ual PD2 responds the first clock signal clk and makes this shift register cell output low level.
When the first clock signal clk enters low-level period, start signal STV also enters low-level period, and second clock signal CLKB enters high level period.Now the first film transistor T 1 is closed, and node A keeps high level; The second thin film transistor (TFT) T2 is held open state, at the effect lower node B of second clock signal CLKB, is high level; The 3rd thin film transistor (TFT) T3 opens, and the 4th thin film transistor (TFT) T4 that is now controlled by the first clock signal clk closes, so node Q is high level; The 8th thin film transistor (TFT) T8 opens; The high level of the 6th thin film transistor (TFT) T6 responsive node A makes node QB in low level, and the 9th thin film transistor (TFT) T9 closes, and the tenth thin film transistor (TFT) T10 responds the first clock signal clk and closes; Therefore this shift register cell output terminal is by the 8th thin film transistor (TFT) T8 response second clock signal CLKB output high level.
When the first clock signal clk enters high level period again, start signal STV and second clock signal CLKB enter low-level period.Now the first film transistor T 1 is opened, and node A discharges by start signal STV port, and the discharge process time is very short, can be similar to and think that the moment node A that the first film transistor T 1 is opened is pulled to low level.The tenth thin film transistor (TFT) T10 responds the first clock signal clk and makes this shift register cell output low level.
After this in stage, if there is no a start signal STV enter again high level period, this shift register cell output terminal will respond the first clock signal clk or second clock signal CLKB keeps low level output.In this stage, the 4th thin film transistor (TFT) T4 responds the low level that the first clock signal clk keeps node Q, guarantees this shift register cell output low level together with second couple of drop-down cells D ual PD2.The 7th thin film transistor (TFT) T7 responds the low level that the first clock signal clk keeps node QB.
A kind of gate driver circuit comprise two above by claim 1 to the shift register cell described in arbitrary claim in claim 13; The output of every grade of shift register cell higher level is as start signal, and the output of subordinate is as reset signal; The external start signal of shift register cell of the first order, the output signal that the reset signal of most end one-level shift register cell is self.Use the gate driver circuit of shift register cell of the present invention to improve reliability and stability, the display effect of liquid crystal display of applying this gate driver circuit is better.
Above; be only preferred embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain that claim was defined.
Claims (11)
1. a shift register cell, is characterized in that, comprise,
Input end, comprising: start signal input end, the first clock signal input terminal, second clock signal input part, useful signal input end, invalid signals input end and reset signal input end;
Pre-charge circuit, in response to the useful signal of the first clock signal and start signal, output useful signal;
The first circuit, in response to the useful signal of described pre-charge circuit output, the useful signal of the invalid signals of the first clock signal and second clock signal, output useful signal; After the useful signal cut-off of described pre-charge circuit output, output invalid signals;
Second circuit, in response to the useful signal of described pre-charge circuit output, output invalid signals; After the useful signal cut-off of described pre-charge circuit output, in response to the useful signal of the first clock signal and the invalid signals of second clock, output invalid signals, in response to the invalid signals of the first clock signal and the useful signal of second clock signal, output useful signal;
Tertiary circuit, is connected in the output terminal of described the first circuit and described second circuit, in response to the useful signal of the first circuit output, invalid signals and the first clock invalid signals of second circuit output, output useful signal; In response to the invalid signals of the first clock useful signal or the output of the first circuit, output invalid signals;
Output terminal, is connected in the output terminal of described tertiary circuit, output signal; And,
Reset circuit, is connected in the output terminal of described shift register cell, in response to the useful signal of reset signal, the output terminal of described shift register cell is resetted.
2. shift register cell according to claim 1, is characterized in that, described the first circuit comprises:
The first pull-up unit: in response to the useful signal of described pre-charge circuit output and the useful signal of second clock signal, output useful signal; And,
Drop-down unit: in response to the useful signal of the first clock signal, the signal of the first pull-up unit output is pulled low to invalid signals.
3. shift register cell according to claim 1, is characterized in that, described second circuit comprises:
The 3rd pull-up unit: in response to the useful signal of second clock signal, output useful signal; In response to the invalid signals of second clock signal, output invalid signals; And,
First pair of drop-down unit: be connected in the output terminal of described pre-charge circuit, in response to the useful signal of described pre-charge circuit output, the signal of the second pull-up unit output be pulled low to invalid signals; After the signal cut-off of pre-charge circuit output, in response to the useful signal of the first clock signal, the signal of described the second pull-up unit output is pulled low to invalid signals;
Described tertiary circuit comprises:
The second pull-up unit: be connected in the output terminal of described the first circuit, in response to the useful signal of described the first circuit output, output useful signal; In response to the invalid signals of described the first circuit output, output invalid signals; And,
Second pair of drop-down unit: be connected in the output terminal of described second circuit, in response to the useful signal of described second circuit output or the useful signal of the first clock signal, the signal of described the second pull-up unit output be pulled low to invalid signals.
4. shift register cell according to claim 2, is characterized in that: described the first pull-up unit, comprising: the second electronic switch and the 3rd electronic switch;
The second electronic switch, it controls the output terminal of pre-charge circuit described in termination, and two controlled ends connect respectively the control end of described second clock signal input part and described the 3rd electronic switch;
The 3rd electronic switch, two controlled end connects respectively described useful signal input end and described the first circuit output end;
Described pre-charge circuit, comprising: the first electronic switch and the first electric capacity;
Described the first electric capacity, its first termination invalid signals input end;
Described the first electronic switch, it controls termination the first clock signal input terminal, and two controlled ends connect respectively the second end of described start signal and described the first electric capacity.
5. shift register cell according to claim 2, it is characterized in that: described drop-down unit comprises quadrielectron switch, it controls termination the first clock signal input terminal, and two controlled ends connect respectively described invalid signals input end and described the first circuit output end.
6. shift register cell according to claim 3, it is characterized in that: described the 3rd pull-up unit comprises the 5th electronic switch, it controls termination second clock signal input part, one of them controlled end is connected to effect signal input part or connects second clock signal, another controlled termination tertiary circuit output terminal.
7. shift register cell according to claim 3, is characterized in that: described first pair of drop-down unit, comprising: the 6th electronic switch and the 7th electronic switch; Wherein,
The 6th electronic switch, it controls termination pre-charge circuit output terminal, and two controlled ends connect respectively second circuit output terminal and invalid signals input end;
The 7th electronic switch, it controls termination the first clock signal input terminal, and two controlled ends connect respectively second circuit output terminal and invalid signals input end.
8. shift register cell according to claim 3, it is characterized in that: described the second pull-up unit comprises the 8th electronic switch, it controls termination the first circuit output end, controlled termination second clock signal input part or a useful signal input end wherein, the output terminal of tertiary circuit described in another controlled termination.
9. shift register cell according to claim 3, is characterized in that: described second pair of drop-down unit: comprise the 9th electronic switch and the tenth electronic switch; Wherein,
The 9th electronic switch, it controls termination second circuit output terminal, and two controlled ends connect respectively invalid signals input end and tertiary circuit output terminal;
The tenth electronic switch, it controls termination the first clock signal input terminal, and two controlled ends connect respectively invalid signals input end and tertiary circuit output terminal.
10. shift register cell according to claim 1, it is characterized in that: described reset circuit comprises the 11 electronic switch, it controls termination reset signal input end, and two controlled ends connect respectively the output terminal of invalid signals input end and this shift register cell.
11. 1 kinds of gate driver circuits, is characterized in that: comprise two above by claim 1 to the shift register cell described in arbitrary claim in claim 10; Every grade of shift register cell is usingd the output of upper level as the start signal of shift register cell at the corresponding levels, and the output of subordinate is as reset signal; The external start signal of shift register cell of the first order, the output signal that the reset signal of most end one-level shift register cell is self.
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Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN103151010B (en) * | 2013-02-27 | 2014-12-10 | 京东方科技集团股份有限公司 | Shift register and display device |
| CN103151013B (en) * | 2013-03-07 | 2015-11-25 | 昆山龙腾光电有限公司 | Gate driver circuit |
| CN103198783B (en) * | 2013-04-01 | 2015-04-29 | 京东方科技集团股份有限公司 | Shifting register unit, shifting register and display device |
| CN103247275B (en) * | 2013-04-22 | 2015-03-11 | 合肥京东方光电科技有限公司 | Shifting register unit, grid drive circuit and array substrate |
| CN103500561B (en) * | 2013-10-12 | 2015-06-17 | 昆山龙腾光电有限公司 | Gate driving circuit |
| CN104252853A (en) * | 2014-09-04 | 2014-12-31 | 京东方科技集团股份有限公司 | Shift register unit, driving method, gate drive circuit and display device |
| CN104332137B (en) * | 2014-11-28 | 2016-11-16 | 京东方科技集团股份有限公司 | Gate driver circuit and display device |
| CN106057161B (en) * | 2016-08-09 | 2018-09-11 | 京东方科技集团股份有限公司 | Shift register, grid line integrated drive electronics, array substrate and display device |
| CN107818749B (en) * | 2016-09-13 | 2020-12-15 | 上海和辉光电股份有限公司 | Shifting register unit, grid driving circuit and display device |
| CN106228942B (en) * | 2016-09-23 | 2018-05-15 | 南京华东电子信息科技股份有限公司 | Gate driving circuit for liquid crystal display |
| CN107424552B (en) | 2017-06-13 | 2019-11-05 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN111179797B (en) * | 2018-11-13 | 2021-11-02 | 合肥京东方卓印科技有限公司 | Shifting register unit and driving method thereof, grid driving circuit and related device |
| CN110246447A (en) * | 2019-06-18 | 2019-09-17 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN110189681B (en) * | 2019-06-28 | 2021-05-07 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN111341257B (en) * | 2020-03-24 | 2021-06-15 | 武汉天马微电子有限公司 | Display panel, driving method thereof and display device |
| CN115909938A (en) * | 2022-11-24 | 2023-04-04 | 惠科股份有限公司 | GOA driving circuit, device and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101122720A (en) * | 2006-08-08 | 2008-02-13 | 三星电子株式会社 | Gate driver and display apparatus having the same |
| CN101752005A (en) * | 2008-12-20 | 2010-06-23 | 乐金显示有限公司 | Shift register |
| US7764761B2 (en) * | 2008-07-01 | 2010-07-27 | Chunghwa Picture Tubes, Ltd. | Shift register apparatus and method thereof |
| US7953201B2 (en) * | 2008-12-12 | 2011-05-31 | Au Optronics Corp. | Shift register with pre-pull-down module to suppress a spike |
-
2011
- 2011-10-21 CN CN201110324771.2A patent/CN102654984B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101122720A (en) * | 2006-08-08 | 2008-02-13 | 三星电子株式会社 | Gate driver and display apparatus having the same |
| US7764761B2 (en) * | 2008-07-01 | 2010-07-27 | Chunghwa Picture Tubes, Ltd. | Shift register apparatus and method thereof |
| US7953201B2 (en) * | 2008-12-12 | 2011-05-31 | Au Optronics Corp. | Shift register with pre-pull-down module to suppress a spike |
| CN101752005A (en) * | 2008-12-20 | 2010-06-23 | 乐金显示有限公司 | Shift register |
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