CN110246447A - Shift register cell, driving method, gate driving circuit and display device - Google Patents
Shift register cell, driving method, gate driving circuit and display device Download PDFInfo
- Publication number
- CN110246447A CN110246447A CN201910528404.0A CN201910528404A CN110246447A CN 110246447 A CN110246447 A CN 110246447A CN 201910528404 A CN201910528404 A CN 201910528404A CN 110246447 A CN110246447 A CN 110246447A
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- Prior art keywords
- pull
- control
- node
- transistor
- down node
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides a kind of shift register cell, driving method, gate driving circuit and display device.Shift register cell includes pull-down node control circuit and bias control circuit, and the pull-down node control circuit is used under the control of the current potential of pull-up node, controls and is connected to or disconnects between pull-down node and first voltage end；The bias control circuit be used for the pull-down node control circuit control pull-down node and first voltage end it is separated when, by controlling the current potential of pull-up node, it is in predetermined voltage range with controlling the gate source voltage for the pull-down node control transistor that pull-down node control circuit includes.The present invention can improve the threshold voltage shift phenomenon for the pull-down node control transistor that pull-down node control circuit includes.
Description
Technical field
The present invention relates to display actuation techniques fields more particularly to a kind of shift register cell, driving method, grid to drive
Dynamic circuit and display device.
Background technique
In the reliability test process of existing display panel, after lighting is more than 300 hours, occurs lighting successively
Show abnormal problem.It is found through parsing, in reliability test process, the pull-down node control circuit in shift register cell
Including pull-down node control transistor threshold voltage positive excursion can gradually occur so that the pull-down node control crystal
The on-state current Ion of pipe is reduced, so that exception occurs in the competitive relation between pull-up node and pull-down node, so that resetting rank
Duan Wufa resets the current potential of pull-up node, and it is abnormal screen display occur
Summary of the invention
The main purpose of the present invention is to provide a kind of shift register cell, driving method, gate driving circuit and show
Showing device solves the pull-down node control transistor that the pull-down node control circuit in existing shift register cell includes
The serious problem of threshold voltage shift phenomenon.
In order to achieve the above object, the present invention provides a kind of shift register cells, including pull-down node control circuit
And bias control circuit, wherein
The control terminal of the pull-down node control circuit is electrically connected with pull-up node, and the of the pull-down node control circuit
One end is electrically connected with pull-down node, and the second end of the pull-down node control circuit is electrically connected with first voltage end, the drop-down
Node control circuit is used under the control of the current potential of pull-up node, is controlled between the pull-down node and the first voltage end
Connection disconnects；
The bias control circuit is electrically connected with the pull-up node, for controlling institute in the pull-down node control circuit
State pull-down node and the first voltage end it is separated when, by controlling the current potential of the pull-up node, with control it is described under
The gate source voltage for the pull-down node control transistor for drawing node control circuit to include is in predetermined voltage range.
When implementation, the pull-down node control transistor is n-type transistor, and the predetermined voltage range is less than 0；Or
Person,
The pull-down node control transistor is p-type transistor, and the predetermined voltage range is greater than 0.
When implementation, the pull-down node control circuit includes that a pull-down node controls transistor；
The control electrode of the pull-down node control transistor is electrically connected with the pull-up node, and the pull-down node control is brilliant
First pole of body pipe is electrically connected with the pull-down node, the second pole of the pull-down node control transistor and first voltage end electricity
Connection；
The bias control circuit includes bias control transistor；
The control electrode of the bias control transistor is electrically connected with bias control terminal, and the first of the bias control transistor
Pole is electrically connected with the pull-up node, and the second pole of the bias control transistor is electrically connected with second voltage end；
The bias control terminal is for providing bias control signal, so that in pull-down node control transistor shutdown
When, control the bias control transistor conducting.
When implementation, the bias control voltage end is drop-down control node；
The pull-down node control circuit further includes drop-down control node control circuit and drop-down control transistor；
The drop-down control node control circuit is used under the control of the current potential of the pull-up node, controls the drop-down
The current potential of control node；
The control electrode of the drop-down control transistor is electrically connected with the drop-down control node, and the drop-down controls transistor
The first pole be electrically connected with power voltage terminal, it is described drop-down control transistor the second pole be electrically connected with the pull-down node.
When implementation, the pull-down node control transistor is n-type transistor, in pull-down node control transistor shutdown
When, second voltage is less than first voltage；Alternatively, the pull-down node control transistor is p-type transistor, in the pull-down node
When controlling transistor shutdown, second voltage is greater than first voltage；
The first voltage end is for inputting the first voltage, and the second voltage end is for inputting second electricity
Pressure.
When implementation, the pull-down node includes the first pull-down node and the second pull-down node；The pull-down node control electricity
Road includes that the first pull-down node control transistor and the second pull-down node control transistor；
The control electrode of the first pull-down node control transistor is electrically connected with the pull-up node, the first drop-down section
First pole of point control transistor is electrically connected with first pull-down node, and the second of the first pull-down node control transistor
Pole is electrically connected with first voltage end；
The control electrode of the second pull-down node control transistor is electrically connected with the pull-up node, the second drop-down section
First pole of point control transistor is electrically connected with second pull-down node, and the second of the second pull-down node control transistor
Pole is electrically connected with first voltage end；
The bias control circuit includes the first bias control transistor and the second bias control transistor；
The control electrode of first bias control transistor is electrically connected with the first bias control terminal, the first biasing control
First pole of transistor is electrically connected with the pull-up node, the second pole and second voltage end of first bias control transistor
Electrical connection；
The control electrode of second bias control transistor is electrically connected with the second bias control terminal, the second biasing control
First pole of transistor is electrically connected with the pull-up node, the second pole and tertiary voltage end of second bias control transistor
Electrical connection；
First bias control terminal is for providing the first bias control signal, so that first pull-down node controls
When transistor and second pull-down node control transistor shutdown, the first bias control transistor conducting is controlled；
Second bias control terminal is for providing the second bias control signal, so that first pull-down node controls
When transistor and second pull-down node control transistor shutdown, the second bias control transistor conducting is controlled.
When implementation, first bias control voltage end is the first drop-down control node, second bias control voltage
End is the second drop-down control node；
The pull-down node control circuit further includes the first drop-down control node control circuit, the first drop-down control crystal
Pipe, the second drop-down control node control circuit and the second drop-down control transistor；
The first drop-down control node control circuit is used under the control of the current potential of the pull-up node, described in control
The current potential of first drop-down control node；
The control electrode of the first drop-down control transistor is electrically connected with the first drop-down control node, under described first
The first pole of control transistor is drawn to be electrically connected with the first power voltage terminal, the second pole of the first drop-down control transistor and institute
State the electrical connection of the first pull-down node；
The second drop-down control node control circuit is used under the control of the current potential of the pull-up node, described in control
The current potential of second drop-down control node；
The control electrode of the second drop-down control transistor is electrically connected with the second drop-down control node, under described second
The first pole of control transistor is drawn to be electrically connected with second source voltage end, the second pole of the second drop-down control transistor and institute
State the electrical connection of the second pull-down node.
When implementation, the first pull-down node control transistor and second pull-down node control transistor are all N-shaped
Transistor, when first pull-down node controls transistor and second pull-down node control transistor shutdown, the second electricity
Pressure is less than first voltage, and tertiary voltage is less than first voltage；Alternatively, first pull-down node controls transistor and described second
It is all p-type transistor that pull-down node, which controls transistor, controls transistor and the second drop-down section in first pull-down node
When point control transistor shutdown, second voltage is greater than first voltage, and tertiary voltage is greater than first voltage；
The first voltage end is for inputting the first voltage, and the second voltage end is for inputting second electricity
Pressure, the tertiary voltage end is for inputting the tertiary voltage end.
The present invention also provides a kind of driving methods, applied to above-mentioned shift register cell, the driving method packet
It includes:
In reseting stage and output cut-off holding stage, control of the pull-down node control circuit in the current potential of pull-up node
Under, control the separated of the pull-down node and the first voltage end；Bias control circuit controls the electricity of the pull-up node
Position is in predetermined voltage range to control the gate source voltage for the pull-down node control transistor that pull-down node control circuit includes
It is interior.
When implementation, the pull-down node control transistor is n-type transistor, and the predetermined voltage range is less than 0；Or
Person,
The pull-down node control transistor is p-type transistor, and the predetermined voltage range is greater than 0.
The present invention also provides a kind of gate driving circuit, multistage above-mentioned shift register cell.
The present invention also provides a kind of display devices, including above-mentioned gate driving circuit.
Compared with prior art, shift register cell of the present invention, driving method, gate driving circuit and display
Device can improve the threshold voltage shift phenomenon for the pull-down node control transistor that pull-down node control circuit includes.
Detailed description of the invention
Fig. 1 is the structure chart of shift register cell described in the embodiment of the present invention；
Fig. 2 is the structure chart of shift register cell described in another embodiment of the present invention；
Fig. 3 is the structure chart of shift register cell described in further embodiment of this invention；
Fig. 4 is the structure chart of shift register cell described in yet another embodiment of the invention；
Fig. 5 is the structure chart of shift register cell described in further embodiment of this invention；
Fig. 6 is the circuit diagram of a specific embodiment of shift register cell of the present invention；
Fig. 7 is the working timing figure of the specific embodiment of shift register cell of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The transistor used in all embodiments of the invention all can be triode, thin film transistor (TFT) or field-effect tube or its
The identical device of his characteristic.In embodiments of the present invention, to distinguish the two poles of the earth of transistor in addition to control electrode, will wherein claim a pole
For the first pole, another pole is known as the second pole.
In practical operation, when the transistor is triode, the control electrode can be base stage, and first pole can
Think collector, second pole can be with emitter；Alternatively, the control electrode can be base stage, described first can be extremely hair
Emitter-base bandgap grading, second pole can be with collector.
In practical operation, when the transistor is thin film transistor (TFT) or field-effect tube, the control electrode can be grid
Pole, described first can be extremely drain electrode, and described second extremely can be source electrode；Alternatively, the control electrode can be grid, described the
One extremely can be source electrode, and described second can be extremely drain electrode.
As shown in Figure 1, shift register cell described in the embodiment of the present invention include pull-down node control circuit 11 and partially
Set control circuit 12, wherein
The control terminal of the pull-down node control circuit 11 is electrically connected with pull-up node PU, the pull-down node control circuit
11 first end is electrically connected with pull-down node PD, second end and first voltage end the VT1 electricity of the pull-down node control circuit 11
Connection, the pull-down node control circuit 11 are used under the control of the current potential of pull-up node PU, control the pull-down node PD
It is connected to or disconnects between the first voltage end VT1；
The bias control circuit 12 is electrically connected with the pull-up node PU, in the pull-down node control circuit 11
Control the pull-down node PD and the first voltage end VT1 it is separated when, by controlling the current potential of the pull-up node PU,
Predetermined voltage model is in control the gate source voltage for the pull-down node control transistor that the pull-down node control circuit 11 includes
In enclosing, so that pull-down node control transistor is in reverse-bias state.
In the specific implementation, the first voltage end VT1 can be the first low-voltage end, but not as being limited.
At work, the display cycle includes setting gradually to the embodiment of present invention shift register cell as shown in Figure 1
Input phase, output stage, reseting stage and output cut-off the holding stage；
In input phase and output stage, pull-down node control circuit 11 is under the control of the current potential of pull-up node PU, control
It makes and is connected between the pull-down node PD and the first voltage end VT1；
In reseting stage and output cut-off holding stage, control of the pull-down node control circuit 11 in the current potential of pull-up node PU
Under system, the separated of the pull-down node PD and first voltage end VT1 is controlled；Bias control circuit 12 controls the pull-up
The current potential of node PU is in pre- to control the gate source voltage for the pull-down node control transistor that pull-down node control circuit 11 includes
Within the scope of constant voltage, so that pull-down node control transistor is in reverse-bias state.
In the specific implementation, pull-down node control transistor is n-type transistor, the predetermined voltage range be less than
0；Alternatively,
The pull-down node control transistor is p-type transistor, and the predetermined voltage range is greater than 0.
Specifically, the pull-down node control circuit may include a pull-down node control transistor；
The control electrode of the pull-down node control transistor is electrically connected with the pull-up node, and the pull-down node control is brilliant
First pole of body pipe is electrically connected with the pull-down node, the second pole of the pull-down node control transistor and first voltage end electricity
Connection；
The bias control circuit includes bias control transistor；
The control electrode of the bias control transistor is electrically connected with bias control terminal, and the first of the bias control transistor
Pole is electrically connected with the pull-up node, and the second pole of the bias control transistor is electrically connected with second voltage end；
The bias control terminal is for providing bias control signal, so that in pull-down node control transistor shutdown
When, control the bias control transistor conducting.
In the specific implementation, the second voltage end can be the second low-voltage end, and but not limited to this.
In the specific implementation, the pull-down node control circuit can only include a pull-down node control transistor, and
Shift register cell described in the embodiment of the present invention can be only with a pull-down node, and but not limited to this.
In the specific implementation, the pull-down node control transistor is n-type transistor, controls crystal in the pull-down node
When pipe turns off, second voltage is less than first voltage；Alternatively, the pull-down node control transistor is p-type transistor, under described
When drawing the shutdown of node control transistor, second voltage is greater than first voltage；
The first voltage end is for inputting the first voltage, and the second voltage end is for inputting second electricity
Pressure.
As shown in Fig. 2, on the basis of the embodiment of shift register cell shown in Fig. 1, the pull-down node control
Circuit 11 may include pull-down node control transistor MDC1；
The grid of the pull-down node control transistor MDC1 is electrically connected with the pull-up node PU, the pull-down node control
The drain electrode of transistor MDC1 processed is electrically connected with the pull-down node PD, the source electrode of pull-down node control transistor MDC1 and the
The electrical connection of one low-voltage end；First low-voltage end is for inputting the first low-voltage LVGL；
The bias control circuit 12 may include bias control transistor MBC1；
The grid of the bias control transistor MBC1 is electrically connected with bias control terminal BCtrl, and the biasing controls crystal
The drain electrode of pipe MBC1 is electrically connected with the pull-up node PU, the source electrode and the second low-voltage end of the bias control transistor MBC1
Electrical connection；Second low-voltage end is for inputting the second low-voltage VGL2；
The bias control terminal BCtrl is for providing bias control signal, so that controlling crystal in the pull-down node
When pipe MDC1 is turned off, the bias control transistor MBC1 conducting is controlled.
In the embodiment of shift register cell shown in Fig. 2, MDC1 and MBC1 are NMOS tube (N-type metal-oxide
Object-semiconductor field effect transistor), but not limited to this.
In the embodiment of shift register cell shown in Fig. 2, in reseting stage and output cut-off holding stage, VGL2
Less than LVGL, the gate source voltage of MDC1 is less than 0, so as to reduce the threshold voltage shift of MDC1.
The embodiment of present invention shift register cell as shown in Figure 2 at work,
In input phase and output stage, the current potential of PU is high level, and MDC1 is opened, and the gate source voltage of MDC1 is greater than 0,
The threshold voltage negative offset of MDC1；The bias control signal of BCtrl input is low level, MBC1 shutdown；
In reseting stage and output cut-off holding stage, the current potential of PU is low level, and the bias control signal is high electricity
Flat, MBC1 conducting, the grid that PU accesses VGL2 namely MDC1 accesses VGL2, and the source electrode of MDC1 accesses LVGL, then the grid source of MDC1
Threshold voltage forward migration of the voltage less than 0, MDC1.
At work, MDC1 is inclined in positive and negative gate source voltage for the embodiment of present invention shift register cell as shown in Figure 2
It presses under reciprocation, the threshold voltage of MDC1 tends to stable state.
In the specific implementation, when MDC1 is replaced by p-type transistor, in input phase and output stage, the grid of MDC1
Source voltage then needs the gate source voltage for controlling MDC1 in reseting stage and output cut-off holding stage to be greater than 0 less than 0, so that
The threshold voltage stabilization of MDC1.
Specifically, the bias control voltage end can be drop-down control node；
The pull-down node control circuit further includes drop-down control node control circuit and drop-down control transistor；
The drop-down control node control circuit is used under the control of the current potential of the pull-up node, controls the drop-down
The current potential of control node；
The control electrode of the drop-down control transistor is electrically connected with the drop-down control node, and the drop-down controls transistor
The first pole be electrically connected with power voltage terminal, it is described drop-down control transistor the second pole be electrically connected with the pull-down node.
As shown in figure 3, on the basis of the embodiment of shift register cell shown in Fig. 2, the bias control voltage
End is drop-down control node PDCN；
The pull-down node control circuit 11 further includes drop-down control node control circuit 30 and drop-down control transistor
MDC2；
The drop-down control node control circuit 30 is used under the control of the current potential of the pull-up node PU, described in control
Pull down the current potential of control node PDCN；
The grid of the drop-down control transistor MDC2 is electrically connected with the drop-down control node PDCN, the drop-down control
The drain electrode of transistor MDC2 is electrically connected with power voltage terminal, the source electrode of the drop-down control transistor MDC2 and the pull-down node
PD electrical connection；
The power voltage terminal is used for input supply voltage VDD.
In the embodiment of shift register cell shown in Fig. 3, MDC2 is NMOS tube, and but not limited to this.
At work, MDC1 and MDC2 control PD to the embodiment of present invention shift register cell as shown in Figure 3 together
Current potential, drop-down control node control circuit 30 control PDCN current potential.
In the specific implementation, the drop-down control node control circuit 30 may include the first control transistor and the second control
Transistor processed；
The first pole and power voltage terminal electricity of the control electrode of the first control transistor and the first control transistor
Second pole of connection, the first control transistor is electrically connected with the drop-down control node；
The control electrode of the second control transistor is electrically connected with the pull-up node, and described second controls the of transistor
One pole is electrically connected with the drop-down control node, and the second pole of the second control transistor is electrically connected with first voltage end.
In the specific implementation, on the basis of the embodiment of present invention shift register cell as shown in Figure 3, the present invention
Shift register cell described in embodiment can also include pull-up node control circuit, storage capacitance, carry signal output end,
Gate drive signal output end, gate drive signal output circuit and carry signal output circuit；
The pull-up node control circuit can be saved with input terminal, initial signal end and reset terminal, pull-down node and pull-up
Point electrical connection, the reset of initial signal, reset terminal offer that input signal, initial signal end for providing in input terminal provide
Under the control of signal and the current potential of pull-down node, the current potential of pull-up node is controlled；
The first end of the storage capacitance can be electrically connected with the pull-up node, and the second end of the storage capacitance can be with
It is electrically connected with gate drive signal output end；
The gate drive signal output circuit respectively with pull-up node, pull-down node, gate drive signal output end, when
Clock signal end and the electrical connection of first voltage end, for controlling the gate driving under the control of the current potential of the pull-up node
It is connected between signal output end and the clock signal terminal, under the control of the current potential of the pull-down node, controls the grid
It is connected between driving signal output end and the first voltage end；
The carry signal output circuit respectively with pull-up node, pull-down node, carry signal output end, clock signal terminal
With first voltage end be electrically connected, under the control of the current potential of the pull-up node, control the carry signal output end with
Be connected between the clock signal terminal, under the control of the current potential of the pull-down node, control the carry signal output end with
It is connected between the first voltage end；
The gate drive signal of the gate drive signal output end output is for driving corresponding line grid line, the carry letter
The carry signal of number output end output is used to provide input signal to adjacent next stage shift register cell, and to adjacent upper one
Grade shift register cell provides reset signal.
Specifically, the pull-down node may include the first pull-down node and the second pull-down node；The pull-down node control
Circuit processed may include the first pull-down node control transistor and the second pull-down node control transistor；
The control electrode of the first pull-down node control transistor is electrically connected with the pull-up node, the first drop-down section
First pole of point control transistor is electrically connected with first pull-down node, and the second of the first pull-down node control transistor
Pole is electrically connected with first voltage end；
The control electrode of the second pull-down node control transistor is electrically connected with the pull-up node, the second drop-down section
First pole of point control transistor is electrically connected with second pull-down node, and the second of the second pull-down node control transistor
Pole is electrically connected with first voltage end；
The bias control circuit includes the first bias control transistor and the second bias control transistor；
The control electrode of first bias control transistor is electrically connected with the first bias control terminal, the first biasing control
First pole of transistor is electrically connected with the pull-up node, the second pole and second voltage end of first bias control transistor
Electrical connection；
The control electrode of second bias control transistor is electrically connected with the second bias control terminal, the second biasing control
First pole of transistor is electrically connected with the pull-up node, the second pole and tertiary voltage end of second bias control transistor
Electrical connection；
First bias control terminal is for providing the first bias control signal, so that in the first pull-down node control
When transistor processed and second pull-down node control transistor shutdown, the first bias control transistor conducting is controlled；
Second bias control terminal is for providing the second bias control signal, so that in the first pull-down node control
When transistor processed and second pull-down node control transistor shutdown, the second bias control transistor conducting is controlled.
In the specific implementation, shift register cell described in the embodiment of the present invention can use two pull-down nodes, institute
Stating pull-down node control circuit may include two pull-down node control transistors, and the bias control circuit may include two
Bias control transistor, but not limited to this.
In the specific implementation, the first voltage end can be the first low-voltage end, the second voltage end and described the
Three voltage ends can be the second low-voltage end, and but not limited to this.
In the specific implementation, the first pull-down node control transistor and second pull-down node control transistor are
N-type transistor, when first pull-down node controls transistor and second pull-down node control transistor shutdown, second
Voltage is less than first voltage, and tertiary voltage is less than first voltage；Alternatively, first pull-down node control transistor and described the
It is p-type transistor that two pull-down nodes, which control transistor, controls transistor and the second drop-down section in first pull-down node
When point control transistor shutdown, second voltage is greater than first voltage, and tertiary voltage is greater than first voltage；
The first voltage end is for inputting the first voltage, and the second voltage end is for inputting second electricity
Pressure, the tertiary voltage end is for inputting the tertiary voltage.
As shown in figure 4, on the basis of the embodiment of shift register cell shown in Fig. 1, the pull-down node can be with
Including the first pull-down node PD1 and the second pull-down node PD2；
The pull-down node control circuit 11 may include the first pull-down node control transistor M6 and the second pull-down node
Control transistor M6 '；
The grid of the first pull-down node control transistor M6 is electrically connected with the pull-up node PU, first drop-down
The drain electrode of node control transistor M6 is electrically connected with the first pull-down node PD1, and first pull-down node controls transistor
The source electrode of M6 is electrically connected with the first low-voltage end；First low-voltage end is for inputting the first low-voltage LVGL；
The grid of the second pull-down node control transistor M6 ' is electrically connected with the pull-up node PU, under described second
The drain electrode of node control transistor M6 ' is drawn to be electrically connected with the second pull-down node PD2, second pull-down node controls crystal
The source electrode of pipe M6 ' is electrically connected with first low-voltage end；
The bias control circuit 12 includes the first bias control transistor M14 and the second bias control transistor M14；
The grid of the first bias control transistor M14 is electrically connected with the first bias control terminal BCtrl1, and described first
The drain electrode of bias control transistor M14 is electrically connected with the pull-up node PU, the source electrode of the first bias control transistor M14
It is electrically connected with the second low-voltage end；Second low-voltage end is for providing the second low-voltage VGL2；
The grid of the second bias control transistor M14 ' is electrically connected with the second bias control terminal BCtrl2, and described second
The drain electrode of bias control transistor M14 ' is electrically connected with the pull-up node PU, the source of the second bias control transistor M14 '
Pole is electrically connected with second low-voltage end；
The first bias control terminal BCtrl1 is for providing the first bias control signal, so that in first drop-down
When node control transistor M6 and second pull-down node control transistor M6 ' are turned off, it is brilliant to control the first biasing control
Body pipe M14 conducting；
The second bias control terminal BCtrl2 is for providing the second bias control signal, so that in first drop-down
When node control transistor M6 and second pull-down node control transistor M6 ' are turned off, it is brilliant to control the second biasing control
Body pipe M14 ' conducting.
In the embodiment of shift register cell shown in Fig. 4, M6, M6 ', M14 and M14 ' be all NMOS tube (N-type gold
Category-Oxide-Semiconductor Field effect transistor), but not limited to this.
In the embodiment of shift register cell shown in Fig. 4, in reseting stage and output cut-off holding stage, VGL2
Less than LVGL, the gate source voltage of M6 is less than 0, so as to reduce the threshold voltage shift of M6, the gate source voltage of M6 ' less than 0, from
And the threshold voltage shift of M6 ' can be reduced.
The embodiment of present invention shift register cell as shown in Figure 4 at work,
In input phase and output stage, the current potential of PU is high level, and M6 and M6 ' are opened, the gate source voltage of M6 and M6's '
The threshold voltage negative offset of the gate source voltage threshold voltage greater than 0, M6 and M6 '；First biasing control letter of BCtrl1 input
Number and BCtrl2 input the second bias control signal be low level, M14 and M14 ' shutdown；
In reseting stage and output cut-off holding stage, the current potential of PU is low level, first bias control signal and
Second bias control signal is high level, and M14 and M14 ' conducting, PU access the grid of VGL2 namely M6 and the grid of M6 '
VGL2 is accessed, the source electrode of M6 and the source electrode of M6 ' access LVGL, then the gate source voltage of M6 and the gate source voltage of M6 ' are less than 0, M6's
The threshold voltage forward migration of threshold voltage and M6 '.
At work, M6 and M6 ' are in positive and negative gate source voltage for the embodiment of present invention shift register cell as shown in Figure 4
Under bias reciprocation, the threshold voltage of M6 and the threshold voltage of M6 ' tend to stable state.
In the specific implementation, as M6 and M6 ' when being replaced by p-type transistor, in input phase and output stage, the grid of M6
The gate source voltage of source voltage and M6 ' then need to control the grid source electricity of M6 in reseting stage and output cut-off holding stage less than 0
The gate source voltage of pressure and M6 ' are greater than 0, so that the threshold voltage stabilization of the threshold voltage of M6 and M6 '.
In the specific implementation, first bias control voltage end can be the first drop-down control node, and described second partially
Setting control voltage end can be the second drop-down control node；
The pull-down node control circuit can also include the first drop-down control node control circuit, the first drop-down control crystalline substance
Body pipe, the second drop-down control node control circuit and the second drop-down control transistor；
The first drop-down control node control circuit is used under the control of the current potential of the pull-up node, described in control
The current potential of first drop-down control node；
The control electrode of the first drop-down control transistor is electrically connected with the first drop-down control node, under described first
The first pole of control transistor is drawn to be electrically connected with the first power voltage terminal, the second pole of the first drop-down control transistor and institute
State the electrical connection of the first pull-down node；
The second drop-down control node control circuit is used under the control of the current potential of the pull-up node, described in control
The current potential of second drop-down control node；
The control electrode of the second drop-down control transistor is electrically connected with the second drop-down control node, under described second
The first pole of control transistor is drawn to be electrically connected with second source voltage end, the second pole of the second drop-down control transistor and institute
State the electrical connection of the second pull-down node.
As shown in figure 5, on the basis of the embodiment of shift register cell shown in Fig. 4, the first biasing control
Voltage end is the first drop-down control node PDCN1, and second bias control voltage end is the second drop-down control node PDCN2；
The pull-down node control circuit 11 can also include that the first drop-down control node control circuit 301, first pulls down
Control transistor M5, the second drop-down control node control circuit 302 and the second drop-down control transistor M5 '；
The first drop-down control node control circuit 301 pulls down control node with pull-up node PU and first respectively
PDCN1 electrical connection, under the control of the current potential of the pull-up node PU, controlling the first drop-down control node PDCN1
Current potential；
The grid of the first drop-down control transistor M5 is electrically connected with the first drop-down control node PDCN1, described
The drain electrode of first drop-down control transistor M5 is electrically connected with the first power voltage terminal, the source of the first drop-down control transistor M5
Pole is electrically connected with the first pull-down node PD1；
The second drop-down control node control circuit 302 pulls down control node with the pull-up node PU and second respectively
PDCN2 electrical connection, under the control of the current potential of the pull-up node PU, controlling the second drop-down control node PDCN2
Current potential；
The grid of the second drop-down control transistor M5 ' is electrically connected with the second drop-down control node PDCN2, described
The drain electrode of second drop-down control transistor M5 ' is electrically connected with second source voltage end, the second drop-down control transistor M5's '
Source electrode is electrically connected with the second pull-down node PD2；
First power voltage terminal is for inputting the first supply voltage VDD1, and the second source voltage end is for inputting
Second source voltage VDD2.
In the embodiment of shift register cell shown in Fig. 5, M5 and M5 ' are NMOS tube, and but not limited to this.
At work, M6 and M5 control the electricity of PD1 to the embodiment of present invention shift register cell as shown in Figure 5 together
Position, the first drop-down control node control circuit 301 control the current potential of PDCN1；M6 ' and M5 ' controls the current potential of PD2 together, and second
Pull down the current potential that control node control circuit 302 controls PDCN2.
As shown in fig. 6, on the basis of the embodiment of present invention shift register cell as shown in Figure 5, in the present invention
In one specific embodiment of the shift register cell,
The first drop-down control node control circuit includes under the first drop-down control node control transistor M9 and second
Control node is drawn to control transistor M8；
The second drop-down control node control circuit includes under third drop-down control node control transistor M9 ' and the 4th
Control node is drawn to control transistor M8 '；
And the specific embodiment of shift register cell of the present invention further includes pull-up node control circuit, storage
Capacitor C1, gate drive signal output end G_out, gate drive signal output circuit, carry signal output end Out_c and carry
Signal output apparatus；
The pull-up node control circuit includes the first pull-up node control transistor M1, the second pull-up node control crystal
Pipe M2, third pull-up node control transistor M0, the 4th pull-up node control transistor M10 ' and the control of the 5th pull-up node are brilliant
Body pipe M10, wherein
The grid of M1 and drain electrode are all electrically connected with input terminal Input, and the source electrode of M1 is electrically connected with pull-up node PU；
The grid of M2 is electrically connected with reset terminal Reset_PU, and the drain electrode of M2 is electrically connected with PU, the source electrode of M2 electricity low with first
Pressure side electrical connection；First low-voltage end is for inputting the first low-voltage LVGL；
The grid of M0 is electrically connected with initial signal end STV, and the drain electrode of M0 is electrically connected with PU, and the source electrode of M0 is low with described first
Voltage end electrical connection；
The grid of M10 ' is electrically connected with the first pull-down node PD1, and the drain electrode of M10 ' is electrically connected with PU, the source electrode of M10 ' and institute
State the electrical connection of the first low-voltage end；
The grid of M10 is electrically connected with the second pull-down node PD2, and the drain electrode of M10 is electrically connected with PU, the source electrode of M10 with it is described
The electrical connection of first low-voltage end；
The first end of C1 is electrically connected with PU, and the second end of C1 is electrically connected with G_out；
The gate drive signal output circuit includes first gate driving signal output transistor M3, second grid driving
Signal output transistor M11 and third gate drive signal output transistor M11 ', wherein
The grid of M3 is electrically connected with PU, and the source electrode of drain electrode the incoming clock signal CLK, M3 of M3 are electrically connected with G_out；
The grid of M11 is electrically connected with PD1, and the drain electrode of M11 is electrically connected with G_out, and the source electrode of M11 accesses LVGL；
The grid of M11 ' is electrically connected with PD2, and the drain electrode of M11 ' is electrically connected with G_out, and the source electrode of M11 ' accesses LVGL；
The carry signal output circuit includes the first carry signal output transistor M13, the second carry signal output crystalline substance
Body pipe M12 and third carry signal output transistor M12 ', wherein
The grid of M13 is electrically connected with PU, and the source electrode of drain electrode the incoming clock signal CLK, M3 of M13 are electrically connected with Out_c；
The grid of M12 is electrically connected with PD1, and the drain electrode of M12 is electrically connected with Out_c, and the source electrode of M12 accesses LVGL；
The grid of M12 ' is electrically connected with PD2, and the drain electrode of M12 ' is electrically connected with Out_c, and the source electrode of M12 ' accesses LVGL.
In the specific embodiment of shift register cell shown in Fig. 6, all transistors are all NMOS tube, but not with
This is limited.
As shown in fig. 7, the specific embodiment of shift register cell of the present invention is at work, the display cycle includes
Input phase t1, output stage t2, reseting stage t3 and the output cut-off holding stage t4 set gradually；In the display week
Phase, VDD1 are high level, and VDD2 is low level；
In input phase t1, the current potential of PU is 30V or so, and LVGL is -8V, and VGL2 is -8V, M6 and M6 ' it opens, PD1's
The current potential of current potential and PD2 are low level, and M8 and M8 ' are opened, and the current potential of PDCN1 and the current potential of PDCN2 are low level, M14 and
M14 ' shutdown, the gate source voltage of M6 and the gate source voltage of M6 ' are 38V or so；
In output stage t2, the current potential of PU is 45V or so, and LVGL is -8V, and VGL2 is -8V, M6 and M6 ' it opens, PD1's
Current potential is low level, and the current potential of PD2 is low level, and M8 and M8 ' are opened, and the current potential of PDCN1 and PDCN2 are low level, M14 and
M14 ' shutdown, the gate source voltage of M6 and the gate source voltage of M6 ' are 53V or so；
It is low level in the current potential of reseting stage t3 and output cut-off holding stage t4, PU, the current potential of PD1 is 28V or so,
The current potential of PD2 be low level, LVGL be -8V, VGL2 be -15V, M6 and M6 ' shutdown, and the current potential of PDCN1 be high level, M5 and
M5 ' is opened, and M14 and M14 ' are opened, so that the grid of the gate source voltage of grid the access -15V, M6 of the grid of M6 and M6 ' and M6 '
Source voltage is -7V.The specific embodiment of shift register cell of the present invention at work, in input phase t1 and output
The threshold voltage positive excursion of the threshold voltage and M6 ' of stage t2, M6 ends holding stage t4 in reseting stage t3 and output,
The threshold voltage of M6 and the threshold voltage reverse excursion of M6 ', so that the threshold voltage of M6 and the threshold voltage of M6 ' become
To stable state.
At work, the display time includes multiple to the specific embodiment of shift register cell described in the embodiment of the present invention
Show that period, each display period include the first display period and the second display period set gradually；
In the first display period, VDD1 is high level, and VDD2 is low level；
In the second display period, VDD1 is low level, and VDD2 is high level；
The first display period may include at least one display cycle, and described second shows that the period may include
At least one display cycle.
In embodiments of the present invention, when CLK is low level, the current potential of CLK can be -8V, when CLK is high level,
The current potential of CLK can be 32V, and but not limited to this.
Driving method described in the embodiment of the present invention, applied to above-mentioned shift register cell, the driving method packet
It includes:
In reseting stage and output cut-off holding stage, control of the pull-down node control circuit in the current potential of pull-up node
Under, control the separated of the pull-down node and the first voltage end；Bias control circuit controls the electricity of the pull-up node
Position is in predetermined voltage range to control the gate source voltage for the pull-down node control transistor that pull-down node control circuit includes
It is interior.
In the specific implementation, the pull-down node control transistor can be n-type transistor, and the predetermined voltage range is
Less than 0；Alternatively,
The pull-down node control transistor can be p-type transistor, and the predetermined voltage range is greater than 0.
Gate driving circuit described in the embodiment of the present invention includes multistage above-mentioned shift register cell.
Display device described in the embodiment of the present invention includes above-mentioned gate driving circuit.
Display device provided by the embodiment of the present invention can be mobile phone, tablet computer, television set, display, notebook
Any products or components having a display function such as computer, Digital Frame, navigator.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, it can also make several improvements and retouch, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (12)
1. a kind of shift register cell, which is characterized in that including pull-down node control circuit and bias control circuit, wherein
The control terminal of the pull-down node control circuit is electrically connected with pull-up node, the first end of the pull-down node control circuit
It is electrically connected with pull-down node, the second end of the pull-down node control circuit is electrically connected with first voltage end, the pull-down node
Control circuit is used under the control of the current potential of pull-up node, is controlled and is connected between the pull-down node and the first voltage end
Or it disconnects；
The bias control circuit is electrically connected with the pull-up node, in the case where pull-down node control circuit control is described
Draw node and the first voltage end it is separated when, by controlling the current potential of the pull-up node, saved with controlling the drop-down
The gate source voltage for the pull-down node control transistor that point control circuit includes is in predetermined voltage range.
2. shift register cell as described in claim 1, which is characterized in that the pull-down node control transistor is N-shaped
Transistor, the predetermined voltage range are less than 0；Alternatively,
The pull-down node control transistor is p-type transistor, and the predetermined voltage range is greater than 0.
3. shift register cell as described in claim 1, which is characterized in that the pull-down node control circuit includes one
Pull-down node controls transistor；
The control electrode of the pull-down node control transistor is electrically connected with the pull-up node, and the pull-down node controls transistor
The first pole be electrically connected with the pull-down node, the second pole of pull-down node control transistor is electrically connected with first voltage end
It connects；
The bias control circuit includes bias control transistor；
The control electrode of the bias control transistor is electrically connected with bias control terminal, the first pole of the bias control transistor with
The pull-up node electrical connection, the second pole of the bias control transistor is electrically connected with second voltage end；
The bias control terminal is used to provide bias control signal, so that in pull-down node control transistor shutdown,
Control the bias control transistor conducting.
4. shift register cell as claimed in claim 3, which is characterized in that the bias control voltage end is drop-down control
Node；
The pull-down node control circuit further includes drop-down control node control circuit and drop-down control transistor；
The drop-down control node control circuit is used under the control of the current potential of the pull-up node, controls the drop-down control
The current potential of node；
The control electrode of the drop-down control transistor is electrically connected with the drop-down control node, and described pull down controls the of transistor
One pole is electrically connected with power voltage terminal, and the second pole of the drop-down control transistor is electrically connected with the pull-down node.
5. shift register cell as described in claim 3 or 4, which is characterized in that the pull-down node control transistor is n
Transistor npn npn, in pull-down node control transistor shutdown, second voltage is less than first voltage；Alternatively, the drop-down section
Point control transistor is p-type transistor, and in pull-down node control transistor shutdown, second voltage is greater than first voltage；
The first voltage end is for inputting the first voltage, and the second voltage end is for inputting the second voltage.
6. shift register cell as described in claim 1, which is characterized in that the pull-down node includes the first pull-down node
With the second pull-down node；The pull-down node control circuit includes the first pull-down node control transistor and the second pull-down node control
Transistor processed；
The control electrode of the first pull-down node control transistor is electrically connected with the pull-up node, the first pull-down node control
First pole of transistor processed is electrically connected with first pull-down node, the second pole of first pull-down node control transistor with
The electrical connection of first voltage end；
The control electrode of the second pull-down node control transistor is electrically connected with the pull-up node, the second pull-down node control
First pole of transistor processed is electrically connected with second pull-down node, the second pole of second pull-down node control transistor with
The electrical connection of first voltage end；
The bias control circuit includes the first bias control transistor and the second bias control transistor；
The control electrode of first bias control transistor is electrically connected with the first bias control terminal, the first biasing control crystal
First pole of pipe is electrically connected with the pull-up node, and the second pole and the second voltage end of first bias control transistor are electrically connected
It connects；
The control electrode of second bias control transistor is electrically connected with the second bias control terminal, the second biasing control crystal
First pole of pipe is electrically connected with the pull-up node, and the second pole and the tertiary voltage end of second bias control transistor are electrically connected
It connects；
First bias control terminal is for providing the first bias control signal, so that first pull-down node controls crystal
When pipe and second pull-down node control transistor shutdown, the first bias control transistor conducting is controlled；
Second bias control terminal is for providing the second bias control signal, so that first pull-down node controls crystal
When pipe and second pull-down node control transistor shutdown, the second bias control transistor conducting is controlled.
7. shift register cell as claimed in claim 6, which is characterized in that first bias control voltage end is first
Control node is pulled down, second bias control voltage end is the second drop-down control node；
The pull-down node control circuit further includes the first drop-down control node control circuit, the first drop-down control transistor, the
Two drop-down control node control circuits and the second drop-down control transistor；
The first drop-down control node control circuit is used under the control of the current potential of the pull-up node, control described first
Pull down the current potential of control node；
The control electrode of the first drop-down control transistor is electrically connected with the first drop-down control node, the first drop-down control
First pole of transistor processed is electrically connected with the first power voltage terminal, the second pole and described the of the first drop-down control transistor
The electrical connection of one pull-down node；
The second drop-down control node control circuit is used under the control of the current potential of the pull-up node, control described second
Pull down the current potential of control node；
The control electrode of the second drop-down control transistor is electrically connected with the second drop-down control node, the second drop-down control
First pole of transistor processed is electrically connected with second source voltage end, the second pole and described the of the second drop-down control transistor
The electrical connection of two pull-down nodes.
8. shift register cell as claimed in claims 6 or 7, which is characterized in that first pull-down node controls crystal
Pipe and second pull-down node control transistor are all n-type transistor, control transistor and institute in first pull-down node
When stating the control transistor shutdown of the second pull-down node, second voltage is less than first voltage, and tertiary voltage is less than first voltage；Or
Person, the first pull-down node control transistor and second pull-down node control transistor are all p-type transistor, described
When first pull-down node controls transistor and second pull-down node control transistor shutdown, second voltage is greater than the first electricity
Pressure, tertiary voltage are greater than first voltage；
The first voltage end is for inputting the first voltage, and the second voltage end is for inputting the second voltage, institute
Tertiary voltage end is stated for inputting the tertiary voltage end.
9. a kind of driving method, applied to the shift register cell as described in any claim in claim 1 to 8,
It is characterized in that, the driving method includes:
In reseting stage and output cut-off holding stage, pull-down node control circuit is under the control of the current potential of pull-up node, control
Make the separated of the pull-down node and the first voltage end；Bias control circuit controls the current potential of the pull-up node, with
The gate source voltage for the pull-down node control transistor that control pull-down node control circuit includes is in predetermined voltage range.
10. driving method as claimed in claim 9, which is characterized in that the pull-down node control transistor is N-shaped crystal
Pipe, the predetermined voltage range are less than 0；Alternatively,
The pull-down node control transistor is p-type transistor, and the predetermined voltage range is greater than 0.
11. a kind of gate driving circuit, which is characterized in that including multistage as described in any claim in claim 1 to 8
Shift register cell.
12. a kind of display device, which is characterized in that including gate driving circuit as claimed in claim 11.
Priority Applications (2)
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| CN201910528404.0A CN110246447A (en) | 2019-06-18 | 2019-06-18 | Shift register cell, driving method, gate driving circuit and display device |
| PCT/CN2020/082940 WO2020253323A1 (en) | 2019-06-18 | 2020-04-02 | Shift register unit, driving method, gate driving circuit, and display device |
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| CN201910528404.0A CN110246447A (en) | 2019-06-18 | 2019-06-18 | Shift register cell, driving method, gate driving circuit and display device |
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| WO (1) | WO2020253323A1 (en) |
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| US20220327975A1 (en) * | 2020-02-24 | 2022-10-13 | Beijing Boe Display Technology Co., Ltd. | Shift register circuit, gate driving circuit and display apparatus |
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