CN110517622A

CN110517622A - Shift register cell and its driving method, gate driving circuit, display device

Info

Publication number: CN110517622A
Application number: CN201910837935.8A
Authority: CN
Inventors: 谢勇贤; 王慧; 吕凤珍; 刘强
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2019-09-05
Filing date: 2019-09-05
Publication date: 2019-11-29

Abstract

The embodiment of the present invention provides a kind of shift register cell and its driving method, gate driving circuit, display device, is related to field of display technology, can avoid leading to operation irregularity because the noise reduction effect of GOA unit is bad.A kind of shift register cell, it include: the first signal output sub-circuit, for storing the signal from pull-up node, and under the control of the signal from pull-up node, by the first clock signal transmission from the first clock signal terminal to the first signal output end；Second signal exports sub-circuit, under the control of the signal from pull-up node, by the first clock signal transmission from the first clock signal terminal to second signal output end；First noise reduction sub-circuit, for under the control of the first clock signal from the first clock signal terminal, signal from the second signal output end being connected electrically is transmitted to pull-up node, or the signal from the first signal output end being connected electrically is transmitted to pull-up node.

Description

Shift register cell and its driving method, gate driving circuit, display device

Technical field

The present invention relates to field of display technology more particularly to a kind of shift register cell and its driving method, grid to drive Dynamic circuit, display device.

Background technique

Due to the structure of display product or the needs of assembling, meeting edge region leaves the frame that can not be shown, should The presence of frame can reduce the visual effect of display product.Therefore, the display product of narrow frame even Rimless has become pursuit The main trend of high-quality display effect.

Wherein, GOA (Gate Driver on Array, integrated gate drive circuitry) technology can be by gate driving circuit It is integrated in the array substrate of display panel, it is integrated can to save gate driving by the driving chip of external silicon wafer to manufacture for substitution Circuit part, to simplify the structure of display product.This gate switch circuit using GOA Integration ofTechnology in array substrate Referred to as GOA circuit or shift-register circuit, wherein each shift register in the gate switch circuit is also referred to as GOA unit.

In the structure of GOA unit, for example, by 4 thin film transistor (TFT)s (Thin Film Transistor, abbreviation TFT) and The GOA unit of the 4T1C structure of 1 parasitic capacitance (Capacitance, abbreviation C) composition, pull-up node and signal output end It only is pulled down to low potential in reseting stage, and within the time before the arrival of next image frame, then no signal is transmitted to pull-up Node and signal output end cause the signal of pull-up node and signal output end not to be pulled low persistently.At this point, in GOA unit In parasitic capacitance under the influence of, pull-up node is easy to generate noise signal, and leads to GOA unit operation irregularity, it is easy to Influence display product quality.

Summary of the invention

The embodiment of the present invention provides a kind of shift register cell and its driving method, gate driving circuit, display dress It sets, can avoid leading to operation irregularity because the noise reduction effect of GOA unit is bad.

In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that

In a first aspect, providing a kind of shift register cell, comprising: the first noise reduction sub-circuit, the first signal output son electricity Road and second signal export sub-circuit；First signal exports sub-circuit, with pull-up node, the first clock signal terminal and The electrical connection of first signal output end；First signal output sub-circuit be configured as will the signal from the pull-up node into Row storage, and under the control of the signal from the pull-up node, by the first clock from first clock signal terminal Signal is transmitted to first signal output end；The second signal exports sub-circuit, with the pull-up node, it is described first when Clock signal end and the electrical connection of second signal output end；The second signal output sub-circuit is configured as from the pull-up It is under the control of the signal of node, the first clock signal transmission from first clock signal terminal is defeated to the second signal Outlet；The first noise reduction sub-circuit, it is defeated with the pull-up node, first clock signal terminal and the second signal Outlet or first signal output end electrical connection；The first noise reduction sub-circuit is configured as from first clock Under the control of first clock signal of signal end, the signal from the second signal output end being connected electrically is transmitted to The pull-up node saves alternatively, the signal from first signal output end being connected electrically is transmitted to the pull-up Point.

Optionally, the shift register cell further includes the second noise reduction sub-circuit；The second noise reduction sub-circuit, with institute State pull-up node, pull-down node and the electrical connection of first voltage end；The second noise reduction sub-circuit is configured as from described Under the control of the signal of pull-down node, the signal from the first voltage end is transmitted to the pull-up node.

On this basis, optionally, the shift register cell further includes the first signal input sub-circuit；Described first Signal inputs sub-circuit, is electrically connected with the first signal input part and the pull-up node；First signal inputs sub-circuit quilt It is configured under the control of the signal from first signal input part, will be passed from the signal of first signal input part Transport to the pull-up node.

And/or the shift register cell further includes second signal input sub-circuit；The second signal input son electricity Road, with second signal input terminal, the pull-up node, first signal output end, the second signal output end, Yi Ji The electrical connection of one voltage end；The second signal input sub-circuit is configured as in the signal from the second signal input terminal Under control, the signal from the first voltage end is transmitted to the pull-up node, first signal output end and described Second signal output end.

And/or the shift register cell further includes drop-down control sub-circuit；The drop-down controls sub-circuit, with the Two clock signal terminals, the pull-up node, the pull-down node and the electrical connection of first voltage end；The drop-down controls sub-circuit It is configured as in the common of the second clock signal from the second clock signal end and the signal from the pull-up node Under control, distinguishes section in different times, the signal from the first voltage end is transmitted to the pull-down node, will be come from The second clock signal of the second clock signal end is transmitted to the pull-down node.

And/or the shift register cell further includes drop-down sub-circuit；The drop-down sub-circuit is saved with the drop-down Point, first signal output end, the second signal output end and the electrical connection of first voltage end；The drop-down sub-circuit It is configured as under the control of the signal from the pull-down node, the signal from the first voltage end is transmitted to described First signal output end and the second signal output end.

Optionally, the first noise reduction sub-circuit includes the first transistor；In the first noise reduction sub-circuit and described the In the case that binary signal output end is electrically connected, the grid of the first transistor is electrically connected with first clock signal terminal, institute The first pole for stating the first transistor is electrically connected with the second signal output end, the second pole of the first transistor and it is described on Draw node electrical connection；In the case where the first noise reduction sub-circuit is electrically connected with first signal output end, described first The grid of transistor is electrically connected with first clock signal terminal, and the first pole of the first transistor and first signal are defeated Outlet electrical connection, the second pole of the first transistor is electrically connected with the pull-up node.

Optionally, the first signal output sub-circuit includes second transistor and storage capacitance；The second transistor Grid be electrically connected with the pull-up node, the first pole of the second transistor is electrically connected with first clock signal terminal, Second pole of the second transistor is electrically connected with first signal output end；First pole of the storage capacitance and it is described on Node electrical connection is drawn, the second pole of the storage capacitance is electrically connected with first signal output end；And/or second letter Number output sub-circuit include third transistor；The grid of the third transistor is electrically connected with the pull-up node, the third First pole of transistor is electrically connected with first clock signal terminal, the second pole of the third transistor and the second signal Output end electrical connection.

Optionally, the second noise reduction sub-circuit includes the 4th transistor；The grid of 4th transistor and it is described under Node electrical connection is drawn, the first pole of the 4th transistor is electrically connected with the pull-up node, and the second of the 4th transistor Pole is electrically connected with the first voltage end.

Optionally, in the case where the shift register cell includes the first signal input sub-circuit, first letter Number input sub-circuit include the 5th transistor；The grid of 5th transistor and first extremely with first signal input part Electrical connection, the second pole of the 5th transistor is electrically connected with the pull-up node.

And/or in the case where the shift register cell includes second signal input sub-circuit, the second signal Inputting sub-circuit includes the 6th transistor, the 7th transistor and the 8th transistor；The grid of 6th transistor with it is described The electrical connection of second signal input terminal, the first pole of the 6th transistor are electrically connected with the pull-up node, the 6th crystal Second pole of pipe is electrically connected with the first voltage end；The grid of 7th transistor is electrically connected with the second signal input terminal Connect, the first pole of the 7th transistor is electrically connected with the second signal output end, the second pole of the 7th transistor with The first voltage end electrical connection；The grid of 8th transistor is electrically connected with the second signal input terminal, and the described 8th First pole of transistor is electrically connected with first signal output end, the second pole of the 8th transistor and the first voltage End electrical connection.

And/or in the case where the shift register cell includes drop-down control sub-circuit, the drop-down control son electricity Road includes the 9th transistor, the tenth transistor, the 11st transistor and the tenth two-transistor；The grid of 9th transistor It is extremely electrically connected with the second clock signal end with first, the second pole and the tenth transistor of the 9th transistor The electrical connection of first pole；The grid of tenth transistor is electrically connected with the pull-up node, the second pole of the tenth transistor It is electrically connected with the first voltage end；Second pole of the grid of the 11st transistor and the 9th transistor and described the First pole of ten transistors is electrically connected, and the first pole of the 11st transistor is electrically connected with the second clock signal end, institute The second pole for stating the 11st transistor is electrically connected with the pull-down node；The grid of tenth two-transistor and the pull-up save Point electrical connection, the first pole of the tenth two-transistor are electrically connected with the pull-down node, and the second of the tenth two-transistor Pole is electrically connected with the first voltage end.

And/or in the case where the shift register cell includes drop-down sub-circuit, the drop-down sub-circuit includes the 13 transistors and the 14th transistor；The grid of 13rd transistor and pull-down node electrical connection, the described tenth First pole of three transistors is electrically connected with first signal output end, the second pole and described first of the 13rd transistor Voltage end electrical connection；The grid of 14th transistor is electrically connected with the pull-down node, and the of the 14th transistor One pole is electrically connected with the second signal output end, and the second pole and the first voltage end of the 14th transistor are electrically connected It connects.

Second aspect provides a kind of shift register cell, comprising: the first noise reduction sub-circuit and the first signal output son electricity Road；First signal exports sub-circuit, is electrically connected with pull-up node, the first clock signal terminal and the first signal output end； The first signal output sub-circuit is configured as to store from the signal of the pull-up node, and is coming from described Under the control for drawing the signal of node, by the first clock signal transmission from first clock signal terminal to first signal Output end；The first noise reduction sub-circuit, it is defeated with the pull-up node, first clock signal terminal and first signal Outlet electrical connection；The first noise reduction sub-circuit is configured as in the first clock signal from first clock signal terminal Under control, the signal from first signal output end is transmitted to the pull-up node.

On this basis, optionally, the first noise reduction sub-circuit includes the first transistor；The grid of the first transistor Pole is electrically connected with first clock signal terminal, and the first pole of the first transistor is electrically connected with first signal output end It connects, the second pole of the first transistor is electrically connected with the pull-up node.

Optionally, the first signal output sub-circuit includes second transistor and storage capacitance；The second transistor Grid be electrically connected with the pull-up node, the first pole of the second transistor is electrically connected with first clock signal terminal, Second pole of the second transistor is electrically connected with first signal output end；First pole of the storage capacitance and it is described on Node electrical connection is drawn, the second pole of the storage capacitance is electrically connected with first signal output end.

The third aspect provides a kind of gate driving circuit, including multiple cascade such as above-mentioned shift register cell；Often First signal output end of the shift register cell of grade is electrically connected with a grid line.

On this basis, optionally, in the case where the shift register cell includes second signal output sub-circuit, Other than first order shift register cell, the first signal input part and its upper level of every level-one shift register cell are moved The second signal output end of bit register unit is connected；Other than afterbody shift register cell, every level-one displacement The second signal input terminal of register cell is connected with the second signal output end of its next stage shift register cell.

Fourth aspect provides a kind of display device, including above-mentioned gate driving circuit.

5th aspect, provides a kind of driving method of shift register cell, and the shift register cell includes first Noise reduction sub-circuit, the first signal output sub-circuit, second signal output sub-circuit, the second noise reduction sub-circuit, the input of the first signal Sub-circuit and drop-down control sub-circuit；The first noise reduction sub-circuit and pull-up node, the first clock signal terminal, Yi Ji One signal output end or the electrical connection of second signal output end；The first signal output sub-circuit and the pull-up node, institute State the first clock signal terminal and first signal output end electrical connection；The second signal output sub-circuit and the pull-up Node, first clock signal terminal and second signal output end electrical connection；The second noise reduction sub-circuit with it is described Pull-up node, pull-down node and the electrical connection of first voltage end；First signal inputs sub-circuit, inputs with the first signal End and pull-up node electrical connection；Drop-down control sub-circuit and second clock signal end, the pull-up node, it is described under Draw node and first voltage end electrical connection；The driving method of the shift register cell includes: in the defeated of picture frame Enter the stage: under the control of the signal from first signal input part, the first signal input sub-circuit will come from institute The signal for stating the first signal input part is transmitted to the pull-up node；In the output stage of described image frame: coming from described Under the control for drawing the signal of node, first signal exports sub-circuit for the first clock from first clock signal terminal Signal is transmitted to first signal output end, and the second signal output sub-circuit will be from first clock signal terminal First clock signal transmission is to the second signal output end；In the noise reduction stage of described image frame: when coming from described first Under the control of first clock signal of clock signal end, the first noise reduction sub-circuit will be from second letter being connected electrically The signal of number output end is transmitted to the pull-up node, alternatively, by from first signal output end being connected electrically Signal is transmitted to the pull-up node；Also, in the second clock signal from the second clock signal end and from described Under the co- controlling of the signal of pull-up node, when the drop-down control sub-circuit is by from the second of the second clock signal end Clock signal is transmitted to pull-down node, so that the signal from the first voltage end is transmitted to institute by the second noise reduction sub-circuit State pull-up node.

The embodiment of the present invention provides a kind of shift register cell and its driving method, gate driving circuit, display device, Sub-circuit is exported including the first noise reduction sub-circuit, the first signal output sub-circuit and second signal.First noise reduction sub-circuit, with Pull-up node, the first clock signal terminal and second signal output end or the electrical connection of the first signal output end.First signal is defeated Sub-circuit out is electrically connected with pull-up node, the first clock signal terminal and the first signal output end.Second signal output son electricity Road is electrically connected with pull-up node, the first clock signal terminal and second signal output end.First noise reduction sub-circuit is for coming from Under the control of first clock signal of the first clock signal terminal, it will be passed from the signal for the second signal output end being connected electrically Pull-up node is transported to, alternatively, the signal from the first signal output end being connected electrically is transmitted to pull-up node.First letter Number output sub-circuit is for storing the signal from pull-up node, and under the control of the signal from pull-up node, By the first clock signal transmission from the first clock signal terminal to the first signal output end.Second signal output sub-circuit is used for Under the control of the signal from pull-up node, by the first clock signal transmission from the first clock signal terminal to second signal Output end.Therefore, under the non-effective output stage of picture frame, the control of the first clock signal of the first clock signal terminal, the One noise reduction sub-circuit is opened, and the signal of second signal output end or the first signal output end is transmitted to pull-up node, so that The current potential of the signal of pull-up node is low potential, realizes and carries out noise reduction to pull-up node, exists to improve shift register cell The noise reduction effect of the non-effective output stage of picture frame avoids the noise signal generated by pull-up node, leads to shift register The problem of cell operation is abnormal, reduces display product quality.

Detailed description of the invention

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with It obtains other drawings based on these drawings.

Fig. 1 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention；

Fig. 2 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention；

Fig. 3 is the structural schematic diagram of another gate driving circuit provided in an embodiment of the present invention；

Fig. 4 is a kind of structural schematic diagram of shift register cell provided in an embodiment of the present invention；

Fig. 5 is the concrete structure schematic diagram of the shift register cell in Fig. 4；

Fig. 6 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention；

Fig. 7 is the concrete structure schematic diagram of the shift register cell in Fig. 6；

Fig. 8 is the signal timing diagram for controlling shift register cell as shown in figure 5 and figure 7；

Fig. 9 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention；

Figure 10 is the concrete structure schematic diagram of the shift register cell in Fig. 9；

Figure 11 is the signal timing diagram for controlling shift register cell as shown in Figure 10；

Figure 12 is a kind of structural schematic diagram for shift register cell that the prior art provides.

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.

The embodiment of the present invention provides a kind of display device, including display panel 10.

As shown in Figure 1, the display panel 10 include viewing area (area active area, AA) and peripheral region S, peripheral region S Such as around the circle setting of the area AA one.The above-mentioned area AA includes multiple sub-pix P.

The explanation carried out so that above-mentioned multiple sub-pix P are in array format arrangement as an example in Fig. 1.In the case, along level The sub-pix P that direction X is arranged in a row is known as with a line sub-pix, and the sub-pix P that Y is arranged in a row along the vertical direction is referred to as same One column sub-pix.The pixel circuit shown for controlling sub-pix P is provided in sub-pix P.The pixel circuit includes more A transistor.

On this basis, as shown in Figure 1, display panel 10 further includes more grid lines (G1, G2 ... Gn).Optionally, together A line sub-pix can be electrically connected with a grid line.

Based on this, in some embodiments of the invention, as shown in Figure 1, above-mentioned display device further includes being set to week The gate driving circuit 20 of border area S.

As shown in Fig. 2, the gate driving circuit 20 includes multiple shift registers (SR1, SR2 ... SRn).

First signal output end Output1 of each shift register is connect with a grid line, sub- to a line by grid line The grid of at least one transistor in each sub-pix of pixel provides gated sweep signal.

In some embodiments of the invention, shift register cell includes being electrically connected with the first signal output end Output1 The the first signal output sub-circuit connect.

In the case, optionally, as shown in figure 3, when multiple shift registers successively cascade, in addition to the first order shifts Other than register cell SR1, the first signal input part IN1 and its upper level shift register of every level-one shift register cell First signal output end Output1 of unit is connected.Other than afterbody shift register cell SRn, every level-one is moved The second signal input terminal IN2 of bit register unit and the first signal output end of its next stage shift register cell Output1 is connected.

In other embodiments of the invention, shift register cell is in addition to including and the first signal output end It further include the be electrically connected with second signal output end Output2 except the first signal output sub-circuit of Output1 electrical connection Binary signal exports sub-circuit.

In the case, optionally, as shown in Fig. 2, when multiple shift registers successively cascade, in addition to the first order shifts Other than register cell SR1, the first signal input part IN1 and its upper level shift register of every level-one shift register cell The second signal output end Output2 of unit is connected.Also, it is each other than afterbody shift register cell SRn The second signal output end of the second signal input terminal IN2 connection next stage shift register cell of grade shift register cell Output2。

It should be noted that above-mentioned first order shift register cell SR1 and afterbody shift register cell SRn are Opposite, depending on 20 forward scan of gate driving circuit and reverse scan.The gate driving circuit 20 be used for grid line into When row forward scan, according to the scanning sequency of grid line, for providing the shift register cell of scanning signal to first grid line, For first order shift register cell SR1；For providing the shift register cell of scanning signal to last root grid line, for most Rear stage shift register cell SRn.When the gate driving circuit 20 is used to carry out reverse scan to grid line, according to sweeping for grid line Sequence is retouched, last root grid line is first entered scanning signal, thus, for providing the displacement of scanning signal to last root grid line Register cell is first order shift register cell SR1；For providing the shift register of scanning signal to first grid line Unit is afterbody shift register cell SRn.

On the basis of above-mentioned, optionally, as shown in Figures 2 and 3, the first letter of first order shift register cell SR1 Number input terminal IN1 can connect initial signal end STV, the second signal input terminal IN2 of afterbody shift register cell SRn It can connect above-mentioned initial signal end STV.

Wherein, initial signal end STV is for exporting initial signal, the first order shift register of the gate driving circuit 20 Cell S R1 starts to progressively scan grid line after receiving above-mentioned initial signal.

In the case, when the first of the initial signal input first order shift register cell SR1 of initial signal end STV When signal input part IN1, the second signal input terminal IN2 of afterbody shift register cell SRn can be by initial signal end The initial signal of STV resetting to afterbody shift register cell SRn as reset signal.

Herein, initialization can also be separately provided in the second signal input terminal IN2 of afterbody shift register cell SRn Signal end, the initializing signal end can transmit multiple to the second signal input terminal IN2 of afterbody shift register cell SRn Position signal.

Based on the description above, as shown in Figure 4 and Figure 6, the embodiment of the present invention provides a kind of shift register cell, packet It includes: the first noise reduction sub-circuit 21, the first signal output sub-circuit 22 and second signal output sub-circuit 23.

Wherein, as shown in figure 4, the first noise reduction sub-circuit 21, with pull-up node PU, the first clock signal terminal CLK and Binary signal output end Output2 electrical connection；Alternatively, as shown in fig. 6, the first noise reduction sub-circuit 21, when with pull-up node PU, first Clock signal end CLK and the first signal output end Output1 electrical connection.

First signal exports sub-circuit 22, with pull-up node PU, the first clock signal terminal CLK and the first signal output end Output1 electrical connection.

Second signal exports sub-circuit 23, with pull-up node PU, the first clock signal terminal CLK and second signal output end Output2 electrical connection.

First noise reduction sub-circuit 21 is used under the control of the first clock signal from the first clock signal terminal CLK, will Signal from the second signal output end Output2 being connected electrically is transmitted to pull-up node PU, alternatively, will be from electric with it The signal of first signal output end Output1 of connection is transmitted to pull-up node PU.

It is understood that including the first signal output sub-circuit 22 and second signal output in shift register cell In the case where circuit 23, as shown in figure 4, when the first noise reduction sub-circuit 21 is electrically connected with second signal output end Output2, In Under the control of the first clock signal from the first clock signal terminal CLK, the first noise reduction sub-circuit 21 will come from and be connected electrically The signal of second signal output end Output2 be transmitted to pull-up node PU.Alternatively, as shown in fig. 6, when the first noise reduction sub-circuit 21 with the first signal output end Output1 when being electrically connected, in the control of the first clock signal from the first clock signal terminal CLK Under, the signal from the first signal output end Output1 being connected electrically is transmitted to pull-up section by the first noise reduction sub-circuit 21 Point PU.

First signal output sub-circuit 22 is saved for storing the signal from pull-up node PU, and from pull-up Under the control of the signal of point PU, by the first clock signal transmission from the first clock signal terminal CLK to the first signal output end Output1。

Second signal exports sub-circuit 23 and is used under the control of the signal from pull-up node PU, will come from the first clock The first clock signal transmission of signal end CLK is to second signal output end Output2.

Due to the non-effective output stage (that is, remaining time in addition to effective output stage) in picture frame, the first signal Output end Output1 and second signal output end Output2 is low potential, therefore, when the first noise reduction sub-circuit 21 and second When signal output end Output2 is electrically connected, first clock signal control of the first noise reduction sub-circuit 21 in the first clock signal terminal CLK System is lower to open, and the signal of second signal output end Output2 is transmitted to pull-up node PU, so that the current potential of pull-up node PU is Low potential, so as to carry out noise reduction to pull-up node PU.Alternatively, when the first noise reduction sub-circuit 21 and the first signal output end When Output1 is electrically connected, the first noise reduction sub-circuit 21 is opened under the first clock signal control of the first clock signal terminal CLK, The signal of first signal output end Output1 is transmitted to pull-up node PU, so that the current potential of pull-up node PU is low potential, from And noise reduction can be carried out to pull-up node PU.

In conclusion a kind of shift register cell provided in an embodiment of the present invention, including the first noise reduction sub-circuit 21, One signal exports sub-circuit 22 and second signal exports sub-circuit 23.First noise reduction sub-circuit 21, with pull-up node PU, first Clock signal terminal CLK and second signal output end Output2 or the first signal output end Output1 electrical connection.First letter Number output sub-circuit 22, be electrically connected with pull-up node PU, the first clock signal terminal CLK and the first signal output end Output1. Second signal exports sub-circuit 23, with pull-up node PU, the first clock signal terminal CLK and second signal output end Output2 Electrical connection.First noise reduction sub-circuit 21 is used under the control of the first clock signal from the first clock signal terminal CLK, in the future It is transmitted to pull-up node PU from the signal for the second signal output end Output2 being connected electrically, is electrically connected alternatively, will come from it The signal of the first signal output end Output1 connect is transmitted to pull-up node PU.First signal exports sub-circuit 22 in the future It is stored, and under the control of the signal from pull-up node PU, will be believed from the first clock from the signal of pull-up node PU Number end CLK the first clock signal transmission to the first signal output end Output1.Second signal exports sub-circuit 23 and is used to come From under the control of the signal of pull-up node PU, by the first clock signal transmission from the first clock signal terminal CLK to the second letter Number output end Output2.Therefore, in the non-effective output stage of picture frame, the first clock signal of the first clock signal terminal CLK Control under, the first noise reduction sub-circuit 21 open, by second signal output end Output2 or the first signal output end The signal of Output1 is transmitted to pull-up node PU, so that the current potential of the signal of pull-up node PU is low potential, realizes and saves to pull-up Point PU carries out noise reduction, to improve shift register cell in the noise reduction effect of the non-effective output stage of picture frame, avoid because The problem of noise signal that pull-up node PU is generated leads to shift register cell operation irregularity, reduces display product quality.

In some embodiments of the invention, as shown in Figure 4 and Figure 6, shift register cell further includes the second noise reduction Circuit 24.

Second noise reduction sub-circuit 24 is connect with pull-up node PU, pull-down node PD and first voltage end electricity VGL.

Second noise reduction sub-circuit 24 is used under the control of the signal from pull-down node PD, will come from first voltage end The signal of VGL is transmitted to pull-up node PU.

Wherein, in a picture frame, first voltage end VGL is low level signal.

It is understood that the second noise reduction sub-circuit 24 is opened under the control of the signal of pull-down node PD, by the first electricity The low level signal of pressure side VGL is transmitted to pull-up node PU, so that the current potential of pull-up node PU is low potential, to save to pull-up Point PU carries out noise reduction.

On this basis, in the non-effective output stage of picture frame, the first noise reduction sub-circuit 21 and the second noise reduction sub-circuit 24 can carry out noise reduction to pull-up node PU, to improve the noise reduction effect of shift register cell.

In some embodiments of the invention, as shown in Figure 4 and Figure 6, shift register cell further includes that the first signal is defeated Enter sub-circuit 25.

First signal input sub-circuit 25 is electrically connected with the first signal input part IN1 and pull-up node PU.

First signal inputs sub-circuit 25 and is used under the control of the signal from the first signal input part IN1, will come from The signal of first signal input part IN1 is transmitted to pull-up node PU.

In some embodiments of the invention, as shown in Figure 4 and Figure 6, shift register cell further includes that second signal is defeated Enter sub-circuit 26.

Second signal input sub-circuit 26 and second signal input terminal IN2, pull-up node PU,

It first signal output end Output1, second signal output end Output2 and states first voltage end VGL and is electrically connected It connects.

Second signal inputs sub-circuit 26 and is used under the control of the signal from second signal input terminal IN2, will come from The signal of first voltage end VGL is transmitted to pull-up node PU, the first signal output end Output1 and second signal output end Output2。

In some embodiments of the invention, as shown in Figure 4 and Figure 6, shift register cell further includes drop-down control Circuit 27.

Drop-down control sub-circuit 27 and second clock signal end CLKB, pull-up node PU, the electricity of pull-down node PD and first Pressure side VGL electrical connection.

Drop-down control sub-circuit 27 is used in the second clock signal from second clock signal end CLKB and from pull-up Under the co- controlling of the signal of node PU, distinguishes section in different times, the signal from first voltage end VGL is transmitted to down Node PD is drawn, the second clock signal from second clock signal end CLKB is transmitted to pull-down node PD.

It should be noted that the of the first clock signal of the first clock signal terminal CLK and second clock signal end CLKB The duty ratio of two clock signals is identical, and the first clock signal of the first clock signal terminal CLK and second clock signal end CLKB Second clock signal phase difference be 180 degree.

On this basis, in some embodiments of the invention, above-mentioned display device further includes and gate driving circuit The timing control IC (Integrated Circuit, integrated circuit) and level conversion IC of electrical connection.Wherein, timing control IC can To control duty ratio and the period of clock signal, level conversion IC can control the height of the current potential of clock signal.In this situation Under, by timing control IC and level conversion IC can each shift register cell into gate driving circuit it is corresponding Clock signal.

It should be noted that the embodiment of the present invention is to pass through 2 clock signal terminals (the first clock signal terminal CLK and the Two clock signal terminal CLKB) it is illustrated to the case where each cascade shift register cell transmission clock signal.In addition, this Field technical staff can according to the actual situation, in the case where guaranteeing shift register cell normal operating conditions, to clock The number of signal end is designed, for example, passing through 4 clock signal terminals or 6 clock signal terminals or 8 clock signal terminals Deng the clock signal transmitted to each cascade shift register cell.

In some embodiments of the invention, as shown in Figure 4 and Figure 6, shift register cell further includes drop-down sub-circuit 28。

Pull down sub-circuit 28 and pull-down node PD, the first signal output end Output1, second signal output end Output2, And first voltage end VGL electrical connection.

Sub-circuit 28 is pulled down to be used under the control of the signal from pull-down node PD, it will be from first voltage end VGL's Signal is transmitted to the first signal output end Output1 and second signal output end Output2.

Detailed illustrate is carried out to the structure of each sub-circuit in Fig. 4 and shift register cell shown in fig. 6 below It is bright.

Specifically, in some embodiments of the invention, as shown in figure 5 and figure 7, the first noise reduction sub-circuit 21 includes first Transistor M1.

Wherein, as shown in figure 5, the grid of the first transistor M1 is electrically connected with the first clock signal terminal CLK, the first transistor The first pole of M1 and second signal output end Output2, the second pole of the first transistor M1 is electrically connected with pull-up node PU；Or Person, as shown in fig. 7, the grid of the first transistor M1 is electrically connected with the first clock signal terminal CLK, the first pole of the first transistor M1 It is electrically connected with the first signal output end Output1, the second pole of the first transistor M1 is electrically connected with pull-up node PU.

In some embodiments of the invention, as shown in figure 5 and figure 7, the first signal output sub-circuit 22 includes second brilliant Body pipe M2 and storage capacitance C.

The grid of second transistor M2 is electrically connected with pull-up node PU, and the first pole of second transistor M2 and the first clock are believed Number end CLK electrical connection, the second pole of second transistor M2 is electrically connected with the first signal output end Output1.

The first pole of storage capacitance C is electrically connected with pull-up node PU, the second pole of storage capacitance C and the first signal output end Output1 electrical connection.

And/or

In some embodiments of the invention, as shown in figure 5 and figure 7, second signal output sub-circuit 23 includes that third is brilliant Body pipe M3.

The grid of third transistor M3 is electrically connected with pull-up node PU, and the first pole of third transistor M3 and the first clock are believed Number end CLK electrical connection, the second pole of third transistor M3 is electrically connected with second signal output end Output2.

In some embodiments of the invention, as shown in figure 5 and figure 7, the second noise reduction sub-circuit 24 includes the 4th transistor M4。

The grid of 4th transistor M4 is electrically connected with pull-down node PD, the first pole of the 4th transistor M4 and pull-up node PU Electrical connection, the second pole of the 4th transistor M4 is electrically connected with first voltage end VGL.

It in some embodiments of the invention, as shown in figure 5 and figure 7, include that the first signal is defeated in shift register cell In the case where entering sub-circuit 25, it includes the 5th transistor M5 that the first signal, which inputs sub-circuit 25,.

The grid of 5th transistor M5 and first is extremely electrically connected with the first signal input part Output1, the 5th transistor The second pole of M5 is electrically connected with pull-up node PU.

And/or

It in some embodiments of the invention, as shown in figure 5 and figure 7, include that second signal is defeated in shift register cell In the case where entering sub-circuit 26, it includes the 6th transistor M6, the 7th transistor M7 and the 8th that second signal, which inputs sub-circuit 26, Transistor M8.

The grid of 6th transistor M6 is electrically connected with second signal input terminal IN2, the first pole of the 6th transistor M6 with it is upper Node PU electrical connection is drawn, the second pole of the 6th transistor M6 is electrically connected with first voltage end VGL.

The grid of 7th transistor M7 is electrically connected with second signal input terminal IN2, the first pole of the 7th transistor M7 and the Binary signal output end Output2 electrical connection, the second pole of the 7th transistor M7 is electrically connected with first voltage end VGL.

The grid of 8th transistor M8 is electrically connected with second signal input terminal IN2, the first pole of the 8th transistor M8 and the One signal output end Output1 electrical connection, the second pole of the 8th transistor M8 is electrically connected with first voltage end VGL.

And/or

It in some embodiments of the invention, as shown in figure 5 and figure 7, include drop-down control in shift register cell In the case where circuit 27, drop-down control sub-circuit 27 includes the 9th transistor M9, the tenth transistor M10, the 11st transistor M11 And the tenth two-transistor M12.

The grid of 9th transistor M9 and first is extremely electrically connected with second clock signal end CLK, the 9th transistor M9's Second pole is electrically connected with the first pole of the tenth transistor M10.

The grid of tenth transistor M10 is electrically connected with pull-up node PU, the second pole of the tenth transistor M10 and first voltage Hold VGL electrical connection.

The first of the grid of 11st transistor M11 and the second pole of the 9th transistor M9 and the tenth transistor M10 is extremely electric Connection, the first pole of the 11st transistor M11 are electrically connected with second clock signal end CLKB, and the second of the 11st transistor M11 Pole is electrically connected with pull-down node PD.

The grid of tenth two-transistor M12 is electrically connected with pull-up node PU, the first pole of the tenth two-transistor M12 and drop-down Node PD electrical connection, the second pole of the tenth two-transistor M12 is electrically connected with first voltage end VGL.

And/or

It in some embodiments of the invention, as shown in figure 5 and figure 7, include drop-down sub-circuit in shift register cell In the case where 28, drop-down sub-circuit 28 includes the 13rd transistor M13 and the 14th transistor M14.

The grid and pull-down node PD of 13rd transistor M13 is electrically connected, the first pole and first of the 13rd transistor M13 Signal output end Output1 electrical connection, the second pole of the 13rd transistor M13 is electrically connected with first voltage end VGL.

The grid of 14th transistor M14 is electrically connected with pull-down node PD, the first pole and second of the 14th transistor M14 Signal output end Output2 electrical connection, the second pole of the 14th transistor M14 is electrically connected with first voltage end VGL.

It should be noted that above-mentioned transistor can be N-type transistor, or P-type transistor；It can be enhanced Transistor, or depletion mode transistor；The first of above-mentioned transistor extremely can be source electrode, and second can be extremely drain electrode, or The first of the above-mentioned transistor of person can be extremely drain electrode, and the second extremely source electrode, this is not limited by the present invention.

In addition, the present invention is illustrated so that above-mentioned transistor is N-type transistor as an example.Also, first voltage end VGL Constant output low level, the first signal input part IN1 receive input signal INPUT, and second signal input terminal IN2, which is received, resets letter Number RESET.Wherein " 0 " indicates low level, and " 1 " indicates high level.

In some embodiments of the invention, the first noise reduction sub-circuit 21 and pull-up node PU, the first clock signal terminal CLK and second signal output end Output2 electrical connection.

In the case, signal timing diagram as shown in connection with fig. 8, to shift register cell shown in fig. 5 different The working condition in stage (P1~P4) carries out detailed illustration.

In input phase P1, INPUT=1, RESET=0, CLK=0, CLKB=1.

In the case, since the signal from the first signal input part IN1 is high level, the 5th transistor M5 Conducting, so that the high level of the first signal input part IN1 is transmitted to pull-up node PU, to fill to pull-up node PU Electricity, so that the current potential of pull-up node PU increases.

At this point, storage capacitance C stores the voltage for being transmitted to pull-up node PU.Also, with pull-up node PU's Current potential gradually rises, so that second transistor M2 is connected under the control of pull-up node PU high potential, so that the first clock be believed Number end CLK low level signal be transmitted to the first signal output end Output1.

Meanwhile under the control of pull-up node PU high potential, third transistor M3 is also switched on, by the first clock signal terminal The low level of CLK is transmitted to second signal output end Output2.

Also, the control of the low level signal of the first clock signal terminal CLK, the first transistor M1 cut-off.Thus will not shadow Sound charges to pull-up node PU.

In addition, as shown in figure 5, under the control of pull-up node PU high potential, the tenth transistor M10 and the tenth two-transistor M12 conducting, under the control of second clock signal end CKLB high level, the 9th transistor M9 conducting, but due to the tenth transistor The breadth length ratio of M10 channel is greater than the breadth length ratio of the 9th transistor M9 channel, so that the grid of the 11st transistor M11 is low electricity It is flat, control the 11st transistor M11 cut-off, so that the current potential of pull-down node PD can be still pulled down to by the tenth two-transistor M12 The low level of first voltage end VGL.At this point, under the control of pull-down node PD low potential, the 4th transistor M4, the 13rd crystal Pipe M13 and the 14th transistor M14 are in off state.

In conclusion the first signal output end Output1 and second signal output end Output2 are equal in input phase P1 Export low level.

In output stage P2, INPUT=0, RESET=0, CLK=1, CLKB=0.

In the case, since the signal from the first signal input part IN1 is low level, at the 5th transistor M5 In off state.Capacitor C discharges the input phase P1 high level stored, to charge to pull-up node PU, thus So that second transistor M2 is kept it turned on.At this point, the high level of the first clock signal terminal CLK is passed by second transistor M2 Transport to the first signal output end Output1.

Also, under the control of pull-up node PU high potential, third transistor M3 is kept it turned on, so that the first clock The high level of signal end CLK is transmitted to second signal output end Output2 by third transistor M3.

At this point, under the control of the high level signal of the first clock signal terminal CLK, the first transistor M1 conducting, so that on The high level signal of node PU is drawn to be transmitted to second signal output end Output2, so as to shorten second signal output end Output2 The time that current potential rises.

On this basis, under bootstrapping (Bootstrapping) effect of storage capacitance C, the current potential of pull-up node PU into One step increases, to maintain second transistor M2 and third transistor M3 to be in the state of conducting, so that the first clock is believed The high level of number end CLK can be continual and steady be transmitted to the first signal output end Output1 and second signal output end Output2。

In addition, under the control of the low level signal of second clock signal end CLKB, the 9th transistor M9 cut-off is being pulled up Under the control of node PU high potential, the tenth transistor M10 conducting, and the low level signal of first voltage end VGL is transmitted to the 11 crystal M11, control the 11st transistor M11 cut-off.At this point, the 12nd is brilliant under the control of pull-up node PU high potential The low level signal of first voltage end VGL is transmitted to pull-down node PD by body pipe M12 conducting, the tenth two-transistor M12.In this feelings Under condition, the 4th transistor M4, the 13rd transistor M13 and the 14th transistor M14 are in the control of pull-down node PD low potential System is lower to be in off state.

In conclusion the first signal output end Output1 and second signal output end Output2 are equal in output stage P2 Export high level.

In reseting stage P3, INPUT=0, RESET=1, CLK=0, CLKB=1.

In the case, since the signal from the first signal input part IN1 is low level, at the 5th transistor M5 In off state.Under the control of the high level signal from second signal input terminal IN2, the 6th transistor M6, the 7th crystal Pipe M7 and the 8th transistor M8 conducting.The current potential of pull-up node PU is pulled down to first voltage end by the 6th transistor M6 The low level of LVGL, to be resetted to pull-up node PU.By the 7th transistor M7 by second signal output end Output2's Current potential is pulled down to first voltage end VGL, to reset to second signal output end Output2.It will by the 8th transistor M8 The current potential of first signal output end Output1 is pulled down to first voltage end VGL, to carry out to the first signal output end Output1 It resets.

At this point, second transistor M2 and third transistor M3 are in cut-off shape under the control of pull-up node PU low potential State.

Also, under the control of pull-up node PU low potential, the tenth transistor M10 and the tenth two-transistor M12 are also cut Only.On this basis, due to the high level signal control from second clock signal end CLKB, so that the 9th transistor M9 is led It is logical, and the high level of second clock signal end CLKB is transmitted to the 11st transistor M11, the 11st transistor M11 of control is led Logical, the high level of second clock signal end CLKB is transmitted to pull-down node PD by the 11st transistor M11.At this point, being saved in drop-down Under the control of the high level signal of point PD, the 4th transistor M4 conducting, by the 4th transistor M4 by the current potential of pull-up node PU It is pulled down to first voltage end VGL.Likewise, under the control of the high level signal of pull-down node PD, the 13rd transistor M13 and The current potential of first signal output end Output1 is pulled down to the by the 13rd transistor M13 by the 14th transistor M14 conducting The current potential of second signal output end Output2 is pulled down to first voltage end by the 14th transistor M14 by one voltage end VGL VGL。

In conclusion the first signal output end Output1 and second signal output end Output2 are equal in reseting stage P3 Export low level signal.

In noise reduction stage P4, INPUT=0, RESET=0.

In the case, since the signal from the first signal input part IN1 is low level, at the 5th transistor M5 In off state.Also, under the control of the low level signal from second signal input terminal IN2, the 6th transistor M6, the 7th Transistor M7 and the 8th transistor M8 are turned off.

On this basis, work as CLK=1, when CLKB=0, the current potential of pull-up node PU will keep the low potential of last moment.

Under the control of pull-up node PU low potential, the tenth transistor M10 and the tenth two-transistor M12 are in cut-off shape State, under the control of second clock signal end CLKB low potential, the 9th transistor M9 cut-off, the 11st transistor M11 is also switched off. At this point, the 11st transistor M11 and the tenth two-transistor M12 can have leakage current.Therefore, pass through the 11st transistor M11 The low level signal of second clock signal end CLKB can be transmitted to pull-down node PD, it can be with by the tenth two-transistor M12 The low level signal of first voltage end VGL is transmitted to pull-down node PD, so that pull-down node PD is low potential.At this point, Under the control of pull-down node PD low potential, the 4th transistor M4 cut-off.

On this basis, under the control of pull-up node PU low potential, second transistor M2 and third transistor M3 locate In off state, and under the control of pull-down node PD low potential, the 13rd transistor M13 and the 14th transistor M14 are equal Cut-off.At this point, the equal no signal input of the first signal output end Output1 and second signal output end Output2, therefore, first Signal output end Output1 and second signal output end Output2 will keep low level signal.

On this basis, the first transistor M1 is connected under the control of the first clock signal terminal CLK high potential, and passes through the The low level signal of second signal output end Output2 is transmitted to pull-up node PU, so that pull-up node PU by one transistor M1 Carry out noise reduction.

Work as CLK=0, when CLKB=1, under the control of the first clock signal terminal CLK low potential, the first transistor M1 is cut Only.

Also, since the current potential of pull-up node PU will keep low potential, so that the tenth transistor M10 and the tenth two-transistor M12 is in off state under the control of pull-up node PU low potential.At this point, believing in second clock signal end CLKB high level Number control under, the 9th transistor M9 conducting, the high level signal of second clock signal end CLKB is transmitted to the 11st crystal Pipe M11, so that the 11st transistor M11 is connected.11st transistor M11 passes second clock signal end CLKB high level signal Pull-down node PD is transported to, so that pull-down node PD is high potential.

On this basis, pull-down node PD high potential controls the 4th transistor M4 conducting, by the 4th transistor M4 by the The low level signal of one voltage end VGL is transmitted to pull-up node PU, so that pull-up node PU carries out noise reduction.

In addition, the 13rd transistor M13 and the 14th transistor M14 are led under the control of pull-down node PD high potential It is logical.The low level signal of first voltage end VGL is transmitted to the first signal output end Output1 by the 13rd transistor M13, The low level signal of first voltage end VGL is transmitted to second signal output end Output2 by the 14th transistor M14, from And the signal of second signal output end Output2 and the first signal output end Output1 is made to be low level signal.

In conclusion the first signal output end Output1 and second signal output end Output2 are equal in noise reduction stage P4 Export low level signal.

It should be noted that due to the first clock signal and second clock signal end CLKB of the first clock signal terminal CLK Second clock signal duty ratio it is identical, and the first clock signal of the first clock signal terminal CLK and second clock signal end The opposite in phase of the second clock signal of CLKB.

Based on the description above, can replace in noise reduction stage P4, the first transistor M1 and the 4th transistor M4 to pull-up Node PU carries out noise reduction, that is, the first clock signal terminal CLK in noise reduction stage P4 is pull-up in the time of high level signal Node PU carries out noise reduction by the first transistor M1, and the second clock signal end CLKB in noise reduction stage P4 is high level signal Time in, pull-up node PU by the 4th transistor M4 carry out noise reduction.It thereby may be ensured that before next frame arrival, pull-up Node PU can carry out always noise reduction, improve shift register cell in the noise reduction effect of the non-effective output stage of picture frame.

Compared to shift register cell as shown in figure 12, the letter of second voltage end VDD1 or tertiary voltage end VDD2 Number for second clock signal input part CLKB second clock signal in the case where, due to second clock signal input part CLKB's The duty ratio of second clock signal is 50%, so that pull-up node PU is only in 50% time of the non-effective output stage of picture frame Interior carry out noise reduction, causes the noise reduction effect of pull-up node PU unstable, still with the presence of noise signal in shift register cell, very It is easy to happen operation irregularity, and reduces product quality.Also, even if second voltage end VDD1's or tertiary voltage end VDD2 In the case that signal is high level signal always, in the low level letter of the non-effective output stage first voltage end VGL of picture frame It number can be transmitted to pull-up node PU always, realize and noise reduction continued to pull-up node PU, but the crystalline substance in shift register cell Body pipe quantity is relatively more, and circuit structure is complex, in practical applications, is unfavorable for reducing the border width of display device, Full screen display difficult to realize.

And the shift register cell in the present invention, in the effective feelings of the first clock signal of the first clock signal terminal CLK Under condition, the first transistor M1 is connected under the control of the first clock signal of the first clock signal terminal CLK, and second signal is exported The low level signal of end Output2 is transmitted to pull-up node PU, so that pull-up node PU carries out noise reduction.In second clock signal end In the effective situation of second clock signal of CLKB, the signal of pull-down node PD controls the 4th transistor M4 conducting, passes through the 4th The low level signal of first voltage end VGL is transmitted to pull-up node PU by transistor M4, so that pull-up node PU carries out noise reduction.In On the basis of this, due to the first clock signal of the first clock signal terminal CLK and the second clock letter of second clock signal end CLKB Number frequency is equal, opposite in phase, therefore, noise reduction stage P4, the first transistor M1 and the 4th transistor M4 can alternately pair Pull-up node PU carries out noise reduction.Compared to shift register cell as shown in figure 12, shift register cell of the invention exists Before next frame arrives after output stage, pull-up node PU can carry out always noise reduction, improve shift register cell and scheming As the noise reduction effect of the non-effective output stage of frame.Also, the number of transistors in shift register cell of the invention is opposite Less, circuit structure is relatively easy, in practical applications, can reduce the border width of display device, is easy to implement full frame aobvious Show.

In some embodiments of the invention, the first noise reduction sub-circuit 21 and pull-up node PU, the first clock signal terminal CLK and the first signal output end Output1 electrical connection.

In the case, signal timing diagram as shown in connection with fig. 8, to shift register cell shown in Fig. 7 different The working condition in stage (P1~P4) carries out detailed illustration.

In input phase P1, INPUT=1, RESET=0, CLK=0, CLKB=1.

Also, under the control of the low level signal in the first clock signal terminal CLK, the first transistor M1 cut-off.To not It will affect and charge to pull-up node PU.

In addition, as shown in fig. 7, under the control of pull-up node PU high potential, the tenth transistor M10 and the tenth two-transistor M12 conducting, under the control of second clock signal end CKLB high level, the 9th transistor M9 conducting, but due to the tenth transistor The breadth length ratio of M10 channel is greater than the breadth length ratio of the 9th transistor M9 channel, so that the grid of the 11st transistor M11 is low electricity It is flat, control the 11st transistor M11 cut-off, so that the current potential of pull-down node PD can be still pulled down to by the tenth two-transistor M12 The low level of first voltage end VGL.At this point, under the control of pull-down node PD low potential, the 4th transistor M4, the 13rd crystal Pipe M13 and the 14th transistor M14 are in off state.

In output stage P2, INPUT=0, RESET=0, CLK=1, CLKB=0.

At this point, under the control of the high level signal of the first clock signal terminal CLK, the first transistor M1 conducting can be incited somebody to action The high level signal of pull-up node PU is transmitted to the first signal output end Output1, so as to shorten the first signal output end The time that Output1 current potential rises.

On this basis, under the boot strap of storage capacitance C, the current potential of pull-up node PU is further increased, to maintain Second transistor M2 and third transistor M3 is in the state of conducting, so that the high level of the first clock signal terminal CLK The first signal output end Output1 and second signal output end Output2 continually and steadily can be transmitted to.

In reseting stage P3, INPUT=0, RESET=1, CLK=0, CLKB=1.

In noise reduction stage P4, INPUT=0, RESET=0.

On this basis, the first transistor M1 is connected under the control of the first clock signal terminal CLK high potential, and passes through the The low level signal of first signal output end Output1 is transmitted to pull-up node PU, so that pull-up node PU by one transistor M1 Carry out noise reduction.

In addition, the 13rd transistor M13 and the 14th transistor M14 are led under the control of pull-down node PD high potential It is logical.The low level signal of first voltage end VGL is transmitted to second signal output end Output2 by the 13rd transistor M13, The low level signal of first voltage end VGL is transmitted to the first signal output end Output1 by the 14th transistor M14, from And the signal of second signal output end Output2 and the first signal output end Output1 is made to be low level signal.

In conclusion the first signal output end Output1 and second signal output end Output2 are equal in noise reduction stage P4 Export low level signal.Also, the first transistor M1 and the 4th transistor M4, which can replace, carries out noise reduction to pull-up node PU, from And can guarantee before next frame arrives, pull-up node PU can carry out always noise reduction, improve shift register cell and scheming As the noise reduction effect of the non-effective output stage of frame.

On the basis of above-mentioned, as shown in figure 9, the present invention also provides a kind of shift register cells, comprising: the first noise reduction Sub-circuit 21 and the first signal export sub-circuit 22.

First signal exports sub-circuit 22 and pull-up node PU, the first clock signal terminal CLK and the first signal output end Output1 electrical connection.

First noise reduction sub-circuit 22 and pull-up node PU, the first clock signal terminal CLK and the first signal output end Output1 electrical connection.

First noise reduction sub-circuit 22 is used under the control of the first clock signal from the first clock signal terminal CLK, will Signal from the first signal output end Output1 is transmitted to pull-up node PU.

Therefore, in the non-effective output stage of picture frame, the control of the first clock signal of the first clock signal terminal CLK Under, the first noise reduction sub-circuit 21 is opened, the signal of the first signal output end Output1 is transmitted to pull-up node PU, so that on The current potential for drawing the signal of node PU is low potential, realizes and carries out noise reduction to pull-up node PU, to improve shift register cell In the noise reduction effect of the non-effective output stage of picture frame, the noise signal generated by pull-up node PU is avoided, displacement is caused to be posted The problem of storage cell operation is abnormal, reduces display product quality.

On this basis, optionally, as shown in Figure 10, the first noise reduction sub-circuit 21 includes the first transistor M1.

The grid of the first transistor M1 is electrically connected with the first clock signal terminal CLK, the first pole of the first transistor M1 and the One signal output end Output1 electrical connection, the second pole of the first transistor M1 is electrically connected with pull-up node PU.

On this basis, optionally, as shown in Figure 10, the first signal output sub-circuit 22 includes second transistor M2 and deposits Storage holds C.

In some embodiments of the invention, as shown in Figure 10, shift register cell further includes second signal input Circuit 26, with second signal input terminal IN2, pull-up node PU, the first signal output end Output1 and first voltage end VGL Electrical connection.Second signal inputs sub-circuit 26 and is used under the control of the signal from second signal input terminal IN2, will be from the The signal of one voltage end VGL is transmitted to pull-up node PU and the first signal output end Output1.

Optionally, second signal input sub-circuit 26 includes the 6th transistor M6 and the 8th transistor M8.Wherein, the 6th is brilliant The grid of body pipe M6 is electrically connected with second signal input terminal IN2, and the first pole of the 6th transistor M6 is electrically connected with pull-up node PU, The second pole of 6th transistor M6 is electrically connected with first voltage end VGL.The grid and second signal input terminal of 8th transistor M8 IN2 electrical connection, the first pole of the 8th transistor M8 is electrically connected with the first signal output end Output1, and the of the 8th transistor M8 Two poles are electrically connected with first voltage end VGL.

In some embodiments of the invention, as shown in Figure 10, shift register cell further includes drop-down sub-circuit 28, with Pull-down node PD, the first signal output end Output1 and first voltage end VGL electrical connection.Sub-circuit 28 is pulled down to be used to come From under the control of the signal of pull-down node PD, the signal from first voltage end VGL is transmitted to the first signal output end Output1。

Optionally, drop-down sub-circuit 28 includes the 13rd transistor M13.The grid and drop-down section of 13rd transistor M13 Point PD electrical connection, the first pole of the 13rd transistor M13 are electrically connected with the first signal output end Output1, the 13rd transistor The second pole of M13 is electrically connected with first voltage end VGL.

In addition, as shown in Figure 10, shift register cell further includes the second noise reduction sub-circuit 24, drop-down control sub-circuit 27 And first signal input sub-circuit 25.

It should be noted that the second noise reduction sub-circuit 24, drop-down control sub-circuit 27 and the first signal input sub-circuit The second noise reduction sub-circuit 24, drop-down control sub-circuit 27 and the first signal in 25, with above-mentioned shift register cell is defeated Enter the structure having the same of sub-circuit 25, function and effect, details are not described herein.

On this basis, the signal timing diagram in conjunction with shown in Figure 11, to shift register cell shown in Fig. 10 in difference The working condition in stage (P1~P4) carry out detailed illustration.

In input phase P1, INPUT=1, RESET=0, CLK=0, CLKB=1.

In addition, as shown in Figure 10, under the control of pull-up node PU high potential, the tenth transistor M10 and the 12nd crystal Pipe M12 conducting, under the control of second clock signal end CKLB high level, the 9th transistor M9 conducting, but due to the tenth crystal The breadth length ratio of pipe M10 channel is greater than the breadth length ratio of the 9th transistor M9 channel, so that the grid of the 11st transistor M11 is low electricity It is flat, control the 11st transistor M11 cut-off, so that the current potential of pull-down node PD can be still pulled down to by the tenth two-transistor M12 The low level of first voltage end VGL.At this point, the 4th transistor M4 and the 13rd is brilliant under the control of pull-down node PD low potential Body pipe M13 is in off state.

In conclusion the first signal output end Output1 exports low level in input phase P1.

In output stage P2, INPUT=0, RESET=0, CLK=1, CLKB=0.

On this basis, under the boot strap of storage capacitance C, the current potential of pull-up node PU is further increased, to maintain The state that second transistor M2 is on, so that the biography that the high level of the first clock signal terminal CLK can be continual and steady Transport to the first signal output end Output1.

In addition, under the control of the low level signal of second clock signal end CLKB, the 9th transistor M9 cut-off is being pulled up Under the control of node PU high potential, the tenth transistor M10 conducting, and the low level signal of first voltage end VGL is transmitted to the 11 crystal M11, control the 11st transistor M11 cut-off.At this point, the 12nd is brilliant under the control of pull-up node PU high potential The low level signal of first voltage end VGL is transmitted to pull-down node PD by body pipe M12 conducting, the tenth two-transistor M12.In this feelings Under condition, the 4th transistor M4 and the 13rd transistor M13 are in off state under the control of pull-down node PD low potential.

In conclusion the first signal output end Output1 exports high level in output stage P2.

In reseting stage P3, INPUT=0, RESET=1, CLK=0, CLKB=1.

In the case, since the signal from the first signal input part IN1 is low level, at the 5th transistor M5 In off state.Under the control of the high level signal from second signal input terminal IN2, the 6th transistor M6 and the 8th crystal Pipe M8 conducting.The current potential of pull-up node PU is pulled down to the low level of first voltage end LVGL by the 6th transistor M6, with right Pull-up node PU is resetted.The current potential of the first signal output end Output1 is pulled down to the first electricity by the 8th transistor M8 Pressure side VGL, to be resetted to the first signal output end Output1.

At this point, second transistor M2 is in off state under the control of pull-up node PU low potential.

Also, under the control of pull-up node PU low potential, the tenth transistor M10 and the tenth two-transistor M12 are also cut Only.On this basis, due to the high level signal control from second clock signal end CLKB, so that the 9th transistor M9 is led It is logical, and the high level of second clock signal end CLKB is transmitted to the 11st transistor M11, the 11st transistor M11 of control is led Logical, the high level of second clock signal end CLKB is transmitted to pull-down node PD by the 11st transistor M11.At this point, being saved in drop-down Under the control of the high level signal of point PD, the 4th transistor M4 conducting, by the 4th transistor M4 by the current potential of pull-up node PU It is pulled down to first voltage end VGL.Likewise, the 13rd transistor M13 is led under the control of the high level signal of pull-down node PD It is logical, the current potential of the first signal output end Output1 is pulled down to by first voltage end VGL by the 13rd transistor M13.

In conclusion the first signal output end Output1 exports low level signal in reseting stage P3.

In noise reduction stage P4, INPUT=0, RESET=0.

In the case, since the signal from the first signal input part IN1 is low level, at the 5th transistor M5 In off state.Also, under the control of the low level signal from second signal input terminal IN2, the 6th transistor M6 and Eight transistor M8 are turned off.

On this basis, under the control of pull-up node PU low potential, second transistor M2 and third transistor M3 locate In off state, and under the control of pull-down node PD low potential, the 13rd transistor M13 cut-off.At this point, the first signal exports The input of Output1 no signal is held, therefore, the first signal output end Output1 will keep low level signal.

In addition, under the control of pull-down node PD high potential, the 13rd transistor M13 conducting.Pass through the 13rd transistor The low level signal of first voltage end VGL is transmitted to the first signal output end Output1 by M13, so that the first signal is defeated The signal of outlet Output1 is low level signal.

In conclusion the first signal output end Output1 exports low level signal in noise reduction stage P4.Also, first is brilliant Body pipe M1 and the 4th transistor M4, which can replace, carries out noise reduction to pull-up node PU, thereby may be ensured that and arrives it in next frame Before, pull-up node PU can carry out always noise reduction, improve shift register cell in the drop of the non-effective output stage of picture frame It makes an uproar effect.

On the basis of above-mentioned, the embodiment of the present invention also provides a kind of driving method of shift register cell, such as Fig. 4 and Shown in Fig. 6, shift register cell includes the first noise reduction sub-circuit 21, the first signal output sub-circuit 22, second signal output Sub-circuit 23, the second noise reduction sub-circuit 24, the first signal input sub-circuit 25 and drop-down control sub-circuit 27.

First noise reduction sub-circuit 21 and pull-up node PU, the first clock signal terminal CLK and the first signal output end Output1 or second signal output end Output2 electrical connection.

Second signal exports sub-circuit 23 and pull-up node PU, the first clock signal terminal CLK and second signal output end Output2 electrical connection.

Second noise reduction sub-circuit 24 is electrically connected with pull-up node PU, pull-down node PD and first voltage end VGL.

First signal input sub-circuit 25 is electrically connected with the first signal input part IN1 and pull-up node PD.

Drop-down control sub-circuit 27 and second clock signal end CLKB, pull-up node PD, the electricity of pull-down node PD and first Pressure side VGL electrical connection.

The driving method of shift register cell includes:

In the input phase P1 of picture frame as shown in Figure 8:

Under the control of the signal from the first signal input part IN1, the first signal, which inputs sub-circuit 25, will come from first The signal of signal input part IN1 is transmitted to pull-up node PU.

In the output stage P2 of picture frame as shown in Figure 8:

Under the control of the signal from pull-up node PU, the first signal output sub-circuit 22 will come from the first clock signal The first clock signal transmission to the first signal output end Output1 of CLK is held, second signal, which exports sub-circuit 23, will come from first The first clock signal transmission of clock signal terminal CLK is to second signal output end Output2.

In the noise reduction stage P4 of picture frame as shown in Figure 8:

Under the control of the first clock signal from the first clock signal terminal CLK, the first noise reduction sub-circuit 21 will be come from The signal for the second signal output end Output2 being connected electrically is transmitted to pull-up node PU, is connected electrically alternatively, will come from The signal of the first signal output end Output1 be transmitted to pull-up node PU.

Also, in being total to for the second clock signal from second clock signal end CLKB and the signal from pull-up node PU With under control, the second clock signal from second clock signal end CLKB is transmitted to pull-down node by drop-down control sub-circuit 27 PD, so that the signal from first voltage end VGL is transmitted to pull-up node PU by the second noise reduction sub-circuit 24.

The driving method of above-mentioned shift register cell has identical with above-mentioned shift register cell beneficial to effect Fruit, therefore repeat no more.

The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims

1. a kind of shift register cell characterized by comprising the first noise reduction sub-circuit, the first signal output sub-circuit with And second signal exports sub-circuit；

First signal exports sub-circuit, is electrically connected with pull-up node, the first clock signal terminal and the first signal output end； The first signal output sub-circuit is configured as to store from the signal of the pull-up node, and is coming from described Under the control for drawing the signal of node, by the first clock signal transmission from first clock signal terminal to first signal Output end；

The second signal exports sub-circuit, exports with the pull-up node, first clock signal terminal and second signal End electrical connection；The second signal output sub-circuit is configured as under the control of the signal from the pull-up node, in the future From the first clock signal transmission of first clock signal terminal to the second signal output end；

The first noise reduction sub-circuit is exported with the pull-up node, first clock signal terminal and the second signal End or first signal output end electrical connection；The first noise reduction sub-circuit is configured as believing from first clock Number end the first clock signal control under, the signal from the second signal output end being connected electrically is transmitted to institute Pull-up node is stated, alternatively, the signal from first signal output end being connected electrically is transmitted to the pull-up node.

2. shift register cell according to claim 1, which is characterized in that the shift register cell further includes Two noise reduction sub-circuits；

The second noise reduction sub-circuit is electrically connected with the pull-up node, pull-down node and first voltage end；Described second Noise reduction sub-circuit is configured as under the control of the signal from the pull-down node, by the signal from the first voltage end It is transmitted to the pull-up node.

3. shift register cell according to claim 1 or 2, which is characterized in that

The shift register cell further includes the first signal input sub-circuit；First signal inputs sub-circuit, with first Signal input part and pull-up node electrical connection；The first signal input sub-circuit is configured as from first letter Under the control of the signal of number input terminal, the signal from first signal input part is transmitted to the pull-up node；

And/or

The shift register cell further includes second signal input sub-circuit；The second signal inputs sub-circuit, with second Signal input part, the pull-up node, first signal output end, the second signal output end and first voltage end Electrical connection；The second signal input sub-circuit is configured as under the control of the signal from the second signal input terminal, Signal from the first voltage end is transmitted to the pull-up node, first signal output end and the second signal Output end；

And/or

The shift register cell further includes drop-down control sub-circuit；The drop-down controls sub-circuit, with second clock signal End, the pull-up node, the pull-down node and the electrical connection of first voltage end；The drop-down control sub-circuit is configured as Second clock signal from the second clock signal end and under the co- controlling of the signal from the pull-up node, respectively Signal from the first voltage end is transmitted to the pull-down node by section in different times, when will come from described second The second clock signal of clock signal end is transmitted to the pull-down node；

And/or

The shift register cell further includes drop-down sub-circuit；The drop-down sub-circuit, with the pull-down node, described first Signal output end, the second signal output end and the electrical connection of first voltage end；The drop-down sub-circuit is configured as coming From under the control of the signal of the pull-down node, the signal from the first voltage end is transmitted to first signal and is exported End and the second signal output end.

4. shift register cell according to claim 1, which is characterized in that the first noise reduction sub-circuit includes first Transistor；

In the case where the first noise reduction sub-circuit is electrically connected with the second signal output end, the grid of the first transistor Pole is electrically connected with first clock signal terminal, and the first pole of the first transistor is electrically connected with the second signal output end It connects, the second pole of the first transistor is electrically connected with the pull-up node；

In the case where the first noise reduction sub-circuit is electrically connected with first signal output end, the grid of the first transistor Pole is electrically connected with first clock signal terminal, and the first pole of the first transistor is electrically connected with first signal output end It connects, the second pole of the first transistor is electrically connected with the pull-up node.

5. shift register cell according to claim 1, which is characterized in that first signal exports sub-circuit and includes Second transistor and storage capacitance；

The grid of the second transistor is electrically connected with the pull-up node, the first pole of the second transistor and described first Clock signal terminal electrical connection, the second pole of the second transistor is electrically connected with first signal output end；

First pole of the storage capacitance is electrically connected with the pull-up node, the second pole of the storage capacitance and first letter The electrical connection of number output end；

And/or

The second signal output sub-circuit includes third transistor；

The grid of the third transistor is electrically connected with the pull-up node, the first pole of the third transistor and described first Clock signal terminal electrical connection, the second pole of the third transistor is electrically connected with the second signal output end.

6. shift register cell according to claim 2, which is characterized in that the second noise reduction sub-circuit includes the 4th Transistor；

The grid of 4th transistor is electrically connected with the pull-down node, the first pole of the 4th transistor and the pull-up Node electrical connection, the second pole of the 4th transistor is electrically connected with the first voltage end.

7. shift register cell according to claim 3, which is characterized in that in the shift register cell include the In the case that one signal inputs sub-circuit, the first signal input sub-circuit includes the 5th transistor；

The grid of 5th transistor and first is extremely electrically connected with first signal input part, the 5th transistor Second pole is electrically connected with the pull-up node；

And/or

In the case where the shift register cell includes second signal input sub-circuit, the second signal inputs sub-circuit Including the 6th transistor, the 7th transistor and the 8th transistor；

The grid of 6th transistor is electrically connected with the second signal input terminal, the first pole of the 6th transistor and institute Pull-up node electrical connection is stated, the second pole of the 6th transistor is electrically connected with the first voltage end；

The grid of 7th transistor is electrically connected with the second signal input terminal, the first pole of the 7th transistor and institute The electrical connection of second signal output end is stated, the second pole of the 7th transistor is electrically connected with the first voltage end；

The grid of 8th transistor is electrically connected with the second signal input terminal, the first pole of the 8th transistor and institute The electrical connection of the first signal output end is stated, the second pole of the 8th transistor is electrically connected with the first voltage end；

And/or

In the case where the shift register cell includes drop-down control sub-circuit, the drop-down control sub-circuit includes the 9th Transistor, the tenth transistor, the 11st transistor and the tenth two-transistor；

The grid of 9th transistor and first is extremely electrically connected with the second clock signal end, the 9th transistor Second pole is electrically connected with the first pole of the tenth transistor；

The grid of tenth transistor is electrically connected with the pull-up node, the second pole and described first of the tenth transistor Voltage end electrical connection；

The first of the grid of 11st transistor and the second pole of the 9th transistor and the tenth transistor is extremely electric Connection, the first pole of the 11st transistor is electrically connected with the second clock signal end, and the of the 11st transistor Two poles are electrically connected with the pull-down node；

The grid of tenth two-transistor is electrically connected with the pull-up node, the first pole of the tenth two-transistor with it is described Pull-down node electrical connection, the second pole of the tenth two-transistor is electrically connected with the first voltage end；

And/or

In the case where the shift register cell includes drop-down sub-circuit, the drop-down sub-circuit includes the 13rd transistor With the 14th transistor；

The grid of 13rd transistor and the pull-down node electrical connection, the first pole of the 13rd transistor with it is described The electrical connection of first signal output end, the second pole of the 13rd transistor is electrically connected with the first voltage end；

The grid of 14th transistor is electrically connected with the pull-down node, the first pole of the 14th transistor with it is described The electrical connection of second signal output end, the second pole of the 14th transistor is electrically connected with the first voltage end.

8. a kind of shift register cell characterized by comprising the first noise reduction sub-circuit and the first signal export sub-circuit；

The first noise reduction sub-circuit is exported with the pull-up node, first clock signal terminal and first signal End electrical connection；The first noise reduction sub-circuit is configured as the control in the first clock signal from first clock signal terminal Under system, the signal from first signal output end is transmitted to the pull-up node.

9. shift register cell according to claim 8, which is characterized in that the first noise reduction sub-circuit includes first Transistor；

The grid of the first transistor is electrically connected with first clock signal terminal, the first pole of the first transistor and institute The electrical connection of the first signal output end is stated, the second pole of the first transistor is electrically connected with the pull-up node.

10. shift register cell according to claim 8, which is characterized in that first signal exports sub-circuit packet Include second transistor and storage capacitance；

First pole of the storage capacitance is electrically connected with the pull-up node, the second pole of the storage capacitance and first letter The electrical connection of number output end.

11. a kind of gate driving circuit, which is characterized in that including multiple cascade such as any one of claim 1-7 or as weighed Benefit requires the described in any item shift register cells of 8-10；

First signal output end of every grade of the shift register cell is electrically connected with a grid line.

12. gate driving circuit according to claim 11, which is characterized in that in the shift register cell include the In the case that binary signal exports sub-circuit,

Other than first order shift register cell, the first signal input part of every level-one shift register cell and thereon one The second signal output end of grade shift register cell is connected；

Other than afterbody shift register cell, under the second signal input terminal of every level-one shift register cell and its The second signal output end of level-one shift register cell is connected.

13. a kind of display device, which is characterized in that including the gate driving circuit as described in claim 11 or 12.

14. a kind of driving method of shift register cell, which is characterized in that

The shift register cell includes the first noise reduction sub-circuit, the first signal output sub-circuit, second signal output son electricity Road, the second noise reduction sub-circuit, the first signal input sub-circuit and drop-down control sub-circuit；

The first noise reduction sub-circuit and pull-up node, the first clock signal terminal and the first signal output end or the second letter The electrical connection of number output end；

The first signal output sub-circuit and the pull-up node, first clock signal terminal and first signal are defeated Outlet electrical connection；

The second signal output sub-circuit and the pull-up node, first clock signal terminal and the second signal are defeated Outlet electrical connection；

The second noise reduction sub-circuit is electrically connected with the pull-up node, pull-down node and first voltage end；

First signal inputs sub-circuit, is electrically connected with the first signal input part and the pull-up node；

The drop-down control sub-circuit and second clock signal end, the pull-up node, the pull-down node and described first Voltage end electrical connection；

The driving method of the shift register cell includes:

In the input phase of picture frame:

Under the control of the signal from first signal input part, first signal input sub-circuit will be from described the The signal of one signal input part is transmitted to the pull-up node；

In the output stage of described image frame:

Under the control of the signal from the pull-up node, the first signal output sub-circuit will come from first clock For first clock signal transmission of signal end to first signal output end, the second signal output sub-circuit will be from described First clock signal transmission of the first clock signal terminal is to the second signal output end；

In the noise reduction stage of described image frame:

Under the control of the first clock signal from first clock signal terminal, the first noise reduction sub-circuit will from Its signal of the second signal output end being electrically connected is transmitted to the pull-up node, alternatively, will be from being connected electrically The signal of first signal output end is transmitted to the pull-up node；

Also, in the common of the second clock signal from the second clock signal end and the signal from the pull-up node Under control, the second clock signal from the second clock signal end is transmitted to drop-down section by the drop-down control sub-circuit Point, so that the signal from the first voltage end is transmitted to the pull-up node by the second noise reduction sub-circuit.